Voltage regulator and charge storage system

Abstract

To suppress application of an excessive voltage to a specific electrolytic capacitor.SOLUTION: A voltage adjustment device (10a) connected to a series circuit of a plurality of electrolytic capacitors (C[1], C[2]) provided between ground wiring and input voltage wiring includes a high-side terminal and a low-side terminal (TMH, TML) connected to the input voltage wiring and the ground wiring, an intermediate terminal (TMM[1]) connected to a connection node between the plurality of electrolytic capacitors, and voltage limiting circuits (11H-13H, 11L-13L) that limit a voltage between the high-side terminal and the intermediate terminal to a high-side limit voltage or less by controlling a high-side adjustment current (IH) between the terminals in accordance with a voltage therebetween, and limit a voltage between the intermediate terminal and the low-side terminal to a low-side limit voltage or less by controlling a low-side adjustment current (IL) between the terminals in accordance with a voltage therebetween.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to voltage regulators and charge storage systems. [Background technology]

[0002] In cases where a single electrolytic capacitor does not have sufficient withstand voltage, multiple electrolytic capacitors may be connected in series (see Patent Document 1 below). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-304414

[0004] [overview] When an input voltage is applied to a series circuit of multiple electrolytic capacitors, the voltage applied to each electrolytic capacitor should ideally be uniform. However, in reality, the voltage applied to each electrolytic capacitor often becomes uneven due to differences in leakage current among the multiple electrolytic capacitors, and as a result, an excessive voltage may be applied to a specific electrolytic capacitor. Application of excessive voltage to electrolytic capacitors should be prevented.

[0005] A voltage adjustment device according to one aspect of the present disclosure is a voltage adjustment device connected to a series circuit of multiple electrolytic capacitors arranged between a ground wiring and an input voltage wiring to which an input voltage higher than the potential of the ground wiring is applied, and includes: a high-side terminal connected to the input voltage wiring; a low-side terminal connected to the ground wiring; an intermediate terminal connected to a connection node between the multiple electrolytic capacitors; and a voltage limiting circuit configured to limit the voltage between the high-side terminal and the intermediate terminal to a high-side limit voltage or less by controlling a high-side adjustment current between the high-side terminal and the intermediate terminal in accordance with the voltage between the high-side terminal and the intermediate terminal, and to limit the voltage between the intermediate terminal and the low-side terminal to a low-side limit voltage or less by controlling a low-side adjustment current between the intermediate terminal and the low-side terminal in accordance with the voltage between the intermediate terminal and the low-side terminal.

[0006] A voltage adjustment device according to another aspect of the present disclosure is a voltage adjustment device connected to a series circuit of multiple electrolytic capacitors arranged between a ground wiring and an input voltage wiring to which an input voltage higher than the potential of the ground wiring is applied, and includes a high-side terminal connected to the input voltage wiring, a low-side terminal connected to the ground wiring, an intermediate terminal connected to a connection node between the multiple electrolytic capacitors, and a voltage leveling circuit configured to reduce the difference between the electrode-to-electrode voltage of a first electrolytic capacitor included in the multiple electrolytic capacitors and the electrode-to-electrode voltage of a second electrolytic capacitor included in the multiple electrolytic capacitors by controlling the current between the connection node and the intermediate terminal based on the voltages of the high-side terminal and the intermediate terminal as viewed from the potential of the low-side terminal. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is an overall configuration diagram of a circuit system according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a diagram illustrating an example of the configuration of a voltage supply device according to an embodiment of the present disclosure. [Figure 3]FIG. 3 is a diagram illustrating another configuration example of a voltage supply device according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a diagram showing the configurations and connections of a capacitance device and a voltage adjustment device according to an embodiment of the present disclosure. [Figure 5] FIG. 5 is a diagram for explaining a reference configuration, showing how the voltages applied to two capacitors connected in series become unequal. [Figure 6] FIG. 6 is a diagram showing a reference configuration. [Figure 7] FIG. 7 is a circuit diagram of a voltage regulator according to Example EX_A1 of the embodiment of the present disclosure. [Figure 8] FIG. 8 is a waveform diagram for explaining the operation of the voltage regulator according to Example EX_A1 of the embodiment of the present disclosure. [Figure 9] FIG. 9 is a waveform diagram for explaining the operation of the voltage regulator according to Example EX_A1 of the embodiment of the present disclosure. [Figure 10] FIG. 10 is a waveform diagram for explaining the operation of the voltage regulator according to Example EX_A1 of the embodiment of the present disclosure. [Figure 11] FIG. 11 is an external plan view of a semiconductor device according to Example EX_A2 of the embodiment of the present disclosure. [Figure 12] FIG. 12 is a diagram for explaining the relationship between the voltage regulator and the semiconductor device according to Example EX_A2 of the embodiment of the present disclosure. [Figure 13] FIG. 13 is an external plan view of two semiconductor devices according to Example EX_A3 belonging to the embodiment of the present disclosure. [Figure 14] FIG. 14 is a diagram for explaining the relationship between two voltage regulators and a semiconductor device according to Example EX_A3 of the embodiment of the present disclosure. [Figure 15] FIG. 15 is a schematic configuration diagram of a voltage regulator according to Example EX_A4 of the embodiment of the present disclosure. [Figure 16] FIG. 16 is a partial circuit diagram of a voltage regulator according to Example EX_A4 of the embodiment of the present disclosure. [Figure 17] FIG. 17 is a circuit diagram of a voltage regulator according to Example EX_B1 of the embodiment of the present disclosure. [Figure 18] FIG. 18 is a circuit diagram of a voltage regulator according to Example EX_B2 of the embodiment of the present disclosure. [Figure 19] FIG. 19 is a configuration diagram of a voltage regulator according to Example EX_B3 of the embodiment of the present disclosure.

[0008] [Detailed explanation] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the drawings referred to, the same parts are given the same reference numerals, and duplicated explanations of the same parts will be omitted as a general rule. In this specification, for the sake of simplicity, by using symbols or signs that refer to information, signals, physical quantities, functional units, circuits, elements, or parts, the names of the information, signals, physical quantities, functional units, circuits, elements, or parts corresponding to the symbols or signs may be omitted or abbreviated. For example, "TM" as described below may be omitted or abbreviated. H The high-side terminal referred to by " (see Figure 4) is the high-side terminal TM H It may also be written as terminal TM H They may be abbreviated as "," but they all refer to the same thing.

[0009] First, some terms used in describing the embodiments of the present disclosure will be explained. Ground refers to a reference conductor having a reference potential of 0 V (zero volts), or refers to the 0 V potential itself. The reference conductor may be formed using a conductor such as metal. The 0 V potential is sometimes referred to as ground potential. In the embodiments of the present disclosure, a voltage indicated without a particular reference represents a potential seen from ground.

[0010] For any transistor configured as a FET (field effect transistor) exemplified by a MOSFET, the on-state refers to a state where conduction exists between the drain and source of the transistor, and the off-state refers to a state where non-conduction (cut-off state) exists between the drain and source of the transistor. The same applies to transistors not classified as FETs. Unless otherwise specified, a MOSFET is understood to be an enhancement-mode MOSFET. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor". Also, unless otherwise specified, in any MOSFET, the back gate may be considered to be short-circuited to the source. Hereinafter, for any transistor, the on-state and off-state may also be simply expressed as on and off, respectively.

[0011] Regarding the connection between a plurality of parts forming a circuit, such as any circuit element, wiring, node, etc., unless otherwise specified, it may be understood to refer to an electrical connection. When any two voltages to be compared are voltage v1 and v2, "v1>v2" represents that voltage v1 is higher than voltage v2, "v1<v2" represents that voltage v1 is lower than voltage v2, and "v1=v2" represents that the value of voltage v1 is the same as the value of voltage v2. The same applies to other expressions including physical quantities other than voltage.

[0012] FIG. 1 shows a schematic overall configuration of a circuit system SYS according to an embodiment of the present disclosure. The circuit system SYS includes a voltage supply device 1, a capacitance device 2, a voltage adjustment device 3, and a load device <0>. Each of the voltage supply device 1, the capacitance device 2, the voltage adjustment device 3, and the load device 4 is connected to a wiring WR which is an input voltage wiring IN and a wiring WR which is a ground wiring GND and is connected thereto. The wiring WR GND is connected to the ground. Therefore, the potential in the wiring WR GND is 0V (zero volts).

[0013] The voltage supply device 1 is based on an AC voltage V supplied from the outside AC and is for the wiring WR GNDThe potential of the wiring WR IN The input voltage V is positive with respect to IN 2 and 3 show an example of the configuration of the voltage supply device 1. As shown in FIG. 2, the voltage supply device 1 supplies a single-phase AC voltage as an AC voltage V AC and full-wave rectifies the single-phase AC voltage to produce the input voltage V IN Alternatively, as shown in FIG. 3, the voltage supply device 1 may be a single-phase full-wave rectifier circuit 1A that generates a three-phase AC voltage V AC and full-wave rectifies the three-phase AC voltage to produce the input voltage V IN Alternatively, the voltage supply device 1 may be a three-phase full-wave rectifier circuit 1B that generates the input voltage V by performing half-wave rectification on a single-phase or three-phase AC voltage. IN Although not shown, the voltage supply device 1 may be a half-wave rectifier circuit that generates an AC voltage V in addition to the full-wave rectifier circuit 1A or 1B. AC The signal may include a noise reduction circuit to reduce noise therein.

[0014] In any case, the AC voltage V AC is input to the voltage supply device 1, the AC voltage V AC The pulsating voltage V IN Wiring WR IN That is, the pulsating voltage is applied to the wiring WR GND The potential of the wiring WR IN Joined Wiring WR IN The instantaneous value of the voltage at the wiring WR is equal to the instantaneous value of the pulsating voltage. GND DC voltage is applied based on the potential of WR IN It may also be a DC voltage source that supplies a voltage to

[0015] The capacitance device 2 is connected to the wiring WR IN and WR GND The capacitance device 2 is a series circuit of a plurality of capacitors C arranged between the input voltage V INEach capacitor C in the capacitance device 2 is an electrolytic capacitor. The voltage regulator 3 is connected to a series circuit of the plurality of capacitors C and regulates the voltage between both electrodes of each capacitor C. The load device 4 receives an input voltage V IN The load device 4 may include an isolated DC / DC converter, which uses a transformer and a switching transistor to convert an input voltage V IN is the output voltage in the secondary circuit (input voltage V IN The load device 4 converts the input voltage V IN Alternatively, it may include any load that operates based on the output voltage generated by the isolated DC / DC converter.

[0016] Referring to FIG. 4, the configuration and connection relationship of the capacitance device 2 and the voltage adjustment device 3 are shown. The capacitance device 2 and the voltage adjustment device 3 form a charge storage system. The capacitance device 2 is composed of a series circuit of n capacitors C, where n is any integer equal to or greater than 2. When distinguishing the n capacitors C from one another, the n capacitors C will be referred to as capacitors C[1] to C[n] hereinafter. Each of the capacitors C[1] to C[n] is an electrolytic capacitor and has an anode and a cathode. In an electrolytic capacitor, the anode and cathode are sometimes referred to as the positive electrode and the negative electrode, respectively. The electrolyte in an electrolytic capacitor may be a liquid electrolyte or a solid electrolyte. It is primarily assumed that aluminum electrolytic capacitors will be used for the capacitors C[1] to C[n]. However, electrolytic capacitors other than aluminum electrolytic capacitors (e.g., tantalum electrolytic capacitors or niobium electrolytic capacitors) may also be used for the capacitors C[1] to C[n].

[0017] The capacitors C[1] to C[n] may have the same breakdown voltage and the same capacitance. However, the capacitors C[1] to C[n] may include two or more capacitors C with different breakdown voltages, or may include two or more capacitors C with different capacitances. Unless otherwise specified below, the capacitors C[1] to C[n] are assumed to have the same breakdown voltage and the same capacitance.

[0018] The anode of the capacitor C[1] is wire WR IN The cathode of the capacitor C[n] is connected to the wire WR GND Nodes ND[1] to ND[n-1] are formed in the series circuit of capacitors C[1] to C[n]. Node ND[i] is the connection node between the cathode of capacitor C[i] and the anode of capacitor C[i+1]. In other words, the cathode of capacitor C[i] and the anode of capacitor C[i+1] are commonly connected at node ND[i]. i represents any integer. Therefore, the cathode of capacitor C[1] and the anode of capacitor C[2] are commonly connected at node ND[1]. If "n≧3", the cathode of capacitor C[2] and the anode of capacitor C[3] are commonly connected at node ND[2]. The same applies to nodes ND[3] to ND[n-1].

[0019] The voltage regulator 3 is connected to the wiring WR IN High side terminal TM connected to H and wiring WR GND Low side terminal TM connected to L High-side terminal TM H is the input voltage V IN Low-side terminal TM L The voltage regulator 3 further includes a total of (n-1) intermediate terminals TM M A total of (n-1) intermediate terminals TM M is an intermediate terminal TM M [1]~TM M [n-1]. The intermediate terminal TM is connected to the voltage regulator 3 via a total of (n-1) wires provided outside the voltage regulator 3. M [1]~TM M [n-1] are connected to the nodes ND[1] to ND[n-1], respectively. M [i] is connected to node ND[i] and therefore to the cathode of capacitor C[i] and the anode of capacitor C[i+1].

[0020] The voltages at the nodes ND[1] to ND[n-1] are respectively the intermediate voltage VMID [1]~V MID In other words, the node ND[i] and the intermediate terminal TM M The voltage at [i] is the intermediate voltage V MID The voltage across the capacitor C[i] is represented by the symbol "V C [i]”. The voltage between both poles V C [i] represents the potential of the anode of the capacitor C[i] as seen from the potential of the cathode of the capacitor C[i]. Therefore, "V MID [1]+V C [1]=V IN " and "V MID [2]+V C [2]=V MID [1]” The intermediate voltage V MID [3]~V MID The same applies to [n-1]. C [i] is simply the voltage V C It can be abbreviated as [i]. Voltage V C [1]~V C The sum of [n] is the input voltage V IN is equal to.

[0021] When an electrolytic capacitor is charged by applying a DC voltage of the correct polarity, ideally no current should flow through it. However, in reality, a small amount of current flows through the electrolytic capacitor as a leakage current. Leakage current varies greatly from capacitor to capacitor. This means that the leakage current can vary greatly between multiple electrolytic capacitors. Furthermore, leakage current varies depending on the temperature of the electrolytic capacitor, and also on the time elapsed since the DC voltage was applied to the electrolytic capacitor. For these reasons, when a DC voltage is applied to a series circuit of multiple electrolytic capacitors, the voltage applied to each electrolytic capacitor can become uneven.

[0022] For example, in a system in which a maximum voltage of 800 V (volts) is expected to be applied to a series circuit of two electrolytic capacitors, if it is assumed that the voltage applied to each electrolytic capacitor is uniform, electrolytic capacitors 911 and 912, each with a withstand voltage of 450 V, can be connected in series as shown in Fig. 5. However, in reality, due to the occurrence of the above-mentioned unevenness, it may happen that 300 V is applied to one electrolytic capacitor and 500 V is applied to the other electrolytic capacitor (excessive withstand voltage may occur).

[0023] For this reason, a reference configuration has been considered in which balancing resistors are provided in parallel with each electrolytic capacitor, as shown in Figure 6. In the reference configuration of Figure 6, electrolytic capacitors 911 and 912 are connected in series, and a first balancing resistor is connected in parallel with electrolytic capacitor 911, and a second balancing resistor is connected in parallel with electrolytic capacitor 912. Because each balancing resistor requires a high withstand voltage, it is often configured with multiple resistors. In Figure 6, the first balancing resistor corresponding to electrolytic capacitor 911 is made up of a series circuit of resistors 921a and 921b, and the second balancing resistor corresponding to electrolytic capacitor 912 is made up of a series circuit of resistors 922a and 922b.

[0024] By providing a balancing resistor, it is possible to equalize the electrode-to-electrode voltage of electrolytic capacitor 911 and the electrode-to-electrode voltage of electrolytic capacitor 912 against the difference in leakage current. However, providing a balancing resistor results in constant loss in the balancing resistor. For example, when 400 V is applied to the series circuit of electrolytic capacitors 911 and 912 and resistors 921a, 921b, 922a, and 922b each have a resistance of 220 kΩ (kiloohms), a constant loss of approximately 0.182 W (watts) is generated in the balancing resistor group (921a, 921b, 922a, and 922b) because "400 V × 400 V / 880 kΩ ≒ 0.182 W." In addition, because four high-voltage resistors (921a, 921b, 922a, and 922b) that can tolerate large heat losses are required, the installation area for the balancing resistors becomes considerably larger.

[0025] Although details will become clear from the following explanation, by using the voltage regulator 3, it is possible to achieve lower loss and smaller area compared to the reference configuration, while preventing the electrolytic capacitor from exceeding its withstand voltage.

[0026] Below, several specific configuration examples, operation examples, application techniques, modified techniques, etc. related to the voltage regulator 3 will be described in multiple embodiments. The matters described above in this embodiment are applied to each of the following embodiments unless otherwise specified and unless there is a contradiction. If there are any matters in each embodiment that contradict the matters described above, the description in that embodiment may take precedence. Furthermore, unless there is a contradiction, the matters described in any of the multiple embodiments described below can also be applied to any other embodiment (i.e., any two or more of the multiple embodiments can be combined).

[0027] <<Example EX_A1>> An example EX_A1 will be described. In the example EX_A1, "n=2". FIG. 7 shows a circuit diagram of a voltage regulator 10a which is the voltage regulator 3 in the example EX_A1. The leakage current of the capacitor C[i] is represented by the symbol "I LK It is represented by "[i]".

[0028] The voltage regulator 10a is connected to a high-side terminal TM H , Low side terminal TM L and intermediate terminal TM M The voltage regulator 10a also includes a high-side controller 11H, a transistor (high-side transistor) 12H, a current limiting resistor 13H, a low-side controller 11L, a transistor (low-side transistor) 12L, and a current limiting resistor 13L. These components (11H to 13H and 11L to 13L) regulate the electrode-to-electrode voltage V C [1] and V C A voltage limiting circuit is formed in the voltage regulator 10a to limit the voltage at the node ND H1 ~ND H3 and ND L1 ~ND L3 , and wiring WR H1 ~WR H4and WR L1 ~WR L4 will be established.

[0029] The high-side controller 11H includes an amplifier 111H, which is an operational amplifier, a voltage divider circuit 112H consisting of voltage divider resistors 113H and 114H, a reference voltage source 115H, and a transistor 116H. The low-side controller 11L includes an amplifier 111L, which is an operational amplifier, a voltage divider circuit 112L consisting of voltage divider resistors 113L and 114L, a reference voltage source 115L, and a transistor 116L. The transistors 12H and 12L are N-channel MOSFETs. The transistors 116H and 116L are N-channel JFETs. JFET is an abbreviation for junction field-effect transistor. The transistors 116H and 116L are normally-on JFETs. Therefore, even if the gate-source voltage of the transistor 116H is 0V, the drain and source of the transistor 116H are conductive, and even if the gate-source voltage of the transistor 116L is 0V, the drain and source of the transistor 116L are conductive.

[0030] The voltage difference (V IN -V MID [1]) high-voltage components that can withstand the high-side terminal TM are used. H and intermediate terminal TM M [1] Voltage applied between (V IN -V MID [1]) fluctuates within a predetermined high-side voltage range, but the breakdown voltages of the transistors 12H and 116H and the voltage dividing resistor 113H are higher than the upper limit voltage (e.g., 220 V) within the high-side voltage range. Similarly, the voltage difference (V MID [1]-0) high-voltage components that can withstand the above conditions are used. M [1] and low side terminal TM L The voltage applied between the MID[1]) fluctuates within a predetermined low-side voltage range, but the breakdown voltages of the transistors 12L and 116L and the voltage dividing resistor 113L are higher than the upper limit voltage (for example, 220 V) within the low-side voltage range.

[0031] Outside the voltage regulator 10a, the high-side terminal TM H is wiring WR IN Connected to the low-side terminal TM L is wiring WR GND At the outside of the voltage regulator 10a, an intermediate terminal TM M [1] is connected to the cathode of the capacitor C[1] and the anode of the capacitor C[2] via the node ND[1]. That is, the cathode of the capacitor C[1] and the anode of the capacitor C[2] and the intermediate terminal TM M Node ND[1] is located between [1] and [2].

[0032] High side terminal TM H and intermediate terminal TM M [1] The configuration and operation between the nodes ND H1 is wiring WR H1 via the high-side terminal TM H and is connected to the wiring WR H2 Therefore, the node ND H1 and wiring WR H1 and WR H2 is the input voltage V IN is added. Node ND H1 is wiring WR H1 and wiring WR H2 Located between Node ND H2 is wiring WR H4 via the intermediate terminal TM M [1] and wiring WR H3 Therefore, the node ND H2 and wiring WR H3 and WR H4 The intermediate voltage V MID [1] is added. Node ND H2 is wiring WR H3 and wiring WR H4 Located between.

[0033] The drain of the transistor 12H, the drain of the transistor 116H, and the first end of the voltage dividing resistor 113H are connected to the wiring WR H2 The second terminal of the voltage dividing resistor 113H and the first terminal of the voltage dividing resistor 114H are connected to a node ND H3 The second end of the voltage dividing resistor 114H is connected to the wiring WR H3 The voltage divider circuit 112H is connected to the high-side terminal TM H and intermediate terminal TM M [1] The voltage V is the divided voltage between DIVH (High-side voltage divider) to generate voltage V DIVH is equal to the voltage drop across the voltage divider resistor 114H. Therefore, the node ND H3 The intermediate voltage V MID [1] Voltage V DIVH The voltage (V MID [1]+V DIVH ) is added.

[0034] The source of the transistor 12H is connected to a first terminal of the current limiting resistor 13H, and the second terminal of the current limiting resistor 13H is connected to the wiring WR H3 The gate of the transistor 116H is connected to the wiring WR H3 The output terminal of the amplifier 111H is connected to the gate of the transistor 12H. The source of the transistor 116H is connected to the positive power supply terminal of the amplifier 111H, and the negative power supply terminal of the amplifier 111H is connected to the wiring WR H3 As described above, since the transistor 116H is a normally-on JFET, the voltage VCC applied to the source of the transistor 116H is H is wiring WR H3 The non-inverting input terminal of the amplifier 111H is connected to the node ND H3 and therefore the voltage (V MID [1]+V DIVH ) is received. The amplifier 111H receives the voltage VCC of the positive power supply terminal with the potential of the negative power supply terminal as a reference. H It operates based on.

[0035] Reference voltage source 115H is wired WR H3 and is connected to the inverting input terminal of the amplifier 111H. The reference voltage source 115H is the voltage VCC H It operates based on the wiring WR H3 Reference voltage V REFH Generates the reference voltage V REFH has a predetermined magnitude (for example, 1 V). The reference voltage source 115H generates an intermediate voltage V MID [1] Reference voltage V REFH The voltage (V MID [1]+V REFH ) is supplied to the inverting input terminal of amplifier 111H.

[0036] Amplifier 111H is Node ND H3 Voltage at (V MID [1]+V DIVH ) and the voltage from the reference voltage source 115H (V MID [1]+V REFH ) and applies the amplified difference signal to the gate of transistor 12H. This comparison is performed by voltage V DIVH and V REFH The amplifier 111H is equivalent to comparing the voltage V DIVH and V REFH The presence or absence and magnitude of the drain current of the transistor 12H are controlled by controlling the gate voltage of the transistor 12H according to the level relationship between the two. H (high side regulated current).

[0037] The amplifier 111H is "V DIVH <V REFH When the condition "" is satisfied, the wiring WR H3 , which sets transistor 12H off (i.e., blocks transistor 12H). When transistor 12H is off, the regulated current I H is zero. Amplifier 111H is "V DIVH >V REFH” is established, the gate voltage of the transistor 12H is increased to set the transistor 12H on (to make the transistor 12H conductive). When the transistor 12H is on, the regulating current I H occurs. DIVH >V REFH When the voltage V DIVH and V REFH As the absolute value of the difference between the input and output voltages increases, amplifier 111H increases the gate voltage of transistor 12H, and this increase in the gate voltage of transistor 12H causes the regulating current I H However, the upper limit of the gate voltage of the transistor 12H is the voltage VCC H Voltage VCC H , based on the values ​​of the current limiting resistor 13H and the gate threshold voltage of the transistor 12H, the regulated current I H An upper limit is also set.

[0038] Intermediate terminal TM M [n-1] and low side terminal TM L In the example EX_A1, since "n=2", the node ND[n-1], the intermediate voltage V MID [n-1], intermediate terminal TM M [n-1] are the node ND[1] and the intermediate voltage V MID [1], Intermediate terminal TM M [1]. Node ND L1 is wiring WR L1 via the intermediate terminal TM M [n-1] and the wiring WR L2 Therefore, the node ND L1 and wiring WR L1 and WR L2 The intermediate voltage V MID [n-1] is added. Node ND L1 is wiring WR L1 and wiring WR L2 Located between Node ND L2 is wiring WR L4 via the low-side terminal TM L and is connected to the wiring WR L3 Therefore, the node NDL2 and wiring WR L3 and WR L4 The voltage at node ND is 0V. L2 is wiring WR L3 and wiring WR L4 Located between.

[0039] The drain of the transistor 12L, the drain of the transistor 116L, and the first end of the voltage dividing resistor 113L are connected to the wiring WR L2 The second terminal of the voltage dividing resistor 113L and the first terminal of the voltage dividing resistor 114L are connected to a node ND L3 The second end of the voltage dividing resistor 114L is connected to the wiring WR L3 The voltage dividing circuit 112L is connected to the intermediate terminal TM M [n-1] and low side terminal TM L Voltage V is the divided voltage between DIVL (low-side voltage divider) to generate voltage V DIVL is equal to the voltage drop across the voltage divider resistor 114L. Therefore, the node ND L3 is the voltage V DIVL is added.

[0040] The source of the transistor 12L is connected to a first end of the current limiting resistor 13L, and the second end of the current limiting resistor 13L is connected to the wiring WR L3 The gate of the transistor 116L is connected to the wiring WR L3 The output terminal of the amplifier 111L is connected to the gate of the transistor 12L. The source of the transistor 116L is connected to the positive power supply terminal of the amplifier 111L, and the negative power supply terminal of the amplifier 111L is connected to the wiring WR L3 As described above, since the transistor 116L is a normally-on JFET, the voltage VCC applied to the source of the transistor 116L is L is wiring WR L3 The non-inverting input terminal of the amplifier 111L is connected to the node ND L3 and hence the voltage V DIVL The amplifier 111L receives the voltage VCC of the positive power supply terminal with the potential of the negative power supply terminal as the reference. LIt operates based on.

[0041] The reference voltage source 115L is wired WR L3 and is connected to the inverting input terminal of the amplifier 111L. The reference voltage source 115L is the voltage VCC L It operates based on the wiring WR L3 Reference voltage V REFL Generates the reference voltage V REFL has a predetermined magnitude (for example, 1 V). The reference voltage source 115L supplies a reference voltage V REFL is supplied to the inverting input terminal of the amplifier 111L.

[0042] Amplifier 111L is Node ND L3 Voltage V at DIVL and the reference voltage V from the reference voltage source 115L REFL The amplifier 111L compares the voltage V DIVL and V REFL The presence or absence and magnitude of the drain current of the transistor 12L are controlled by controlling the gate voltage of the transistor 12L according to the level relationship between the two. L (low-side regulating current).

[0043] The amplifier 111L is "V DIVL <V REFL When the condition "" is satisfied, the wiring WR L3 , which sets transistor 12L off (i.e., blocks transistor 12L). When transistor 12L is off, the regulated current I L is zero. Amplifier 111L is DIVL >V REFL ” is established, the gate voltage of the transistor 12L is increased to set the transistor 12L on (to make the transistor 12L conductive). When the transistor 12L is on, the regulating current I L occurs. DIVL >V REFL When the voltage V DIVL and VREFL As the absolute value of the difference between the two increases, amplifier 111L increases the gate voltage of transistor 12L, and the increase in the gate voltage of transistor 12L causes the regulating current I L However, the upper limit of the gate voltage of the transistor 12L is the voltage VCC L Voltage VCC L , based on the values ​​of the current limiting resistor 13L and the gate threshold voltage of the transistor 12L, the regulated current I L An upper limit is also set.

[0044] Furthermore, node ND H2 From intermediate terminal TM M The current flowing toward [n-1] is a combination of the current consumption Ih1 of the amplifier 111H, which corresponds to the drain current of the transistor 116H, the current Ih2 flowing in the voltage dividing circuit 112H, and the adjustment current I H The sum of and. Intermediate terminal TM M [n-1] to node ND L1 The current flowing toward the amplifier 111L is a consumption current Il1 of the amplifier 111L corresponding to the drain current of the transistor 116L, a current Il2 flowing in the voltage dividing circuit 112L, and an adjustment current I L The controllers 11H and 11L have the same configuration, and the wiring WR H2 and WR H3 potential difference between the wires and WR L2 and WR L3 The potential difference between the two electrodes is completely or approximately equal. Therefore, it can be considered that "Ih1 = Il1" and "Ih2 = Il2". H =I L ", then the node ND[1] and the intermediate terminal TM M [1] The current between them can be considered to be zero.

[0045] Refer to Figure 8. LK [1]=I LK The operation of the voltage regulator 10a in case CS1 where [2]" holds will be described. In FIG. 8, solid line waveforms 611 and 612 respectively represent the input voltage V IN and intermediate voltage V MID [1]. Here, the AC voltage VAC 8 shows the output voltage waveform of the voltage supply circuit 1 when it is assumed that a full-wave rectified voltage of I is output from the voltage supply circuit 1 (see FIG. 1), and that no smoothing is performed by the capacitance device 2. In FIG. 8, waveforms 614 and 615 show the output voltage waveform of the regulated current I in case CS1. H and I L This is the waveform.

[0046] AC voltage V for voltage supply device 1 AC When the supply of input voltage V IN and intermediate voltage V MID [1] starts rising from 0V, and then the AC voltage V AC The input voltage V IN and intermediate voltage V MID [1] fluctuates. LK [1]=I LK In case CS1, where "V[2]" is the voltage applied equally to capacitors C[1] and C[2], C [1]=V C [2]=V IN / 2” holds (ignoring errors). In the circuit system SYS, the input voltage V IN The maximum voltage that can be taken is the input maximum voltage V INMAX When "n=2", the breakdown voltage of each of the capacitors C[1] and C[2] is the voltage (V INMAX / 2). For example, the maximum input voltage V INMAX is 400V, an electrolytic capacitor with a withstand voltage of 250V is used as capacitor C[i].

[0047] “V C [1]=V INMAX / 2” is established, DIVH <V REFH " so that the reference voltage V REFH The resistance ratio between the voltage dividing resistors 113H and 114H is set, and "V C [2]=V INMAX / 2” is established, DIVL <V REFL " so that the reference voltage V REFLand the resistance ratio between the voltage dividing resistors 113L and 114L is set. Therefore, in case CS1, the transistors 12H and 12L are always off, and therefore the regulating current I H and I L is maintained at zero. Then, in case CS1, the node ND[1] and the intermediate terminal TM M [1] The current between them is zero.

[0048] Referring to Figure 9, LK [1]>I LK The operation of the voltage regulator 10a in case CS2 where [2]" holds will be described. In FIG. 9, solid line waveforms 621 and 622 respectively represent the input voltage V IN and intermediate voltage V MID The waveforms of the regulated current I in case CS2 are shown in Fig. 9. The dashed waveform 623 in Fig. 9 is the same as the dashed waveform 613 in Fig. 8. In Fig. 9, waveforms 624 and 625 respectively represent the regulated current I in case CS2. H and I L This is the waveform.

[0049] AC voltage V for voltage supply device 1 AC When the supply of input voltage V IN and intermediate voltage V MID [1] starts rising from 0V, and then the AC voltage V AC The input voltage V IN and intermediate voltage V MID [1] fluctuates. LK [1]>I LK The state in which "V[2]" holds is equivalent to a state in which the internal resistance of capacitor C[1] is lower than the internal resistance of capacitor C[2]. Therefore, in case CS2, due to the characteristics of capacitors C[1] and C[2], "V C [1] <V C [2]” is established. Then, “V C [1] <V INMAX / 2” is true, so “V DIVH <V REFH " holds. As a result, in case CS2, transistor 12H is always off, and therefore the regulating current I H is maintained at zero.

[0050] On the other hand, in case CS2, “V C [2]>V INMAX / 2” occurs. C [2]>V INMAX During the period when " / 2" is established, the input voltage V IN Depending on the instantaneous value of "V DIVL >V REFL " can be established. "V DIVL >V REFL When " is established, the amplifier 111L functions to generate a voltage V DIVL and V REFL The regulating current I has a magnitude according to the difference between L In case CS2, the regulated current I L is from node ND[1] to intermediate terminal TM M In case CS2, the current Il2 is slightly higher than the current Ih2, but the difference between the currents Ih2 and Il2 is so small that it is not DIVL >V REFL The regulating current I L This is significantly lower than the DIVL >V REFL During the period when " is established, the node ND[1] and the intermediate terminal TM M [1] The magnitude of the current flowing between them is the adjusting current I L can be considered to be equal in magnitude to

[0051] “V DIVL >V REFL The regulated current I L is the intermediate terminal TM M [1] to low side terminal TM L Since current flows towards the capacitor C[2], the voltage V C [2] or suppress the increase of the electrode-to-electrode voltage V C [2]. The regulating current I is greater than zero. L By "V DIVL >V REFL " from the established state of "V DIVL <V REFL If the state transitions to "IL =0”, and the adjusted current I L becomes zero again, and "V DIVL >V REFL If " is true, the adjustment current I L This feedback action causes the voltage V across the capacitor C[2] in case CS2. C [2] is the predetermined limit voltage VL LIM The input voltage V IN The instantaneous value of "I L =0” even if “V DIVL <V REFL If we move to a period where "I" holds, L = 0”. Then, in case CS2, the input voltage V IN In conjunction with the up and down movement of L >0” period and “I L =0” periods alternate.

[0052] Clamping voltage VL LIM is "V DIVL =V REFL When " is established, the voltage V between the electrodes of the capacitor C[2] C [2] corresponds to the reference voltage V REFL and the resistance ratio between the voltage dividing resistors 113L and 114L. LIM is lower than the breakdown voltage of capacitor C[2]. For example, if the breakdown voltage of capacitor C[2] is 250V, the clamping voltage VL LIM can be set to 220V. Therefore, a voltage higher than the breakdown voltage will not be applied to capacitor C[2].

[0053] Referring to Figure 10, LK [1] LK The operation of the voltage regulator 10a in case CS3 where [2]" holds will be described. In FIG. 10, solid line waveforms 631 and 632 respectively represent the input voltage V IN and intermediate voltage V MID The waveforms 634 and 635 in Fig. 10 are the same as the waveform 613 in Fig. 8. The waveforms 634 and 635 in Fig. 10 are the same as the waveforms 633 and ...​H and I L This is the waveform.

[0054] AC voltage V for voltage supply device 1 AC When the supply of input voltage V IN and intermediate voltage V MID [1] starts rising from 0V, and then the AC voltage V AC The input voltage V IN and intermediate voltage V MID [1] fluctuates. LK [1] LK The state in which "V[2]" holds is equivalent to a state in which the internal resistance of capacitor C[1] is higher than the internal resistance of capacitor C[2]. Therefore, in case CS3, due to the characteristics of capacitors C[1] and C[2], "V C [1]>V C [2]” is established. Then, “V C [2] <V INMAX / 2” is true, so “V DIVL <V REFL " holds. As a result, in case CS3, transistor 12L is always off, and therefore the regulating current I L is maintained at zero.

[0055] On the other hand, in case CS3, “V C [1]>V INMAX / 2” occurs. C [1]>V INMAX During the period when " / 2" is established, the input voltage V IN Depending on the instantaneous value of "V DIVH >V REFH " can be established. "V DIVH >V REFH When " is established, the amplifier 111H functions to generate a voltage V DIVH and V REFH The regulating current I has a magnitude according to the difference between H In case CS3, the regulated current I H is an intermediate terminal TM M ​In case CS3, the current Ih2 is slightly higher than the current Il2, but the difference between the currents Ih2 and Il2 is small, and the current Ih2 is slightly higher than the current Il2. DIVH >V REFH The regulating current I H This is significantly lower than the DIVH >V REFH During the period when " is established, the intermediate terminal TM M The magnitude of the current flowing between node ND[1] and node ND[1] is the regulated current I H can be considered to be equal in magnitude to

[0056] “V DIVH >V REFH The regulated current I H is the high side terminal TM H From intermediate terminal TM M Since current flows towards [1], the voltage V between the two poles of the capacitor C[1] C [1] or suppress the increase of the inter-electrode voltage V C [1]. The regulating current I is greater than zero. H By "V DIVH >V REFH " from the established state of "V DIVH <V REFH If the state transitions to "I H =0”, and the adjusted current I H becomes zero again, and "V DIVH >V REFH If " is true, the adjustment current I H This feedback action causes the voltage V across the capacitor C[1] in case CS3. C [1] is the predetermined limit voltage VH LIM The input voltage V IN The instantaneous value of "I H =0” even if “V DIVH <V REFH If we move to a period where "I" holds, H = 0”. Then, in case CS3, the input voltage V IN In conjunction with the up and down movement of H>0” period and “I H =0” periods alternate.

[0057] Clamping voltage VH LIM is "V DIVH =V REFH When " is established, the voltage V between the electrodes of the capacitor C[1] C [1] corresponds to the reference voltage V REFH and the resistance ratio between voltage dividing resistors 113H and 114H. LIM is lower than the breakdown voltage of capacitor C[1]. For example, if the breakdown voltage of capacitor C[1] is 250V, the clamping voltage VH LIM can be set to 220V. Therefore, a voltage higher than the breakdown voltage will not be applied to the capacitor C[1].

[0058] For convenience of explanation, the operations in the cases CS1 to CS3 have been described separately. However, the voltage regulation circuit 10a C [1] is the clamping voltage VH LIM The voltage V between the electrodes of the capacitor C[2] is limited to the following: C [2] Limit voltage VL LIM The limit voltage VH is as follows: LIM and clamping voltage VL LIM are primarily assumed to have the same voltage value, but as a variant they may have different voltage values.

[0059] Here is a concrete numerical example. For simplicity, the input voltage V IN is constant at 400V and “V C [1]=V C [2]=V IN / 2". The current consumption (Ih1, Il1) of each of the amplifiers 111H and 111L is about 10 μA. The series resistance values ​​of the voltage dividing resistors 113H and 114H and the voltage dividing resistors 113L and 114L are both 100 MΩ (megohms). Then, the currents Ih2 and Il2 are both 2 μA. Therefore, "I H =I L=0”, the power consumption of the voltage regulator 10a is 0.0048W from “200V×12μA×2=0.0048W”, which is much smaller than the loss of about 0.182W that occurs constantly in the reference configuration of FIG. 6. Here, 0.0048W corresponds to the standby power of the voltage regulator 10a. C [1] and V C [2] becomes uneven and “V DIVH >V REFH " or "V DIVL >V REFL " does not hold, the voltage regulator 10a consumes only a very small amount of standby power.

[0060] Leakage current I LK [i] is at most several hundred μA, so the adjustment current I is about 1 mA (milliampere) to several mA. H and I L The amplifiers 111H and 111L are designed to generate a voltage V, and the values ​​of the current limiting resistors 13H and 13L are determined in advance. Each current limiting resistor (13H, 13L) can be a resistance of, for example, several kΩ (kilo-ohms). It is known that a large amount of leakage current from an electrolytic capacitor occurs immediately after a voltage is applied to the electrolytic capacitor, and that the leakage current decreases significantly and converges after several tens of seconds have passed since the start of voltage application to the electrolytic capacitor. For this reason, the voltage V C [1] and V C Even if [2] is uneven, the adjusting current I H or I L occurs for a very limited time, and the regulating current I H or I L The power consumption due to this is kept significantly lower than that of the reference configuration in FIG.

[0061] Furthermore, by integrating the voltage regulator 10a using semiconductors, the installation area of ​​the voltage regulator 10a (e.g., 5 mm x 5 mm) can be made much smaller than the installation area (e.g., 20 mm x 20 mm) of the four high-voltage resistors (921a, 921b, 922a, 922b).

[0062] The value of the voltage dividing resistor 113H is much larger than the value of the voltage dividing resistor 114H, and the wiring WR H2 and WR H3 Most of the voltage between the resistors 113H and 114H is applied to the resistor 113H. Specifically, for example, the ratio of the value of the resistor 113H to the value of the resistor 114H is set to 199:1 (this ratio is set to the desired clamping voltage VH LIM Similarly, the value of the voltage dividing resistor 113L is much larger than the value of the voltage dividing resistor 114L, and the value of the wiring WR L2 and WR L3 Most of the voltage between the resistors 113L and 114L is applied to the resistor 113L. Specifically, for example, the ratio of the value of the resistor 113L to the value of the resistor 114L is set to 199:1 (this ratio is set to the desired clamping voltage VL LIM (The decision should be made based on the above.)

[0063] <<Example EX_A2>> Example EX_A2 will be described. The voltage regulator 3 of FIG. 1 can be formed using a semiconductor device. FIG. 11 shows a schematic plan view of the semiconductor device SD. The semiconductor device SD is an electronic component comprising a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) CS that houses the semiconductor chip, and a plurality of external terminals exposed to the outside of the semiconductor device SD from the housing CS. The semiconductor device SD is formed by encapsulating the semiconductor chip in a housing CS made of resin. Note that the number of external terminals of the semiconductor device SD and the type of housing CS of the semiconductor device SD shown in FIG. 11 are merely examples and can be designed as desired.

[0064] In the example EX_A2, "n=2" and the voltage regulator 10a shown in FIG. 7 is configured by one semiconductor device SD. The configuration of the voltage regulator 10a according to the example EX_A2 will be described with reference to FIG. 12. The voltage regulator 10a according to the example EX_A2 is one semiconductor device SD itself. The voltage regulator 10a according to the example EX_A2 is configured by a frame FL, which is a metal body separated from each other. H and FL L The first semiconductor chip on which the high-side controller 11H, the transistor 12H, and the current limiting resistor 13H are formed is mounted on a frame FL HThe second semiconductor chip on which the low-side controller 11L, the transistor 12L, and the current limiting resistor 13L are formed is fixed to the frame FL. L Then, the frame FL on which the first semiconductor chip is fixed is H and a frame FL to which the second semiconductor chip is fixed. L A single semiconductor device SD formed by housing all of the above in a single housing CS is used as the voltage regulator 10a.

[0065] Terminal TM H , TM M [1] and TM L is an external terminal in the voltage regulator 10a (an external terminal of the semiconductor device SD). H1 and ND H2 is a pad on the first semiconductor chip, and node ND H1 and high side terminal TM H Between them is wiring WR H1 The node ND is connected by wire bonding using H2 and intermediate terminal TM H [1] Between the wires is WR H4 The node ND is connected by wire bonding using L1 and ND L2 is a pad on the second semiconductor chip, and node ND L1 and intermediate terminal TM H [1] Between the wires is WR L1 The node ND is connected by wire bonding using L2 and low side terminal TM L Between them is wiring WR L4 The connection is made by wire bonding using a

[0066] The embodiment EX_A2 has the advantage that the voltage regulator 10a can be formed with a single electronic component (SD). However, the frame FL H and FL L It is necessary to set up

[0067] <<Example EX_A3>> Example EX_A3 will be described. The voltage regulator 3 of FIG. 1 can be formed using multiple semiconductor devices. FIG. 13 shows a schematic plan view of two semiconductor devices SD1 and SD2. The semiconductor devices SD1 and SD2 are two semiconductor devices with the same configuration. The semiconductor device SD1 is an electronic component including a first semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) CS1 that houses the first semiconductor chip, and multiple external terminals exposed from the housing CS1 to the outside of the semiconductor device SD1. The semiconductor device SD1 is formed by encapsulating the first semiconductor chip in the housing CS1 made of resin. The semiconductor device SD2 is an electronic component including a second semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) CS2 that houses the second semiconductor chip, and multiple external terminals exposed from the housing CS2 to the outside of the semiconductor device SD2. The semiconductor device SD2 is formed by encapsulating the second semiconductor chip in the housing CS2 made of resin. Note that the number of external terminals of each semiconductor device and the type of housing for each semiconductor device shown in FIG. 13 are merely examples and can be designed as desired.

[0068] In the example EX_A3, "n=2" and the voltage regulator 10a shown in Fig. 7 is configured by two semiconductor devices SD1 and SD2. The configuration of the voltage regulator 10a according to the example EX_A3 will be described with reference to Fig. 14. The semiconductor device SD1 is mounted on a frame FL H a first semiconductor chip on which a high-side controller 11H, a transistor 12H, and a current limiting resistor 13H are formed is mounted on a frame FL H The first semiconductor chip is fixed on the frame FL. H The semiconductor device SD2 is housed in a frame FL, which is a metal body. L a second semiconductor chip on which a low-side controller 11L, a transistor 12L, and a current limiting resistor 13L are formed is mounted on a frame FL L The second semiconductor chip is fixed to the frame FL. L The semiconductor device SD2 is formed by housing these components in a housing CS2.

[0069] The semiconductor device SD1 is connected to the node ND H1 As an external terminal connected to the high-side terminal TM H Equipped with Node ND H2 The external terminal TMa is connected to the node ND. H1 and ND H2 is a pad on the first semiconductor chip. Node ND H1 and high side terminal TM H Between them is wiring WR H1 The node ND is connected by wire bonding using H2 and external terminal TMa is wired WR H4 The connection is made by wire bonding using a

[0070] The semiconductor device SD2 is connected to the node ND L2 Low-side terminal TM as an external terminal connected to L Equipped with Node ND L1 The external terminal TMb is connected to the node ND L1 and ND L2 is a pad on the second semiconductor chip. Node ND L2 and low side terminal TM L Between them is wiring WR L4 The node ND is connected by wire bonding using L1 and between external terminal TMb and external terminal TMb is wiring WR L1 The connection is made by wire bonding using a

[0071] In the example EX_A3, the external terminals TMa and TMb are connected to each other through wiring provided outside the semiconductor devices SD1 and SD2, and the external terminals TMa and TMb are connected to the intermediate terminal TM M [1] is formed. The connection node between the external terminals TMa and TMb is the intermediate terminal TM M It can be understood that this corresponds to [1]. In this way, in Example EX_A3, the voltage V C [1] and V C Voltage limiting circuits (11H to 13H and 11L to 13L) that impose a limit on [2] are housed separately in two housings CS1 and CS2.

[0072] Unlike Example EX_A2 (see FIG. 12), Example EX_A3 does not require multiple frames to be installed within a single enclosure, which may be advantageous in terms of manufacturing. Furthermore, it is possible to arrange the semiconductor device SD1 on a printed circuit board in association with the capacitor C[1] and the semiconductor device SD2 on a printed circuit board in association with the capacitor C[2], making the layout design simple and easy. On the other hand, two electronic components (SD1 and SD2) must be installed to form the voltage regulator 10a.

[0073] <<Example EX_A4>> An example EX_A4 will be described. In the examples EX_A1 to EX_A3, it is assumed that "n=2", but as mentioned above, the value of n can be any integer equal to or greater than 2. FIG. 15 shows a schematic configuration of a voltage regulator 10b according to the example EX_A4. The voltage regulator 10b is the voltage regulator 3 according to the example EX_A4 (see FIG. 1). The voltage regulator 10b includes a voltage limiting circuit 20 and a high-side terminal TM H , Intermediate terminal TM M [1]~TM M [n-1] and low side terminal TM L The voltage limiting circuit 20 limits the electrode-to-electrode voltage of each of the capacitors C[1] to C[n] to a predetermined limit voltage or less (i.e., it controls the electrode-to-electrode voltage of each of the capacitors C[1] to C[n] so that the electrode-to-electrode voltage of each of the capacitors C[1] to C[n] is equal to or less than the predetermined limit voltage). The total of n limit voltages corresponding to the capacitors C[1] to C[n] are assumed to be equal to each other. However, as a modification, the total of n limit voltages corresponding to the capacitors C[1] to C[n] may include two or more limit voltages having different voltage values.

[0074] The voltage limiting circuit 20 includes limiting circuits 30, each assigned to a corresponding capacitor C[1] to C[n]. The limiting circuit 30 assigned to capacitor C[i] is specifically referred to as limiting circuit 30[i]. Therefore, the voltage limiting circuit 20 includes limiting circuits 30[1] to 30[n]. Among the limiting circuits 30[1] to 30[n], limiting circuit 30[1] can be specifically referred to as a high-side limiting circuit, and limiting circuit 30[n] can be specifically referred to as a low-side limiting circuit. When "n=2," the voltage regulating device 10b is the same as the voltage regulating device 10a of FIG. 7. When "n=2," the voltage limiting circuit 20 of FIG. 15 is formed by the controllers 11H and 11L, transistors 12H and 12L, and current limiting resistors 13H and 13L shown in FIG. 7. However, in the following example EX_A4, it is considered that "n≧3" holds. Among the limiting circuits 30[1] to 30[n], the limiting circuit 30[i] for an integer i that satisfies "2≦i≦n-1" can be referred to as an intermediate limiting circuit. In the description of the intermediate limiting circuit 30[i], the integer i represents any integer that satisfies "2≦i≦n-1."

[0075] The high-side limiting circuit 30[1] is connected to the high-side terminal TM H and intermediate terminal TM M The high-side limiting circuit 30[1] is connected to the high-side terminal TM. The high-side limiting circuit 30[1] includes a high-side controller 11H, a transistor 12H, and a current-limiting resistor 13H shown in FIG. 7. The configuration and operation of the high-side limiting circuit 30[1] are the same as those of the circuit consisting of the high-side controller 11H, the transistor 12H, and the current-limiting resistor 13H shown in the embodiment EX_A1. Therefore, the high-side limiting circuit 30[1] is connected to the high-side terminal TM. H and intermediate terminal TM M [1] Voltage between (V C [1]) according to the regulated current I H By controlling the presence and size of the high-side terminal TM H and intermediate terminal TM M [1] Voltage between (V C [1]) is applied to a predetermined clamping voltage VH LIM Restrict to the following:

[0076] The low-side limiting circuit 30[n] is connected to the intermediate terminal TM M [n-1] and low side terminal TM L The low-side limiting circuit 30[n] includes a low-side controller 11L, a transistor 12L, and a current-limiting resistor 13L shown in FIG. 7. The configuration and operation of the low-side limiting circuit 30[n] are the same as those of the circuit including the low-side controller 11L, the transistor 12L, and the current-limiting resistor 13L shown in Example EX_A1. Therefore, the low-side limiting circuit 30[n] is connected to the intermediate terminal TM M [n-1] and low side terminal TM L Voltage between (V C [n]) according to the adjusted current I L By controlling the presence and size of the intermediate terminal TM M [n-1] and low side terminal TM L Voltage between (V C [n]) to a predetermined limit voltage VL LIM Restrict to the following:

[0077] Each intermediate limiting circuit is connected to an intermediate terminal TM M [1]~TM M The intermediate terminals TM are connected to two adjacent intermediate terminals among [n-1], and the presence or absence and magnitude of the regulating current between the two intermediate terminals are controlled according to the voltage between the two intermediate terminals, thereby limiting the voltage between the two intermediate terminals to a predetermined limit voltage or less. M [i-1] and TM M [i] (where i is an integer between 2 and (n-1)). Therefore, the intermediate limiting circuit 30[1] has a M [1] and TM M [2] and the intermediate terminal TM M [1] and TM M [2] Voltage between (V C [2]) according to the intermediate terminal TM M [1] and TM M [2] By controlling the presence and magnitude of the regulated current between the intermediate terminal TM M [1] and TM M [2] Voltage between (VC [2]) below a specified limit voltage (the limit voltage VM LIM Similarly, when "n≧4", the intermediate limiting circuit 30[2] limits the voltage at the intermediate terminal TM M [2] and TM M [3] and the intermediate terminal TM M [2] and TM M [3] Voltage between (V C [3]) according to the intermediate terminal TM M [2] and TM M [3] By controlling the presence and magnitude of the regulated current between the intermediate terminal TM M [2] and TM M [3] Voltage between (V C [3]) below a predetermined limit voltage (the limit voltage VM LIM The intermediate limiting circuit 30[i] limits the intermediate terminal TM M [i-1] and TM M [i] and the intermediate terminal TM M [i-1] and TM M Voltage between [i] (V C [i]) according to the intermediate terminal TM M [i-1] and TM M By controlling the presence and magnitude of the regulating current between [i], the intermediate terminal TM M [i-1] and TM M Voltage between [i] (V C [i]) is below a predetermined limit voltage (the limit voltage VM LIM (below).

[0078] When "n≧4," (n−2) intermediate controllers are provided in the voltage regulator 10b, and the configurations and operations of the (n−2) intermediate controllers are the same as each other. Therefore, with reference to FIG. 16, the configuration and operation of one of the intermediate limiting circuits of interest, the intermediate limiting circuit 30[i], will be described in detail. The configuration and operation of the intermediate limiting circuit 30[i] are basically the same as those of the high-side limiting circuit 30[1] or the low-side limiting circuit 30[n].

[0079] The intermediate limiting circuit 30[i] includes an intermediate controller 11M, a transistor (intermediate transistor) 12M, and a current limiting resistor 13M. A node ND M1 ~ND M3 and wiring WR M1 ~WR M4 is provided in the voltage regulator 10b.

[0080] The intermediate controller 11M includes an amplifier 111M which is an operational amplifier, a voltage divider circuit 112M consisting of voltage divider resistors 113M and 114M, a reference voltage source 115M, and a transistor 116M. The transistor 12M is an N-channel MOSFET. The transistor 116M is an N-channel JFET. The transistor 116M is a normally-on JFET. Therefore, even if the gate-source voltage of the transistor 116M is 0V, the drain and source of the transistor 116M are conductive.

[0081] The transistors 12M and 116M and the voltage dividing resistor 113M in the intermediate limiting circuit 30[i] are MID [i-1]-V MID [i]) high-voltage components that can withstand the above conditions are used. M [i-1] and TM M [i] Voltage applied between (V MID [i-1]-V MID [i]) fluctuates within a predetermined intermediate voltage range, but the withstand voltages of the transistors 12M and 116M and the withstand voltage of the voltage dividing resistor 113M are higher than the upper limit voltage (for example, 220V) within the intermediate voltage range.

[0082] Outside the voltage regulator 10b, an intermediate terminal TM M [i-1] is connected to the anode of the capacitor C[i] via the node ND[i-1]. That is, the anode of the capacitor C[i] and the intermediate terminal TM M A node ND[i-1] is located between the voltage regulator 10b and the intermediate terminal TM[i-1]. M[i] is connected to the cathode of the capacitor C[i] via the node ND[i]. That is, the cathode of the capacitor C[i] and the intermediate terminal TM M Node ND[i] is located between node ND[i] and node ND[i].

[0083] In the intermediate limiting circuit 30[i], the node ND M1 is wiring WR M1 via the intermediate terminal TM M [i-1] and the wiring WR M2 Therefore, the node ND corresponding to the intermediate limiting circuit 30[i] is connected to M1 and wiring WR M1 and WR M2 The intermediate voltage V MID [i-1] is added. Node ND M1 is wiring WR M1 and wiring WR M2 In the intermediate limiting circuit 30[i], the node ND M2 is wiring WR M4 via the intermediate terminal TM M [i] and the wiring WR M3 Therefore, the node ND corresponding to the intermediate limiting circuit 30[i] is connected to M2 and wiring WR M3 and WR M4 The intermediate voltage V MID [i] is added. Node ND M2 is wiring WR M3 and wiring WR M4 Located between.

[0084] The drain of the transistor 12M, the drain of the transistor 116M, and the first end of the voltage dividing resistor 113M are connected to the wiring WR M2 The second terminal of the voltage dividing resistor 113M and the first terminal of the voltage dividing resistor 114M are connected to a node ND M3 The second end of the voltage dividing resistor 114M is connected to the wiring WR M3 The voltage divider circuit 112M is connected to the intermediate terminal TM M [i-1] and TM M Voltage V is the divided voltage between [i] DIVM (intermediate voltage) is generated. DIVMis equal to the voltage drop across the voltage divider resistor 114M. Therefore, the node ND M3 The intermediate voltage V MID [i] voltage V DIVM The voltage (V MID [i]+V DIVM ) is added.

[0085] The source of the transistor 12M is connected to a first terminal of a current limiting resistor 13M, and the second terminal of the current limiting resistor 13M is connected to a wiring WR M3 The gate of the transistor 116M is connected to the wiring WR M3 The output terminal of the amplifier 111M is connected to the gate of the transistor 12M. The source of the transistor 116M is connected to the positive power supply terminal of the amplifier 111M, and the negative power supply terminal of the amplifier 111M is connected to the wiring WR M3 As described above, since the transistor 116M is a normally-on JFET, the voltage VCC applied to the source of the transistor 116M is M is wiring WR M3 The non-inverting input terminal of the amplifier 111M is connected to the node ND M3 and therefore the voltage (V MID [i]+V DIVM ) is received. The amplifier 111M receives the voltage VCC of the positive power supply terminal with the potential of the negative power supply terminal as a reference. M It operates based on.

[0086] Reference voltage source 115M is wired WR M3 and is connected to the inverting input terminal of the amplifier 111M. The reference voltage source 115M is the voltage VCC M It operates based on the wiring WR M3 Reference voltage V REFM Generates the reference voltage V REFM has a predetermined magnitude (for example, 1 V). The reference voltage source 115M supplies an intermediate voltage V MID [i] Reference voltage V REFM The voltage (V MID [i]+V REFM ) is supplied to the inverting input terminal of amplifier 111M.

[0087] Amplifier 111M is Node ND M3 Voltage at (V MID [i]+V DIVM ) and the voltage from the reference voltage source 115M (V MID [i]+V REFM ) and applies the amplified difference signal to the gate of transistor 12M. This comparison is performed by voltage V DIVM and V REFM The amplifier 111M is equivalent to a comparison between voltage V DIVM and V REFM The presence or absence and magnitude of the drain current of the transistor 12M are controlled by controlling the gate voltage of the transistor 12M according to the level relationship between the two. M It is called.

[0088] The amplifier 111M is "V DIVM <V REFM When the condition "A" is satisfied, the wiring WR M3 , which sets transistor 12M off (i.e., blocks transistor 12M). When transistor 12M is off, the regulated current I M is zero. The amplifier 111M is DIVM >V REFM ” is established, the gate voltage of the transistor 12M is increased to set the transistor 12M on (to make the transistor 12M conductive). When the transistor 12M is on, the regulating current I M occurs. DIVM >V REFM When the voltage V DIVM and V REFM As the absolute value of the difference between the input and output voltages increases, amplifier 111M increases the gate voltage of transistor 12M, and the increase in the gate voltage of transistor 12M causes the regulation current I M However, the upper limit of the gate voltage of the transistor 12M is the voltage VCC M Voltage VCC M , based on the values ​​of the current limiting resistor 13M and the gate threshold voltage of the transistor 12M, the regulated current IM An upper limit is also set.

[0089] Furthermore, node ND M2 From intermediate terminal TM M The current flowing toward [i] is a combination of the consumption current Im1 of the amplifier 111M, which corresponds to the drain current of the transistor 116M, the current Im2 flowing in the voltage divider circuit 112M, and the adjustment current I M The controllers 11H, 11M, and 11L have the same configuration, and the wiring WR H2 and WR H3 potential difference between the wires and WR M2 and WR M3 potential difference between the wires and WR L2 and WR L3 The potential differences between the electrodes are completely or approximately equal. Therefore, it can be considered that "Ih1 = Im1 = Il1" and "Ih2 = Im2 = Il2".

[0090] The input voltage V IN Depending on the instantaneous value of "V DIVM >V REFM " can be established. "V DIVM >V REFM " is established, the amplifier 111M functions to generate a voltage V DIVM and V REFM The regulating current I has a magnitude according to the difference between M occurs. DIVM >V REFM The regulated current I M is an intermediate terminal TM M [i-1] to intermediate terminal TM M [i], the voltage V between the two electrodes of the capacitor C[i] C Suppress the increase of [i] or the inter-electrode voltage V C This reduces the regulating current I M By "V DIVM >V REFM " from the established state of "V DIVM <V REFM If the state transitions to "I M =0”, and the adjusted current I Mbecomes zero again, and "V DIVM >V REFM If " is true, the adjustment current I M This feedback action generates the voltage V between the electrodes of the capacitor C[i]. C [i] is the predetermined limit voltage VM LIM It is limited to the following:

[0091] The intermediate limiting circuit 30[i] limits the voltage VM LIM is "V DIVM =V REFM When " is established, the voltage V between the electrodes of the capacitor C[i] C [i] corresponds to the reference voltage V REFM and the resistance ratio between voltage dividing resistors 113M and 114M. LIM is lower than the breakdown voltage of the capacitor C[i]. For example, if the breakdown voltage of the capacitor C[i] is 250V, the clamping voltage VM LIM may be set to 220 V. Therefore, a voltage higher than the withstand voltage is never applied to the capacitor C[i].

[0092] As shown in the embodiment EX_A2, the voltage regulator 10b of Fig. 15 may be configured by one semiconductor device SD. In this case, the entire voltage limiting circuit 20 is housed in one housing CS. In this case, the terminal TM H , TM M [1]~TM M [n-1] and TM L are external terminals in the voltage regulator 10b (external terminals of the semiconductor device SD).

[0093] Alternatively, as shown in Example EX_A3, the voltage regulator 10b in FIG. 15 may be configured with a plurality of semiconductor devices SD, typically with n semiconductor devices SD. When configuring the voltage regulator 10b with n semiconductor devices SD, limiting circuits 30[1] to 30[n] may be provided in the first to nth semiconductor devices SD, respectively, and these may be connected in the connection manner shown in FIG. 15. In this case, the limiting circuits 30[1] to 30[n] are housed in the first to nth housings CS of the first to nth semiconductor devices SD, respectively. In other words, the voltage limiting circuits 20 are housed in the first to nth housings CS of the first to nth semiconductor devices SD in a distributed manner. The first semiconductor device SD has a high-side terminal TM H When "n=3", the second external terminal provided on the first semiconductor device SD and the first external terminal provided on the second semiconductor device SD are connected to each other to form an intermediate terminal TM M [1], and the second external terminal provided on the second semiconductor device SD and the first external terminal provided on the third semiconductor device SD are connected to each other to form an intermediate terminal TM M [2], and the second external terminal provided on the third semiconductor device SD functions as the low-side terminal TM M The same applies when "n≧4".

[0094] <<Example EX_A5>> An example EX_A5 will be described. Each limiting circuit 30 shown in FIG. 15 is provided with a current limiting resistor (13H, 13M, or 13L). The provision of the current limiting resistor prevents excessive current from flowing through the voltage limiting circuit 20, thereby protecting the voltage regulator 10b. For example, in the case of the voltage regulator 10a (see FIG. 7) corresponding to the voltage regulator 10b when "n=2", if an abnormality occurs such as a short circuit between both ends of the capacitor C[1], if the current limiting resistor 13L was not provided, an excessive regulated current I L However, by installing a current limiting resistor 13L, the adjusted current I L Therefore, the voltage regulator 10a is protected.

[0095] Each voltage adjusting resistor may be an external resistor provided outside the semiconductor device SD. That is, for example, in the embodiment EX_A2 corresponding to Figures 11 and 12, the current limiting resistors 13H and 13L may be provided outside the semiconductor device SD, and in the embodiment EX_A3 corresponding to Figures 13 and 14, the current limiting resistors 13H and 13L may be provided outside the semiconductor devices SD1 and SD2. Similarly, in the embodiment EX_A4 corresponding to Figures 15 and 16, the current limiting resistors 13H, 13M, and 13L may be provided outside one or more semiconductor devices SD forming the voltage adjusting device 20.

[0096] <<Example EX_A6>> An example EX_A6 will be described. Electrolytic capacitors with various breakdown voltages can be used as the capacitors C[1] to C[n]. An appropriate clamping voltage (VH LIM , VM LIM , V.L. LIM In order to make it possible to arbitrarily set each limit voltage (VH LIM , VM LIM , V.L. LIM ) can be set and adjusted arbitrarily, and the clamping voltage VH LIM , VM LIM and VL LIM can also be different from each other.

[0097] That is, for example, in the embodiment EX_A2 corresponding to Figures 11 and 12, the voltage dividing resistors 113H, 114H, 113L, and 114L may be provided outside the semiconductor device SD, and in the embodiment EX_A3 corresponding to Figures 13 and 14, the voltage dividing resistors 113H, 114H, 113L, and 114L may be provided outside the semiconductor devices SD1 and SD2. Similarly, in the embodiment EX_A4 corresponding to Figures 15 and 16, the voltage dividing resistors 113H, 114H, 113M, 114M, 113L, and 114L may be provided outside one or more semiconductor devices SD that form the voltage regulator 20.

[0098] If the voltage-dividing resistor 113H is an external resistor to the semiconductor device SD, an expensive resistor with a high breakdown voltage is required for the voltage-dividing resistor 113H. Taking this into consideration, of the voltage-dividing resistors 113H and 114H, the voltage-dividing resistor 113H may be built into the semiconductor device SD, and only the voltage-dividing resistor 114H may be provided externally to the semiconductor device SD. The same applies to the other voltage-dividing resistors. For example, in the embodiment EX_A2 corresponding to FIGS. 11 and 12, the voltage-dividing resistors 113H and 113L may be built into the semiconductor device SD, while the voltage-dividing resistors 114H and 114L may be provided externally to the semiconductor device SD. Alternatively, in the embodiment EX_A2 corresponding to FIGS. 13 and 14, the voltage-dividing resistors 113H and 113L may be built into the semiconductor device SD1 and SD2, respectively, while the voltage-dividing resistors 114H and 114L may be provided externally to the semiconductor devices SD1 and SD2. Similarly, in embodiment EX_A4 corresponding to Figures 15 and 16, voltage dividing resistors 113H, 113M, and 113L may be built into one or more semiconductor devices SD that form voltage adjusting device 20, while voltage dividing resistors 114H, 114M, and 114L may be provided outside one or more semiconductor devices SD that form voltage adjusting device 20.

[0099] <<Example EX_B1>> An example EX_B1 will be described. In the example EX_B1, "n=2." Fig. 17 shows a circuit diagram of a voltage regulator 20a which is the voltage regulator 3 in the example EX_B1.

[0100] The voltage regulator 20a is connected to the high-side terminal TM H , Low side terminal TM L and intermediate terminal TM M In addition to [1], a voltage leveling circuit 210a is provided. The voltage leveling circuit 210a includes an amplifier 211, which is an operational amplifier, and a voltage dividing circuit 212. The voltage dividing circuit 212 includes voltage dividing resistors 213 and 214. Note that a node ND H , N.D. M and ND L The voltage regulator 20a can be configured by a semiconductor device SD (see FIG. 11). H , TML and TM M [1] is provided as an external terminal on the semiconductor device SD, and the semiconductor chip on which the voltage leveling circuit 210a is integrated is housed in a housing CS. H , N.D. M and ND L is a pad on a semiconductor chip.

[0101] Outside the voltage regulator 20a, the high-side terminal TM H is wiring WR IN Connected to the low-side terminal TM L is wiring WR GND At the outside of the voltage regulator 20a, an intermediate terminal TM M [1] is connected to the cathode of the capacitor C[1] and the anode of the capacitor C[2] via the node ND[1]. That is, the cathode of the capacitor C[1] and the anode of the capacitor C[2] and the intermediate terminal TM M Node ND[1] is located between [1] and [2].

[0102] Node ND H is the high side terminal TM H connected to node ND L is the low side terminal TM L connected to node ND M is an intermediate terminal TM M The first end of the voltage dividing resistor 213 is connected to the node ND H The second end of the voltage dividing resistor 213 is connected to a first end of the voltage dividing resistor 214 at a node 215. The second end of the voltage dividing resistor 214 is connected to a node ND L The voltage divider circuit 212 is connected to the high-side terminal TM H and low side terminal TM L Voltage V is the divided voltage between DIV215 Generates a voltage V DIV215 is equal to the voltage drop across the voltage divider resistor 214. Therefore, the voltage V DIV215 is added.

[0103] The non-inverting input terminal of amplifier 211 is connected to node 215 and supplies voltage V DIV215The inverting input terminal and the output terminal of the amplifier 211 are connected to the node ND M is connected to, and therefore to node ND M and intermediate terminal TM M [1] is connected to node ND[1]. Therefore, the voltages at the inverting input terminal and the output terminal of amplifier 211 are the intermediate voltage V MID [1]

[0104] The positive and negative power supply terminals of the amplifier 211 are connected to the nodes ND H and ND L The amplifier 211 is connected to the negative power supply terminal (therefore, the ground potential) as a reference to the voltage at the positive power supply terminal (therefore, the input voltage V IN ) as the amplifier 211. INMAX (See Figure 8) A high-voltage amplifier with a larger breakdown voltage is used.

[0105] The resistance ratio of the voltage dividing resistors 213 and 214 is 1:1. That is, the value of the voltage dividing resistor 213 and the value of the voltage dividing resistor 214 are equal (ignoring errors). Therefore, if errors are ignored, DIV215 =V IN / 2" holds.

[0106] “V DIV215 >V MID When [1]" is established, the amplifier 211 outputs a signal from its output terminal to the intermediate terminal TM M [1] outputs a current (positive charge) to node ND[1], and the output of this current is an intermediate voltage V MID [1] Increase the intermediate voltage V MID The increase in [1] is the voltage V C [1] Decrease in voltage V C [2] leads to an increase in “V DIV215 >V MID [1]” when the intermediate voltage V MID The rise in [1] is due to the voltage (V IN / 2) and the intermediate voltage V MID [1] subtract the difference, i.e., voltage V C [1] and V C [2] Reduce the difference between

[0107] On the other hand, “V DIV215 <V MID When the signal [1]" is established, the amplifier 211 outputs a signal from the node ND[1] to the intermediate terminal TM M [1] draws current (positive charge) towards its own output terminal, and the current draw is an intermediate voltage V MID [1] Lower the intermediate voltage V MID The drop in [1] is the voltage V C [1] Increase in voltage V C [2] leads to a decrease in “V DIV215 <V MID [1]” when the intermediate voltage V MID The drop in [1] is the voltage (V IN / 2) and the intermediate voltage V MID [1] subtract the difference, i.e., voltage V C [1] and V C [2] Reduce the difference between

[0108] In this way, the amplifier 211 generates a first comparison voltage, V DIV215 (i.e., voltage (V IN / 2)) and the second comparison voltage, the intermediate voltage V MID [1], and a current according to the comparison result is supplied to the node ND[1] and the intermediate terminal TM M [1] By generating a voltage V C [1] and V C [2] subtract the difference between the voltage V C [1] and V C [2] (Keep the difference between voltages to zero.) For any difference between voltages, subtracting the difference means reducing the difference so that it equals or approaches zero.

[0109] According to the voltage regulator 20a, even when there is a difference in leakage current between the capacitors C[1] and C[2], the voltage V C [1] and V C This prevents the capacitors C[1] and C[2] from exceeding their voltage tolerance due to the difference in leakage current. For example, the maximum input voltage V INMAXis 400V, an electrolytic capacitor with a withstand voltage of 250V can be used as capacitor C[i], and the voltage regulator 20a will keep the voltage between the electrodes of each capacitor below 200V. In addition, since voltage is applied equally to capacitors C[1] and C[2], the voltage dependence of the capacitance value will be the same for both capacitors C[1] and C[2].

[0110] <<Example EX_B2>> An example EX_B2 will be described. In the example EX_B2, "n=3." Fig. 18 shows a circuit diagram of a voltage regulator 20b which is the voltage regulator 3 in the example EX_B2.

[0111] The voltage regulator 20b is connected to the high-side terminal TM H , Low side terminal TM L and intermediate terminal TM M [1] and TM M In addition to [2], a voltage leveling circuit 210b is provided. The voltage leveling circuit 210b includes amplifiers 221 and 231, which are operational amplifiers, and voltage dividing circuits 222 and 232. The voltage dividing circuit 222 includes voltage dividing resistors 223 and 224. The voltage dividing circuit 232 includes voltage dividing resistors 233 and 234. Note that a node ND H , N.D. M1 , N.D. M2 and ND L The voltage regulator 20b can be configured by a semiconductor device SD (see FIG. 11). H , TM L , TM M [1] and TM M [2] is provided as an external terminal on the semiconductor device SD, and the semiconductor chip on which the voltage leveling circuit 210b is integrated is housed in a housing CS. H , N.D. M1 , N.D. M2 and ND L is a pad on a semiconductor chip.

[0112] Outside the voltage regulator 20b, the high-side terminal TM H is wiring WR INConnected to the low-side terminal TM L is wiring WR GND At the outside of the voltage regulator 20b, an intermediate terminal TM M [1] is connected to the cathode of the capacitor C[1] and the anode of the capacitor C[2] via the node ND[1]. That is, the cathode of the capacitor C[1] and the anode of the capacitor C[2] and the intermediate terminal TM M A node ND[1] is located between the voltage regulator 20b and the intermediate terminal TM[1]. M [2] is connected to the cathode of the capacitor C[2] and the anode of the capacitor C[3] via the node ND[2]. That is, the cathode of the capacitor C[2] and the anode of the capacitor C[3] and the intermediate terminal TM M Node ND[2] is located between [2] and Node ND H is the high side terminal TM H connected to node ND L is the low side terminal TM L connected to node ND M1 , N.D. M2 are the intermediate terminals TM, respectively. M [1], TM M [2] is connected.

[0113] The first end of the voltage dividing resistor 223 is connected to the node ND H The second end of the voltage dividing resistor 223 is connected to a first end of the voltage dividing resistor 224 at a node 225. The second end of the voltage dividing resistor 224 is connected to a node ND L The voltage divider circuit 222 is connected to the high-side terminal TM H and low side terminal TM L Voltage V is the divided voltage between DIV225 Generates a voltage V DIV225 is equal to the voltage drop across the voltage divider resistor 224. Therefore, the voltage V DIV225 is added.

[0114] The non-inverting input terminal of amplifier 221 is connected to node 225 and supplies voltage V DIV225 The inverting input terminal and the output terminal of the amplifier 221 are connected to the node ND M1 is connected to, and therefore to node ND M1and intermediate terminal TM M [1] is connected to node ND[1]. Therefore, the voltages at the inverting input terminal and the output terminal of amplifier 221 are the intermediate voltage V MID The positive and negative power supply terminals of the amplifier 221 are connected to the nodes ND H and ND L The amplifier 221 is connected to the negative power supply terminal (therefore, the ground potential) as a reference and outputs the voltage at the positive power supply terminal (therefore, the input voltage V IN ) as the amplifier 221. INMAX (See Figure 8) A high-voltage amplifier with a larger breakdown voltage is used.

[0115] The resistance value ratio of the voltage dividing resistors 223 and 224 is set so that the resistance value R223 of the voltage dividing resistor 223 and the resistance value R224 of the voltage dividing resistor 224 are "R223:R224=1:2". DIV225 =2 V IN / 3” is established.

[0116] “V DIV225 >V MID When [1]" is established, the amplifier 221 outputs a signal from its output terminal to the intermediate terminal TM M [1] outputs a current (positive charge) to node ND[1], and the output of this current is an intermediate voltage V MID [1] Increase the intermediate voltage V MID The increase in [1] is the voltage V C [1] Decrease in voltage V C [2] and V C [3] leads to an increase in “V DIV225 >V MID [1]” when the intermediate voltage V MID The increase in [1] is due to the voltage (2 V IN / 3) and the intermediate voltage V MID [1] Subtract the difference. DIV225 <V MID When the signal [1]" is established, the amplifier 221 outputs a signal from the node ND[1] to the intermediate terminal TM M[1] draws current (positive charge) towards its own output terminal, and the current draw is an intermediate voltage V MID [1] Lower the intermediate voltage V MID The drop in [1] is the voltage V C [1] Increase in voltage V C [2] and V C [3] leads to a decrease in “V DIV225 <V MID [1]” when the intermediate voltage V MID The drop in [1] is due to the voltage (2 V IN / 3) and the intermediate voltage V MID [1]. In this way, the amplifier 221 subtracts the difference between the first comparison voltage, voltage V DIV225 (i.e., voltage (2 V IN / 3)) and the second comparison voltage, the intermediate voltage V MID [1], and a current according to the comparison result is supplied to the node ND[1] and the intermediate terminal TM M [1] By generating a voltage (2 V IN / 3) and the intermediate voltage V MID [1] Subtract the difference (ideally keep the difference at zero).

[0117] The first end of the voltage dividing resistor 233 is connected to the node ND H The second end of the voltage dividing resistor 233 is connected to a first end of the voltage dividing resistor 234 at a node 235. The second end of the voltage dividing resistor 234 is connected to a node ND L The voltage divider circuit 232 is connected to the high-side terminal TM H and low side terminal TM L Voltage V is the divided voltage between DIV235 Generates a voltage V DIV235 is equal to the voltage drop across the voltage divider resistor 234. Therefore, the voltage V DIV235 is added.

[0118] The non-inverting input terminal of amplifier 231 is connected to node 235 and supplies voltage V DIV235 The inverting input terminal and the output terminal of the amplifier 231 are connected to the node ND M2 is connected to, and therefore to node ND M2 and intermediate terminal TM M[2] is connected to node ND[2]. Therefore, the voltages at the inverting input terminal and the output terminal of amplifier 231 are the intermediate voltage V MID The positive and negative power supply terminals of the amplifier 231 are connected to the nodes ND H and ND L The amplifier 231 is connected to the negative power supply terminal (therefore, the ground potential) as a reference and calculates the voltage at the positive power supply terminal (therefore, the input voltage V IN ) as the amplifier 231. INMAX (See Figure 8) A high-voltage amplifier with a larger breakdown voltage is used.

[0119] The resistance value ratio of the voltage dividing resistors 233 and 234 is set so that the resistance value R233 of the voltage dividing resistor 233 and the resistance value R234 of the voltage dividing resistor 234 are "R233:R234=2:1". DIV235 =V IN / 3” is established.

[0120] “V DIV235 >V MID When [2]” is established, the amplifier 231 outputs a signal from its output terminal to the intermediate terminal TM M [2] outputs a current (positive charge) to node ND[2], and the output of this current is an intermediate voltage V MID [2] Increase the intermediate voltage V MID [2] rises in voltage V C [1] and V C [2] Decrease in voltage V C [3] leads to an increase in “V DIV235 >V MID [2]” when the intermediate voltage V MID The increase in [2] is due to the voltage (V IN / 3) and the intermediate voltage V MID [2] Subtract the difference. DIV235 <V MID When the signal [2]” is established, the amplifier 231 connects the node ND[2] to the intermediate terminal TM M [2] draws current (positive charge) towards its own output terminal, and the current draw is an intermediate voltage V MID[2] Lower the intermediate voltage V MID The drop in [2] is the voltage V C [1] and V C [2] Increase in voltage V C [3] leads to a decrease in “V DIV235 <V MID [2]” when the intermediate voltage V MID The drop in [2] is the voltage (V IN / 3) and the intermediate voltage V MID [2]. In this way, the amplifier 231 subtracts the difference between the first comparison voltage, voltage V DIV235 (i.e., voltage (V IN / 3)) and the second comparison voltage, the intermediate voltage V MID [2], and a current according to the comparison result is supplied to the node ND[2] and the intermediate terminal TM M [2] By generating a voltage (V IN / 3) and the intermediate voltage V MID [2] Subtract the difference (ideally keep the difference at zero).

[0121] Amplifier 221 detects the voltage (2 V IN / 3) and the intermediate voltage V MID The difference with [1] is subtracted, and the voltage (V IN / 3) and the intermediate voltage V MID [2] is subtracted, so the voltage V C [1] and voltage V C [2] and voltage V C [3] is subtracted, and ideally the voltage V C [1]~V C [3] are all equal. According to the voltage regulator 20b, even if there is a difference in leakage current between the capacitors C[1] to C[3], the voltage V C [1]~V C [3] is controlled to be equal. This prevents the capacitors C[1] to C[3] from exceeding their withstand voltage due to differences in leakage current. Also, since voltage is applied equally to capacitors C[1] to C[3], the voltage dependence of the capacitance value is the same for all capacitors C[1] to C[3].

[0122] <<Example EX_B3>> An example EX_B3 will be described. The techniques shown in examples EX_B1 and EX_B2 can also be applied to the voltage regulator 3 when "n≧4". Fig. 19 shows the configuration of a voltage regulator 20c, which is the voltage regulator 3 in example EX_B4. When "n=2", the voltage regulator 20c is the same as the voltage regulator 20a in Fig. 17, and when "n=3", the voltage regulator 20c is the same as the voltage regulator 20b in Fig. 18.

[0123] The voltage regulator 20c is connected to the high-side terminal TM H , Low side terminal TM L and intermediate terminal TM M [1]~TM M In addition to [n-1], a voltage leveling circuit 210c is provided. The voltage adjustment device 20c can be configured by a semiconductor device SD (see FIG. 11). In this case, the terminal TM H , TM L , TM M [1]~TM M [n-1] is provided as an external terminal on the semiconductor device SD, and a semiconductor chip on which the voltage leveling circuit 210c is integrated is housed in a housing CS. The voltage leveling circuit 210b includes amplifiers AMP[1] to AMP[n-1], which are operational amplifiers, and voltage dividing circuits DIV[1] to DIV[n-1]. In the following description of the embodiment EX_B3, "i" represents any natural number equal to or less than (n-1) unless otherwise specified.

[0124] Outside the voltage regulator 20c, the high-side terminal TM H is wiring WR IN Connected to the low-side terminal TM L is wiring WR GND At the outside of the voltage regulator 20c, the intermediate terminal TM M [i] is connected to the cathode of the capacitor C[i] and the anode of the capacitor C[i+1] via the node ND[i]. That is, the cathode of the capacitor C[i] and the anode of the capacitor C[i+1] are connected to the intermediate terminal TM M Node ND[i] is located between node ND[i] and node ND[i].

[0125] The voltage divider circuit DIV[i] is connected to the terminal TM H and TM L connected to terminal TM H and TM L Voltage V is the divided voltage between DIV Therefore, the voltage V is generated by the voltage divider circuits DIV[1] to DIV[n-1]. DIV [1]~V DIV [n-1] is generated.

[0126] The voltage V from the voltage divider DIV[i] to the non-inverting input terminal of the amplifier AMP[i] DIV The inverting input terminal and output terminal of the amplifier AMP[i] are connected to the intermediate terminal TM M [i] and the intermediate terminal TM M [i] is connected to node ND[i]. Therefore, the voltages at the inverting input terminal and output terminal of amplifier AMP[i] are the intermediate voltage V MID The positive and negative power supply terminals of the amplifier AMP[i] are terminals TM H and TM L The amplifier AMP[i] is connected to the negative power supply terminal (therefore the ground potential) and the positive power supply terminal voltage (therefore the input voltage V IN ) is used as the input voltage for the amplifier AMP[i]. INMAX (See Figure 8) A high-voltage amplifier with a larger breakdown voltage is used.

[0127] “V DIV [i]=V IN The voltage divider circuit DIV[i] is formed so that (ni) / n" holds. In other words, the first comparison voltage in the amplifier AMP[i] is L High side terminal TM as seen from the potential of H Voltage (V IN ) and “(ni) / n”. The second comparison voltage in the amplifier AMP[i] is the intermediate voltage V MID [i] (low side terminal TM L The intermediate terminal TM seen from the potential of M [i] is the voltage).

[0128] “V DIV [i]>V MID When [i]” is established, the amplifier AMP[i] connects its output terminal to the intermediate terminal TM M [i] to node ND[i], and the output of this current (positive charge) is the intermediate voltage V MID Increase [i]. Intermediate voltage V MID The increase in [i] is the voltage V C [1]~V C Decrease in [i] and voltage V C [i+1]~V C This leads to an increase in [n]. DIV [i]>V MID [i]” holds true when the intermediate voltage V MID The increase in [i] is due to the voltage V DIV [i] and the intermediate voltage V MID Subtract the difference with [i]. DIV [i] <V MID When [i]” is established, the amplifier AMP[i] connects the node ND[i] to the intermediate terminal TM M [i] draws current (positive charge) towards its own output terminal, and the current draw is an intermediate voltage V MID Decrease [i]. Intermediate voltage V MID The drop in [i] is the voltage V C [1]~V C Increasing [i] and voltage V C [i+1]~V C This results in a decrease in [n]. DIV [i] <V MID [i]” holds true when the intermediate voltage V MID The drop in [i] is the voltage V DIV [i] and the intermediate voltage V MID [i]. In this way, the amplifier AMP[i] subtracts the difference between the first comparison voltage, voltage V DIV [i] (i.e., voltage V IN (n i) / n) and the second contrast voltage, the intermediate voltage V MID [i], and a current according to the comparison result is supplied to the node ND[i] and the intermediate terminal TM M By generating a voltage V between [i] DIV [i] and the intermediate voltage V MIDSubtract the difference with [i] (ideally keeping the difference at zero).

[0129] The amplifiers AMP[1] to AMP[n-1] generate a voltage V for each integer i that satisfies "1≦i≦n-1". DIV [i] and V MID The difference between [i] is subtracted, which reduces the voltage V C [1]~V C The difference between [n] is reduced. Ideally, the voltage V C [1]~V C [n] are all equal. According to the voltage regulator 20c, even if there is a difference in the leakage current between the capacitors C[1] to C[n], the voltage V C [1]~V C Control is performed to equalize the capacitance values ​​of capacitors C[1] to C[n]. This prevents capacitors C[1] to C[n] from exceeding their withstand voltage due to differences in leakage current. In addition, since voltage is applied equally to capacitors C[1] to C[n], the voltage dependence of the capacitance value is the same for all capacitors C[1] to C[n].

[0130] <<Example EX_C>> Example EX_C will be described.

[0131] The channel types of the FETs (field effect transistors) shown in the above embodiments are merely examples, and the channel type of any FET may be changed between P-channel and N-channel types without departing from the spirit of the above.

[0132] Any of the transistors described above may be any type of transistor, provided that no disadvantages arise. For example, any of the transistors described above as MOSFETs may be replaced with junction field effect transistors (FETs), insulated gate bipolar transistors (IGBTs), or bipolar transistors, provided that no disadvantages arise. Any of the transistors has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate. In a bipolar transistor that is not an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.

[0133] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0134] <<Additional Notes>> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0135] A voltage regulator according to one aspect of the present disclosure (see FIGS. 1, 4, 7, 15, etc.) includes a ground wiring (WR GND ) and an input voltage (V IN ) is added to the input voltage wiring (WR IN ) and a voltage regulator (3, 10a, 10b) connected to a series circuit of a plurality of electrolytic capacitors (C[1] to C[n]) provided between the input voltage wiring and the high-side terminal (TM H ) and the low-side terminal (TM L) and an intermediate terminal (TM) connected to a connection node between the plurality of electrolytic capacitors. M [i]), and a high-side regulating current (I H ) to regulate the voltage between the high-side terminal and the intermediate terminal to the high-side clamp voltage (VH LIM ) or less, and a low-side regulating current (I L ) to regulate the voltage between the intermediate terminal and the low-side terminal to the low-side clamping voltage (VL LIM and a voltage limiting circuit (20) configured to limit the voltage to or below 100 V (first configuration).

[0136] When multiple electrolytic capacitors are connected in series, there is a concern that an excessive voltage may be applied to a specific electrolytic capacitor due to differences in leakage current among the multiple electrolytic capacitors, etc. By using the voltage regulator device of the first configuration, it is possible to limit the voltage applied to the electrolytic capacitors to a desired limit voltage or less despite variations in leakage current, etc., and therefore it is possible to operate a system including each electrolytic capacitor safely.

[0137] In the voltage regulator device according to the first configuration, the voltage limiting circuit may be configured (second configuration) to include: a high-side transistor (12H) inserted between the high-side terminal and the intermediate terminal; a high-side controller (11H) configured to control the presence or absence and magnitude of the high-side regulating current by controlling the gate voltage of the high-side transistor in accordance with the voltage between the high-side terminal and the intermediate terminal, thereby limiting the voltage between the high-side terminal and the intermediate terminal to equal to or lower than the high-side limiting voltage; and a low-side transistor (12L) inserted between the intermediate terminal and the low-side terminal; and a low-side controller (11L) configured to control the presence or absence and magnitude of the low-side regulating current by controlling the gate voltage of the low-side transistor in accordance with the voltage between the intermediate terminal and the low-side terminal, thereby limiting the voltage between the intermediate terminal and the low-side terminal to equal to or lower than the low-side limiting voltage.

[0138] In the voltage regulator according to the second configuration, the high-side controller controls a high-side divided voltage (V DIVH ), and a high-side voltage divider circuit (112H) configured to generate a high-side reference voltage (V REFH and a high-side amplifier (111H) configured to control the presence and magnitude of the high-side adjustment current by controlling the gate voltage of the high-side transistor according to the high-level relationship between the intermediate terminal and the low-side terminal, and the low-side controller controls a low-side divided voltage (V DIVL ), and a low-side voltage dividing circuit (112L) configured to generate a low-side reference voltage (V REFL and a low-side amplifier (111L) configured to control the presence or absence and magnitude of the low-side adjustment current by controlling the gate voltage of the low-side transistor in accordance with the level relationship between the low-side adjustment current and the gate voltage of the low-side transistor (111L).

[0139] In the voltage regulator device according to the third configuration, the high-side amplifier may be configured so that when the high-side divided voltage is lower than the high-side reference voltage, the high-side transistor is turned off, and when the high-side divided voltage is higher than the high-side reference voltage, the high-side regulating current is generated by turning on the high-side transistor, thereby limiting the voltage between the high-side terminal and the intermediate terminal to equal to or lower than the high-side limit voltage; and the low-side amplifier is configured so that when the low-side divided voltage is lower than the low-side reference voltage, the low-side transistor is turned off, and when the low-side divided voltage is higher than the low-side reference voltage, the low-side regulating current is generated by turning on the low-side transistor, thereby limiting the voltage between the intermediate terminal and the low-side terminal to equal to or lower than the low-side limit voltage (fourth configuration).

[0140] In the voltage regulator according to any one of the second to fourth configurations, a current limiting resistor (13H) may be connected in series to the high-side transistor, and another current limiting resistor (13L) may be connected in series to the low-side transistor (fifth configuration).

[0141] This prevents the high-side regulating current or the low-side regulating current from becoming excessive, thereby protecting the voltage regulator.

[0142] In the voltage adjustment device according to the first to fifth configurations, the plurality of electrolytic capacitors may be a first electrolytic capacitor (C[1]) and a second electrolytic capacitor (C[2]) connected in series with each other, the anode of the first electrolytic capacitor is connected to the input voltage wiring, the cathode of the second electrolytic capacitor is connected to the ground wiring, and a connection node (ND[1]) between the cathode of the first electrolytic capacitor and the anode of the second electrolytic capacitor is connected to the intermediate terminal (TM[1]) (sixth configuration).

[0143] In the voltage regulator according to any one of the first to fifth configurations, the plurality of electrolytic capacitors are first to n-th electrolytic capacitors (C[1] to C[n]) connected in series with each other, the intermediate terminals include first to (n-1)-th intermediate terminals (ND[1] to ND[n-1]), where n represents an integer of 3 or more, the anode of the first electrolytic capacitor is connected to the input voltage wiring, the cathode of the n-th electrolytic capacitor is connected to the ground wiring, and the connection node (ND[i]) between the cathode of the ith electrolytic capacitor and the anode of the (i+1)-th electrolytic capacitor is the ith intermediate terminal (TM M [i]), where i represents a natural number equal to or less than (n-1), the high-side regulating current is a current between the high-side terminal and the first intermediate terminal, and the low-side regulating current is a current between the (n-1)th intermediate terminal and the low-side terminal, the voltage limiting circuit controls the high-side regulating current in accordance with the voltage between the high-side terminal and the first intermediate terminal to limit the voltage between the high-side terminal and the first intermediate terminal to be equal to or less than the high-side limit voltage, and controls the low-side regulating current in accordance with the voltage between the (n-1)th intermediate terminal and the low-side terminal to limit the voltage between the (n-1)th intermediate terminal and the low-side terminal to be equal to or less than the low-side limit voltage, and the voltage limiting circuit controls an intermediate regulating current (I M ) to limit the voltage between the two intermediate terminals to the intermediate clamp voltage (VM LIM ) or less (seventh configuration).

[0144] The voltage regulator device according to any of the first to seventh configurations may be configured (eighth configuration) to be formed by a semiconductor device (SD) having a housing (CS) that houses the voltage limiting circuit and a plurality of external terminals exposed from the housing.

[0145] The voltage regulator device according to any of the first to seventh configurations may be formed by a housing and a plurality of semiconductor devices each having a plurality of external terminals exposed from the housing, and the voltage limiting circuit may be housed in a distributed manner in the plurality of housings (ninth configuration).

[0146] A charge storage system according to one aspect of the present disclosure has a configuration (tenth configuration) including the voltage adjustment device according to any one of the first to ninth configurations and the plurality of electrolytic capacitors.

[0147] A voltage regulator according to another aspect of the present disclosure (see FIGS. 1, 4, and 17 to 19) includes a ground wiring (WR GND ) and an input voltage (V IN ) is added to the input voltage wiring (WR IN ) and a voltage adjusting device (3, 20a, 20b, 20c) connected to a series circuit of a plurality of electrolytic capacitors (C[1] to C[n]) provided between the high-side terminal (TM H ) and the low-side terminal (TM L ) and an intermediate terminal (TM) connected to a connection node between the plurality of electrolytic capacitors. M [i]) and the current between the connection node and the intermediate terminal based on the voltages of the high-side terminal and the intermediate terminal seen from the potential of the low-side terminal, thereby controlling the inter-electrode voltage (V C [1]) and the voltage between the electrodes of the second electrolytic capacitor included in the plurality of electrolytic capacitors (V C and a voltage leveling circuit (210a, 210b, 210c) configured to reduce the difference with the voltage level [2] (eleventh configuration).

[0148] When multiple electrolytic capacitors are connected in series, there is a concern that an excessive voltage may be applied to a specific electrolytic capacitor due to differences in leakage current among the multiple electrolytic capacitors, etc. By using the voltage regulator according to the eleventh configuration, the voltage applied to the multiple electrolytic capacitors is leveled against variations in leakage current, etc., and therefore the system including each electrolytic capacitor can be operated safely.

[0149] In the voltage regulator according to the eleventh configuration, the series circuit of the plurality of electrolytic capacitors is a series circuit of the first electrolytic capacitor (C[1]) and the second electrolytic capacitor (C[2]), an anode of the first electrolytic capacitor is connected to the input voltage wiring, a cathode of the second electrolytic capacitor is connected to the ground wiring, a connection node (ND[1]) between the cathode of the first electrolytic capacitor and the anode of the second electrolytic capacitor is connected to the intermediate terminal, and the voltage leveling circuit outputs a first reference voltage (V DIV215 , V DIV [1]) and the second contrast voltage (V MID [1]) and generates a current between the connection node and the intermediate terminal according to the comparison result, and the voltage between both electrodes of the first electrolytic capacitor (V C [1]) and the voltage between the two electrodes of the second electrolytic capacitor (V C [2]), the first comparison voltage is half the voltage of the high-side terminal seen from the potential of the low-side terminal, and the second comparison voltage is the voltage of the intermediate terminal seen from the potential of the low-side terminal (twelfth configuration).

[0150] In the voltage adjustment device according to any of the twelfth configurations, the amplifier may be configured (a thirteenth configuration) such that, when the first reference voltage is higher than the second reference voltage, the amplifier outputs a current from the intermediate terminal toward the connection node, thereby decreasing the electrode-to-electrode voltage of the first electrolytic capacitor and increasing the electrode-to-electrode voltage of the second electrolytic capacitor, and when the first reference voltage is lower than the second reference voltage, the amplifier draws a current from the connection node via the intermediate terminal, thereby increasing the electrode-to-electrode voltage of the first electrolytic capacitor and decreasing the electrode-to-electrode voltage of the second electrolytic capacitor.

[0151] In the voltage regulator according to the eleventh configuration, the plurality of electrolytic capacitors are first to n-th electrolytic capacitors (C[1] to C[n]) connected in series with each other, and the intermediate terminals are first to (n-1)-th intermediate terminals (TM M [1]~TM M the anode of the first electrolytic capacitor is connected to the input voltage wiring, the cathode of the nth electrolytic capacitor is connected to the ground wiring, a first connection node to a (n-1)th connection node (ND[1] to ND[n-1]) are formed in the series circuit of the plurality of electrolytic capacitors, the i-th connection node is a connection node between the cathode of the i-th electrolytic capacitor and the anode of the (i+1)th electrolytic capacitor and is connected to the i-th intermediate terminal, i represents a natural number equal to or less than (n-1), the voltage leveling circuit comprises a first amplifier to a (n-1)th amplifier (AMP[1] to AMP[n-1]), output terminals of the first amplifier to the (n-1)th amplifier are connected to the first intermediate terminal to the (n-1)th intermediate terminal, respectively, and the i-th amplifier outputs a first comparison voltage (V DIV [i]) and the second comparison voltage (V MID [i]), and generates a current according to the comparison result between the ith connection node and the ith intermediate terminal, and the voltage leveling circuit uses the generated current of each amplifier to generate a voltage between the electrodes of the first electrolytic capacitor to the electrode of the nth electrolytic capacitor (V C [1]~V C[n]), the first comparison voltage in the i amplifier is the product of the voltage of the high-side terminal seen from the potential of the low-side terminal and (ni) / n, and the second comparison voltage in the i amplifier is the voltage of the i intermediate terminal seen from the potential of the low-side terminal (fourteenth configuration).

[0152] In the voltage adjustment device according to any of the fourteenth configurations, the i-th amplifier may be configured such that, when the first reference voltage in the i-th amplifier is higher than the second reference voltage in the i-th amplifier, the i-th amplifier outputs a current from the i-th intermediate terminal to the i-th connection node, thereby decreasing the inter-electrode voltages of the first electrolytic capacitor through the i-th electrolytic capacitor while increasing the inter-electrode voltages of the (i+1)th electrolytic capacitor through the n-th electrolytic capacitor; and, when the first reference voltage in the i-th amplifier is lower than the second reference voltage in the i-th amplifier, the i-th amplifier draws a current from the i-th connection node via the i-th intermediate terminal, thereby increasing the inter-electrode voltages of the first electrolytic capacitor through the i-th electrolytic capacitor while decreasing the inter-electrode voltages of the (i+1)th electrolytic capacitor through the n-th electrolytic capacitor (fifteenth configuration).

[0153] A charge storage system according to another aspect of the present disclosure has a configuration (sixteenth configuration) including the voltage adjustment device according to any one of the eleventh to fifteenth configurations and the plurality of electrolytic capacitors. [Explanation of symbols]

[0154] SYS Circuit System 1, 1A, 1B voltage supply 2 capacity device 3, 10a, 10b, 20a, 20b, 20c Voltage regulator 4 Load device V AC AC voltage V IN Input voltage WR IN Wiring (input voltage wiring) WR GND Wiring (ground wiring) C[1]~C[n] capacitors V C [1]~V C [n] Polarity voltage ND[1]~ND[n] nodes V MID [1]~V MID [n] Intermediate voltage TM H High side terminal TM L Low side terminal TM M [1]~TM M [n] Intermediate terminal 911, 912 Capacitors 921a, 921b, 922a, 922b resistor 11H High-side controller 11L Low-side controller 11M Intermediate Controller 12H, 12L, 12M transistors 13H, 13L, 12M Current limiting resistors 111H, 111L, 12M amplifiers 112H, 112L, 12M voltage divider circuit 113H, 114H, 113L, 114L, 113M, 114M Voltage divider resistors 115H, 115L, 115M Reference voltage source 116H, 116L, 116M transistors V DIVH Voltage (high-side divided voltage) V DIVL Voltage (low-side voltage divider) V DIVM Voltage (intermediate voltage) I H Regulated current (high side regulated current) I L Adjustment current (low side adjustment current) I M Adjustment current (intermediate adjustment current) I LK [1], I LK [2] Leakage current V INMAX Maximum input voltage VHLIM , V.L. LIM Clamping Voltage SD, SD1, SD2 Semiconductor Devices CS, CS1, CS2 housing FL H , F.L. L Frame TMa, TMb external terminal 20 Voltage limiting circuit 30[1]~30[n] Limiting circuit 210a, 210b, 210c voltage equalization circuit 211, 221, 231, AMP[1]~AMP[n-1] Amplifiers 212, 222, 232, DIV[1]~DIV[n-1] voltage divider circuit 213, 214, 223, 224, 233, 234 Voltage dividing resistors

Claims

1. 1. A voltage adjustment device connected to a series circuit of a plurality of electrolytic capacitors provided between a ground wiring and an input voltage wiring to which an input voltage higher than the potential of the ground wiring is applied, a high-side terminal connected to the input voltage wiring; a low-side terminal connected to the ground wiring; an intermediate terminal connected to a connection node between the plurality of electrolytic capacitors; a voltage limiting circuit configured to limit the voltage between the high-side terminal and the intermediate terminal to a high-side limit voltage or less by controlling a high-side regulating current between the high-side terminal and the intermediate terminal in accordance with the voltage between the high-side terminal and the intermediate terminal, and to limit the voltage between the intermediate terminal and the low-side terminal to a low-side limit voltage or less by controlling a low-side regulating current between the intermediate terminal and the low-side terminal in accordance with the voltage between the intermediate terminal and the low-side terminal. , voltage regulator.

2. The voltage limiting circuit a high-side transistor inserted between the high-side terminal and the intermediate terminal; and a high-side controller configured to control the presence and magnitude of the high-side regulating current by controlling a gate voltage of the high-side transistor according to a voltage between the high-side terminal and the intermediate terminal, thereby limiting the voltage between the high-side terminal and the intermediate terminal to be equal to or less than the high-side limit voltage; a low-side transistor inserted between the intermediate terminal and the low-side terminal; and a low-side controller configured to control the presence or absence and magnitude of the low-side regulating current by controlling a gate voltage of the low-side transistor according to a voltage between the intermediate terminal and the low-side terminal, thereby limiting the voltage between the intermediate terminal and the low-side terminal to be equal to or less than the low-side limit voltage.

10. The voltage regulator of claim 1.

3. the high-side controller comprises: a high-side voltage divider circuit configured to generate a high-side divided voltage that is a divided voltage of a voltage between the high-side terminal and the intermediate terminal; and a high-side amplifier configured to control the presence or absence and magnitude of the high-side adjustment current by controlling a gate voltage of the high-side transistor according to a high-level relationship between the high-side divided voltage and a high-side reference voltage; The low-side controller includes a low-side voltage divider circuit configured to generate a low-side divided voltage that is a divided voltage of a voltage between the intermediate terminal and the low-side terminal, and a low-side amplifier configured to control the presence or absence and magnitude of the low-side adjustment current by controlling a gate voltage of the low-side transistor according to a high-low relationship between the low-side divided voltage and a low-side reference voltage.

3. The voltage regulator according to claim 2.

4. the high-side amplifier cuts off the high-side transistor when the high-side divided voltage is lower than the high-side reference voltage, and turns on the high-side transistor when the high-side divided voltage is higher than the high-side reference voltage, thereby generating the high-side adjustment current, thereby limiting the voltage between the high-side terminal and the intermediate terminal to equal to or lower than the high-side limiting voltage; The low-side amplifier cuts off the low-side transistor when the low-side divided voltage is lower than the low-side reference voltage, and turns on the low-side transistor when the low-side divided voltage is higher than the low-side reference voltage, thereby generating the low-side adjustment current, thereby limiting the voltage between the intermediate terminal and the low-side terminal to equal to or lower than the low-side limit voltage.

4. The voltage regulator according to claim 3.

5. A current limiting resistor is connected in series to the high-side transistor, and another current limiting resistor is connected in series to the low-side transistor.

5. The voltage regulator according to claim 2.

6. The plurality of electrolytic capacitors include a first electrolytic capacitor and a second electrolytic capacitor connected in series with each other, The anode of the first electrolytic capacitor is connected to the input voltage wiring, the cathode of the second electrolytic capacitor is connected to the ground wiring, and a connection node between the cathode of the first electrolytic capacitor and the anode of the second electrolytic capacitor is connected to the intermediate terminal.

5. A voltage regulator according to claim 1.

7. the plurality of electrolytic capacitors are first to n-th electrolytic capacitors connected in series with each other, and the intermediate terminals include first to (n-1)-th intermediate terminals, where n is an integer of 3 or more; an anode of the first electrolytic capacitor is connected to the input voltage wiring, and a cathode of the nth electrolytic capacitor is connected to the ground wiring; a connection node between the cathode of the ith electrolytic capacitor and the anode of the (i+1)th electrolytic capacitor is connected to the ith intermediate terminal, where i represents a natural number equal to or less than (n-1); the high-side regulating current is a current between the high-side terminal and the first intermediate terminal, and the low-side regulating current is a current between the (n-1)th intermediate terminal and the low-side terminal; the voltage limiting circuit limits the voltage between the high-side terminal and the first intermediate terminal to equal to or less than the high-side limiting voltage by controlling the high-side regulating current in accordance with the voltage between the high-side terminal and the first intermediate terminal, and limits the voltage between the (n-1)th intermediate terminal and the low-side terminal to equal to or less than the low-side limiting voltage by controlling the low-side regulating current in accordance with the voltage between the (n-1)th intermediate terminal and the low-side terminal; The voltage limiting circuit limits the voltage between the two intermediate terminals to an intermediate limiting voltage or less by controlling an intermediate adjustment current between the two intermediate terminals according to the voltage between two adjacent intermediate terminals among the first intermediate terminal to the (n-1)th intermediate terminal.

5. A voltage regulator according to claim 1.

8. The voltage regulator is formed by a semiconductor device having a housing that houses the voltage limiting circuit and a plurality of external terminals exposed from the housing.

5. A voltage regulator according to claim 1.

9. The voltage regulator is formed by a plurality of semiconductor devices each having a housing and a plurality of external terminals exposed from the housing, and the voltage limiting circuit is housed in a distributed manner in the plurality of housings.

5. A voltage regulator according to claim 1.

10. A voltage regulator according to any one of claims 1 to 4; the plurality of electrolytic capacitors; , charge storage system.

11. 1. A voltage adjustment device connected to a series circuit of a plurality of electrolytic capacitors provided between a ground wiring and an input voltage wiring to which an input voltage higher than the potential of the ground wiring is applied, a high-side terminal connected to the input voltage wiring; a low-side terminal connected to the ground wiring; an intermediate terminal connected to a connection node between the plurality of electrolytic capacitors; a voltage leveling circuit configured to reduce a difference between a voltage between both electrodes of a first electrolytic capacitor included in the plurality of electrolytic capacitors and a voltage between both electrodes of a second electrolytic capacitor included in the plurality of electrolytic capacitors by controlling a current between the connection node and the intermediate terminal based on the voltages of the high-side terminal and the intermediate terminal viewed from the potential of the low-side terminal. , voltage regulator.

12. the series circuit of the plurality of electrolytic capacitors is a series circuit of the first electrolytic capacitor and the second electrolytic capacitor, an anode of the first electrolytic capacitor is connected to the input voltage wiring, a cathode of the second electrolytic capacitor is connected to the ground wiring, and a connection node between the cathode of the first electrolytic capacitor and the anode of the second electrolytic capacitor is connected to the intermediate terminal; the voltage leveling circuit includes an amplifier configured to compare a first comparison voltage with a second comparison voltage and generate a current between the connection node and the intermediate terminal according to a comparison result, and the current generated by the amplifier reduces a difference between a voltage across the electrodes of the first electrolytic capacitor and a voltage across the electrodes of the second electrolytic capacitor; The first comparison voltage is half the voltage of the high-side terminal as viewed from the potential of the low-side terminal, and the second comparison voltage is the voltage of the intermediate terminal as viewed from the potential of the low-side terminal.

12. The voltage regulator of claim 11.

13. When the first reference voltage is higher than the second reference voltage, the amplifier outputs a current from the intermediate terminal toward the connection node, thereby decreasing the inter-electrode voltage of the first electrolytic capacitor and increasing the inter-electrode voltage of the second electrolytic capacitor; and when the first reference voltage is lower than the second reference voltage, the amplifier draws a current from the connection node via the intermediate terminal, thereby increasing the inter-electrode voltage of the first electrolytic capacitor and decreasing the inter-electrode voltage of the second electrolytic capacitor.

13. The voltage regulator of claim 12.

14. the plurality of electrolytic capacitors are first to n-th electrolytic capacitors connected in series with each other, and the intermediate terminals include first to (n-1)-th intermediate terminals, where n is an integer of 3 or more; an anode of the first electrolytic capacitor is connected to the input voltage wiring, and a cathode of the nth electrolytic capacitor is connected to the ground wiring; a first connection node to an (n-1)th connection node are formed in the series circuit of the plurality of electrolytic capacitors, the i-th connection node is a connection node between the cathode of the i-th electrolytic capacitor and the anode of the (i+1)-th electrolytic capacitor and is connected to the i-th intermediate terminal, where i represents a natural number equal to or less than (n-1); the voltage leveling circuit includes a first amplifier to an (n-1)th amplifier, output terminals of the first amplifier to the (n-1)th amplifier are connected to the first intermediate terminal to the (n-1)th intermediate terminal, respectively; the i-th amplifier compares the first comparison voltage with the second comparison voltage and generates a current corresponding to the comparison result between the i-th connection node and the i-th intermediate terminal, the voltage leveling circuit reduces the difference between the electrode-to-electrode voltage of the first electrolytic capacitor and the electrode-to-electrode voltage of the n-th electrolytic capacitor by the current generated by each amplifier; The first comparison voltage in the i-th amplifier is the product of the voltage of the high-side terminal seen from the potential of the low-side terminal and (n-i) / n, and the second comparison voltage in the i-th amplifier is the voltage of the i-th intermediate terminal seen from the potential of the low-side terminal.

12. The voltage regulator of claim 11.

15. When the first comparison voltage in the i amplifier is higher than the second comparison voltage in the i amplifier, the i amplifier outputs a current from the i intermediate terminal toward the i connection node, thereby decreasing the inter-electrode voltages of the first electrolytic capacitor to the i electrolytic capacitor while increasing the inter-electrode voltages of the (i+1) electrolytic capacitor to the n electrolytic capacitor; and when the first comparison voltage in the i amplifier is lower than the second comparison voltage in the i amplifier, the i amplifier draws a current from the i connection node via the i intermediate terminal, thereby increasing the inter-electrode voltages of the first electrolytic capacitor to the i electrolytic capacitor while decreasing the inter-electrode voltages of the (i+1) electrolytic capacitor to the n electrolytic capacitor.

15. The voltage regulator of claim 14.

16. A voltage regulator according to any one of claims 11 to 15; the plurality of electrolytic capacitors; , charge storage system.

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