MOS transistor manufacturing method

Abstract

To suppress silicon agglomeration in a MOS transistor manufacturing method in which the interface state density at the interface between a silicon oxide film and a SiC substrate is low.SOLUTION: A MOS transistor manufacturing method includes the steps of etching a surface of a SiC substrate by heating the SiC substrate in hydrogen gas, growing a silicon film on the surface of the SiC substrate by heating the SiC substrate in a gas containing hydrogen gas and a silicon source gas to a temperature lower than the heating temperature of the SiC substrate in the etching, forming a gate insulating film made of silicon oxide on the surface of the silicon film, and performing a nitrogen termination treatment on the SiC substrate after forming the gate insulating film.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a method for manufacturing a MOS transistor.

[0002] In the method for manufacturing a MOS transistor disclosed in Patent Document 1, a SiC substrate (i.e., a substrate made of silicon carbide) is heated in a gas containing hydrogen gas and a silicon source gas. The hydrogen gas etches the surface of the SiC substrate, and a silicon film (i.e., Si) is formed on the surface of the SiC substrate. Next, a silicon oxide film (i.e., SiO2) is formed on the surface of the silicon film as a gate insulating film. The silicon film is oxidized during this process, thereby suppressing oxidation of the surface of the SiC substrate. Suppressing oxidation of the surface of the SiC substrate in this manner reduces the interface state density at the interface between the silicon oxide film and the SiC substrate. The reduction in interface state density at the interface between the silicon oxide film and the SiC substrate improves channel mobility and reduces channel resistance. This reduces the on-resistance of the MOS transistor. After the silicon oxide film is formed, a nitrogen termination process is performed. The nitrogen termination process further reduces the interface state density at the interface between the silicon oxide film and the SiC substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2021-192397 Summary of the Invention [Problem to be solved by the invention]

[0004] In the technology of Patent Document 1, silicon agglomeration may occur in a part of the surface of the SiC substrate when the silicon film is grown. As a result, leakage current may occur through the silicon agglomeration. This specification proposes a technology to suppress silicon agglomeration in a manufacturing method of a MOS transistor with a low interface state density at the interface between a silicon oxide film and a SiC substrate. [Means for solving the problem]

[0005] The method for manufacturing a MOS transistor disclosed in this specification includes the steps of: etching a surface of a SiC substrate by heating the SiC substrate in hydrogen gas; growing a silicon film on the surface of the SiC substrate by heating the SiC substrate in a gas containing hydrogen gas and a silicon source gas to a temperature lower than the heating temperature of the SiC substrate in the etching; forming a gate insulating film made of silicon oxide on the surface of the silicon film; and performing nitrogen termination on the SiC substrate after forming the gate insulating film.

[0006] In this manufacturing method, after the step of etching the surface of the SiC substrate, a silicon film formation step is performed at a temperature lower than that of the etching step. Because the etching of the SiC substrate is performed at a high temperature, the surface of the SiC substrate can be appropriately cleaned. Because the silicon film formation step is performed at a temperature lower than that of the etching step, silicon migration is less likely to occur on the surface of the SiC substrate during the silicon film formation step. Therefore, a uniform silicon film can be formed while suppressing silicon agglomeration. In the gate insulating film formation step, the silicon film is oxidized to form silicon oxide. This suppresses oxidation of the surface of the SiC substrate, making it less likely that interface states will form at the interface between the gate insulating film and the SiC substrate. Then, nitrogen termination treatment is performed to terminate the SiC crystal with nitrogen at the interface between the gate insulating film and the SiC substrate. As described above, this manufacturing method makes it possible to manufacture a MOS transistor with a low interface state density at the interface between the gate insulating film and the SiC substrate while suppressing silicon agglomeration. [Brief explanation of the drawings]

[0007] [Figure 1] Cross-sectional view of a MOS transistor. [Figure 2] FIG. [Figure 3]FIG. [Figure 4] FIG. 1 is an explanatory diagram of silicon agglomeration. [Figure 5] 10 is a graph showing the relationship between the heating temperature and the number of elements in which agglomeration portions occur in a silicon film formation process. DETAILED DESCRIPTION OF THE INVENTION

[0008] FIG. 1 shows a MOS transistor 10 manufactured by a manufacturing method according to the embodiment. The MOS transistor 10 includes a SiC substrate 12, a gate insulating film 14, a gate electrode 16, an interlayer insulating film 18, a source electrode 20, and a drain electrode 22. The SiC substrate 12 has an upper surface 12a and a lower surface 12b as major surfaces. A plurality of trenches 24 are provided in the upper surface 12a of the SiC substrate 12. The trenches 24 extend linearly and parallel to each other on the upper surface 12a. The gate insulating film 14 covers the inner surfaces of each trench 24 (i.e., the side surfaces 24a and bottom surfaces 24b of the trenches 24). A gate electrode 16 is disposed in each trench 24. The gate electrode 16 is insulated from the SiC substrate 12 by the gate insulating film 14. The interlayer insulating film 18 covers the upper surface of the gate electrode 16. The source electrode 20 covers the upper surface 12a of the SiC substrate 12 and the upper surface of the interlayer insulating film 18. The source electrode 20 is insulated from the gate electrode 16 by an interlayer insulating film 18. The drain electrode 22 covers the lower surface 12b of the SiC substrate 12.

[0009] The SiC substrate 12 has a source region 30, a contact region 32, a body region 34, a drift region 36, and a drain region 38. The source region 30 is an n-type region having a high n-type impurity concentration. The source region 30 is in contact with a source electrode 20 and a gate insulating film 14. The contact region 32 is a p-type region having a high p-type impurity concentration. The contact region 32 is in contact with the source electrode 20. The body region 34 is a p-type region having a lower p-type impurity concentration than the contact region 32. The body region 34 is in contact with the source region 30 and the contact region 32 from below. The body region 34 is in contact with the gate insulating film 14 below the source region 30. The drift region 36 is an n-type region having a lower n-type impurity concentration than the source region 30. The drift region 36 is in contact with the body region 34 from below. The drift region 36 is in contact with the body region 34 from below. The drift region 36 is in contact with the gate insulating film 14 below the body region 34. The drain region 38 is an n-type region having a higher n-type impurity concentration than the drift region 36. The drain region 38 contacts the drift region 36 from below. The drain region 38 contacts the drain electrode 22.

[0010] When a potential equal to or greater than the threshold is applied to the gate electrode 16, a channel is formed in the body region 34 along the gate insulating film 14 (i.e., the side surface 24a of the trench 24). The channel connects the source region 30 and the drift region 36. When a potential higher than that of the source electrode 20 is applied to the drain electrode 22 with the channel formed, electrons flow from the source region 30 to the drain region 38 via the channel and the drift region 36.

[0011] Next, an embodiment of a method for manufacturing the MOS transistor 10 will be described. Note that the manufacturing method of the embodiment is characterized by the method for forming the gate structure, and therefore the method for forming the gate structure will be mainly described below.

[0012] As shown in FIG. 2(a), a SiC substrate 12 is prepared before trench formation. The SiC layer exposed on the upper surface 12a is an epitaxial layer (i.e., a SiC layer formed by epitaxial growth). + area, p + area, p - Area and n - The regions are respectively a source region 30, a contact region 32, a body region 34, and a drift region 36. Although not shown, a drain region 38 is provided on the lower surface side of the SiC substrate 12 in FIG.

[0013] First, as shown in FIG. 2(b), the upper surface 12a of the SiC substrate 12 is selectively etched to form a trench 24 in the upper surface 12a, which penetrates the source region and the body region and reaches the drift region.

[0014] Next, as shown in FIG. 2(c), the SiC substrate 12 is heated and oxidized to form a sacrificial oxide film 40 (i.e., a silicon oxide film) on the upper surface 12a and the inner surfaces of the trenches 24 (i.e., the side surfaces 24a and bottom surfaces 24b). Next, as shown in FIG. 2(d), the sacrificial oxide film 40 is removed by etching. In this manner, by forming the sacrificial oxide film 40 on the surface of the SiC substrate 12 and then removing it, defects and contamination can be removed from the surface of the SiC substrate 12.

[0015] The sacrificial oxide film forming step and the sacrificial oxide film removing step are not essential and may be omitted. Regardless of whether the sacrificial oxide film forming step and the sacrificial oxide film removing step are performed, a high density of carbon defects having C-C bonds exists on the surface of the SiC substrate 12. The carbon defects form interface states and capture electrons. If a high density of carbon defects exists at the interface between the channel and the gate insulating film 14 (i.e., the side surface 24a of the trench 24), Coulomb scattering occurs due to electrons captured in the interface states, increasing the channel resistance. In contrast, as described below, in the manufacturing method of the embodiment, a gate structure can be formed with a low interface state density on the side surface 24a of the trench 24.

[0016] Next, the high-temperature hydrogen etching step shown in FIG. 3(a) is performed. In the high-temperature hydrogen etching step, first, the SiC substrate 12 is placed in a chamber of a CVD apparatus, and hydrogen (H) gas is supplied into the chamber. Note that no silicon source gas is supplied into the chamber during the high-temperature hydrogen etching step. Next, the SiC substrate 12 is heated in hydrogen gas to a temperature of 1200°C or higher (e.g., 1300°C). The hydrogen gas then etches the surface of the SiC substrate 12 (i.e., the upper surface 12a and the inner surface of the trench 24). Here, a very thin layer near the surface of the SiC substrate 12 is etched. As a result, carbon defects can be removed from the surface of the SiC substrate 12. In other words, the high-temperature hydrogen etching step can reduce the carbon defect density on the surface of the SiC substrate 12.

[0017] Next, the silicon film formation process shown in FIG. 3(b) is performed. The silicon film formation process is performed consecutively in the same chamber as the high-temperature hydrogen etching process. Performing the high-temperature hydrogen etching process and the silicon film formation process in the same chamber stabilizes the quality of the manufactured MOS transistor and increases the manufacturing efficiency of the MOS transistor. In the silicon film formation process, hydrogen gas and a silicon source gas are supplied into the chamber. The silicon source gas is a gas containing silicon atoms and serves as the source gas for the silicon film 42 to be formed. For example, silane (SiH4) can be used as the silicon source gas. Next, the SiC substrate 12 is heated in the hydrogen gas and the silicon source gas. Here, the temperature of the SiC substrate 12 is controlled to be higher than the decomposition temperature of the silicon source gas but lower than the heating temperature in the high-temperature hydrogen etching process. For example, the temperature of the SiC substrate 12 can be controlled to be higher than 400°C (i.e., the decomposition temperature of silane) and not higher than 1100°C. In the silicon film formation process, a reaction in which the SiC substrate 12 is etched by the hydrogen gas and a reaction in which a single-crystal silicon film 42 is formed on the surface of the SiC substrate 12 by the silicon source gas occur in parallel on the surface of the SiC substrate 12 (i.e., the upper surface 12a and the inner surface of the trench 24). Because the etching reaction and the film formation reaction occur in parallel in this way, the silicon film 42 grows on the clean surface of the SiC substrate 12. Furthermore, because the etching reaction and the film formation reaction occur in parallel, a thin silicon film 42 having a thickness of 6 nm or less is formed in the silicon film formation process.

[0018] Next, the gate insulating film formation step shown in FIG. 3(c) is carried out. Here, a low-pressure CVD apparatus is used to form a silicon oxide layer 44 on the surface of the silicon film 42. That is, the silicon oxide layer 44 is formed on the upper surface 12a and in the trenches 24. Furthermore, the silicon film 42 is oxidized during the formation of the silicon oxide layer 44. The silicon oxide film 42a formed by the oxidation of the silicon film 42 is integrated with the silicon oxide layer 44 formed by CVD. In this way, the gate insulating film 14 is formed.

[0019] Next, nitrogen termination is performed. In nitrogen termination, the SiC substrate 12 is heated to a temperature of 1200°C or higher (e.g., 1250°C) in nitrogen gas (i.e., N2 gas) or nitrogen oxide gas (e.g., NO gas, N2O gas, etc.). This nitrogen-terminates the SiC crystal.

[0020] Next, as shown in FIG. 3(d), a gate electrode 16 is formed in the trench 24. An interlayer insulating film 18 is formed on the gate electrode 16. This completes the trench gate structure. Next, as shown in FIG. 1, the gate insulating film 14 on the upper surface 12a is selectively removed to form a contact hole 20a. Next, a source electrode 20 is formed so as to cover the upper surface 12a of the SiC substrate 12. Next, a drain electrode 22 is formed so as to cover the lower surface 12b of the SiC substrate 12. Through the above steps, the MOS transistor 10 shown in FIG. 1 is completed.

[0021] Next, the manufacturing method of Comparative Example 1 and the manufacturing method of the Example will be described by comparison. In the manufacturing method of Comparative Example 1, a silicon oxide layer 44 is formed directly on the surface of the SiC substrate 12 without forming a silicon film 42. When the silicon oxide layer 44 is formed in this manner, the surface of the SiC substrate 12 is oxidized during the formation of the silicon oxide layer 44. In this case, the surface of the SiC substrate may be oxidized during the subsequent nitrogen termination treatment. For example, when nitrogen oxide gas is used in the nitrogen termination treatment, the surface of the SiC substrate may be oxidized by oxygen atoms in the nitrogen oxide gas. Even when nitrogen gas is used in the nitrogen termination treatment, the surface of the SiC substrate may be oxidized by a trace amount of oxidizing gas mixed into the chamber. When the surface of the SiC substrate is oxidized during the gate insulating film formation process and the nitrogen termination treatment process, carbon defects are generated on the surface of the SiC substrate.

[0022] In contrast, in the manufacturing method of the embodiment, the silicon film 42 is oxidized instead of the SiC substrate 12 in the gate insulating film forming process and the nitrogen termination process. By oxidizing the silicon film 42 instead of the SiC substrate 12, oxidation of the surface of the SiC substrate 12 is suppressed. Therefore, carbon defects are less likely to be generated on the surface of the SiC substrate 12 (i.e., the interface between the SiC substrate 12 and the gate insulating film 14). This reduces the interface state density at the interface between the SiC substrate 12 and the gate insulating film 14. This effect, along with the effect of nitrogen-terminating the SiC crystal by the nitrogen termination process, significantly reduces the interface state density at the interface between the SiC substrate 12 and the gate insulating film 14. Therefore, a MOS transistor 10 with a low interface state density at the side surface 24a (i.e., the interface between the body region 34 and the gate insulating film 14) can be manufactured. Therefore, this manufacturing method can increase the channel mobility of the MOS transistor 10. Therefore, this manufacturing method can manufacture a MOS transistor 10 with low on-resistance.

[0023] Next, the manufacturing method of Comparative Example 2 and the manufacturing method of the Example will be described by comparison. In the manufacturing method of Comparative Example 2, the silicon film formation process is performed without performing the high-temperature hydrogen etching process. In the silicon film formation process of Comparative Example 2, the SiC substrate 12 is heated in hydrogen gas to a temperature of 1200°C or higher (e.g., 1300°C). That is, in the silicon film formation process of Comparative Example 2, the SiC substrate 12 is heated to a higher temperature than in the silicon film formation process of the Example. When the silicon film formation process is performed at such a high temperature, silicon atoms migrate in the growing silicon film 42, forming silicon agglomerates 46 on parts of the side surfaces 24a of the trench 24, as shown in FIG. 4(a). In the agglomerates 46, the thickness of the silicon film 42 is locally increased. Therefore, as shown in FIG. 4(b), when the trench gate structure is completed, part of the agglomerates 46 (i.e., the silicon layer) remains without being oxidized. If the agglomerates 46 remain adjacent to the body region as shown in FIG. 4(b), leakage current flows between the source and drain of the MOS transistor.

[0024] In contrast, in the manufacturing method of the embodiment, the surface of the SiC substrate is etched in the high-temperature hydrogen etching step, followed by a silicon film formation step at a lower heating temperature than in the high-temperature hydrogen etching step. In the high-temperature hydrogen etching step, the SiC substrate 12 is heated to a high temperature, allowing the surface of the SiC substrate 12 to be appropriately cleaned. In the silicon film formation step, the temperature of the SiC substrate 12 is controlled to a lower temperature than in the high-temperature hydrogen etching step, thereby suppressing silicon migration in the silicon film 42. Therefore, the silicon film 42 can be formed with a uniform thickness, and the occurrence of agglomeration portions 46 can be suppressed. Therefore, the manufacturing method of the embodiment can suppress the occurrence of defects due to leakage current.

[0025] 5 shows the results of evaluating the number of agglomeration portions 46 that occurred when the silicon film formation process was performed at different temperatures. When the heating temperature of the SiC substrate in the silicon film formation process was 1150°C, 3653 agglomeration portions 46 occurred per wafer, whereas when the heating temperature was 1100°C or 900°C, the number of agglomeration portions 46 that occurred per wafer was zero. Thus, by controlling the heating temperature of the SiC substrate in the silicon film formation process to 1100°C or less, the occurrence of agglomeration portions 46 can be significantly suppressed.

[0026] In the above examples, a method for manufacturing a trench MOS transistor has been described. However, the techniques disclosed herein may also be applied to the manufacture of a MOS transistor having a planar gate structure. In this case, the techniques disclosed herein can be used to form a gate insulating film so as to cover the main surface (e.g., the upper surface) of the SiC substrate. However, since silicon agglomerates are likely to occur in trenches, greater effects can be obtained by using the techniques disclosed herein in trench MOS transistors.

[0027] The configurations of the techniques disclosed in this specification are listed below. (Configuration 1) A method for manufacturing a MOS transistor, comprising: Etching a surface of the SiC substrate by heating the SiC substrate in hydrogen gas; After the etching, the SiC substrate is heated in a gas containing hydrogen gas and a silicon source gas to a temperature lower than the heating temperature of the SiC substrate in the etching, thereby growing a silicon film on the surface of the SiC substrate; forming a gate insulating film made of silicon oxide on the surface of the silicon film; performing a nitrogen termination process on the SiC substrate after forming the gate insulating film; A manufacturing method comprising the steps of: (Configuration 2) a trench is provided in a main surface of the SiC substrate, The etching etches the side surface of the trench, In the step of growing the silicon film, the silicon film is grown on the side surface of the trench; In the step of forming the gate insulating film, the gate insulating film is formed on the surface of the silicon film covering the side surface of the trench. The manufacturing method according to configuration 1. (Configuration 3) 3. The manufacturing method according to claim 1, wherein in the step of growing the silicon film, the temperature of the SiC substrate is controlled to 1100° C. or less. (Configuration 4) 4. The manufacturing method according to any one of configurations 1 to 3, wherein in the step of growing the silicon film, the temperature of the SiC substrate is controlled to a temperature equal to or higher than the decomposition temperature of the silicon raw material gas. (Configuration 5) 5. The manufacturing method according to any one of aspects 1 to 4, wherein the silicon film has a thickness of 6 nm or less. (Configuration 6) 6. The manufacturing method according to any one of configurations 1 to 5, wherein the etching and the step of growing the silicon film are carried out in the same chamber. (Configuration 7) 7. The manufacturing method according to any one of Configurations 1 to 6, wherein a step of forming a sacrificial oxide film on the surface of the SiC substrate and then removing the sacrificial oxide film is performed before the etching. (Configuration 8) 8. The manufacturing method according to any one of configurations 1 to 7, wherein the surface of the SiC substrate is the surface of an epitaxial layer. (Configuration 9) 9. The manufacturing method according to any one of configurations 1 to 8, wherein in the step of forming the gate insulating film, the gate insulating film is formed by chemical vapor deposition. (Configuration 10) 10. The manufacturing method according to any one of configurations 1 to 9, wherein the nitrogen termination treatment involves heating the SiC substrate to a temperature of 1200° C. or higher in nitrogen gas or nitrogen oxide gas.

[0028] According to the second aspect, it is possible to suppress the aggregation of silicon on the side surface of the trench.

[0029] According to the third aspect, the aggregation of silicon can be more effectively suppressed.

[0030] According to the fourth aspect, the silicon film can be grown appropriately.

[0031] According to the fifth aspect, the silicon film can be appropriately oxidized when the gate insulating film is formed.

[0032] According to the sixth aspect, MOS transistors can be manufactured efficiently.

[0033] According to the seventh aspect, defects on the surface of the SiC substrate can be removed.

[0034] According to the tenth aspect, the interface state density at the interface between the SiC substrate and the gate insulating film can be further reduced.

[0035] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0036] 12: SiC substrate, 14: gate insulating film, 16: gate electrode, 24: trench, 42: silicon film, 44: silicon oxide layer

Claims

1. A method for manufacturing a MOS transistor, comprising: Etching the surface of the SiC substrate (12) by heating the SiC substrate in hydrogen gas; After the etching, the SiC substrate is heated in a gas containing hydrogen gas and a silicon source gas to a temperature lower than the heating temperature of the SiC substrate in the etching, thereby growing a silicon film (42) on the surface of the SiC substrate; forming a gate insulating film (44) made of silicon oxide on the surface of the silicon film; performing a nitrogen termination process on the SiC substrate after forming the gate insulating film; A manufacturing method comprising the steps of:

2. A trench (24) is provided in the main surface of the SiC substrate, The etching etches the side surface of the trench, In the step of growing the silicon film, the silicon film is grown on the side surface of the trench; In the step of forming the gate insulating film, the gate insulating film is formed on the surface of the silicon film covering the side surface of the trench. The method of claim 1.

3. The manufacturing method according to claim 1 , wherein the temperature of the SiC substrate is controlled to 1100° C. or less in the step of growing the silicon film.

4. 3. The manufacturing method according to claim 1, wherein in the step of growing the silicon film, the temperature of the SiC substrate is controlled to a temperature equal to or higher than the decomposition temperature of the silicon source gas.

5. The manufacturing method according to claim 1 or 2, wherein the silicon film has a thickness of 6 nm or less.

6. The manufacturing method according to claim 1 or 2, wherein the etching and the step of growing the silicon film are carried out in the same chamber.

7. 3. The manufacturing method according to claim 1, further comprising the steps of forming a sacrificial oxide film on the surface of the SiC substrate and then removing the sacrificial oxide film before the etching.

8. The manufacturing method according to claim 1 or 2, wherein the surface of the SiC substrate is a surface of an epitaxial layer.

9. 3. The manufacturing method according to claim 1, wherein in the step of forming the gate insulating film, the gate insulating film is formed by chemical vapor deposition.

10. 3. The manufacturing method according to claim 1, wherein the nitrogen termination treatment comprises heating the SiC substrate to a temperature of 1200° C. or higher in nitrogen gas or nitrogen oxide gas.

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