Semiconductor device

Abstract

To provide a semiconductor with a novel structure.SOLUTION: In a semiconductor device, a plurality of memory cells 200 are connected in series, and each of the memory elements (cells) includes first to third transistors 201-203 which include first to third gate electrodes, first to third source electrodes and first to third drain electrodes. The second transistor 202 contains an oxide semiconductor layer. The first gate electrode is electrically connected to one of the second source electrode and the second drain electrode, first wiring SL, the first source electrode and the third source electrode are electrically connected, second wiring BL, the first drain electrode and the third drain electrode are electrically connected, third wiring S1 is electrically connected to the other of the second source electrode and the second drain electrode, fourth wiring S2 is electrically connected to the second gate electrode, and fifth wiring WL is electrically connected to the third gate electrode.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The disclosed invention relates to a semiconductor device using a semiconductor element and a manufacturing method thereof. do. [Background technology]

[0002] Memory devices that use semiconductor elements are volatile memory devices that lose their contents when the power supply is cut off. and non-volatile memory devices, which retain their contents even when the power supply is cut off. can be.

[0003] A typical example of a volatile memory device is a DRAM (Dynamic Random Access Memory). DRAM is a memory element that can be selected from transistors. By storing charge in the capacitor, information is stored.

[0004] Based on the above principle, in DRAM, when information is read, the charge in the capacitor is lost. Therefore, every time data is read, a write operation is required again. The transistors that make up the transistors have leakage current, and when the transistors are not selected, Therefore, the data retention period is short. A write operation (refresh operation) is required, and power consumption must be reduced sufficiently. Furthermore, if the power supply is cut off, the memory contents are lost, making it difficult to store long-term memories. To store the data, a separate storage device using magnetic or optical materials is required.

[0005] Another example of a volatile memory device is SRAM (Static Random Access Memory). SRAM uses circuits such as flip-flops to store the memory contents. In order to retain data, no refresh operation is required, which is an advantage over DRAM. However, because it uses circuits such as flip-flops, the cost per unit of memory capacity is high. In addition, there is a problem that the memory contents are lost when the power supply is cut off. In this regard, it is no different from DRAM.

[0006] A typical example of a nonvolatile memory device is flash memory. A floating gate is provided between the gate electrode of the transistor and the channel forming region, Since memory is stored by holding an electric charge in the floating gate, the data retention period is extremely long. The advantage is that it lasts for a very long time (semi-permanent) and does not require the refresh operations required for volatile storage devices. The point is as follows (see, for example, Patent Document 1).

[0007] However, the gate insulating layer that constitutes the memory element is damaged by the tunnel current that occurs during writing. This causes a problem in that the memory element will stop functioning after a certain number of writes. To mitigate the effect of this problem, for example, the number of writes to each memory element is made uniform. However, to achieve this, complex peripheral circuits are required. However, even if such a method is adopted, the fundamental problem of lifespan will not be resolved. Therefore, flash memory is not suitable for applications where information needs to be rewritten frequently.

[0008] Also, to introduce or remove charge from the floating gate. High voltages are required for this purpose. Furthermore, the introduction and removal of charge takes a relatively long time. There is also the problem that it takes time to write and erase data, and it is not easy to speed up the writing and erasing. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 57-105889 Summary of the Invention [Problem to be solved by the invention]

[0010] In view of the above-mentioned problems, one embodiment of the disclosed invention provides a method for storing stored contents even when power is not supplied. To provide a semiconductor device having a new structure that can retain data and has no limit on the number of times it can be written. This is one of the purposes of the organization. [Means for solving the problem]

[0011] One embodiment of the present invention is a transistor formed using an oxide semiconductor and a transistor formed using other materials. The semiconductor device has a stacked structure with a transistor formed using the above-mentioned method. Such a configuration can be adopted.

[0012] One embodiment of the present invention is a semiconductor device including a first wiring (source line), a second wiring (bit line), and a third wiring. (first signal line), a fourth wiring (second signal line), and a fifth wiring (word line), A plurality of memory elements are connected in series between the first wiring and the second wiring. One of the elements is a first transistor having a first gate electrode, a first source electrode, and a first drain electrode. a first transistor, a second gate electrode, a second source electrode, and a second drain electrode; a second transistor having a third gate electrode, a third source electrode, and a third drain electrode; a third transistor having a drain electrode, the first transistor being made of a semiconductor material the second transistor includes an oxide semiconductor layer, and the first The gate electrode and one of the second source electrode and the second drain electrode are electrically connected. The first wiring (source line), the first source electrode, and the third source electrode are electrically connected to each other. The second wiring (bit line), the first drain electrode, and the third drain electrode are connected. , electrically connected to the third wiring (first signal line) and the second source electrode or the second drain The other of the gate electrodes is electrically connected to the fourth wiring (second signal line) and the second gate electrode. The fifth wiring (word line) and the third gate electrode are electrically connected. It is a semiconductor device connected to the

[0013] Another aspect of the present invention is a semiconductor device including a first wiring, a second wiring, a third wiring, and a fourth wiring. and a fifth wiring, and a plurality of memory elements are directly connected between the first wiring and the second wiring. A plurality of memory elements are connected in a column, and each memory element has a first gate electrode, a first source electrode, and a second a first transistor having a drain electrode, a second gate electrode, and a second source electrode; a second transistor having a second drain electrode and a capacitance element, The first transistor is disposed on a substrate including a semiconductor material, and the second transistor is disposed on an oxide semiconductor. a first gate electrode and a second source electrode or a second drain electrode; One of the electrodes is electrically connected to one of the electrodes of the capacitor element, and the first wiring and the first source The first drain electrode is electrically connected to the second wiring. The third wiring and the other of the second source electrode and the second drain electrode are electrically connected. The fourth wiring and the second gate electrode are electrically connected, and the fifth wiring and the capacitor The other electrode of the element is electrically connected to the semiconductor device.

[0014] In the above, the semiconductor device includes a sixth wiring, a seventh wiring, a sixth wiring, and a gate electrode. a fourth transistor electrically connected to a seventh wiring and a gate electrode; a fifth transistor electrically connected to the second wiring; The first drain electrode and the third drain electrode are electrically connected via the first wiring. The line is electrically connected to the first source electrode and the third source electrode through the fifth transistor. It is preferable that the power supply is connected to the power supply.

[0015] In the above, the first transistor is a channel transistor provided in a substrate including a semiconductor material. impurity regions provided so as to sandwich the channel forming region; a first gate insulating layer on the impurity region; a first gate electrode on the first gate insulating layer; and and a first source electrode and a first drain electrode electrically connected to the first transistor.

[0016] In the above, the second transistor has a second gate electrode on a substrate including a semiconductor material. a second gate insulating layer on the second gate electrode; and an oxide semiconductor layer on the second gate insulating layer. a second source electrode and a second drain electrode electrically connected to the oxide semiconductor layer; and,

[0017] In the above, the third transistor is a channel transistor provided in a substrate including a semiconductor material. impurity regions provided so as to sandwich the channel forming region; a third gate insulating layer on the impurity region; a third gate electrode on the third gate insulating layer; and and a third source electrode and a third drain electrode electrically connected to the first source electrode and the second drain electrode.

[0018] In the above, the substrate containing a semiconductor material may be a single crystal semiconductor substrate or an SOI substrate. It is preferable to use a plate, and it is particularly preferable that the semiconductor material is silicon.

[0019] In the above, the oxide semiconductor layer is made of an In-Ga-Zn-O based oxide semiconductor material. In particular, the oxide semiconductor layer preferably contains In2Ga2ZnO7 crystals. Furthermore, the hydrogen concentration of the oxide semiconductor layer is preferably 5×10 19 ato ms / cm 3 The off-state current of the second transistor is preferably 1× or less. 10 -13 It is preferable to set it to A or less.

[0020] In the above, the second transistor is provided in a region overlapping with the first transistor. The configuration can be as follows.

[0021] In this specification, the terms "above" and "below" refer to the positional relationship of the components "directly above" and "below." For example, the term "the first layer on the gate insulating layer" is not limited to "directly under" the first layer. The expression "gate electrode" means that other components are included between the gate insulating layer and the gate electrode. In addition, the terms "upper" and "lower" are merely expressions used for the convenience of explanation. Unless otherwise specified, the terms "top" and "bottom" are interchangeable.

[0022] In addition, in this specification, the terms "electrode" and "wiring" are used to refer to these components functionally. For example, an "electrode" may be used as part of a "wiring." Furthermore, the terms "electrode" and "wire" are used interchangeably to refer to the plural "electrodes." This also includes cases where "wires" and "circuits" are formed integrally.

[0023] Also, the functions of "source" and "drain" may differ depending on whether transistors with different polarities are used or not. However, they may be swapped when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" are used interchangeably. It is assumed that this is possible.

[0024] In this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a " is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects.

[0025] For example, "something that has some kind of electrical effect" includes not only electrodes and wiring, but also transistors. Switching elements such as transistors, resistive elements, inductors, capacitors, and other various devices This includes elements that have functions such as:

[0026] Generally, an "SOI substrate" is a substrate with a silicon semiconductor layer on an insulating surface. However, in this specification and the like, a semiconductor layer made of a material other than silicon is provided on an insulating surface. In other words, the semiconductor that "SOI substrate" has is used as a concept that includes the substrate with the structure. The layer is not limited to a silicon semiconductor layer. Not only semiconductor substrates such as silicon wafers, but also glass substrates, quartz substrates, sapphire substrates, and metal substrates In other words, it includes a conductive substrate with an insulating surface and a semiconductor substrate on an insulator substrate. The term "SOI substrate" broadly includes those having a layer made of a silicon material. In this document, "semiconductor substrate" does not only refer to a substrate made of semiconductor material, but also to a substrate made of semiconductor material. In other words, in this specification, the term "SOI substrate" is also used broadly. "Semiconductor substrate" is included in the category. [Effects of the Invention]

[0027] In one embodiment of the present invention, a transistor including a material other than an oxide semiconductor is provided in a lower portion, and A semiconductor device including a transistor including an oxide semiconductor is provided.

[0028] Since a transistor using an oxide semiconductor has an extremely small off-state current, It is possible to retain the memory contents for a much longer period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations to an extremely low level. Therefore, power consumption can be reduced sufficiently. , it is possible to retain the stored contents for a long period of time.

[0029] Furthermore, no high voltage is required to write information, and there is no problem of element degradation. Since information is written depending on the on / off state of the transistor, high-speed operation is also possible. This can be easily realized. In addition, it is possible to erase necessary information in flash memory, etc. There is also the advantage that the above operation is not required.

[0030] In addition, a transistor using a material other than an oxide semiconductor is Compared to the conventional memory, it can operate at a higher speed, so by using it, the contents of the memory can be It is possible to perform reading at high speed.

[0031] In this way, transistors using materials other than oxide semiconductors and transistors using oxide semiconductors By integrating a transistor, a semiconductor device with unprecedented features can be realized. It is possible. [Brief explanation of the drawings]

[0032] [Figure 1] Circuit diagram for explaining a semiconductor device [Figure 2] 1A and 1B are cross-sectional and plan views illustrating a semiconductor device; [Figure 3] 1A and 1B are cross-sectional views illustrating a manufacturing process of a semiconductor device; [Figure 4] 1A and 1B are cross-sectional views illustrating a manufacturing process of a semiconductor device; [Figure 5] 1A and 1B are cross-sectional views illustrating a manufacturing process of a semiconductor device; [Figure 6] 1 is a cross-sectional view illustrating a semiconductor device; [Figure 7] 1 is a cross-sectional view illustrating a semiconductor device; [Figure 8] 1 is a cross-sectional view illustrating a semiconductor device; [Figure 9] 1 is a cross-sectional view illustrating a semiconductor device; [Figure 10] Circuit diagram for explaining a semiconductor device [Figure 11] Block circuit diagram for explaining a semiconductor device [Figure 12] FIG. 1 is a timing chart of a write operation for explaining a semiconductor device; [Figure 13] Circuit diagram for explaining a semiconductor device [Figure 14] Block circuit diagram for explaining a semiconductor device [Figure 15] Circuit diagram for explaining a semiconductor device [Figure 16] Block circuit diagram for explaining a semiconductor device [Figure 17] Graph of the potential of the fifth wire WL and node A [Figure 18] Circuit diagram for explaining a semiconductor device [Figure 19] Circuit diagram for explaining a semiconductor device [Figure 20] Circuit diagram for explaining a semiconductor device [Figure 21] FIG. 1 is a diagram illustrating an electronic device using a semiconductor device. [Figure 22] Vertical cross-sectional view of an inverted staggered transistor using an oxide semiconductor [Figure 23] Energy band diagram (schematic diagram) at the A-A' cross section of Figure 22 [Figure 24] (A) A diagram showing the state when a positive potential (+VG) is applied to the gate (GE1), and (B) a diagram showing the state when a negative potential (-VG) is applied to the gate (GE1). [Figure 25] Diagram showing the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ) DETAILED DESCRIPTION OF THE INVENTION

[0033] An example of an embodiment of the present invention will be described below with reference to the drawings. and the present invention is not limited to the above description, and may be modified in various forms and forms without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. The present invention is not to be construed as being limited to the description of the embodiment shown in the accompanying drawings.

[0034] In addition, the position, size, range, etc. of each component shown in the drawings etc. are for ease of understanding. Therefore, the actual position, size, range, etc. may not necessarily be represented in the drawings, etc. The present invention is not limited to the position, size, range, etc. disclosed in the above.

[0035] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components. It should be noted that the numbers are added to avoid confusion and are not intended to limit the number.

[0036] (Embodiment 1) In this embodiment, a structure and a manufacturing method of a semiconductor device according to one embodiment of the disclosed invention will be described. This will be described with reference to FIGS.

[0037] <Circuit configuration of semiconductor device> FIG. 1 shows an example of a circuit configuration of a semiconductor device. The transistor 160 is made of a material and the transistor 162 is made of an oxide semiconductor. It is done.

[0038] Here, the gate electrode of transistor 160 and the source electrode or drain of transistor 162 are The first wiring SL (1st Li ne (also called a source line) and the source electrode of the transistor 160 are electrically connected, The second wiring BL (also called the bit line) and the drain of the transistor 160 The third wiring S1 (3rd Line) is electrically connected to the first electrode. 1 signal line) and the other of the source electrode and the drain electrode of the transistor 162. The fourth wiring S2 (also called the 4th Line: second signal line) and the The gate electrode of the transistor 162 is electrically connected.

[0039] The transistor 160 using a material other than an oxide semiconductor is a transistor using an oxide semiconductor. Compared to the conventional memory, it can operate at a higher speed, so by using it, the contents of the memory can be In addition, a transistor using an oxide semiconductor can be used. The transistor 162 has a feature of having an extremely small off-state current. By turning off the transistor 62, the potential of the gate electrode of the transistor 160 is maintained for a very long time. It is possible to maintain the

[0040] By utilizing the feature that the potential of the gate electrode can be maintained, It is possible to write, hold, and read data.

[0041] First, writing and holding of data will be described. First, the potential of the fourth wiring S2 is set to The transistor 162 is turned on as a potential at which the transistor 162 is turned on. As a result, the potential of the third wiring S1 is applied to the gate electrode of the transistor 160. After that, the potential of the fourth wiring S2 is set to 0 when the transistor 162 is turned off. By setting the potential of the transistor 160 to the value that is the same as the potential of the transistor 162, the transistor 162 is turned off. The potential of the gate electrode is maintained (retained).

[0042] Since the off-state current of the transistor 162 is extremely small, the gate electrode of the transistor 160 For example, if the potential of the gate electrode of transistor 160 is If the potential is such that the transistor 160 is turned on, the transistor 160 will remain on for a long time. The potential of the gate electrode of the transistor 160 is maintained for a certain period of time. If the potential is such that the transistor 160 is turned off, the transistor 160 will remain in the off state for a long time. is maintained over time.

[0043] Next, the reading of information will be described. As described above, when the transistor 160 is in the ON state, Alternatively, when the OFF state is maintained, a predetermined potential (low potential) is applied to the first wiring SL. When the transistor 160 is turned on or off, the second wiring BL For example, when the transistor 160 is turned on, the potential of the first wiring The potential of the second wiring BL decreases depending on the potential of the transistor SL. When 160 is in the off state, the potential of the second wiring BL does not change.

[0044] In this way, in the state where the information is held, the potential of the second wiring BL is compared with a predetermined potential. This allows the information to be read out.

[0045] Next, the rewriting of information will be described. That is, the potential of the fourth wiring S2 is held in the same manner as when the transistor 162 is turned on. The transistor 162 is turned on by applying a potential to the third wiring S A potential of 1 (a potential associated with new information) is applied to the gate electrode of the transistor 160 . After that, the potential of the fourth wiring S2 is set to a potential that turns off the transistor 162. By turning off the transistor 162, the new information is held.

[0046] In this way, the semiconductor device according to the disclosed invention can directly write information again. It is possible to rewrite information. This is why it is necessary for flash memory etc. This eliminates the need for an erase operation, and can suppress a decrease in operation speed due to the erase operation. That is, high-speed operation of the semiconductor device is realized.

[0047] The above explanation is for n-type transistors (n-channel transistors) in which electrons are the majority carriers. This is about using a large number of hole-capacitors instead of n-type transistors. It goes without saying that a p-type transistor can be used as a carrier.

[0048] <Plane and cross-sectional configurations of semiconductor device> 2A and 2B show an example of the configuration of the semiconductor device. 2(B) shows a plan view of the semiconductor device. These correspond to the cross sections taken along lines A1-A2 and B1-B2 in FIG. 2(A) and FIG. 2(B). The semiconductor device shown in FIG. 1 has a transistor 160 using a material other than an oxide semiconductor in the lower part. The transistor 162 includes an oxide semiconductor in the upper portion. Transistor 160 and transistor 162 are both described as n-type transistors. However, a p-type transistor may also be used. In particular, the transistor 160 is preferably a p-type transistor. It is easy to do this.

[0049] The transistor 160 includes a channel forming region 11 provided in a substrate 100 including a semiconductor material. 6, and the impurity region 114 and the high concentration impurity region 115 provided so as to sandwich the channel forming region 116. The pure region 120 (collectively referred to as the impurity region) and the channel forming region 11 6, and a gate electrode provided on the gate insulating layer 108. 110 and an impurity region 114 provided on one side of a channel forming region 116. The source electrode or drain electrode 130a to be connected and the other side of the channel forming region 116 a source electrode or drain electrode 130 electrically connected to the impurity region 114 provided in the It has b.

[0050] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110. In addition, the region of the substrate 100 that does not overlap the sidewall insulating layer 118 on the surface is provided with a high concentration The semiconductor device has an impurity region 120, and a metal compound region 124 exists on the high concentration impurity region 120. In addition, an element isolation insulating layer 106 is provided on the substrate 100 so as to surround the transistor 160. The transistor 160 is covered with an interlayer insulating layer 126 and an interlayer insulating layer 1 Through the openings formed in the interlayer insulating layer 126 and the interlayer insulating layer 128, Therefore, the source electrode or drain electrode 130a is disposed on one side of the channel forming region 116. The source electrode or the drain electrode 1 is electrically connected to the metal compound region 124 provided thereon. 30b is electrically connected to the metal compound region 124 provided on the other side of the channel forming region 116. That is, the source electrode or the drain electrode 130a is electrically connected to the channel forming The channel forming region 11 is connected to the metal compound region 124 provided on one side of the region 116. The high concentration impurity region 120 and the channel forming region 116 are provided on one side of the substrate 6. The source electrode or the drain electrode is electrically connected to the impurity region 114 provided on the side of the 130b is formed through the metal compound region 124 provided on the other side of the channel forming region 116. A high concentration impurity region 120 and a channel region 116 are provided on the other side of the channel region 116. The impurity region 114 is electrically connected to the other side of the channel forming region 116. The gate electrode 110 is provided with a source or drain electrode 130a and a source or drain electrode 130b. Alternatively, an electrode 130c provided similarly to the drain electrode 130b is electrically connected.

[0051] The transistor 162 using an oxide semiconductor has a gate electrode provided over the interlayer insulating layer 128. a gate insulating layer 138 provided on the gate electrode 136d; an oxide semiconductor layer 140 provided on the oxide semiconductor layer 138; a source electrode or drain electrode 142a electrically connected to the oxide semiconductor layer 140; and a source or drain electrode 142b.

[0052] Here, the gate electrode 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. Similarly to the gate electrode 136d, the transistor 16 Electrode 136a is in contact with the source or drain electrode 130a of transistor 160. Electrode 136b is in contact with the source or drain electrode 130b of 0, and electrode 136c is in contact with electrode 130c. Electrodes 136c are formed on the respective electrodes.

[0053] In addition, a protective film is formed on the transistor 162 so as to be in contact with part of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 are provided with a source electrode or a drain electrode. An opening is provided that reaches the source electrode 142a and the source or drain electrode 142b. Through the openings, the electrodes 150d and 150e are connected to the source and drain electrodes. The electrode 142a is formed in contact with the source electrode or the drain electrode 142b. As well as electrodes 150d and 150e, gate insulating layer 138, protective insulating layer 144, interlayer insulating layer The electrodes 136a, 136b, and 136c are in contact with each other through openings provided in the layer 146. Electrodes 150a, 150b, and 150c are formed.

[0054] Here, the oxide semiconductor layer 140 is highly purified by sufficiently removing impurities such as hydrogen. Specifically, the hydrogen concentration of the oxide semiconductor layer 140 is preferably 5×10 19 atoms / cm 3 Below 5×10 18 atoms / cm 3 Below, more hope Preferably 5 x 10 17 atoms / cm 3 In addition, the hydrogen concentration is sufficiently reduced. The oxide semiconductor layer 140 is highly purified by the above method, and is not affected by the effects of a general silicon wafer (such as phosphorus or boron). The carrier concentration (1×10 1 4 / cm 3 The carrier concentration is sufficiently small compared to the hydrogen An oxide semiconductor that has been sufficiently reduced in concentration and highly purified to be i-type or substantially i-type By using the above, the transistor 162 can have excellent off-state current characteristics. For example, when the drain voltage Vd is +1V or +10V, and the gate voltage Vg is - In the range of 5V to -20V, the off-state current is 1×10 -13 A or less. The oxide semiconductor layer 140 is highly purified by sufficiently reducing the elemental concentration, and a transistor is formed using the oxide semiconductor layer 140. By reducing the off-current of 162, a semiconductor device with a new configuration can be realized. The hydrogen concentration in the oxide semiconductor layer 140 was measured by secondary ion mass spectrometry (SIM). S: Secondary Ion Mass Spectroscopy) That is why.

[0055] An insulating layer 152 is provided on the interlayer insulating layer 146, and a buried insulating layer 152 is provided on the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so that the electrodes are embedded in the Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150a. b, electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 54d is in contact with electrode 150e.

[0056] That is, in the semiconductor device shown in FIG. 2, the gate electrode 110 of the transistor 160 and the The source electrode or drain electrode 142a of the transistor 162 is connected to the electrode 130c, the electrode 1 36c, electrode 150c, electrode 154c and electrode 150d. do.

[0057] <Method for manufacturing semiconductor device> Next, an example of a method for manufacturing the semiconductor device will be described. The method for fabricating the transistor 160 will be explained with reference to FIG. A method for manufacturing the capacitor 162 will be described with reference to FIGS.

[0058] <Method for manufacturing the lower transistor> First, a substrate 100 containing a semiconductor material is prepared (see FIG. 3(A)). The plate 100 may be a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. Compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be used. Here, the substrate 100 containing a semiconductor material is a single crystal silicon substrate. An example will be given below.

[0059] A protective layer 102 is formed on the substrate 100 to serve as a mask for forming an element isolation insulating layer. (See FIG. 3(A)). The protective layer 102 may be made of, for example, silicon oxide or silicon nitride. An insulating layer made of silicon nitride oxide or the like can be used. In order to control the threshold voltage of the transistor, impurities that give n-type conductivity are used. The substrate 100 may be doped with an impurity element that imparts p-type conductivity or a metal element that imparts p-type conductivity. In the case of silicon, impurities that give n-type conductivity include phosphorus and arsenic. In addition, impurities that impart p-type conductivity include, for example, boron and aluminum. Sodium, gallium, etc. can be used.

[0060] Next, etching is performed using the protective layer 102 as a mask, and the The part of the substrate 100 in the uncovered area (exposed area) is removed. The semiconductor region 104 is formed by etching (see FIG. 3(B)). It is preferable to use etching, but wet etching may also be used. The etching gas and etching solution can be appropriately selected depending on the material to be etched.

[0061] Next, an insulating layer is formed so as to cover the semiconductor region 104, and the region overlapping the semiconductor region 104 is The insulating layer is selectively removed to form an element isolation insulating layer 106 (see FIG. 3(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon nitride oxide, etc. The insulating layer can be removed by polishing such as CMP or etching. After the semiconductor region 104 is formed or after the element isolation insulating film is formed, After the layer 106 is formed, the protective layer 102 is removed.

[0062] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. do.

[0063] The insulating layer will later become the gate insulating layer and is obtained using a CVD method, sputtering method, etc. Silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide It is preferable to use a single layer or multilayer structure of a film containing aluminum, tantalum oxide, etc. The surface of the semiconductor region 104 is oxidized or nitrided by plasma treatment or thermal oxidation treatment. The insulating layer may be formed by the high density plasma treatment. Using a mixture of rare gases such as Xe and oxygen, nitrogen oxide, ammonia, nitrogen, and hydrogen The thickness of the insulating layer is not particularly limited, but may be, for example, 1 nm or more and 10 nm or less. It can be 0 nm or less.

[0064] The layer containing the conductive material is made of a metal material such as aluminum, copper, titanium, tantalum, or tungsten. Also, the insulating film can be formed using a semiconductor material such as polycrystalline silicon containing a conductive material. The method for forming the conductive material is not particularly limited, and examples thereof include vapor deposition, C Various film formation methods such as VD method, sputtering method, and spin coating method can be used. In this embodiment mode, the layer containing a conductive material is formed using a metal material. The following information will be provided.

[0065] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108. Then, the gate electrode 110 is formed (see FIG. 3(C)).

[0066] Next, an insulating layer 112 is formed to cover the gate electrode 110 (see FIG. 3(C)). Phosphorus (P) or arsenic (As) is added to the conductive region 104 to form a shallow junction with the substrate 100. In this case, an n-type transistor is formed. However, when forming a p-type transistor, Impurity elements such as boron (B) and aluminum (Al) can be added. By forming the region 114, a channel-forming region is formed below the gate insulating layer 108 in the semiconductor region 104. A region 116 is formed (see FIG. 3C). Here, the concentration of the added impurity is set appropriately. However, when semiconductor elements are highly miniaturized, the concentration can be increased. In this case, the impurity region 114 is formed after the insulating layer 112 is formed. However, the process of forming the insulating layer 112 after forming the impurity region 114 is adopted. It is also possible to do so.

[0067] Next, a sidewall insulating layer 118 is formed (see FIG. 3(D)). The layer 118 is formed by forming an insulating layer to cover the insulating layer 112 and then applying a highly anisotropic By applying a simple etching process, it can be formed in a self-aligned manner. Then, the insulating layer 112 is partially etched to expose the upper surface of the gate electrode 110 and the impurity region 1 It is advisable to expose the top surface of 14.

[0068] Next, a layer is formed so as to cover the gate electrode 110, the impurity region 114, the sidewall insulating layer 118, etc. An insulating layer is formed on the impurity region 114. Then, phosphorus ( By adding ions such as P and arsenic (As), a high concentration impurity region 120 is formed (see FIG. 3(E)). After that, the insulating layer is removed, and the gate electrode 110, the sidewall insulating layer 118, A metal layer 122 is formed so as to cover the high concentration impurity region 120 and the like (see FIG. 3(E)). The metal layer 122 can be formed by various film forming methods such as vacuum deposition, sputtering, and spin coating. The metal layer 122 can be formed using the semiconductor material that constitutes the semiconductor region 104. It is desirable to form the electrode using a metal material that reacts with the electrode to form a low-resistance metal compound. Such metal materials include, for example, titanium, tantalum, tungsten, nickel, and cobalt. Examples include platinum and platinum.

[0069] Next, a heat treatment is performed to react the metal layer 122 with the semiconductor material. A metal compound region 124 is formed in contact with the high concentration impurity region 120 (see FIG. 3(F)). When polycrystalline silicon or the like is used as the gate electrode 110, the gate electrode 110 A metal compound region is also formed in the portion in contact with the metal layer 122.

[0070] The heat treatment may be, for example, a heat treatment by irradiation with a flash lamp. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds In order to improve the controllability of the heat treatment, it is desirable to use a method that can realize a very short time of heat treatment. The metal compound region is preferably formed by a reaction between a metal material and a semiconductor material. The metal compound region is formed in a region where the conductivity is sufficiently increased. This can sufficiently reduce the electrical resistance and improve the device characteristics. After forming region 124, metal layer 122 is removed.

[0071] Next, an interlayer insulating layer 126 and an interlayer insulating layer 127 are formed to cover the respective components formed by the above-described steps. The interlayer insulating layer 126 and the interlayer insulating layer 128 are formed by oxidation. Silicon, silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide, titanium oxide The insulating layer can be formed using a material containing an inorganic insulating material such as palladium. It is also possible to form the insulating layer using an organic insulating material such as acrylic. Although the structure is a two-layer structure of an edge layer 126 and an interlayer insulating layer 128, the structure of the interlayer insulating layer is not limited to this. After the interlayer insulating layer 128 is formed, the surface is not subjected to a CMP or etching process. Therefore, it is desirable to flatten it.

[0072] Thereafter, an opening is formed in the interlayer insulating layer so as to reach the metal compound region 124. The source or drain electrode 130a and the source or drain electrode 130b are The source or drain electrode 130a and the source or drain electrode 130b are formed (see FIG. 3(H)). The drain electrode 130b is formed by, for example, using a PVD method or a CVD method in the region including the opening. After forming the conductive layer, a part of the conductive layer is removed by etching or CMP. It can be formed by removing the

[0073] In addition, a part of the conductive layer is removed to form the source electrode or drain electrode 130a and the source electrode Alternatively, when forming the drain electrode 130b, the surface thereof is processed to be flat. For example, after forming a thin titanium film or titanium nitride film in the region including the opening, When a tungsten film is formed to fill the opening, the inclusions are removed by the subsequent CMP. It removes the necessary tungsten film, titanium film, titanium nitride film, etc., and also maintains the flatness of the surface. In this way, the source electrode or drain electrode 130a, By planarizing the surface including the source or drain electrode 130b, it is possible to This makes it possible to form good electrodes, wiring, insulating layers, semiconductor layers, and the like.

[0074] Here, the source electrode or drain electrode 130 in contact with the metal compound region 124 Although only the gate electrode 130a and the source electrode or the drain electrode 130b are shown, The electrode in contact with the port electrode 110 (for example, the electrode 130c in FIG. 2) is also formed. The source or drain electrode 130a, the source or drain electrode There are no particular limitations on the material that can be used for the electrode 130b, and various conductive materials can be used. For example, molybdenum, titanium, chromium, tantalum, tungsten, Conductive materials such as aluminum, copper, neodymium, and scandium can be used.

[0075] In this manner, the transistor 160 is formed using the substrate 100 containing a semiconductor material. After the above steps, electrodes, wiring, insulating layers, etc. may be further formed. In addition, by adopting a multilayer wiring structure consisting of a laminated structure of interlayer insulating layers and conductive layers, Therefore, it is possible to provide a highly integrated semiconductor device.

[0076] <How to make the upper transistor> Next, referring to FIGS. 4 and 5, a process for forming a transistor 162 on the interlayer insulating layer 128 will be described. 4 and 5 show various electrodes and transistors on the interlayer insulating layer 128. Since the figure shows the manufacturing process of the transistor 162, the The transistor 160 and other components that correspond to it are omitted.

[0077] First, an interlayer insulating layer 128, a source electrode or drain electrode 130a, and a source electrode or drain electrode 130b are formed. An insulating layer 132 is formed on the drain electrode 130b and the electrode 130c (see FIG. 4(A)). The edge layer 132 can be formed by using a PVD method, a CVD method, or the like. silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide The insulating film 10 can be formed using a material containing an inorganic insulating material such as silica.

[0078] Next, the source or drain electrode 130a, the source or drain electrode 130b, and the insulating layer 132 are Openings are formed that reach the drain electrode 130b and the electrode 130c. An opening is also formed in the region where the gate electrode 136d is to be formed. A conductive layer 134 is formed to fill the opening (see FIG. 4B). The mask can be formed by a method such as etching using a photomask. It can be formed by exposure or other methods. Wet etching is also used. Either etching or dry etching may be used, but from the viewpoint of fine processing, dry etching is preferred. The conductive layer 134 is preferably formed by a deposition method such as PVD or CVD. The conductive layer 134 can be formed by a film method. , molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium Conductive materials such as ZnO, ZnS, and scandium, as well as alloys and compounds thereof (e.g., nitrides), are examples of such materials. can be done.

[0079] More specifically, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then CV After forming a thin titanium nitride film by the D method, a tungsten film is formed to fill the opening. Here, the titanium film formed by the PVD method is The outer electrode (here, the source electrode or the drain electrode 130a, the source electrode or the drain electrode The oxide film at the interface with the lower electrode (electrode 130b, electrode 130c, etc.) is reduced to reduce the contact resistance with the lower electrode. The titanium nitride film formed afterwards also serves to reduce the diffusion of conductive materials. It also has a barrier function that suppresses the formation of a barrier film made of titanium or titanium nitride. After that, a copper film may be formed by plating.

[0080] After the conductive layer 134 is formed, the conductive layer 13 is removed by etching, CMP, or other methods. 4 is removed to expose the insulating layer 132, and the electrodes 136a, 136b, and 13 6c, a gate electrode 136d is formed (see FIG. 4(C)). The electrode 136a, the electrode 136b, the electrode 136c, and the gate electrode 136d are formed by removing the portions. When forming the insulating layer 132, it is desirable to process it so that the surface is flat. , the surfaces of the electrodes 136a, 136b, 136c, and gate electrode 136d are planarized. This allows for the formation of good electrodes, wiring, insulating layers, semiconductor layers, etc. in subsequent processes. This makes it possible to:

[0081] Next, the insulating layer 132, the electrode 136a, the electrode 136b, the electrode 136c, and the gate electrode 136d The gate insulating layer 138 is formed to cover the gate insulating layer 138 (see FIG. 4(D)). The gate insulating layer can be formed by using a CVD method, a sputtering method, or the like. 138 is silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, oxide It is preferable to form the gate insulating film so as to contain hafnium, tantalum oxide, etc. The layer 138 may have a single layer structure or a multilayer structure. Silicon oxynitride was produced by plasma CVD using silane (SiH4), oxygen, and nitrogen. The thickness of the gate insulating layer 138 is not particularly limited. However, it can be, for example, 10 nm or more and 500 nm or less. For example, a first gate insulating layer having a film thickness of 50 nm or more and 200 nm or less and a first gate insulating layer It is preferable to laminate a second gate insulating layer having a thickness of 5 nm to 300 nm on the layer.

[0082] Note that an oxide semiconductor (high-temperature oxide semiconductor) that has been made i-type or substantially i-type by removing impurities is Since the purified oxide semiconductor is extremely sensitive to the interface states and the interface charges, When such an oxide semiconductor is used for the oxide semiconductor layer, the interface with the gate insulating layer is important. That is, the gate insulating layer 138 in contact with the highly purified oxide semiconductor layer has a high-quality oxide semiconductor layer. Quality will be required.

[0083] For example, the high density plasma CVD method using microwaves (2.45GHz) produces dense and high dielectric strength materials. This is advantageous in that a high quality gate insulating layer 138 can be formed. The close contact between the conductor layer and the high-quality gate insulating layer reduces the interface state density and improves the interface characteristics. This is because it is possible to improve the

[0084] Of course, if it can form a good insulating layer as a gate insulating layer, highly purified Even when an oxide semiconductor layer is used, other methods such as sputtering and plasma CVD are used. In addition, the film quality and the oxide semiconductor layer can be improved by heat treatment after the formation. Alternatively, an insulating layer may be applied to modify the interface properties of the gate insulating layer 138. The film quality as a gate insulating film is good, and the interface state density with the oxide semiconductor layer is reduced, resulting in a good interface. All that is required is to form something that can form a surface.

[0085] Furthermore, at 85°C, 2 × 10 6 V / cm, 12-hour gate bias thermal stress test (B In the T test, when impurities are added to an oxide semiconductor, the impurities and the oxide semiconductor The bond with the main component of is broken by a strong electric field (B: bias) and high temperature (T: temperature), and The dangling bonds induce a shift in the threshold voltage (Vth).

[0086] In response to this, impurities in the oxide semiconductor, especially hydrogen and water, are eliminated as much as possible, and the gate electrode is By improving the interface characteristics with the base insulating layer, a stable transistor is produced even during BT tests. It is possible to obtain data.

[0087] Next, an oxide semiconductor layer is formed over the gate insulating layer 138 and etched using a mask. The oxide semiconductor layer is processed by the above method to form an island-shaped oxide semiconductor layer 140. (See FIG. 4(E)).

[0088] The oxide semiconductor layer includes In-Ga-Zn-O, In-Sn-Zn-O, and In-A l-Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn -O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn- It is preferable to use an O-based or Zn—O-based oxide semiconductor layer, especially an amorphous oxide semiconductor layer. In this embodiment, an In—Ga—Zn—O-based oxide semiconductor is formed as the oxide semiconductor layer. An amorphous oxide semiconductor layer is formed by a sputtering method using a target for sputtering. Note that by adding silicon to the oxide semiconductor layer, crystallization of the oxide semiconductor layer can be suppressed. Therefore, for example, oxidation can be performed using a target containing 2% to 10% by weight of SiO2. A compound semiconductor layer may be formed.

[0089] Examples of targets for forming an oxide semiconductor layer by sputtering include oxide A target for forming an oxide semiconductor film containing zinc as a main component can be used. A target for forming oxide semiconductor films containing Ga and Zn (composition ratio: In2O3:G It is also possible to use In As a target for forming oxide semiconductor films containing In2O3:Ga2O 3:ZnO=1:1:2 [molar ratio], or In2O3:Ga2O3:ZnO=1: A target having a composition ratio of 1:4 (molar ratio) may also be used. The filling rate of the film target is 90% or more and 100% or less, preferably 95% or more (for example, 99 By using a target for oxide semiconductor film formation with a high filling rate, Thus, an oxide semiconductor layer is formed.

[0090] The oxide semiconductor layer is formed in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or Alternatively, it is preferable to use a mixed atmosphere of rare gas (typically argon) and oxygen. In practice, the concentration of impurities such as hydrogen, water, hydroxyl groups, or hydrides is about several ppm ( It is preferable to use a high purity gas with a purity reduced to about several ppb.

[0091] When forming the oxide semiconductor layer, the substrate is held in a treatment chamber kept in a reduced pressure state. The temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating, the impurity concentration in the oxide semiconductor layer can be reduced. Damage caused by sputtering can also be reduced. The residual moisture in the metal oxide layer is removed, and a sputtering gas from which hydrogen and water have been removed is introduced. The oxide semiconductor layer is formed using a target of It is preferable to use an adsorption type vacuum pump. For example, a cryopump or an ion pump A titanium sublimation pump can be used. A cryopump with a cold trap may be used. The deposition chamber is filled with, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) (preferably Since the oxide semiconductor formed in the film formation chamber is exhausted, The concentration of impurities contained in the layer can be reduced.

[0092] The formation conditions are, for example, a distance of 100 mm between the substrate and the target, a pressure of 0.6 Pa, DC power 0.5kW, oxygen atmosphere (oxygen flow rate 100%), The following conditions can be applied. When a pulsed direct current (DC) power supply is used, film formation can be performed. This reduces the amount of powdery material (also called particles or dust) that is generated at times, and the film thickness distribution is uniform. The thickness of the oxide semiconductor layer is preferably 2 nm or more and 200 nm or less, more preferably 5 nm or less. The thickness is from 100 nm to 30 nm. The appropriate thickness varies depending on the oxide semiconductor material used. Therefore, the thickness may be appropriately selected depending on the material used.

[0093] Before forming the oxide semiconductor layer by sputtering, argon gas was introduced to Reverse sputtering is performed to generate a smear, and dust adhering to the surface of the gate insulating layer 138 is removed. Here, the reverse sputtering is a method of removing the sputtering Instead of bombarding the target with ions, the treatment surface is bombarded with ions. The method of bombarding the treated surface with ions is as follows: A high frequency voltage is applied to the surface to be treated in an argon atmosphere to generate plasma near the substrate. In addition, nitrogen atmosphere, helium atmosphere, oxygen atmosphere, etc. can be used instead of argon atmosphere. An atmosphere or the like may also be used.

[0094] The oxide semiconductor layer can be etched by either dry etching or wet etching. Of course, both can be used in combination. To enable matching, etching conditions (etching gas, etching solution, etc.) are set according to the material. The etching time, temperature, etc. are set appropriately.

[0095] The etching gas used in dry etching is, for example, a gas containing chlorine (chlorine-based gas, For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride ( CCl4) and other gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride). Fluorine (CF4), sulfur fluoride (SF6), nitrogen fluoride (NF3), trifluoromethane (CHF 3), hydrogen bromide (HBr), oxygen (O2), and the addition of helium (He) or argon A gas containing a rare gas such as argon (Ar) may also be used.

[0096] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A plasma-coupled plasma etching method can be used. As shown in the figure, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) The amount of power, the temperature of the electrode on the substrate, etc. are set appropriately.

[0097] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) or the like may be used.

[0098] Next, the oxide semiconductor layer is preferably subjected to first heat treatment. The oxide semiconductor layer can be dehydrated or dehydrogenated by the first heat treatment. The temperature is set to 300°C or higher and 750°C or lower, preferably 400°C or higher and lower than the strain point of the substrate. For example, The substrate is placed in an electric furnace using a resistance heating element or the like, and the oxide semiconductor layer 140 is heated in a nitrogen atmosphere. Heat treatment is performed at 450° C. in air for 1 hour. Avoid contact and ensure that water or hydrogen is not recontaminated.

[0099] The heat treatment device is not limited to an electric furnace, and may be any device that uses heat conduction from a medium such as heated gas, or It may also be a device that heats the object to be treated by thermal radiation. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be equipped with halogen lamps, metal halide lamps, etc. Lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure water A device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp such as a silver lamp. The GRTA device is a device that performs heat treatment using high-temperature gas. An inert gas that does not react with the material to be treated by heat treatment, such as a rare gas such as argon or nitrogen. A gas is used.

[0100] For example, in the first heat treatment, the substrate is immersed in an inert gas heated to a high temperature of 650°C to 700°C. After heating for several minutes, the substrate is taken out of the inert gas (GRTA) treatment. GRTA treatment allows high-temperature heat treatment in a short time. Because it is a heat treatment, it can be applied even at temperatures exceeding the distortion point of the substrate.

[0101] The first heat treatment is performed in a gas atmosphere containing nitrogen or a rare gas (helium, neon, argon, etc.) as the main component. It is desirable to carry out the process in an atmosphere that does not contain water, hydrogen, etc. The purity of nitrogen or rare gases such as helium, neon, and argon introduced into the heat treatment device is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e. The impurity concentration is 1 ppm or less, preferably 0.1 ppm or less.

[0102] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be crystallized. For example, the crystallinity may be 90% or more, or 80% or more. % or more of a microcrystalline oxide semiconductor layer. Depending on the material of the oxide semiconductor layer, it may become an amorphous oxide semiconductor layer that does not contain crystalline components. There are also cases where this is the case.

[0103] In addition, microcrystals (grain size of 1 nm or less) are formed on the amorphous oxide semiconductor (for example, on the surface of the oxide semiconductor layer). The oxide semiconductor layer is a mixture of the upper 20 nm or less (typically 2 nm to 4 nm). There are cases like this.

[0104] In addition, the electrical characteristics of the oxide semiconductor layer can be changed by arranging microcrystals in the amorphous state. For example, an In-Ga-Zn-O oxide semiconductor film formation target can be used. When forming an oxide semiconductor layer using In2Ga2ZnO7 By forming a microcrystalline portion in which the crystal grains are oriented, the electrical characteristics of the oxide semiconductor layer can be changed. It is possible.

[0105] More specifically, for example, the c-axis of In2Ga2ZnO7 is perpendicular to the surface of the oxide semiconductor layer. By orienting the oxide semiconductor layer in this direction, the conductivity in the direction parallel to the surface of the oxide semiconductor layer is improved. This can improve the insulating properties in the direction perpendicular to the surface of the oxide semiconductor layer. The microcrystalline portion has a function of suppressing the penetration of impurities such as water and hydrogen into the oxide semiconductor layer. It has.

[0106] The oxide semiconductor layer having the above-described microcrystalline portion is formed by GRTA treatment. It can be formed by surface heating. Also, the content of Zn is higher than the content of In or Ga. A more suitable formation can be achieved by using a smaller sputtering target.

[0107] The first heat treatment on the oxide semiconductor layer 140 is performed to process the oxide semiconductor layer 140 into an island-shaped oxide semiconductor layer 140. In this case, the first heat treatment is performed on the oxide semiconductor layer. The substrate is then removed and subjected to a photolithography process.

[0108] The first heat treatment has the effect of dehydrating and dehydrogenating the oxide semiconductor layer 140. Therefore, it can also be called dehydration treatment, dehydrogenation treatment, etc. The hydrogenation treatment is carried out after forming the oxide semiconductor layer, by forming a source electrode or a drain electrode on the oxide semiconductor layer 140. After laminating the source electrode and drain electrode, a protective insulating layer is formed on the source electrode or drain electrode. In addition, such dehydration treatment, dehydration The oxidation treatment may be carried out not only once but also multiple times.

[0109] Next, a source electrode or drain electrode 142a, The source or drain electrode 142b is formed (see FIG. 4(F)). The drain electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 1 After forming a conductive layer to cover 40, the conductive layer is selectively etched. It can be formed.

[0110] The conductive layer is formed using PVD methods such as sputtering, or CVD methods such as plasma CVD. The conductive layer can be formed using a material such as aluminum, chromium, copper, An element selected from tantalum, titanium, molybdenum, and tungsten, or the above-mentioned elements Alloys containing manganese, magnesium, zirconium, and beryllium can be used. Alternatively, one or more materials selected from the group consisting of arsenic, thorium, and arsenic may be used. Aluminum, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scum A material containing a single element selected from the group consisting of indium and gallium may also be used. It may be a single layer structure or a laminated structure of two or more layers. a single-layer structure of an aluminum film containing titanium; a two-layer structure with a titanium film laminated on an aluminum film; One example is a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated.

[0111] Here, the exposure to light when forming the mask used for etching is ultraviolet light, KrF laser light, or ArF Preferably, a laser beam is used.

[0112] The channel length (L) of the transistor is the distance from the bottom end of the source or drain electrode 142a to the , is determined by the distance between the lower end of the source electrode or drain electrode 142b. When exposure is performed with a channel length (L) of less than 25 nm, the channel length is extremely small, ranging from several nm to several tens of nm. Extreme ultraviolet light with extremely short wavelengths is used to create a mask-shaped Extreme ultraviolet light exposure provides high resolution and a large depth of focus. The channel length (L) of the formed transistor is set to 10 nm or more and 1000 nm or less. Furthermore, the off-state current is extremely small, This avoids a large power consumption.

[0113] When etching the conductive layer, the oxide semiconductor layer 140 is not removed. The materials and etching conditions are adjusted appropriately. In this step, a part of the oxide semiconductor layer 140 is etched to form a groove (a recess ) may be formed as an oxide semiconductor layer.

[0114] In addition, between the oxide semiconductor layer 140 and the source electrode or the drain electrode 142a, An oxide conductive layer is formed between the conductive layer 140 and the source or drain electrode 142b. The oxide conductive layer and the source or drain electrode 142a or the source or drain electrode 142b may be The metal layer for forming the drain electrode 142b is formed continuously (continuous film formation). The oxide conductive layer can function as a source region or a drain region. By providing such an oxide conductive layer, it is possible to reduce the resistance of the source region or the drain region. This allows the transistor to operate at high speed.

[0115] In order to reduce the number of masks used and the number of processes, an exposure method is used in which the transmitted light has multiple intensities. A resist mask is formed using a multi-tone mask, which is a mask, and an etching process is performed using this. The resist mask formed using the multi-tone mask has a plurality of thicknesses. The shape becomes stepped, and the shape can be further deformed by ashing. It can be used for multiple etching processes to process different patterns. A multi-tone mask allows for resist masks that correspond to at least two different patterns. Therefore, the number of exposure masks can be reduced, and the corresponding photomasks can be formed. The lithography process can also be eliminated, simplifying the process.

[0116] After the above process, plasma treatment using gas such as N2O, N2, or Ar may be performed. It is preferable that the plasma treatment is performed on the exposed surface of the oxide semiconductor layer. Adhered water and other substances are removed. In addition, plasma treatment is performed using a mixture of oxygen and argon gas. You may go.

[0117] Next, the protective insulating layer 14 in contact with a part of the oxide semiconductor layer 140 is removed without being exposed to the air. 4 is formed (see Figure 4(G)).

[0118] The protective insulating layer 144 is formed by a method such as sputtering, which does not mix impurities such as water or hydrogen into the protective insulating layer 144. The thickness of the insulating film is 1 nm or more. Examples of materials that can be used for the protective insulating layer 144 include silicon oxide, silicon nitride, and silicon oxynitride. The structure may be a single layer structure or a multilayer structure. The substrate temperature when the protective insulating layer 144 is formed is set to be equal to or higher than room temperature and equal to or lower than 300° C. The atmosphere is preferably a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare A mixed atmosphere of gas (typically argon) and oxygen is preferred.

[0119] If hydrogen is contained in the protective insulating layer 144, the hydrogen may penetrate into the oxide semiconductor layer or the oxide semiconductor layer may be damaged by the hydrogen. Oxygen is extracted from the oxide semiconductor layer by the oxide semiconductor layer. Therefore, the protective insulating layer 1 may have a low resistance and a parasitic channel may be formed. It is important to avoid using hydrogen in the formation method so that 44 does not contain as much hydrogen as possible. is.

[0120] In addition, it is preferable to form the protective insulating layer 144 while removing residual moisture in the processing chamber. The compound semiconductor layer 140 and the protective insulating layer 144 are formed so as not to contain hydrogen, hydroxyl groups, or water. This is because.

[0121] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen atoms and water (H2 O) and other compounds containing hydrogen atoms are removed, The concentration of impurities contained in the layer 144 can be reduced.

[0122] The sputtering gas used when forming the protective insulating layer 144 is hydrogen, water, a hydroxyl group, or The concentration of impurities such as hydrides is reduced to a few ppm (preferably a few ppb). It is preferable to use a high purity gas.

[0123] Then, a second heat treatment (preferably 20 It is desirable to carry out the heating at a temperature of 0°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. Then, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. This can reduce variations in the electrical characteristics of the transistors.

[0124] In addition, even if heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours, This heat treatment can be carried out by maintaining a constant heating temperature, or by heating from room temperature to 100°C or higher. Repeat the heating process several times to a temperature of 200°C or less and then to room temperature. This heat treatment may also be carried out under reduced pressure before the formation of the protective insulating layer. When the heat treatment is performed under reduced pressure, the heating time can be shortened. This may be carried out instead of the second heat treatment, or may be carried out before or after the second heat treatment.

[0125] Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see FIG. 5(A)). The edge layer 146 can be formed by using a PVD method, a CVD method, or the like. silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide The interlayer insulating layer 146 can be formed using a material containing an inorganic insulating material such as silica. After that, it is desirable to flatten the surface by a method such as CMP or etching. It's nice.

[0126] Next, the electrode 1 is formed on the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138. 36a, electrode 136b, electrode 136c, source or drain electrode 142a, source An opening is formed so as to reach the electrode or drain electrode 142b, and a conductive layer is formed so as to be embedded in the opening. A conductive layer 148 is formed (see FIG. 5B). The opening is formed by etching using a mask or the like. The mask can be formed by a method such as exposure using a photomask. The etching can be wet etching or dry etching. However, from the viewpoint of fine processing, it is recommended to use dry etching. The conductive layer 148 is preferably formed by a film forming method such as a PVD method or a CVD method. Materials that can be used to form the conductive layer 148 include molybdenum, titanium, and the like. Tantalum, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. Examples include any conductive material, their alloys, and compounds (e.g., nitrides).

[0127] Specifically, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then a CVD method is applied. After forming a thin titanium nitride film by this method, a tungsten film is formed so as to fill the opening. Here, the titanium film formed by the PVD method is Electrodes (here, electrode 136a, electrode 136b, electrode 136c, source electrode or drain electrode) The oxide film at the interface with the electrode 142a, the source electrode or the drain electrode 142b is reduced. The titanium nitride formed after that has the function of reducing the contact resistance with the external electrode. It has a barrier function that suppresses the diffusion of conductive materials. After forming the barrier film, a copper film may be formed by plating.

[0128] After the conductive layer 148 is formed, the conductive layer 148 is removed by etching, CMP, or other methods. A portion of the interlayer insulating layer 146 is removed to expose the electrodes 150a, 150b, and 150c. Electrode 150c, electrode 150d, and electrode 150e are formed (see FIG. 5(C)). 48 is removed to form electrodes 150a, 150b, 150c, 150d, and When forming 150e, it is desirable to process it so that the surface is flat. Next, an interlayer insulating layer 146, an electrode 150a, an electrode 150b, an electrode 150c, an electrode 150d, an electrode By flattening the surface of the electrode 150e, it is possible to obtain good electrodes, wiring, and insulation in the subsequent processes. It is possible to form a layer, a semiconductor layer, etc.

[0129] Furthermore, an insulating layer 152 is formed, and the electrodes 150a, 150b, and 150c are attached to the insulating layer 152. 50c, the electrode 150d, and the electrode 150e are formed, and the insulating layer 150 is embedded in the opening. After forming the conductive layer as shown above, a part of the conductive layer is removed by a method such as etching or CMP. , the insulating layer 152 is exposed, and the electrodes 154a, 154b, 154c, and 154 This step is the same as that for forming the electrodes 150a and the like. So I will omit the details.

[0130] When the transistor 162 is manufactured by the above method, the hydrogen concentration in the oxide semiconductor layer 140 is Degrees are 5 x 10 19 atoms / cm 3 and the off-current of the transistor 162 is is 1 x 10 -13 A or less. In this way, the hydrogen concentration is sufficiently reduced and the resulting product is highly purified. By using the oxide semiconductor layer 140, the transistor 162 can have excellent characteristics. In addition, a transistor 160 using a material other than an oxide semiconductor is provided in the lower portion, and A semiconductor device with excellent characteristics having a transistor 162 using an oxide semiconductor in a portion thereof is manufactured. It is possible.

[0131] In addition, examples of semiconductor materials that can be compared with oxide semiconductors include silicon carbide (e.g., 4H Oxide semiconductors and 4H-SiC have several things in common. The intrinsic carrier density of oxide semiconductors at room temperature is 10 -7 / cm 3 This is estimated to be about 6.7 × 10 in 4H-SiC. -11 / cm 3 and This is also an extremely low value. The intrinsic carrier density of silicon (1.4 × 10 10 / cm 3 Process When compared to the degree of

[0132] The energy band gap of oxide semiconductors is 3.0 to 3.5 eV, and 4H-S The energy band gap of iC is 3.26 eV, so it is called a wide-gap semiconductor. Oxide semiconductors and silicon carbide have in common this point as well.

[0133] On the other hand, there is a significant difference between oxide semiconductors and silicon carbide. The process temperature is 1500℃ to 2000℃. However, it is difficult to form a laminated structure with semiconductor elements using other semiconductor materials. This is because the semiconductor substrate and semiconductor elements are destroyed. It is made by heat treatment at 300 to 500°C (below the glass transition temperature, at most about 700°C). It is possible to form an integrated circuit using other semiconductor materials and then use an oxide semiconductor. This makes it possible to form a semiconductor element.

[0134] In addition, unlike silicon carbide, it is possible to use a substrate with low heat resistance, such as a glass substrate. Furthermore, compared to silicon carbide, it has the advantage that it does not require high-temperature heat treatment. This has the advantage of reducing energy costs.

[0135] Although many studies have been conducted on the physical properties of oxide semiconductors, these studies have focused on the energy The present invention does not include the idea of ​​sufficiently reducing the localized levels in the energy gap. In one embodiment, water or hydrogen that may cause localized levels is removed from an oxide semiconductor, This is because the localized level in the energy gap itself is This is based on the idea of ​​sufficiently reducing the It allows for the production of industrial products.

[0136] Furthermore, oxygen is supplied to the dangling bonds of the metal that are generated due to oxygen deficiency, and oxygen vacancies are eliminated. By reducing the localized levels, a more highly purified (i-type) oxide semiconductor can be obtained. For example, it is possible to form an oxide film with excess oxygen in close proximity to the channel formation region. By supplying oxygen from the oxide film, it is possible to reduce the localized level due to oxygen defects. do.

[0137] Donors in oxide semiconductors are formed in shallow intermediate states 0.1 eV to 0.2 eV below the conduction band due to excess hydrogen. These defects are thought to be caused by the lack of oxygen and the deep levels due to the lack of oxygen. The technical idea of ​​thoroughly removing hydrogen and providing sufficient oxygen to reduce the This is probably the case.

[0138] In addition, although oxide semiconductors are generally n-type, in one embodiment of the disclosed invention, In particular, the i-type is achieved by removing water and hydrogen. It is not an i-type product made by adding impurities, so it can be said to include a technological concept that has not been seen before. .

[0139] <Conduction mechanism of transistors using oxide semiconductors> Here, the conduction mechanism of a transistor using an oxide semiconductor will be described with reference to FIGS. 22 to 25. The following explanation is merely a consideration, and the validity of the invention is not denied based on this. It should be noted that this is not a

[0140] FIG. 22 shows the vertical direction of an inverted staggered transistor (thin film transistor) using an oxide semiconductor. A cross-sectional view of an oxide semiconductor layer formed on a gate electrode (GE1) via a gate insulating layer (GI). (OS) is provided, and a source electrode (S) and a drain electrode (D) are provided thereon. There are.

[0141] 23(A) and 23(B) show the energy band structure along A-A' in FIG. 22. Figure 23(B) shows the case where a positive voltage (V D >0) and then the dashed line is when no voltage is applied to the gate (V G =0), the solid line indicates a positive voltage on the gate (V G >0) When no voltage is applied to the gate, the potential barrier is high and no current flows. This indicates the off state in which no carriers (electrons) are injected from the electrode to the oxide semiconductor side, and no current flows. On the other hand, when a positive voltage is applied to the gate, the potential barrier decreases, and the current flows in the on state. Shows.

[0142] 24(A) and 24(B) show energy band diagrams in the cross section taken along the line B-B' in FIG. 22. (Schematic diagram) is shown. Figure 24(A) shows the gate (GE1) with a positive potential +V G (V G >0) The on state is a given state in which carriers (electrons) flow between the source and drain. FIG. 24(B) shows a case where a negative potential −V G (V G >0) is given, which indicates the off state (state in which minority carriers do not flow).

[0143] Figure 25 shows the relationship between the vacuum level and the work function (φ M ) and the electron affinity (χ) of the oxide semiconductor Shows.

[0144] Metals are degenerate, with the Fermi level located within the conduction band. It is n-type and its Fermi level (E f ) is the intrinsic Fermi element located in the center of the band gap. Level (E i ) and is located closer to the conduction band. It is known that a part of the ions acts as a donor, which is one of the factors that causes the ions to become n-type.

[0145] In contrast, an oxide semiconductor according to one embodiment of the disclosed invention can convert hydrogen, which is a factor in making the oxide semiconductor n-type, into an oxide. The oxide semiconductor is made of a material that contains as few impurity elements as possible, other than the main components of the oxide semiconductor. By purifying it to such a high level, it becomes intrinsic (type i) or approaches intrinsic. That is, instead of adding impurity elements to make it i-type, impurities such as hydrogen and water are removed as much as possible. This is characterized by the fact that it produces a highly purified i-type (intrinsic semiconductor) or something close to it. This results in the Fermi level (E f ) is the intrinsic Fermi level (E i ) It is possible.

[0146] The band gap (E g ) is 3.15 eV, and the electron affinity (χ) is 4.3 e V. The work function of titanium (Ti) that makes up the source and drain electrodes is The electron affinity (χ) of the oxide semiconductor is approximately equal to the electron affinity (χ) of the metal-oxide semiconductor interface. In this case, no Schottky barrier is formed for electrons.

[0147] That is, the work function of the metal (φ M ) and the electron affinity (χ) of the oxide semiconductor are equal, When a person comes into contact with the surface, an energy band diagram (schematic diagram) such as that shown in FIG. 23(A) is displayed.

[0148] In Figure 23(B), black circles (●) represent electrons. When a positive potential is applied to the drain, The electrons cross the barrier (h) and are injected into the oxide semiconductor, then flow toward the drain. The height of (h) changes depending on the gate voltage and drain voltage. When a voltage is applied, the barrier height in Figure 23(A) without voltage application, i.e., the band gap Top (E g ) or lower.

[0149] At this time, the electrons are transported between the gate insulating layer and the highly purified oxide semiconductor, as shown in FIG. They move near the interface with the body (the lowest energetically stable part of the oxide semiconductor).

[0150] Also, as shown in FIG. 24(B), when a negative potential is applied to the gate electrode (GE1), Since the number of holes, which are minority carriers, is essentially zero, the current is close to zero. .

[0151] In this way, oxide semiconductors are oxidized so that elements other than the main components (impurity elements) are not included as much as possible. By purifying semiconductors, they become intrinsic (i-type) or substantially intrinsic. The interface characteristics with the gate insulating layer become apparent. A material that can form a good interface is required. Specifically, for example, Insulating layers produced by CVD using high-density plasma generated at source frequencies, and sputtering It is preferable to use an insulating layer produced by the ring method.

[0152] The oxide semiconductor is highly purified while the interface between the oxide semiconductor and the gate insulating layer is improved. For example, the channel width W of a transistor is 1×10 4 μm, channel length is 3 In the case of μm, it is 10 -13 Off-state current of less than A, sub-0.1V / dec. A threshold swing value (S value) (gate insulating layer thickness: 100 nm) can be achieved .

[0153] In this way, the oxide semiconductor is made to contain as few elements (impurity elements) as possible other than the main components of the oxide semiconductor. By purifying the compound semiconductor, it is possible to improve the operation of the transistor. can.

[0154] <Modification> 6 to 9 show modified examples of the configuration of the semiconductor device. In the following, the following modified examples are mentioned: The following describes a case where the configuration of the transistor 162 is different from that described above. The configuration of the controller 160 is the same as above.

[0155] 6, a gate electrode 136d is provided under the oxide semiconductor layer 140, and a source electrode or drain electrode The drain electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 14. The transistor 162 has a structure in which the lower surface of the transistor 162 is in contact with the oxide semiconductor layer 140. An example of a semiconductor device is shown below. The planar structure can be changed as needed to correspond to the cross section. Here, only the cross section will be shown.

[0156] The major difference between the configuration shown in FIG. 6 and the configuration shown in FIG. 2 is the source electrode or drain electrode. 142a or the source electrode or drain electrode 142b and the oxide semiconductor layer 140. That is, in the configuration shown in FIG. 2, the upper surface of the oxide semiconductor layer 140 has a , the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, 6, the oxide semiconductor layer 140 is in contact with the lower surface of the oxide semiconductor layer 140. The source electrode or drain electrode 142a and the source electrode or drain electrode 142b are in contact with each other. Due to this difference in contact, the arrangement of other electrodes, insulating layers, etc. may differ. The details of each component are the same as in Figure 2.

[0157] Specifically, the semiconductor device shown in FIG. 6 includes a gate electrode 136 provided on an interlayer insulating layer 128. d, a gate insulating layer 138 provided on the gate electrode 136d, and a source electrode or drain electrode 142a, a source electrode or drain electrode 142b, and the source or drain electrode 142a, the source or drain electrode 1 and an oxide semiconductor layer 140 in contact with the upper surface of 42b.

[0158] Here, the gate electrode 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. Similarly to the gate electrode 136d, the source electrode or The electrode 136a is in contact with the drain electrode 130a, and the source or drain electrode 130b Electrode 136b is formed in contact with electrode 130c, and electrode 136c is formed in contact with electrode 130c. do.

[0159] In addition, a protective film is formed on the transistor 162 so as to be in contact with part of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 are provided with a source electrode or a drain electrode. An opening is provided that reaches the source electrode 142a and the source or drain electrode 142b. Through the openings, the electrodes 150d and 150e are connected to the source and drain electrodes. The electrode 142a is formed in contact with the source electrode or the drain electrode 142b. As well as electrodes 150d and 150e, gate insulating layer 138, protective insulating layer 144, interlayer insulating layer The electrodes 136a, 136b, and 136c are in contact with each other through openings provided in the layer 146. Electrodes 150a, 150b, and 150c are formed.

[0160] An insulating layer 152 is provided on the interlayer insulating layer 146, and a buried insulating layer 152 is provided on the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so that the electrodes are embedded in the Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150a. b, electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 54d is in contact with electrode 150e.

[0161] FIG. 7 shows an example of a configuration in which a gate electrode 136d is provided on an oxide semiconductor layer 140. 7A shows the source or drain electrode 142a and the source or drain electrode 142b. The oxide semiconductor layer 140 is connected to the lower surface of the oxide semiconductor layer 140 by a contact electrode 142b. 7B shows an example of a configuration in which the source electrode or drain electrode 142a and the source The drain electrode 142b is formed on the upper surface of the oxide semiconductor layer 140. This is an example of a configuration in contact with the conductor layer 140.

[0162] 7 is different from the configurations shown in FIGS. 2 and 6 in that a 7A and 7B. The major difference in the configuration is the source electrode or drain electrode 142a. The drain electrode 142b is located on either the lower surface or the upper surface of the oxide semiconductor layer 140. These differences lead to the question of whether the other electrodes, insulators, The arrangement of layers is different. The details of each component are the same as in Figure 2.

[0163] Specifically, the semiconductor device shown in FIG. 7A has a source electrode provided on an interlayer insulating layer 128. a source or drain electrode 142a, a source or drain electrode 142b, and a source electrode or in contact with the upper surface of the drain electrode 142a, the source electrode or the drain electrode 142b. an oxide semiconductor layer 140 formed on the oxide semiconductor layer 140; and a gate insulating layer 138 provided on the oxide semiconductor layer 140. , the gate electrode 136d in the region overlapping with the oxide semiconductor layer 140 on the gate insulating layer 138; , has.

[0164] 7B, the semiconductor device shown in FIG. 7B has an oxide semiconductor layer 124 formed on the interlayer insulating layer 128. 140, and a source electrode or The drain electrode 142a, the source or drain electrode 142b, and the oxide semiconductor layer 14 0, source electrode or drain electrode 142a, and source electrode or drain electrode 1 A gate insulating layer 138 is provided on the gate insulating layer 138. 40 and a gate electrode 136d in an area overlapping the gate electrode 136a.

[0165] In the configuration shown in FIG. 7, compared to the configuration shown in FIG. 2, some components can be omitted. In this case, the manufacturing process can be simplified. Of course, this is not essential in the configuration shown in FIG. It goes without saying that components can be omitted.

[0166] FIG. 8 shows a case where the size of the element is relatively large, and a gate electrode is provided below the oxide semiconductor layer 140. This is an example of a configuration having an electrode 136d. In this case, the requirements for surface flatness and coverage are met. Since the requirements are relatively gentle, wiring, electrodes, etc. can be formed by embedding them in the insulating layer. For example, the gate electrode 136 can be formed by patterning the conductive layer after it is formed. Although not shown here, it is possible to form the transistor 160 can also be fabricated in the same manner.

[0167] The major difference between the configuration shown in FIG. 8(A) and the configuration shown in FIG. 8(B) is the source electrode or drain electrode. The source electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 140. The question is whether the contact occurs on the lower or upper surface of the Due to these differences, the arrangement of other electrodes, insulating layers, etc. is also different. The details of the components are the same as those in FIG.

[0168] Specifically, the semiconductor device shown in FIG. 8A has a gate electrode provided on an interlayer insulating layer 128. a gate insulating layer 138 provided on the gate electrode 136d; A source or drain electrode 142a, a source or drain electrode 142b, a source or drain electrode 142a; and an oxide semiconductor layer 140 in contact with the upper surface of the back electrode 142b.

[0169] 8B, the semiconductor device shown in FIG. 8B has a gate electrode 13 provided on the interlayer insulating layer 128. 6d, a gate insulating layer 138 provided on the gate electrode 136d, and the gate insulating layer 138 an oxide semiconductor layer 140 provided in a region overlapping with the upper gate electrode 136d; A source electrode or drain electrode 142 provided in contact with the upper surface of the conductor layer 140 a, and a source or drain electrode 142b.

[0170] In addition, the configuration shown in FIG. 8 also allows for elimination of components compared to the configuration shown in FIG. 2, etc. In this case, too, the effect of simplifying the manufacturing process can be obtained.

[0171] FIG. 9 shows a case where the size of the element is relatively large, in which a gate electrode is formed on the oxide semiconductor layer 140. This is an example of a configuration having an electrode 136d. In this case, too, consideration is given to the flatness of the surface and coverage. Since the requirements for this are relatively mild, wiring and electrodes can be embedded in the insulating layer. For example, by patterning after forming the conductive layer, the gate electrode 1 Although not shown here, it is possible to form transistor 1 60 can also be produced in the same manner.

[0172] The major difference between the configuration shown in FIG. 9(A) and the configuration shown in FIG. 9(B) is the source electrode or drain electrode. The source electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 140. The question is whether the contact occurs on the lower or upper surface of the Due to these differences, the arrangement of other electrodes, insulating layers, etc. is also different. The details of the components are the same as those in FIG.

[0173] Specifically, the semiconductor device shown in FIG. 9A has a source electrode provided on an interlayer insulating layer 128. a source or drain electrode 142a, a source or drain electrode 142b, and a source electrode or in contact with the upper surface of the drain electrode 142a, the source electrode or the drain electrode 142b. The oxide semiconductor layer 140, the source electrode or drain electrode 142a, The drain electrode 142b, the gate insulating layer 138 provided on the oxide semiconductor layer 140, and the gate The gate electrode 13 is provided in a region on the gate insulating layer 138 that overlaps with the oxide semiconductor layer 140. 6d and has.

[0174] 9B, the semiconductor device shown in FIG. 9B has an oxide semiconductor layer 124 formed on the interlayer insulating layer 128. 140, and a source electrode or A drain electrode 142a, a source or drain electrode 142b, and a source or drain electrode The drain electrode 142a, the source electrode or the drain electrode 142b, and the oxide semiconductor layer 140 The gate insulating layer 138 is provided on the oxide semiconductor layer 140 and overlaps the gate insulating layer 138. and a gate electrode 136d provided in the overlapping region.

[0175] In addition, the configuration shown in FIG. 9 also allows for elimination of components compared to the configuration shown in FIG. 2. In this case, too, the effect of simplifying the manufacturing process can be obtained.

[0176] As described above, one embodiment of the disclosed invention realizes a semiconductor device with a novel structure. In this embodiment, the transistor 160 and the transistor 162 are stacked. However, the configuration of the semiconductor device is not limited to this example. In this configuration, the channel lengths of the transistors 160 and 162 are perpendicular to each other. The positional relationship between the transistor 160 and the transistor 162 is the same as in the above example. Furthermore, the transistor 160 and the transistor 162 may be overlapped. It may be provided.

[0177] For ease of understanding, the present embodiment will be described with reference to a semiconductor device with a minimum storage unit (1 bit). However, the configuration of the semiconductor device is not limited to this. By appropriately connecting the components, it is possible to construct a more advanced semiconductor device. By using multiple devices, it is possible to configure a NAND or NOR type semiconductor device. The configuration is not limited to that shown in FIG. 1 and can be modified as appropriate.

[0178] The semiconductor device according to this embodiment has a very low off-state current due to the low off-state current of the transistor 162. It is possible to retain information for a long time. No refresh operation is required, which reduces power consumption. It can be used as a non-volatile memory device.

[0179] In addition, since information is written by the switching operation of the transistor 162, It does not require high voltage and does not have the problem of element degradation. Therefore, since information can be written and erased, high speed operation can be easily realized. By controlling the potential input to the transistor, it is possible to directly rewrite information. Therefore, the erase operation required in flash memory is not necessary. This can suppress the resulting decrease in operation speed.

[0180] In addition, a transistor using a material other than an oxide semiconductor is Compared to the conventional memory, it can operate at a higher speed, so by using it, the contents of the memory can be It is possible to perform reading at high speed.

[0181] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0182] (Embodiment 2) In this embodiment, a circuit configuration and an operation method of a semiconductor device according to one embodiment of the present invention will be described. explain.

[0183] FIG. 10 shows an example of a circuit diagram of a memory element (hereinafter also referred to as a memory cell) included in a semiconductor device. The memory cell 200 shown in FIG. 10 has a third wiring S1 (first signal line) and a fourth wiring S2 (second signal line). A line S2 (second signal line), a fifth wiring WL (word line), a transistor 201, and a transistor The transistor 201 and the transistor 202 are connected to each other. The transistor 203 is formed using a material other than an oxide semiconductor. The transistor 202 is formed using an oxide semiconductor. The transistor 203 preferably has a structure similar to that of the transistor 160 described in Embodiment 1. The transistor 202 has a structure similar to that of the transistor 162 described in Embodiment 1. The memory cell 200 is preferably configured as a first wiring SL (source line) and 2 wiring BL (bit line), and the transistor (other memory cell The first wiring SL and the second wiring BL are electrically connected to each other through the It is preferable that the temperature be

[0184] Here, the gate electrode of the transistor 201 and the source electrode or drain of the transistor 202 are The first wiring SL is electrically connected to one of the drain electrodes. The source electrode of the transistor 201 and the source electrode of the transistor 203 are electrically connected. The wiring BL of No. 2, the drain electrode of the transistor 201, and the drain electrode of the transistor 203 The third wiring S1 and the electrode of the transistor 202 are electrically connected to each other. The other of the source electrode and the drain electrode is electrically connected to the fourth wiring S2. The gate electrode of the transistor 202 is electrically connected to the fifth wiring WL. The first wiring SL and the gate electrode of the transistor 203 are electrically connected. The source electrode of the transistor 201 and the source electrode of the transistor 203 are connected to the transistor (other The second wiring B may be connected via a second wiring B. L, the drain electrode of transistor 201, and the drain electrode of transistor 203 are They may be connected via a transistor (including those constituting other memory cells). .

[0185] FIG. 11 shows a block diagram of a semiconductor device according to one embodiment of the present invention having a storage capacity of m×n bits. A circuit diagram is shown. Here, as an example, a NAND-type memory cell 200 is connected in series. 1 shows a semiconductor device.

[0186] The semiconductor device according to one aspect of the present invention includes m fifth wirings WL(1) to WL(m) and a fourth wiring The wirings S2(1) to S2(m), n first wirings SL(1) to SL(n), and a second wiring Lines BL(1) to BL(n), third wirings S1(1) to S1(n), and two sixth wirings SEL(1), SEL(2), and a plurality of memory cells 200(1, 1) to 200(m, n) The memory cells are arranged in a matrix of m rows x n columns (m and n are natural numbers). The second wirings BL(1) to BL(n ) and the transistor 21 arranged between the memory cells 200(1, 1) to 200(1, n). 5(1,1) to 215(1,n) and the sixth wiring SEL(2), the first wiring SL (1) to SL(n) and memory cells 200(m,1) to 200(m,n) Transistors 215(2,1) to 215(2,n) and driving of the second wiring and third wiring A circuit 211, a driver circuit 213 for the fourth wiring and the fifth wiring, and a read circuit 212 are provided. The peripheral circuits are also provided with a refresh circuit, etc. It may be possible.

[0187] Consider each memory cell 200 (representatively, memory cell 200(i, j)). Here, i is m is an integer between 1 and m, and j is an integer between 1 and n. The fourth wiring S2(i) and the fifth wiring WL(i) are connected to the memory The transistor 201 and the transistor j of the cell 200 (i1, j) (i1 is an integer from 2 to m) The drain electrode of the transistor 203 is connected to the transistor of the memory cell 200 (i1-1, j). The source electrodes of the transistors 201 and 203 are connected to the memory cells 200 (i2, j ) (i2 is an integer from 1 to m-1) The source electrode is connected to the transistor 201 and the transistor 202 of the memory cell 200(i2+1, j). The transistor 203 in the memory cell 200(1, j) is connected to the drain electrode of the transistor 203. The drain electrodes of transistor 201 and transistor 203 are connected to transistor 215(1,j). The transistor 201 and the transistor 202 included in the memory cell 200(m, j) are connected to the source electrodes of the transistors 201 and 202. The source electrode of the transistor 203 is connected to the drain electrode of the transistor 215(2, j). The drain electrode of the transistor 215(1, j) is connected to the second wiring BL(j). The source electrode of the transistor 215(2, j) is connected to the first wiring SL(j). The gate electrode of the transistor 215(1,j) is connected to the sixth wiring SEL(1). The gate electrode of the transistor 215(2,j) is connected to the sixth wiring SEL(2). can be.

[0188] The second wirings BL(1) to BL(n) and the third wirings S1(1) to S1(n) are The fifth wiring WL(1) to WL(m), the fourth wiring WL(1) to WL(m) are connected to the driving circuit 211 of the third wiring WL(1) to WL(m). The wirings S2(1) to S2(m) and the sixth wirings SEL(1) and SEL(2) are the fourth wiring and The second wiring BL(1) is connected to the driving circuit 213 of the fifth wiring. The first wirings SL(1) to SL(n) are also connected to the read circuit 212. The potential Vs is applied to the first wirings SL(1) to SL(n). Furthermore, they do not need to be separated, and may be configured so that they are electrically connected to each other. .

[0189] The operation of the semiconductor device shown in Fig. 11 will be described. In this configuration, writing and and reads it.

[0190] When writing to the memory cells 200(i,1) to 200(i,n) in the i-th row, The wiring S2(i) is set to 2 V, and the transistor 202 of the selected memory cell is turned on. On the other hand, the fourth wiring S2 other than the i-th row is set to 0V, and the transistors of the unselected memory cells are set to The third wiring S1(1) to S1(n) are connected to the transistors 202 and 203, respectively, to write data "1". The column to which data "0" is written is set to 2V, and the column to which data "0" is written is set to 0V. In other words, before the potential of the third wirings S1(1) to S1(n) changes, the fourth wiring S2(i) is set to 0 V, turning off the transistor 202 of the selected memory cell. For example, the second wirings BL(1) to BL(n) are set to 0V, and the fifth wirings WL(1) to WL(m ) to 0V, the sixth wiring SEL(1) and SEL(2) to 0V, the first wiring SL(1) to SL The potential Vs of (n) is set to 0 V. An example of the timing chart for the above write operation is shown in FIG. Shown in 2.

[0191] As a result, the gate voltage of the transistor 201 of the memory cell in which data "1" is written The potential of the node connected to the pole (hereinafter referred to as node A) is about 2V, and data "0" is written. The potential of node A of the selected memory cell is about 0V. The potential remains unchanged. Since the potential of the gate electrode (node ​​A) of the transistor 201 is 0, the potential of the gate electrode of the transistor 201 is It is held upright.

[0192] When reading out the memory cells 200(i,1) to 200(i,n) in the i-th row, The wiring SEL(1) and SEL(2) are set to 2V, and the transistors 215(1, 1) to 215 The potential Vs of the first wirings SL(1) to SL(n) is set to 0 V. The readout circuits 212 connected to the second wirings BL(1) to BL(n) are set to an operating state. The fourth wirings S2(1) to S2(m) are set to 0V, and the transistors of all the memory cells are set to The third wirings S1(1) to S1(n) are set to 0V.

[0193] The fifth wiring WL(i) is set to 0V, and the fifth wiring WL other than the i-th row is set to 2V. When the transistor 203 of the memory cell in the i-th row is turned off, the transistor 203 of the memory cell in the other row is turned off. The transistor 203 of the cell is turned on. As a result, the transistor of the memory cell in the i-th row The resistance state of the memory cell column is determined by whether the memory cell 201 is in the on or off state. In the memory cell having data "0", node A is approximately 0V. The resistor 201 is turned off, and the resistance of the memory cell string is high (hereinafter, the memory cell On the other hand, among the memory cells in the i-th row, the data “1” is In the memory cell having this, node A is about 2 V, so transistor 201 is in the on state. The resistance of the memory cell string is in a low state (hereinafter, when the memory cell string is in a low resistance state, As a result, the read circuit determines whether the data is "0" or "1" based on the difference in the resistance state of the memory cell. ","1" can be read out.

[0194] When writing, if a thin film transistor is formed on an SOI substrate, etc., When the entire device does not have a substrate potential, the fifth wirings WL(i+1) to WL(m) are set to 2V, It is preferable to set the sixth wiring SEL(2) to 2 V. This allows the memory cells in the i-th row At least one of the source electrode and the drain electrode of the transistor 201 is set to about 0V. Alternatively, the sixth wiring SEL(1) can be set to 2V, and the fifth wirings WL(1) to WL( i-1) may be set to 2 V. On the other hand, when a transistor is formed over a single crystal semiconductor substrate, In the case where the semiconductor device has a substrate potential, the substrate potential may be set to 0V.

[0195] In addition, the second wirings BL(1) to BL(n) were set to 0V during writing, but the sixth wirings SE If L(1) is 0V, it may be in a floating state or charged to a potential above 0V. The third wirings S1(1) to S1(n) were set to 0V during reading, but the floating It does not matter if the capacitor is in a dangling state or is charged to a potential above 0V.

[0196] Note that the definitions of data "1" and data "0" are for convenience, and they may be reversed. The above-mentioned operating voltage is an example. When data is "01", the transistor 201 is turned off, and when data is "1", the transistor 201 is turned on. Also, the transistor 202 is in an on state during writing and in an off state during other times. In addition, the transistor 203 of the selected memory cell is turned off during reading, and the transistor 203 of the unselected memory cell is turned off during reading. The transistor 203 of the selected memory cell should be selected so as to be in an on state. Alternatively, the power supply potential VDD of the peripheral logic circuits may be used. The potential GND may also be used.

[0197] Next, another example of the circuit configuration and operation of the semiconductor device according to one embodiment of the present invention will be described. do.

[0198] An example of a memory cell circuit included in a semiconductor device is shown in FIG. 0 is the third wiring S1, the fourth wiring S2, the fifth wiring WL, the transistor 201, and , transistor 202, and transistor 203. The transistor 201 and the transistor 203 are formed using a material other than an oxide semiconductor. The transistor 202 is formed using an oxide semiconductor. The transistor 203 has a structure similar to that of the transistor 160 described in Embodiment 1. The transistor 202 is preferably the same as the transistor 162 described in Embodiment 1. In addition, the memory cell 220 has a first wiring SL and a second wiring SL. It is electrically connected to the line BL and is a transistor (including those that constitute other memory cells). ) are preferably electrically connected to the first wiring SL and the second wiring BL. .

[0199] The memory cell circuit shown in FIG. 13 has a third wiring, The direction of the fourth wiring S1 is different from that of the fourth wiring S2. The line S2 is arranged in the direction of the second wiring BL (column direction), and the third wiring S1 is arranged in the direction of the fifth wiring WL. The configuration is such that the pixels are arranged in a row direction.

[0200] FIG. 14 shows a block diagram of a semiconductor device according to one embodiment of the present invention having a storage capacity of m×n bits. A circuit diagram is shown in which, as an example, a NAND-type memory cell 220 is connected in series. 1 shows a semiconductor device.

[0201] The semiconductor device according to one aspect of the present invention includes m fifth wirings WL and third wirings S1, and n the first wiring SL, the second wiring BL, the fourth wiring S2, and two sixth wirings SEL; A plurality of memory cells 220(1, 1) to 220(m, n) are arranged vertically in m rows by horizontally in n columns ( m and n are natural numbers), and a memory cell array 230 arranged in a matrix form. Along EL(1), the second wirings BL(1) to BL(n) and the memory cells 220(1, 1) Transistors 235(1,1) to 235(1,n) arranged between 220(1,n) and 220(1,n) The first wirings SL(1) to SL(n) and the memory cells SL(n) are connected along the sixth wiring SEL(2). Transistors 235(2,1) to 235(m,n) arranged between 220(m,1) to 220(m,n) 235(2, n), the driving circuit 231 for the second wiring and the fourth wiring, and the third wiring and 5 wiring drive circuit 233 and peripheral circuits such as readout circuit 232. As other peripheral circuits, a refresh circuit or the like may be provided.

[0202] The semiconductor device shown in FIG. 14 has the following advantages compared to the semiconductor device shown in FIG. 11: 14, the direction of the fourth wiring S2 is different. The third wiring S1 is arranged in the direction of the fifth wiring WL (row direction). The configuration is such that

[0203] Consider each memory cell 220 (representatively, memory cell 220(i, j)). Here, i is m is an integer between 1 and m, and j is an integer between 1 and n) are the third wiring S1(i), the fifth wiring S2(i), WL(i) and the fourth wiring S2(j). 0(i1, j) (i1 is an integer from 2 to m) The drain electrode of the transistor 201 in the memory cell 220 (i1-1, j) is connected to the drain electrode of the transistor 201 in the memory cell 220 (i1-1, j). and connected to the source electrode of the transistor 203, and the memory cell 220(i2, j)(i2 (where m is an integer from 1 to m-1) The transistor 201 and the transistor 202 included in the memory cell 220(i2+1, j) are The drain electrode of the transistor 220(1, j) is connected to the drain electrode of the transistor 220(1, j). The drain electrode of transistor 203 is connected to the source of transistor 235(1,j). The transistor 201 and the transistor 202 of the memory cell 220(m, j) are connected to the electrodes. The source electrode of the transistor 203 is connected to the drain electrode of the transistor 235(2,j). The drain electrode of the transistor 235(1, j) is connected to the second wiring BL(j). The source electrode of the transistor 235(2,j) is connected to the first wiring SL(j). The gate electrode of the transistor 235(1,j) is connected to the sixth wiring SEL(1). The gate electrode of the transistor 235(2,j) is connected to the sixth wiring SEL(2).

[0204] The second wirings BL(1) to BL(n) and the fourth wirings S2(1) to S2(n) are The fifth wiring WL(1) to WL(m), the third wiring WL(1) to WL(m) are connected to the driving circuit 231 of the fourth wiring WL(1) to WL(m). The wirings S1(1) to S1(m) and the sixth wirings SEL(1) and SEL(2) are the third wiring and The second wiring BL(1) is connected to the driving circuit 233 of the fifth wiring. .about.BL(n) are also connected to the read circuit 232. The first wirings SL(1) to SL The potential Vs is applied to the first wirings SL(1) to SL(n). Furthermore, they do not need to be separated, and may be configured so that they are electrically connected to each other. .

[0205] The operation of the semiconductor device shown in Fig. 14 will be described. In this configuration, writing is performed for each column, and reading is performed for each column. The overflow is done line by line.

[0206] When writing to the memory cells 220(1, j) to 220(m, j) in the j-th column, The wiring S2(j) is set to 2 V, and the transistor 202 of the selected memory cell is turned on. On the other hand, the fourth wiring S2 other than the j-th column is set to 0V, and the transistors of the unselected memory cells are set to 202 is turned off. The third wirings S1(1) to S1(m) are used to write data "1". The line where data "0" is written is set to 2V, and the line where data "0" is written is set to 0V. In other words, before the potential of the third wirings S1(1) to S1(m) changes, the fourth wiring S2(j) is set to 0 V, turning off the transistor 202 of the selected memory cell. For example, the second wirings BL(1) to BL(n) are set to 0V, and the fifth wirings WL(1) to WL(m ) to 0V, the sixth wiring SEL(1) and SEL(2) to 0V, the first wiring SL(1) to SL The potential Vs of (n) is set to 0V.

[0207] As a result, the gate voltage of the transistor 201 of the memory cell in which data "1" is written The potential of the node connected to the pole (hereinafter referred to as node A) is about 2V, and data "0" is written. The potential of node A of the selected memory cell is about 0V. The potential remains unchanged. Since the potential of the gate electrode (node ​​A) of the transistor 201 is 0, the potential of the gate electrode of the transistor 201 is It is held upright.

[0208] When reading out the memory cells 220(i,1) to 220(i,n) in the i-th row, The wiring SEL(1) and SEL(2) are set to 2V, and the transistors 235(1, 1) to 235 The potential Vs of the first wirings SL(1) to SL(n) is set to 0 V. The readout circuits 232 connected to the second wirings BL(1) to BL(n) are set to an operating state. The fourth wirings S2(1) to S2(n) are set to 0V, and the transistors of all the memory cells are set to The third wirings S1(1) to S1(m) are set to 0V.

[0209] The fifth wiring WL(i) is set to 0V, and the fifth wiring WL other than the i-th row is set to 2V. When the transistor 203 of the memory cell in the i-th row is turned off, the transistor 203 of the memory cell in the other row is turned off. The transistor 203 of the cell is turned on. As a result, the transistor of the memory cell in the i-th row The resistance state of the memory cell column is determined by whether the memory cell 201 is in the on or off state. In the memory cell having data "0", node A is approximately 0V. The resistor 201 is turned off, and the memory cell column is in a high resistance state. Among the res- ells, in the memory cell having data "1", node A is about 2V, The transistor 201 is turned on, and the memory cell column is in a low resistance state. The read circuit 232 reads data "0" and "1" based on the difference in the resistance state of the memory cell. This can be done.

[0210] When writing, if a thin film transistor is formed on an SOI substrate, etc., When the entire device does not have a substrate potential, the fifth wiring WL(1) to WL(m) are set to 2V, and the sixth wiring WL(1) to WL(m) are set to 1V. It is preferable to set the first wiring SEL(1) or the sixth wiring SEL(2) to 2V. Therefore, at least one of the source electrode or drain electrode of the transistor 201 of the memory cell in the i-th row At least one of the two voltages can be set to about 0 V. On the other hand, when a transistor is formed on a single crystal semiconductor substrate, When a semiconductor device has a substrate potential, such as when a semiconductor device is fabricated, the substrate potential can be set to 0V. good.

[0211] In addition, the second wirings BL(1) to BL(n) were set to 0V during writing, but the sixth wirings SE If L(1) is 0V, it may be in a floating state or charged to a potential above 0V. The third wirings S1(1) to S1(n) were set to 0V during reading, but the floating It does not matter if the capacitor is in a dangling state or is charged to a potential above 0V.

[0212] Note that the definitions of data "1" and data "0" are for convenience, and they may be reversed. The above-mentioned operating voltage is an example. When data is "01", the transistor 201 is turned off, and when data is "1", the transistor 201 is turned on. Also, the transistor 202 is in an on state during writing and in an off state during other times. In addition, the transistor 203 of the selected memory cell is turned off during reading, and the transistor 203 of the unselected memory cell is turned off during reading. The transistor 203 of the selected memory cell should be selected so as to be in an on state. Alternatively, the power supply potential VDD of the peripheral logic circuits may be used. The potential GND may also be used.

[0213] The semiconductor device according to this embodiment has an extremely low off-state current due to the low off-state current of the transistor 202. It is possible to retain information for a long time. No refresh operation is required, which reduces power consumption. It can be used as a non-volatile memory device.

[0214] In addition, since information is written by the switching operation of the transistor 202, It does not require high voltage and does not have the problem of element degradation. Therefore, since information can be written and erased, high-speed operation can be easily realized. By controlling the potential input to the transistor, data can be directly rewritten. Therefore, the erase operation required in flash memory etc. is not necessary. This can suppress the decrease in operation speed caused by the above.

[0215] In addition, a transistor using a material other than an oxide semiconductor is Compared to the conventional memory, it can operate at a higher speed, so by using it, the contents of the memory can be It is possible to perform reading at high speed.

[0216] (Embodiment 3) In this embodiment mode, an example of a circuit configuration and operation of a semiconductor device different from that of Embodiment 2 will be described. I will explain.

[0217] An example of a circuit diagram of a memory cell included in a semiconductor device is shown in FIG. 240 includes the third wiring S1, the fourth wiring S2, the fifth wiring WL, and the transistor 20 1, a transistor 202, and a capacitance element 204. The transistor 01 is formed using a material other than an oxide semiconductor, and the transistor 202 is formed using an oxide semiconductor. Here, the transistor 201 is formed using a semiconductor. It is preferable that the transistor 202 has the same structure as the transistor 160. It is preferable that the transistor 162 has the same structure as that of the transistor 162 shown in the first embodiment. 240 is electrically connected to the first wiring SL and the second wiring BL, and (including those constituting other memory cells) through the first wiring SL and the second wiring BL It is preferable that the power supply 100 is electrically connected to the power supply 100.

[0218] Here, the gate electrode of the transistor 201 and the source electrode or drain of the transistor 202 are One of the drain electrodes and one of the electrodes of the capacitor 204 are electrically connected. The first wiring SL and the source electrode of the transistor 201 are electrically connected to each other. The drain electrode of the transistor 201 and the second wiring BL are electrically connected. The other of the source electrode and the drain electrode of the transistor 202 and the third wiring S1 are The fourth wiring S2 and the gate electrode of the transistor 202 are electrically connected to each other. The fifth wiring WL and the other electrode of the capacitor 204 are electrically connected to each other. The first wiring SL and the source electrode of the transistor 201 are connected to the transistor (other The second wiring may be connected via a second wiring (including a wiring that configures the memory cell). BL and the drain electrode of the transistor 201 are connected to the transistor (which constitutes another memory cell). The connection may be via a

[0219] FIG. 16 shows a block diagram of a semiconductor device according to one embodiment of the present invention having a storage capacity of m×n bits. A circuit diagram is shown. Here, as an example, a NAND-type memory cell 240 is connected in series. 1 shows a semiconductor device.

[0220] The semiconductor device according to one aspect of the present invention includes m fifth wirings WL and fourth wirings S2, and n The first wiring SL, the second wiring BL, the third wiring S1, and the two sixth wirings SEL (1 ), SEL(2), and a plurality of memory cells 240(1, 1) to 240(m, n) are arranged vertically in m rows ( A memory cell array 2 arranged in a matrix of n rows x n columns (m and n are natural numbers) 50, and along the sixth wiring SEL(1), the second wirings BL(1) to BL(n) and the memory The transistors 255(1,1) arranged between the cells 240(1,1) to 240(1,n) ) to 255(1, n), and along the sixth wiring SEL(2), the first wiring SL(1) to S L(n) and the transistors arranged between the memory cells 240(m, 1) to 240(m, n). 255(2,1) to 255(2,n), and the driving circuit 251 for the second wiring and the third wiring. and a peripheral circuit such as a driving circuit 253 for the fourth wiring and the fifth wiring, and a read circuit 252. As other peripheral circuits, a refresh circuit etc. may be provided. stomach.

[0221] Consider each memory cell 240 (representatively, memory cell 240(i, j)). Here, i is m is an integer between 1 and m, and j is an integer between 1 and n. The fourth wiring S2(i) and the fifth wiring WL(i) are connected to the memory The drain of the transistor 201 in the cell 240 (i1, j) (i1 is an integer from 2 to m) The electrode is connected to the source electrode of the transistor 201 of the memory cell 240 (i1-1, j). The transistors of the memory cells 240 (i2, j) (i2 is an integer between 1 and m-1) are connected to the The source electrode of the transistor 201 is connected to the transistor 2 of the memory cell 240(i2+1, j). The drain electrode of the transistor 240(1, j) is connected to the drain electrode of the transistor 240(1, j). The drain electrode of O1 is connected to the source electrode of transistor 255(1, j), and the memory The source electrode of the transistor 201 in the cell 240(m, j) is connected to the transistor 255 The drain electrode of transistor 255(1, j) is connected to the drain electrode of transistor 255(2, j). is connected to the second wiring BL(j), and the source electrode of the transistor 255(2, j) is connected to the first wiring BL(j). is connected to the wiring SL(j).

[0222] The second wirings BL(1) to BL(n) and the third wirings S1(1) to S1(n) are The fifth wiring WL(1) to WL(m), the fourth wiring WL(1) to WL(m) are connected to the driving circuit 251 of the third wiring WL(1) to WL(m). The wirings S2(1) to S2(m) and the sixth wirings SEL(1) and SEL(2) are the fourth wiring and The second wiring BL(1) is connected to the driving circuit 253 of the fifth wiring. .about.BL(n) are also connected to the read circuit 252. The first wirings SL(1) to SL The potential Vs is applied to the first wirings SL(1) to SL(n). Furthermore, they do not need to be separated, and may be configured so that they are electrically connected to each other. .

[0223] The operation of the semiconductor device shown in Fig. 16 will be described. In this configuration, writing and and reads it.

[0224] When writing to the memory cells 240(i,1) to 240(i,n) in the i-th row, The wiring S2(i) is set to 2 V, and the transistor 202 of the memory cell in the i-th row is turned on. On the other hand, the fourth wiring S2 other than the i-th row is set to 0V, and the transistors of the memory cells other than the i-th row are set to 0V. The third wiring S1(1) to S1(n) is a wiring for writing data "1". The column where data "0" is written is set to 2V, and the column where data "0" is written is set to 0V. Before the potential of the third wirings S1(1) to S1(n) changes, the fourth wiring S2( i) is set to 0 V to turn off the transistor 202 of the selected memory cell. For example, the second wirings BL(1) to BL(n) are set to 0 V, and the fifth wirings WL(1) to WL(n) are set to 0 V. (m) to 0V, the sixth wiring SEL(1) and SEL(2) to 0V, the first wiring SL(1) to The potential Vs of SL(n) is set to 0V.

[0225] As a result, the gate voltage of the transistor 201 of the memory cell in which data "1" is written The potential of the node connected to the pole (hereinafter referred to as node A) is about 2V, and data "0" is written. The potential of node A of the selected memory cell is about 0V. The potential remains unchanged. Since the potential of the gate electrode (node ​​A) of the transistor 201 is 0, the potential of the gate electrode of the transistor 201 is It is held upright.

[0226] When reading out the memory cells 240(i,1) to 240(i,n) in the i-th row, The wiring SEL(1) and SEL(2) are set to 2V, and the transistors 255(1, 1) to 255 The potential Vs of the first wirings SL(1) to SL(n) is set to 0 V. The readout circuits 252 connected to the second wirings BL(1) to BL(n) are set to the operating state. The fourth wirings S2(1) to S2(m) are set to 0V, and the transistors of all the memory cells are set to The third wirings S1(1) to S1(n) are set to 0V.

[0227] The fifth wiring WL(i) is set to 0V, and the fifth wiring WL other than the i-th row is set to 2V. In this case, the fifth wiring WL(i) is set to 0V, and the fifth wiring WL other than the i-th row is set to 2V. The state of transistor 201 will be explained. Node A determines the state of transistor 201. The potential of the fifth wiring WL and the node A is The potential of the fifth wiring WL and the potential of the node A depend on the capacitance C2 between the drain and the source. Here, as an example, when the transistor 201 is in an off state, C1 / C2 >>1, assume that C1 / C2=1 in the on state. Also, the threshold voltage of transistor 201 is The voltage is set to 0.5V. From FIG. 17, when the potential of the fifth wiring WL is 0V, the data In a memory cell having a 0", node A is at approximately 0V, so transistor 201 is in an off state. In the memory cell having data "1", the node A is about 2V, so the transistor 20 On the other hand, when the potential of the fifth wiring WL is 2V, data "0" is enabled. In the memory cell that stores data "1", node A is about 1.25V. The voltage at node A becomes approximately 3V, and transistor 201 is turned on regardless of whether the data is "0" or "1." Therefore, the fifth wiring WL(i) is set to 0V, and the fifth wiring WL other than the i-th row is set to 2V. In this case, the memory cell column having data "0" in the i-th row is in a high resistance state. The memory cell column having data "1" is in a low resistance state. Data "0" and "1" can be read out based on the difference in the resistance state of the recell.

[0228] In addition, the second wirings BL(1) to BL(n) were set to 0V during writing, but the sixth wirings SE If L(1) is 0V, it may be in a floating state or charged to a potential above 0V. The third wirings S1(1) to S1(n) were set to 0V during reading, but the floating It does not matter if the capacitor is in a dangling state or is charged to a potential above 0V.

[0229] Note that the definitions of data "1" and data "0" are for convenience, and they may be reversed. The above-mentioned operating voltage is an example. The operating voltage is set to a value at which the transistor 202 is turned on during writing. The data is set to "0" when reading. The transistor 201 of the selected memory cell is in an off state, and the transistor of the selected memory cell with data "1" is in an off state. The transistor 201 of the selected memory cell is turned on, and the transistor 201 of the unselected memory cell is turned on. In particular, instead of 2V, the power supply potential VDD of the peripheral logic circuits may be used. Also, instead of 0V, the ground potential GND may be used.

[0230] Next, another example of the circuit configuration and operation of the semiconductor device according to one embodiment of the present invention will be described. .

[0231] An example of a memory cell circuit included in a semiconductor device is shown in FIG. 0 is the third wiring S1, the fourth wiring S2, the fifth wiring WL, the transistor 201, and The transistor 201 is composed of a transistor 202 and a capacitor element 204. The transistor 201 is formed using a material other than an oxide semiconductor, and the transistor 202 is formed using an oxide semiconductor. Here, the transistor 201 is formed using the same material as that of the transistor described in Embodiment 1. It is preferable that the transistor 202 has a similar structure to that of the transistor 160. It is preferable that the memory cell 26 has the same structure as the transistor 162 shown in the first embodiment. 0 is electrically connected to the first wiring SL and the second wiring BL, and The first wiring SL and the second wiring BL are connected via the It is preferable that they are electrically connected.

[0232] The memory cell circuit shown in FIG. 18 has a third wiring S1 and a The direction of the fourth wiring S2 is different. That is, in the memory cell of FIG. The third wiring S1 is arranged in the direction of the fifth wiring WL (row direction). The configuration is such that

[0233] Furthermore, a block circuit of a semiconductor device according to one embodiment of the present invention having a storage capacity of m×n bits The figure shows the memory cell 260 of FIG. 18 applied to the memory cell of the block circuit diagram shown in FIG. The drive voltage and timing of the drive circuit are set in accordance with the operation of the memory cell 260. Once configured, column-by-column writing and row-by-row reading can be performed in the same manner as the block diagram shown in Figure 14. It is possible to perform a write operation.

[0234] The semiconductor device according to this embodiment has an extremely low off-state current due to the low off-state current of the transistor 202. It is possible to retain information for a long time. No refresh operation is required, which reduces power consumption. It can be used as a non-volatile memory device.

[0235] In addition, since information is written by the switching operation of the transistor 202, It does not require high voltage and does not have the problem of element degradation. Therefore, since information can be written and erased, high speed operation can be easily realized. By controlling the potential input to the transistor, it is possible to directly rewrite information. Therefore, the erase operation required in flash memory is not necessary. This can suppress the resulting decrease in operation speed.

[0236] In addition, a transistor using a material other than an oxide semiconductor is Compared to the conventional memory, it can operate at a higher speed, so by using it, the contents of the memory can be It is possible to perform reading at high speed.

[0237] (Fourth embodiment) In this embodiment, the circuit configuration and the like of a semiconductor device different from those of the second or third embodiment are An example of the operation will be described below.

[0238] FIG. 19 illustrates an example of a circuit diagram of a memory cell included in a semiconductor device according to one embodiment of the present invention.

[0239] The memory cell 280 shown in FIG. 19 has a different structure from the memory cell circuit of FIG. 10 in that the node A and the first A capacitor 205 is provided between the wiring SL. By having this, the retention characteristics are improved.

[0240] The operation of the memory cell circuit shown in FIG. 19 is similar to that of the memory cell circuit shown in FIG. Therefore, detailed description will be omitted.

[0241] (Embodiment 5) An example of a readout circuit included in a semiconductor device according to one embodiment of the present invention will be described with reference to FIG. Reveal.

[0242] The read circuit shown in FIG. 20 includes a transistor 206 and a differential amplifier.

[0243] When reading, terminal A is connected to the second wiring BL to which the memory cell to be read is connected. The potential Vdd is applied to either the source or drain electrode of the transistor 206. A bias voltage Vbias is applied to the gate electrode of the transistor 206. and a predetermined current flows.

[0244] The resistance of the memory cell varies depending on the data stored, "1" or "0". When the transistor 201 of the selected memory cell is in an on state, the resistance is low. When the transistor 201 of the memory cell is in an off state, it is in a high resistance state.

[0245] When the memory cell is in a high resistance state, the potential at terminal A becomes higher than the reference potential Vref, and the differential amplifier On the other hand, when the memory cell is in a low resistance state, the terminal The potential at A becomes lower than the reference potential Vref, and the differential amplifier outputs data "0". will be done.

[0246] In this way, the read circuit can read data from the memory cell. The readout circuit of this embodiment is an example. Other known circuits may be used. For example, A precharge circuit may be provided. Instead of the differential amplifier, a latch-type sense amplifier may be used. stomach.

[0247] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0248] (Embodiment 6) In this embodiment, an example of an electronic device equipped with the semiconductor device obtained in the above embodiment will be described. The semiconductor device obtained in the above embodiment is a semiconductor device that does not require power supply. Even if the data is written or erased, it is possible to retain the data. Furthermore, the operation is also fast. Therefore, it is possible to use this semiconductor device to develop new electrical circuits. It is possible to provide a sub-device. The semiconductor device is then mounted on a circuit board or the like and installed inside various electronic devices.

[0249] FIG. 21A shows a notebook personal computer including the semiconductor device according to the above embodiment. The computer is composed of a main body 301, a housing 302, a display unit 303, a keyboard 304, etc. The semiconductor device according to one embodiment of the present invention is implemented in a notebook personal computer. By applying this technology, it is possible to retain information even when there is no power supply. There is no deterioration due to writing and erasing. Furthermore, the operation is fast. The semiconductor device according to the present invention is preferably applied to a notebook personal computer. is.

[0250] FIG. 21B shows a personal digital assistant (PDA) including the semiconductor device according to the above embodiment. The main body 311 includes a display unit 313, an external interface 315, an operation button 314, etc. The stylus 312 is also provided as an accessory for operation. By applying the semiconductor device according to the present invention to a PDA, information can be retained even when there is no power supply. In addition, there is no deterioration due to writing and erasing. Therefore, it is preferable to apply the semiconductor device according to one aspect of the present invention to a PDA. is.

[0251] FIG. 21C shows an example of electronic paper including the semiconductor device according to the above embodiment. The electronic book 320 is shown. The electronic book 320 is made up of two housings, housing 321 and housing 323. The housing 321 and the housing 323 are integrated by a shaft portion 337. The opening and closing operation can be performed around the axis 337. The semiconductor device 320 can be used like a paper book. By applying this technology to electronic paper, it is possible to retain information even when there is no power supply. In addition, there is no deterioration due to writing and erasing. Furthermore, the operation is fast. For this reason, it is preferable to apply a semiconductor device according to one embodiment of the present invention to electronic paper. do.

[0252] The housing 321 incorporates a display unit 325, and the housing 323 incorporates a display unit 327. The display unit 325 and the display unit 327 may be configured to display a continuous screen, or may be configured to display different screens. By configuring to display different screens, for example, The text is displayed on the right display unit (display unit 325 in FIG. 21(C)), and the text is displayed on the left display unit (display unit 325 in FIG. 21(C)). In (C), an image can be displayed on the display unit 327).

[0253] FIG. 21C shows an example in which an operation unit and the like are provided on the housing 321. The body 321 includes a power supply 331, operation keys 333, a speaker 335, etc. You can turn the page by pressing the arrow 333. In addition, there is a keyboard and a pointer on the same surface as the display unit of the housing. The back and sides of the housing may be provided with an external Connection terminals (earphone jack, USB terminal, AC adapter and USB cable, etc.) terminals that can be connected to various cables, a recording medium insertion section, etc. Furthermore, the electronic book 320 may be configured to have the function of an electronic dictionary.

[0254] The electronic book 320 may also be configured to be able to send and receive information wirelessly. It is also possible to purchase and download desired book data from the child book server. It is possible.

[0255] Electronic paper can be applied to any field that displays information. For example, in addition to e-books, posters, advertisements on trains and other vehicles, credit cards, etc. The present invention can be applied to displays on various cards such as gift cards.

[0256] FIG. 21D shows a mobile phone including the semiconductor device according to the above embodiment. The phone is made up of two housings, housing 340 and housing 341. Housing 341 has a front display panel 342, speaker 343, microphone 344, pointing device 3 46, a camera lens 347, an external connection terminal 348, etc. The mobile phone includes a solar cell 349 for charging the mobile phone, an external memory slot 350, etc. The antenna is built into the housing 341. By applying the body device to a mobile phone, information can be retained even when there is no power supply. In addition, there is no deterioration due to writing and erasing. Therefore, it is preferable to apply the semiconductor device according to one embodiment of the present invention to a mobile phone. be.

[0257] The display panel 342 has a touch panel function, and in FIG. 21(D) an image is displayed. The multiple operation keys 345 are shown by dotted lines. A boost circuit is implemented to boost the voltage output by 9 to the voltage required for each circuit. In addition to the above configuration, it may be configured to incorporate a contactless IC chip, a small recording device, etc. It is also possible.

[0258] The display direction of the display panel 342 changes appropriately depending on the usage mode. The camera lens 347 is located on the same surface as the camera 42, making it possible to make video calls. The speaker 343 and microphone 344 are not limited to voice calls, but also video calls, recording, playback Furthermore, the housing 340 and the housing 341 can be slid, and as shown in FIG. It can be folded from the unfolded state to the overlapping state, making it possible to make it compact and portable. It is Noh.

[0259] The external connection terminal 348 can be connected to various cables such as an AC adapter or a USB cable. The external memory slot 350 can store a recording medium. It can insert and store and move larger amounts of data. In addition to the above functions, It may also be equipped with infrared communication functions, television reception functions, etc.

[0260] FIG. 21E shows a digital camera including the semiconductor device according to the previous embodiment. The digital camera comprises a main body 361, a display unit (A) 367, an eyepiece 363, and an operation switch 364. , a display unit (B) 365, a battery 366, etc. By applying the semiconductor device according to the present invention to a digital camera, information can be stored even when there is no power supply. Furthermore, there is no deterioration due to writing and erasing. Therefore, the semiconductor device according to one embodiment of the present invention is suitable for a digital camera. It is preferable to use

[0261] FIG. 21F shows a television set including the semiconductor device according to the above embodiment. In the vision device 370, a display unit 373 is built into a housing 371. In this case, the stand 375 is used to hold the case in place. 371 is shown in the supporting configuration.

[0262] The television device 370 can be operated using an operation switch provided on the housing 371 or a separate remote control. This can be done by operating the operating device 380. The remote control operating device 380 has an operating key 379. This allows you to control the channel and volume, and to operate the image displayed on the display unit 373. In addition, the remote control operation device 380 can receive the output from the remote control operation device 380. A display unit 377 for displaying information may be provided. By applying the body device to a television device, information can be retained even when there is no power supply. In addition, there is no deterioration due to writing and erasing. Therefore, the semiconductor device according to one embodiment of the present invention is applied to a television set. This is preferable.

[0263] It is preferable that the television device 370 is configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts. By connecting to a wired or wireless communication network, The purpose of this communication is to communicate information between two parties (one party) or two-way (between a sender and a receiver, or between receivers). It is possible to do this.

[0264] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination. [Explanation of symbols]

[0265] 100 boards 102 Protective layer 104 Semiconductor Area 106 Element isolation insulating layer 108 Gate insulating layer 110 gate electrode 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulating layer 120 High concentration impurity region 122 Metal layer 124 Metal compound area 126 Interlayer insulation layer 128 Interlayer Insulation Layer 130a Source electrode or drain electrode 130b Source electrode or drain electrode 130c electrode 132 Insulating layer 134 Conductive Layer 136a electrode 136b Electrode 136c electrode 136d Gate electrode 138 Gate insulating layer 140 Oxide semiconductor layer 142a Source electrode or drain electrode 142b Source electrode or drain electrode 144 Protective Insulation Layer 146 Interlayer insulation layer 148 Conductive Layer 150a electrode 150b electrode 150c electrode 150d electrode 150e electrode 152 Insulating layer 154a electrode 154b electrode 154c electrode 154d electrode 160 transistors 162 transistors 200 memory cells 201 Transistor 202 Transistor 203 Transistor 204 Capacitor element 205 Capacitor 206 Transistor 210 memory cell array 211 Drive circuit for second wiring and third wiring 212 readout circuit 213 Driving circuit for fourth wiring and fifth wiring 215 transistors 220 memory cells 230 Memory Cell Array 231 Second wiring and fourth wiring drive circuit 232 readout circuit 233 Third wiring and fifth wiring drive circuit 235 transistors 240 memory cells 250 memory cell array 251 Second wiring and third wiring drive circuit 252 readout circuit 253 Driving circuit for fourth wiring and fifth wiring 255 transistors 260 memory cells 280 memory cells 301 Main Unit 302 Case 303 Display section 304 keyboard 311 Main Unit 312 Stylus 313 Display section 314 Operation Button 315 External Interface 320 e-books 321 Case 323 Case 325 Display section 327 Display section 331 Power supply 333 Operation Key 335 Speaker 337 Shaft 340 Case 341 Case 342 Display Panel 343 Speaker 344 Microphone 345 Operation Key 346 Pointing Device 347 Camera Lenses 348 External connection terminal 349 Solar Cells 350 external memory slot 361 Main Unit 363 Eyepiece 364 Operation Switch 365 Display section (B) 366 Battery 367 Display section (A) 370 Television Equipment 371 Case 373 Display section 375 Stand 377 Display section 379 Operation Key 380 Remote Controlled Device

Claims

1. A plurality of circuits arranged in a matrix, At least one circuit of the plurality of circuits includes a first transistor and a second transistor; one of the source and the drain of the second transistor is electrically connected to the gate electrode of the first transistor; a semiconductor device in which a potential corresponding to data is input to a gate electrode of the first transistor through at least a channel formation region of the second transistor, a silicon semiconductor layer having a channel formation region of the first transistor; a first conductive layer having a region disposed above the silicon semiconductor layer and functioning as a gate electrode of the first transistor; a first insulating layer having a region disposed above the first conductive layer; a second conductive layer having a region disposed above the first insulating layer and functioning as a gate electrode of the second transistor; a third conductive layer having a region disposed above the first insulating layer and electrically connected to the first conductive layer; an oxide semiconductor layer having a region disposed above the second conductive layer and including a channel formation region of the second transistor; a second insulating layer having a region disposed above the oxide semiconductor layer and a region disposed above the third conductive layer; a fourth conductive layer having a region disposed above the second insulating layer, electrically connected to the oxide semiconductor layer, and electrically connected to the first conductive layer via the third conductive layer; a fifth conductive layer having a region disposed above the second insulating layer and electrically connected to one of a source electrode or a drain electrode of the first transistor; the oxide semiconductor layer does not overlap with the first conductive layer; Semiconductor device.

2. A plurality of circuits arranged in a matrix, At least one circuit of the plurality of circuits includes a first transistor and a second transistor; one of the source and the drain of the second transistor is electrically connected to the gate electrode of the first transistor; a potential corresponding to data is input to a gate electrode of the first transistor via at least a channel formation region of the second transistor; a gate electrode of the second transistor is electrically connected to a drive circuit via a first wiring; a silicon semiconductor layer having a channel formation region of the first transistor; a first conductive layer having a region disposed above the silicon semiconductor layer and functioning as a gate electrode of the first transistor; a first insulating layer having a region disposed above the first conductive layer; a second conductive layer having a region disposed above the first insulating layer and functioning as a gate electrode of the second transistor; a third conductive layer having a region disposed above the first insulating layer and electrically connected to the first conductive layer; an oxide semiconductor layer having a region disposed above the second conductive layer and including a channel formation region of the second transistor; a second insulating layer having a region disposed above the oxide semiconductor layer and a region disposed above the third conductive layer; a fourth conductive layer having a region disposed above the second insulating layer, electrically connected to the oxide semiconductor layer, and electrically connected to the first conductive layer via the third conductive layer; a fifth conductive layer having a region disposed above the second insulating layer and electrically connected to one of a source electrode or a drain electrode of the first transistor; the oxide semiconductor layer does not overlap with the first conductive layer; Semiconductor device.

3. In claim 1 or claim 2, the fourth conductive layer contains at least one of chromium, copper, tantalum, titanium, molybdenum, and tungsten; Semiconductor device.

4. In any one of claims 1 to 3, the oxide semiconductor layer contains an In—O-based oxide semiconductor; Semiconductor device.

Images