Semiconductor device and semiconductor module

Abstract

To provide a semiconductor device that suppresses undesirable electric field concentration due to noise and suppresses a transformer from varying in electric characteristic.SOLUTION: A semiconductor device A3 includes: a semiconductor chip 40 which has a principal surface 401; a first conductive layer 36 which is formed on the principal surface 401; a first insulation part 50 which is formed on the principal surface 401 to cover a first conductive layer 36, and includes at least three or more first insulation layers 57; a second insulation part 7 which is formed on the first insulation part 50, and includes a second insulation layer 84 having a different dielectric constant from the first insulation layer 57 and not included in the first insulation part 50; and a second conductive layer 33 which is formed on the second insulation part 7, opposed to the first conductive layer 36 across the first insulation part 50 and second insulation part 7, and connected to a different potential from the first conductive layer 36.SELECTED DRAWING: Figure 36

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a semiconductor module including the semiconductor device. [Background technology]

[0002] For example, Patent Document 1 discloses an integrated circuit comprising: a power supply; a constant current source powered by the power supply and having an output terminal connected to the anode of a temperature-sensitive diode; a PWM comparator having a non-inverting input terminal and an inverting input terminal, with the voltage of the anode of the temperature-sensitive diode applied to the non-inverting input terminal and a carrier signal (triangular wave signal) output by a carrier generation circuit applied to the inverting input terminal; and a photocoupler connected to the output terminal of the PWM comparator as an isolation means for transmitting signals from one high-voltage system to the other while isolating the high-voltage system from the low-voltage system. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-7580 Summary of the Invention [Means for solving the problem]

[0004] A semiconductor device according to one embodiment of the present disclosure includes a semiconductor layer having a main surface, a first conductive layer formed on the main surface of the semiconductor layer, a first insulating section formed on the main surface of the semiconductor layer so as to cover the first conductive layer and including at least three or more first insulating layers, a second insulating section formed on the first insulating section and including a second insulating layer having a different dielectric constant from the first insulating layer and not included in the first insulating section, and a second conductive layer formed on the second insulating section, facing the first conductive layer via the first insulating section and the second insulating section, and connected to a potential different from that of the first conductive layer. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a plan view showing a semiconductor module according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a plan view showing the semiconductor module of FIG. 1 (sealing resin is omitted). [Figure 3] FIG. 3 is a left side view showing the semiconductor module of FIG. [Figure 4] FIG. 4 is a right side view showing the semiconductor module of FIG. [Figure 5] FIG. 5 is a front view showing the semiconductor module of FIG. [Figure 6] FIG. 6 is a rear view showing the semiconductor module of FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. [Figure 9] FIG. 9 is a plan view showing the lead frame of the semiconductor module of FIG. [Figure 10] FIG. 10 is a schematic diagram of a vehicle according to one embodiment of the present disclosure. [Figure 11] FIG. 11 is a block diagram showing an example configuration of a motor drive device according to an embodiment of the present disclosure. [Figure 12] FIG. 12 is a detailed diagram of the transmitting and receiving circuit portion via the transformer. [Figure 13] FIG. 13 is a schematic diagram showing an example of the terminal arrangement of a semiconductor module and the chip arrangement within the sealing resin. [Figure 14] FIG. 14 is an example of an explanation table for the external terminals of a semiconductor module. [Figure 15] FIG. 15 is an example of an electrical characteristics table of the semiconductor module 1. [Figure 16] FIG. 16 is a circuit block diagram showing a first embodiment of a signal transmission device. [Figure 17] FIG. 17 is a schematic plan view of a semiconductor device according to an embodiment of the present disclosure. [Figure 18] FIG. 18 is a plan view showing a layer in which a low potential coil is formed in the semiconductor device of FIG. [Figure 19] FIG. 19 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device of FIG. [Figure 20] FIG. 20 is a schematic cross-sectional view of the semiconductor device of FIG. [Figure 21] FIG. 21 is an enlarged view of a main part of the semiconductor device of FIG. [Figure 22] FIG. 22 is an enlarged view of area A in FIG. [Figure 23] FIG. 23 is an enlarged view of region B in FIG. [Figure 24] FIG. 24 is an enlarged view of area C in FIG. [Figure 25A] FIG. 25A is a diagram showing a part of the manufacturing process of the semiconductor device of FIG. [Figure 25B] FIG. 25B is a diagram showing a part of the manufacturing process of the semiconductor device of FIG. [Figure 26A] FIG. 26A is a diagram showing the next step of FIG. 25A. [Figure 26B] FIG. 26B shows the next step in FIG. 25B. [Figure 27A] FIG. 27A shows the next step in FIG. 26A. [Figure 27B] FIG. 27B shows the next step in FIG. 26B. [Figure 28A] FIG. 28A shows the next step in FIG. 27A. [Figure 28B] FIG. 28B shows the next step in FIG. 27B. [Figure 29A] FIG. 29A shows the next step in FIG. 28A. [Figure 29B] FIG. 29B shows the next step in FIG. 28B. [Figure 30A] FIG. 30A shows the next step in FIG. 29A. [Figure 30B] FIG. 30B shows the next step in FIG. 29B. [Figure 31A]FIG. 31A shows the next step in FIG. 30A. [Figure 31B] FIG. 31B shows the next step in FIG. 30B. [Figure 32A] FIG. 32A shows the next step in FIG. 31A. [Figure 32B] FIG. 32B is a diagram showing the next step of FIG. 31B. [Figure 33] FIG. 33 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. [Figure 34] FIG. 34 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. [Figure 35] FIG. 35 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. [Figure 36] FIG. 36 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. [Figure 37] FIG. 37 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. [Figure 38] FIG. 38 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. [Figure 39] FIG. 39 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. [Figure 40] FIG. 40 is a schematic plan view of a semiconductor device according to an embodiment of the present disclosure. [Figure 41] FIG. 41 is a plan view showing a layer in which a low potential coil is formed in the semiconductor device of FIG. [Figure 42] FIG. 42 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device of FIG. [Figure 43] FIG. 43 is a schematic cross-sectional view of the semiconductor device of FIG. [Figure 44] FIG. 44 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. [Figure 45] FIG. 45 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. [Figure 46]FIG. 46 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. [Figure 47] FIG. 47 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. [Figure 48] FIG. 48 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. [Figure 49] FIG. 49 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. [Figure 50] FIG. 50 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. [Figure 51] FIG. 51 is a schematic plan view of a semiconductor device according to an embodiment of the present disclosure. [Figure 52] FIG. 52 is a plan view showing a layer in which a low potential coil is formed in the semiconductor device of FIG. [Figure 53] FIG. 53 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device of FIG. [Figure 54] FIG. 54 is a schematic cross-sectional view of the semiconductor device of FIG. [Figure 55] FIG. 55 is an enlarged view of a main part of the semiconductor device of FIG. [Figure 56] FIG. 56 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. [Figure 57] FIG. 57 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. [Figure 58] FIG. 58 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. [Figure 59] FIG. 59 is a schematic plan view of a semiconductor device D1 according to an embodiment of the present disclosure. [Figure 60] FIG. 60 is a plan view showing a layer in which the low potential coil 915 is formed in the semiconductor device D1 of FIG. [Figure 61] FIG. 61 is a plan view showing the layer in which the high-potential coil 916 is formed in the semiconductor device D1 of FIG. [Figure 62]FIG. 62 is a schematic cross-sectional view of the semiconductor device D1 of FIG. [Figure 63] FIG. 63 is a diagram for explaining the effect of the semiconductor device of FIG. [Figure 64] FIG. 64 is a schematic cross-sectional view of a semiconductor device D1 according to an embodiment of the present disclosure. [Figure 65] FIG. 65 is a diagram for explaining the effect of the semiconductor device of FIG. [Figure 66] FIG. 66 is a schematic cross-sectional view of a semiconductor device D1 according to an embodiment of the present disclosure. [Figure 67] FIG. 67 is a schematic plan view of a semiconductor device E1 according to an embodiment of the present disclosure. [Figure 68] FIG. 68 is a plan view showing a layer in which the low potential coil 20 is formed in the semiconductor device E1 of FIG. [Figure 69] FIG. 69 is a plan view showing the layer in which the high-potential coil 1016 is formed in the semiconductor device E1 of FIG. [Figure 70] FIG. 70 is a schematic cross-sectional view of the semiconductor device E1 of FIG. [Figure 71] FIG. 71 is an enlarged view of a main part of the high potential coil 1016 of FIG. [Figure 72] FIG. 72 shows the steps involved in forming the high potential coil 1016 of FIG. [Figure 73] FIG. 73 shows the next step in FIG. [Figure 74] FIG. 74 shows the next step in FIG. [Figure 75] FIG. 75 shows the next step in FIG. [Figure 76] FIG. 76 shows the next step in FIG. [Figure 77] FIG. 77 shows the next step of FIG. [Figure 78] FIG. 78 is a schematic cross-sectional view of a semiconductor device E1 according to an embodiment of the present disclosure. [Figure 79] FIG. 79 is a schematic cross-sectional view of a semiconductor device E1 according to an embodiment of the present disclosure. [Figure 80] FIG. 80 is an enlarged view of a main part of the high potential coil 1016 of FIG. [Figure 81] FIG. 81 shows the steps involved in forming the high potential coil 1016 of FIG. [Figure 82] FIG. 82 shows the next step in FIG. [Figure 83] FIG. 83 shows the next step in FIG. [Figure 84] FIG. 84 shows the next step of FIG. [Figure 85] FIG. 85 shows the next step of FIG. [Figure 86] FIG. 86 is a schematic cross-sectional view of a semiconductor device E1 according to an embodiment of the present disclosure. [Figure 87] FIG. 87 shows a modification of the embodiment. [Figure 88] FIG. 88 shows a modification of the embodiment. [Figure 89] FIG. 89 shows a modification of the embodiment. [Figure 90] FIG. 90 shows a modification of the embodiment. [Figure 91] FIG. 91 shows a modification of the embodiment. [Figure 92] FIG. 92 shows a modification of the embodiment. [Figure 93] FIG. 93 is a diagram showing a modification of the above embodiment. [Figure 94] FIG. 94 is a diagram showing a modification of the above embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0006] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. [Semiconductor module structure] The structure of the semiconductor module 1 will be described with reference to Figures 1 to 9. For convenience of explanation, the up-down direction in the plan view is defined as a first direction X, and the left-right direction in the plan view, which is perpendicular to the first direction X, is defined as a second direction Y. Both the first direction X and the second direction Y are perpendicular to the thickness direction of the semiconductor module 1.

[0007] FIG. 1 is a plan view showing a semiconductor module 1. FIG. 2 is a plan view in which the sealing resin 6 described below is omitted from FIG. 1 for ease of understanding. FIG. 3 is a left side view showing the semiconductor module 1. FIG. 4 is a right side view showing the semiconductor module 1. FIG. 5 is a front view showing the semiconductor module 1. FIG. 6 is a rear view showing the semiconductor module 1. FIG. 7 is a cross-sectional view taken along line VII-VII (a dashed line) in FIG. 2. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 2. In FIG. 2, the sealing resin 6 is shown by an imaginary line (a dashed line). In FIGS. 7 and 8, the sealing resin 6 is not omitted.

[0008] The semiconductor module 1 is surface-mounted on a circuit board of an inverter device in, for example, an electric vehicle or a hybrid vehicle, and is packaged in an SOP format. Note that the semiconductor module 1 is not limited to an SOP, and may be packaged in various formats such as a QFN (Quad For Non-Lead Package), a DFP (Dual Flat Package), a DIP (Dual Inline Package), a QFP (Quad Flat Package), a SIP (Single Inline Package), or an SOJ (Small Outline J-leaded Package), or similar.

[0009] The semiconductor module 1 includes a semiconductor element 11, an insulating element 12, a conductive support member 80, a sealing resin 6, bonding wires 71, an interior plating layer 72, and an exterior plating layer 73. In this embodiment, the semiconductor module 1 has a rectangular shape in a plan view.

[0010] The semiconductor element 11 and the insulating element 12 are elements that cause the semiconductor module 1 to function. The semiconductor element 11 includes a control element 111 and a drive element 112. The control element 111 has a circuit that converts a control signal input from, for example, an ECU into a PWM control signal, a transmission circuit that transmits the PWM control signal to the drive element 112, and a receiving circuit that receives an electrical signal from the drive element 112. The drive element 112 has a receiving circuit that receives the PWM control signal, a circuit (gate driver) that performs a switching operation of a power semiconductor element such as an IGBT based on the PWM signal, and a transmission circuit that transmits an electrical signal to the control element 111. The electrical signal can be, for example, an output signal from a temperature sensor installed near the motor.

[0011] Isolation element 12 is an element for transmitting the PWM control signal and other electrical signals in an insulated state. Because drive element 112 requires a higher voltage than control element 111, a significant potential difference occurs between control element 111 and drive element 112, which is why isolation element 12 is necessary. Specifically, in an inverter device for an electric vehicle or hybrid vehicle, for example, the power supply voltage supplied to control element 111 is 5 V or 3.3 V with respect to the ground potential.

[0012] In contrast, a voltage of, for example, 600 V or more is transiently applied to the drive element 112 compared to the ground potential of the control element 111. More specifically, a motor driver circuit in an inverter device for a hybrid vehicle or the like generally uses a half-bridge circuit in which a low-side switching element and a high-side switching element are connected in a totem pole configuration.

[0013] In an isolated gate driver, only one switch, either the low-side switching element or the high-side switching element, is turned on at any given time. In a high-voltage system, the source of the low-side switching element and the reference potential of the isolated gate driver that drives that switching element are connected to ground potential, so the gate-source voltage operates with respect to ground potential. On the other hand, the source of the high-side switching element and the reference potential of the isolated gate driver that drives that switching element are connected to the output node of the half-bridge circuit. Depending on whether the low-side switching element or the high-side switching element is on, the potential of the output node of the half-bridge circuit changes, so the reference potential of the isolated gate driver that drives the high-side switching element changes. When the high-side switching element is on, the reference potential becomes a voltage equivalent to the voltage applied to the drain of the high-side switching element (e.g., 600 V or higher).

[0014] When the semiconductor module 1 is used as an insulated gate driver that drives a high-side switching element, the ground potentials of the driving element 112 and the control element 111 are separated to ensure insulation, and therefore a voltage of 600 V or more is transiently applied to the driving element 112 compared to the ground potential of the control element 111. Therefore, particularly in an insulated gate driver that drives a switching element on the high side, a voltage of 600 V or more is transiently applied to the driving element 112 compared to the ground potential of the control element 111. The ground potential of the driving element 112 may be common to the external element (power transistor) described above.

[0015] In this embodiment, the insulating element 12 is an inductively coupled insulating element. An inductively coupled insulating element transmits electrical signals in an isolated state by inductively coupling two inductors (coils). The insulating element 12 has a substrate made of Si. An inductor made of Cu is formed on the substrate. The inductors include a transmitting inductor and a receiving inductor, and these inductors are stacked on top of each other in the thickness direction of the insulating element 12. A dielectric layer made of SiO2 or the like is interposed between the transmitting inductor and the receiving inductor. The dielectric layer electrically insulates the transmitting inductor from the receiving inductor. The specific structure of the insulating element 12 will be described later.

[0016] As shown in FIG. 2, the insulating element 12 is located between the control element 111 and the driving element 112 in the second direction Y. In this embodiment, the control element 111, the driving element 112, and the insulating element 12 all have a rectangular shape in plan view with their longer sides extending in the first direction X. The control element 111 and the insulating element 12 are mounted on a first die pad 21 of a die pad 2, which will be described later. The driving element 112 is mounted on a second die pad 22 of the die pad 2, which will be described later. A plurality of pads 111a are formed on the upper surface of the control element 111 (the upper surface of the control element 111 shown in FIG. 7). Similarly, a plurality of pads 112a are formed on the upper surface of the driving element 112 (the upper surface of the driving element 112 shown in FIG. 7), and a plurality of pads 12a are formed on the upper surface of the insulating element 12 (the upper surface of the insulating element 12 shown in FIG. 7).

[0017] The conductive support member 80 is a member in the semiconductor module 1 that carries the semiconductor element 11 and the insulating element 12 and that forms a conductive path between the semiconductor element 11 and the insulating element 12 and the circuit board of the inverter device. The conductive support member 80 is made of an alloy containing Cu, for example. The conductive support member 80 is formed from a lead frame 81, which will be described later. The conductive support member 80 includes a die pad 2, a plurality of first terminals 3, a plurality of second terminals 4, and a support terminal 5.

[0018] The die pad 2 is a member on which the semiconductor element 11 and the insulating element 12 are mounted. The die pad 2 includes a first die pad 21 and a second die pad 22. As shown in FIG. 2, the first die pad 21 and the second die pad 22 are spaced apart from each other in the second direction Y. In this embodiment, the area of ​​the first die pad 21 is larger than the area of ​​the second die pad 22. In addition, in this embodiment, the first die pad 21 and the second die pad 22 each have a rectangular shape in plan view with the longer side extending in the first direction X. As shown in FIGS. 7 and 8, the first die pad 21 and the second die pad 22 are both flat.

[0019] 7 and 8, the first die pad 21 has a first die pad upper surface 211 and a first die pad lower surface 212. The first die pad upper surface 211 and the first die pad lower surface 212 face in opposite directions. In this embodiment, an interior plating layer 72 is formed on the first die pad upper surface 211. The control element 111 and the insulating element 12 are respectively mounted on the interior plating layer 72 formed on the first die pad upper surface 211 by die bonding via a bonding layer (not shown). The entire surface of the first die pad lower surface 212 is in contact with the sealing resin 6.

[0020] 7, the second die pad 22 has a second die pad upper surface 221 and a second die pad lower surface 222. The second die pad upper surface 221 and the second die pad lower surface 222 face opposite each other. In this embodiment, an interior plating layer 72 is formed on the second die pad upper surface 221. The driving element 112 is mounted on the interior plating layer 72 formed on the second die pad upper surface 221 by die bonding via a bonding layer (not shown). The entire surface of the second die pad lower surface 222 is in contact with the sealing resin 6.

[0021] 2 and 7, a sealing resin 6 is interposed between the first die pad 21 and the second die pad 22 in the second direction Y. In this embodiment, the sealing resin 6 is made of, for example, a black epoxy resin having electrical insulation properties, as will be described later. Therefore, the first die pad 21 and the second die pad 22 are electrically insulated by the insulating element 12 and the sealing resin 6.

[0022] The multiple first terminals 3 are components that are joined to a circuit board of an inverter device to form a conductive path between the semiconductor module 1 and the circuit board. As shown in FIGS. 1 and 3 , the multiple first terminals 3 are arranged along a first direction X. Furthermore, the multiple first terminals 3 are exposed from one first resin side surface 63 of a sealing resin 6 (described later) so as to extend in a second direction Y. The multiple first terminals 3 include multiple first intermediate terminals 31 and a pair of first side terminals 32.

[0023] 2 and 3, the first intermediate terminals 31 are arranged in the first direction X, sandwiched between a pair of first side terminals 32. Each of the first intermediate terminals 31 has a lead portion 311 and a pad portion 312.

[0024] The lead portion 311 is a rectangular portion extending along the second direction Y, and as shown in FIGS. 5 and 6, the portion exposed from the one resin first side surface 63 is bent into a gull-wing shape. Furthermore, as shown in FIG. 7, the exposed portion is covered with an exterior plating layer 73. Portions of the lead portion 311 where the exterior plating layer 73 is not formed are covered with the sealing resin 6. The pad portion 312 is connected to the lead portion 311 and is a rectangular portion that is wider than the lead portion 311 in the first direction X. As shown in FIG. 7, in this embodiment, an interior plating layer 72 is formed on the upper surface of the pad portion 312. The entire surface of the pad portion 312 is covered with the sealing resin 6. Furthermore, the pad portion 312 is flat.

[0025] 2 and 3, the pair of first side terminals 32 are arranged on both sides of the plurality of first intermediate terminals 31 in the first direction X. Each of the pair of first side terminals 32 has a lead portion 321 and a pad portion 322.

[0026] The lead portion 321 is an elongated rectangular portion extending along the second direction Y, and as shown in FIGS. 5 and 6 , the portion exposed from the one resin first side surface 63 is bent into a gull-wing shape. Similar to the lead portion 311 of the first intermediate terminal 31, the exposed portion is covered with an exterior plating layer 73. The portion of the lead portion 321 where the exterior plating layer 73 is not formed is covered with the sealing resin 6. The pad portion 322 is connected to the lead portion 321 and is wider than the lead portion 321 in the first direction X. In this embodiment, similar to the pad portion 312 of the first intermediate terminal 31, an interior plating layer 72 is formed on the upper surface of the pad portion 322 (the surface facing the same direction as the first die pad upper surface 211 in FIG. 7 ). The entire surface of the pad portion 322 is covered with the sealing resin 6. The pad portion 322 is flat.

[0027] Like the multiple first terminals 3, the multiple second terminals 4 are members that are joined to a circuit board of an inverter device to form a conductive path between the semiconductor module 1 and the circuit board. As shown in FIGS. 1 and 4 , the multiple second terminals 4 are arranged along a first direction X. As shown in FIG. 2 , the multiple second terminals 4 are located on the opposite side of the multiple first terminals 3 in the second direction Y, with the semiconductor element 11 sandwiched between them. The multiple second terminals 4 are exposed from the other first resin side surface 63 of the sealing resin 6, which will be described later, so as to extend in the second direction Y. The multiple second terminals 4 include multiple second intermediate terminals 41 and a pair of second side terminals 42.

[0028] 2 and 4, the second intermediate terminals 41 are arranged in the first direction X, sandwiched between a pair of second side terminals 42. Furthermore, the second intermediate terminals 41 are arranged in the first direction X, sandwiched between a pair of second support terminals 52 of a support terminal 5, which will be described later. Each of the second intermediate terminals 41 has a lead portion 411 and a pad portion 412.

[0029] The lead portion 411 is an elongated rectangular portion extending along the second direction Y. As shown in FIGS. 5 and 6, the portion exposed from the other resin first side surface 63 is bent into a gull-wing shape. As shown in FIG. 7, the exposed portion is covered with an exterior plating layer 73. The portion of the lead portion 411 where the exterior plating layer 73 is not formed is covered with the sealing resin 6. The pad portion 412 is connected to the lead portion 411 and has a rectangular shape that is wider than the lead portion 411 in the first direction X. As shown in FIG. 7, an interior plating layer 72 is formed on the upper surface of the pad portion 412 (the upper surface of the pad portion 412 shown in FIG. 7). The entire surface of the pad portion 412 is covered with the sealing resin 6. The pad portion 412 is flat. In this embodiment, the shape of the second terminal 4 is the same as the shape of the first terminal 3.

[0030] 2 and 4, the pair of second side terminals 42 are arranged on both sides of the plurality of second side terminals 42 in the first direction X. Each of the pair of second side terminals 42 has a lead portion 421 and a pad portion 422.

[0031] The lead portion 421 is an elongated rectangular portion extending along the second direction Y, and as shown in FIGS. 5 and 6 , the portion exposed from the other resin first side surface 63 is bent into a gull-wing shape. Similar to the lead portion 411 of the second intermediate terminal 41, the exposed portion is covered with an exterior plating layer 73. Portions of the lead portion 421 on which the exterior plating layer 73 is not formed are covered with the sealing resin 6. The length of the portion of the lead portion 421 covered with the sealing resin 6 is longer than the length of the corresponding portion of the lead portion 411 of the second intermediate terminal 41. The pad portion 422 is connected to the lead portion 421 and extends in the first direction X. As shown in FIG. 2 , an end of the pad portion 422 is spaced apart from the second die pad 22. In this embodiment, an interior plating layer 72 is formed on the upper surface of the pad portion 422 (the surface facing in the same direction as the second die pad upper surface 221 in FIG. 7), similar to the pad portion 412 of the second intermediate terminal 41. The pad portion 422 is entirely covered with the sealing resin 6. The pad portion 422 is also flat.

[0032] The support terminals 5 are connected to the die pad 2. The support terminals 5 are members that support the die pad 2 and, like the plurality of first terminals 3 and the plurality of second terminals 4, are joined to the circuit board of the inverter device to form a conductive path between the semiconductor module 1 and the circuit board. The support terminals 5 include one configured from a pair of members, and further include a pair of first support terminals 51 and a pair of second support terminals 52. As shown in FIG. 2 , the pair of first support terminals 51 are arranged spaced apart in the first direction X and are connected to both ends of the first die pad 21. The pair of second support terminals 52 are arranged spaced apart in the first direction X and are connected to both ends of the second die pad 22.

[0033] 2 and 3, the pair of first support terminals 51 are arranged on both sides of the plurality of first terminals 3 in the first direction X. The pair of first support terminals 51 are exposed so as to extend in the second direction Y from the one first resin side surface 63 on which the plurality of first terminals 3 are exposed. Each of the pair of first support terminals 51 has a lead portion 511 and a pad portion 512.

[0034] The lead portion 511 is an elongated rectangular portion extending along the second direction Y. As shown in FIGS. 5 and 6 , the portion exposed from the first resin side surface 63 is bent into a gull-wing shape. Similar to the lead portion 311 of the first intermediate terminal 31, the exposed portion is covered with an exterior plating layer 73. The portion of the lead portion 511 not covered with the exterior plating layer 73 is covered with the sealing resin 6. The length of the portion of the lead portion 511 covered with the sealing resin 6 is longer than the length of the lead portion 311 of the first intermediate terminal 31 or the corresponding portion of the lead portion 311 of the first side terminal 32. The pad portion 512 is connected to the lead portion 511 and extends in the first direction X. As shown in FIG. 2 , an end of the pad portion 512 is connected to the first die pad 21. As shown in FIG. 8 , in this embodiment, similar to the pad portion 312 of the first intermediate terminal 31, an interior plating layer 72 is formed on the upper surface of the pad portion 512. The entire surface of the pad portion 512 is covered with the sealing resin 6. The pad portion 512 is flat.

[0035] 2 and 4, a plurality of second intermediate terminals 41 are arranged inside the pair of second support terminals 52 in the first direction X. Furthermore, the second side terminals 42 are arranged outside the pair of second support terminals 52 in the first direction X. Therefore, the second terminals 4 are arranged on both sides of each of the pair of second support terminals 52. The pair of second support terminals 52 are exposed so as to extend in the second direction Y from the other first resin side surface 63 from which the plurality of second terminals 4 are exposed. Each of the pair of second support terminals 52 has a lead portion 521, a pad portion 522, and a connecting portion 524.

[0036] The lead portion 521 is an elongated rectangular portion extending along the second direction Y, and as shown in FIGS. 5 and 6 , the portion exposed from the other resin first side surface 63 is bent into a gull-wing shape. Similar to the lead portion 411 of the second intermediate terminal 41, the exposed portion is covered with an exterior plating layer 73. The portion of the lead portion 521 where the exterior plating layer 73 is not formed is covered with the sealing resin 6. The pad portion 522 is connected to the lead portion 521 and is wider than the lead portion 521 in the first direction X. The pad portion 522 extends in the second direction Y. In this configuration, similar to the pad portion 412 of the second intermediate terminal 41, an interior plating layer 72 is formed on the upper surface of the pad portion 522 (the surface facing the same direction as the second die pad upper surface 221 in FIG. 7 ). The entire surface of the pad portion 522 is covered with the sealing resin 6. The pad portion 522 is flat. The connecting portion 524 is a portion that is connected to the pad portion 522 and extends in the first direction X. As shown in FIG. 2, an end of the connecting portion 524 is connected to the second die pad 22. In this embodiment, similar to the pad portion 522, an interior plating layer 72 is formed on the upper surface of the connecting portion 524 (the surface facing in the same direction as the upper surface of the pad portion 522). The connecting portion 524 is entirely covered with the sealing resin 6.

[0037] Fig. 9 is a plan view showing a lead frame 81 of the semiconductor module 1. In Fig. 9, the region where the sealing resin 6 is formed is indicated by an imaginary line (two-dot chain line), and the region where the interior plating layer 72 is formed is indicated by a diagonal line.

[0038] The aforementioned conductive support member 80 is formed from a lead frame 81. In the manufacturing process of the semiconductor module 1, the die pad 2, the plurality of first terminals 3, the plurality of second terminals 4, and the support terminal 5 are all formed from the same lead frame 81. The lead frame 81 is made of an alloy containing Cu, for example. The lead frame 81 has an outer frame 811, an island portion 812, a plurality of first leads 813, a plurality of second leads 814, a support lead 815, and a dam bar 816. Of these, the outer frame 811 and the dam bar 816 do not constitute the semiconductor module 1. The lead frame 81 will be described below with reference to FIG. 9.

[0039] The outer frame 811 is a member formed to surround the island portion 812, the plurality of first leads 813, the plurality of second leads 814, the support lead 815, and the dam bar 816. The plurality of first leads 813, the plurality of second leads 814, and the support lead 815 are connected to each other along the first direction X of the outer frame 811. In addition, the dam bar 816 is connected to the outer frame 811 along the second direction Y.

[0040] The island portion 812 is a rectangular member with its long sides extending in the first direction X in a plan view. The island portion 812 corresponds to the die pad 2. The island portion 812 is supported by the outer frame 811 via support leads 815. The island portion 812 includes a first island portion 812a and a second island portion 812b. The first island portion 812a corresponds to the first die pad 21, and the second island portion 812b corresponds to the second die pad 22. The first island portion 812a and the second island portion 812b are arranged spaced apart from each other.

[0041] The multiple first leads 813 are arranged along the first direction X and are components that each extend in the second direction Y. The multiple first leads 813 correspond to the multiple first terminals 3. One end of each of the first leads 813 is connected to the outer frame 811. The multiple first leads 813 include multiple first intermediate leads 813a and a pair of first side leads 813b. The first intermediate lead 813a corresponds to the first intermediate terminals 31, and the first side lead 813b corresponds to the first side terminals 32.

[0042] The multiple second leads 814 are arranged along the first direction X and each extend in the second direction Y. The multiple second leads 814 are located on opposite sides of the island portion 812 in the second direction Y. The multiple second leads 814 correspond to the multiple second terminals 4. One end of each second lead 814 is connected to the outer frame 811. The multiple second leads 814 include multiple second intermediate leads 814a and a pair of second side leads 814b. The second intermediate lead 814a corresponds to the second intermediate terminal 41, and the second side lead 814b corresponds to the second side terminal 42.

[0043] The support leads 815 are components that extend in the second direction Y and have one end connected to the outer frame 811 and the other end connected to the island portion 812. The support leads 815 correspond to the support terminals 5. The support leads 815 include a pair of first support leads 815a and a pair of second support leads 815b. The first support leads 815a correspond to the first support terminals 51, and the second support leads 815b correspond to the second support terminals 52. The pair of first support leads 815a are spaced apart in the first direction X and are connected to both ends of the first island portion 812a. The pair of second support leads 815b are spaced apart in the first direction X and are connected to both ends of the second island portion 812b.

[0044] The dam bars 816 are a pair of members that extend in the first direction X and have both ends connected to the outer frame 811. The dam bars 816 support the multiple first leads 813, the multiple second leads 814, and the support leads 815 in the first direction X, and also function to hold back the molten synthetic resin in the process of forming the sealing resin 6. One dam bar 816 is connected to the multiple first intermediate leads 813a, a pair of first side leads 813b, and a pair of first support leads 815a. The other dam bar 816 is connected to the multiple second intermediate leads 814a, a pair of second side leads 814b, and a pair of second support leads 815b.

[0045] The sealing resin 6 is made of, for example, black epoxy resin having electrical insulation properties. The sealing resin 6 covers a portion of each of the plurality of first terminals 3, the plurality of second terminals 4, and the support terminal 5, as well as the semiconductor element 11, the insulating element 12, the die pad 2, the bonding wires 71, and the interior plating layer 72. The sealing resin 6 is formed by transfer molding using a mold. The sealing resin 6 has a resin upper surface 61, a resin lower surface 62, a pair of resin first side surfaces 63, and a pair of resin second side surfaces 64.

[0046] 3 to 6, the resin upper surface 61 is a surface facing upward. The resin lower surface 62 is a surface facing downward. The resin upper surface 61 and the resin lower surface 62 face in opposite directions. Both the resin upper surface 61 and the resin lower surface 62 are flat.

[0047] 1 and 2, a pair of resin first side surfaces 63 are formed and spaced apart in the second direction Y. The pair of resin first side surfaces 63 face opposite each other. In this embodiment, a plurality of first terminals 3 and a pair of first support terminals 51 are exposed from one resin first side surface 63. Furthermore, a plurality of second terminals 4 and a pair of second support terminals 52 are exposed from the other resin first side surface 63.

[0048] 3 to 6, each of the pair of resin first side surfaces 63 has a resin first side surface upper portion 631, a resin first side surface central portion 632, and a resin first side surface lower portion 633. The resin first side surface upper portion 631 is a portion whose upper end is connected to the resin upper surface 61 and whose lower end is connected to the resin first side surface central portion 632. The resin first side surface upper portion 631 is inclined so that its upper end is located inside the semiconductor module 1.

[0049] As shown in FIGS. 3 to 6, resin first side surface central portion 632 is a portion whose upper end is connected to resin first side surface upper portion 631 and whose lower end is connected to resin first side surface lower portion 633. Resin first side surface central portion 632 is perpendicular to resin upper surface 61 and resin lower surface 62. A plurality of first terminals 3 and a pair of first support terminals 51 are exposed from one resin first side surface central portion 632. A plurality of second terminals 4 and a pair of second support terminals 52 are exposed from the other resin first side surface central portion 632.

[0050] 3 to 6, resin first side surface lower portion 633 is a portion whose upper end is connected to resin first side surface central portion 632 and whose lower end is connected to resin lower surface 62. Resin first side surface lower portion 633 is inclined so that its lower end is located inside semiconductor module 1.

[0051] 1 and 2, the pair of resin second side surfaces 64 are formed to be spaced apart in the first direction X. The pair of resin second side surfaces 64 face opposite each other. As shown in FIGS. 2, 5, and 6, in this embodiment, the conductive support member 80 is not exposed from the pair of resin second side surfaces 64. Each of the pair of resin second side surfaces 64 has a resin second side surface upper portion 641, a resin second side surface central portion 642, and a resin second side surface lower portion 643.

[0052] 3 to 6, resin second side surface upper portion 641 is a portion whose upper end is connected to resin upper surface 61 and whose lower end is connected to resin second side surface central portion 642. Resin second side surface upper portion 641 is inclined so that its upper end is located inside semiconductor module 1.

[0053] 3 to 6, resin second side surface central portion 642 is a portion whose upper end is connected to resin second side surface upper portion 641 and whose lower end is connected to resin second side surface lower portion 643. Resin second side surface central portion 642 is perpendicular to resin upper surface 61 and resin lower surface 62, and is orthogonal to resin first side surface central portion 632. In this embodiment, in the thickness direction of semiconductor module 1, resin second side surface central portion 642 and resin first side surface central portion 632 have approximately the same height.

[0054] 3 to 6, resin second side surface lower portion 643 is a portion whose upper end is connected to resin second side surface central portion 642 and whose lower end is connected to resin lower surface 62. Resin second side surface lower portion 643 is inclined so that its lower end is located inside semiconductor module 1.

[0055] The bonding wires 71, together with the first terminals 3, second terminals 4, and support terminals 5 described above, form conductive paths for the semiconductor element 11 and insulating element 12 to perform predetermined functions inside the semiconductor module 1. The bonding wires 71 include first bonding wires 711, second bonding wires 712, third bonding wires 713, and fourth bonding wires 714.

[0056] 2, the multiple first bonding wires 711 form conductive paths between the control element 111 and the multiple first terminals 3 and the pair of first support terminals 51. The multiple first bonding wires 711 electrically connect the control element 111 to at least one of the first terminals 3 and the first support terminals 51. The multiple first bonding wires 711 are bonded to the pad 111a of the control element 111 and the pad portion 312 of the first intermediate terminal 31, the pad portion 322 of the first side terminal 32, or the pad portion 512 of the first support terminal 51, respectively.

[0057] 2, the plurality of second bonding wires 712 form a conductive path between the insulating element 12 and the control element 111. The insulating element 12 and the control element 111 are electrically connected to each other by the plurality of second bonding wires 712. The plurality of second bonding wires 712 are bonded to the pads 12a of the insulating element 12 and the pads 111a of the control element 111, respectively. In this embodiment, the plurality of second bonding wires 712 are arranged along the second direction Y.

[0058] 2, the plurality of third bonding wires 713 form a conductive path between the insulating element 12 and the driving element 112. The insulating element 12 and the driving element 112 are electrically connected to each other by the plurality of third bonding wires 713. The plurality of third bonding wires 713 are bonded to the pads 12a of the insulating element 12 and the pads 112a of the driving element 112, respectively. In this embodiment, the plurality of third bonding wires 713 are arranged along the second direction Y.

[0059] 2, the multiple fourth bonding wires 714 form conductive paths between the driving element 112 and the multiple second terminals 4 and the pair of second support terminals 52. The multiple fourth bonding wires 714 electrically connect the driving element 112 to at least one of the second terminals 4 and the second support terminals 52. The multiple fourth bonding wires 714 are bonded to the pads 112a of the driving element 112 and the pad portion 412 of the second intermediate terminal 41, the pad portion 422 of the second side terminal 42, or the pad portion 522 of the second support terminal 52, respectively. [Motor drive device operation] Next, a detailed description will be given of an example of a configuration in which the semiconductor module 1 is applied to a motor drive device 101 mounted on a hybrid automobile (vehicle 100 shown in FIG. 10). FIG. 11 is a block diagram showing an example of a configuration of a motor drive device 101 using a semiconductor device according to the present disclosure.

[0060] The motor driving device 101 includes a high-side switch SWH, a low-side switch SWL, a semiconductor module 1 (switch control device) that is a control means for the high-side switch SWH, an engine control unit 102 (hereinafter referred to as ECU [Engine Control Unit] 102), DC voltage sources E1 and E2, an npn-type bipolar transistor Q1, a pnp-type bipolar transistor Q2, capacitors C1 to C3, resistors R1 to R8, and a diode D1.

[0061] As described above, the semiconductor module 1 is formed by sealing the control element 111 (first semiconductor chip), the drive element 112 (second semiconductor chip), and the insulating element 12 with the sealing resin 6.

[0062] The semiconductor module 1 may have, for example, an input-output insulation breakdown voltage of 600 V or more. The semiconductor module 1 may also have a built-in UVLO. The semiconductor module 1 may also have a built-in watchdog timer function. The semiconductor module 1 may also have a built-in overcurrent protection function (automatic recovery type). The semiconductor module 1 may also have a built-in slow-off function during overcurrent protection operation. The semiconductor module 1 may also have a built-in external error detection function (ERRIN). The semiconductor module 1 may also have a built-in abnormal state output function (FLT, OCPOUT). The semiconductor module 1 may also have a built-in active Miller clamp function. The semiconductor module 1 may also have a built-in short-circuit clamp function.

[0063] The control element 111 may be a controller chip that is driven by a first power supply voltage VCC1 (e.g., 5 V or 3.3 V relative to GND1) supplied from a DC voltage source E1 and that integrates a controller that generates switch control signals S1 and S2 based on an input signal IN. The main functions of the control element 111 include generating or outputting the switch control signals S1 and S2, monitoring a transformer transmission abnormality (monitoring the input / output logic of the input signal IN), outputting an error status, UVLO, and processing an external error input signal. The withstand voltage of the control element 111 may be designed to be an appropriate withstand voltage (e.g., 7 V) taking into account the first power supply voltage VCC1 (relative to GND1).

[0064] The driving element 112 may be a driver chip integrating a driver that is driven by receiving a second power supply voltage VCC2 (10 to 30 V relative to GND2) from a DC voltage source E2 and controls the driving of a high-side switch SWH, one end of which is applied with a high voltage of 600 V or more, based on switch control signals S1 and S2 input from the control element 111 via the isolation element 12. The main functions of the driving element 112 include generating or outputting an output signal OUT, overcurrent / overvoltage protection, and UVLO. The withstand voltage of the driving element 112 may be designed to be an appropriate withstand voltage (e.g., 40 V) taking into account the second power supply voltage VCC2 (relative to GND2).

[0065] The isolation element 12 may be a transformer chip that integrates transformers that transmit and receive switch control signals S1 and S2, watchdog signal S3, and driver abnormality signal S4 while providing DC isolation between the control element 111 and the drive element 112.

[0066] As described above, the semiconductor module 1 has an independent insulating element 12 equipped with only a transformer, in addition to the control element 111 in which a controller is integrated and the drive element 112 in which a driver is integrated.

[0067] With this configuration, both the control element 111 and the drive element 112 can be fabricated using a general low-voltage process (withstand voltage of several volts or more, and several tens of volts or less), eliminating the need to use a dedicated high-voltage process (withstand voltage of several kV), thereby reducing manufacturing costs.

[0068] Furthermore, the control element 111 and the drive element 112 can both be produced using existing processes with a proven track record, and there is no need to conduct new reliability tests, which can contribute to shortening development time and reducing development costs.

[0069] Furthermore, even when a DC isolation element other than a transformer (for example, a photocoupler, a capacitor, etc.) is used, this can be easily accommodated by simply replacing the isolation element 12, eliminating the need to redevelop the controller chip and driver chip, which contributes to shortening the development period and reducing development costs.

[0070] The ECU 102 is a means for comprehensively performing electrical control of engine operation and motor operation, and is a microcontroller that exchanges various signals (IN, RST, FLT, OCPOUT) with the semiconductor module 1.

[0071] The high-side switch SWH and the low-side switch SWL are connected between an application terminal of a first motor drive voltage VD1 and one end of the motor coil, and between an application terminal of a second motor drive voltage VD2 and one end of the motor coil, respectively, and are means for controlling the supply of motor drive current according to the on / off control of each. While the motor drive device 101 uses insulated gate bipolar transistors (IGBTs) as the high-side switch SWH and the low-side switch SWL, this is not limiting and metal oxide semiconductor (MOS) field-effect transistors using silicon carbide (SiC) semiconductors or MOS field-effect transistors using silicon semiconductors may also be used. In particular, MOS field-effect transistors using SiC semiconductors consume less power and have a higher heat resistance than MOS field-effect transistors using silicon semiconductors, making them suitable for use in hybrid vehicles.

[0072] Next, the internal configuration of the semiconductor module 1 will be described in detail.

[0073] The control element 111 may include a first transmitting unit 103, a second transmitting unit 104, a first receiving unit 105, a second receiving unit 106, a logic unit 107, a first undervoltage lockout unit 108 (hereinafter referred to as the first UVLO [Under Voltage Lock Out] unit 108), an external error detection unit (external error detection comparator) 109, and N-channel MOS field effect transistors Na and Nb.

[0074] The driving element 112 may include a third receiving unit 121, a fourth receiving unit 122, a third transmitting unit 123, a fourth transmitting unit 124, a logic unit 125, a driver unit 126, a second undervoltage lockout unit 127 (hereinafter referred to as the second UVLO unit 127), an overcurrent detection unit (overcurrent detection comparator) 128, an OCP (Over Current Protection) timer 129, P-channel MOS field effect transistors P1 and P2, N-channel MOS field effect transistors N1 to N3, and an SR flip-flop FF.

[0075] The isolation element 12 may include a first transformer 131, a second transformer 132, a third transformer 133, and a fourth transformer .

[0076] The first transmitting unit 103 is a means for transmitting the switch control signal S1 input from the logic unit 107 to the third receiving unit 121 via the first transformer 131. The second transmitting unit 104 is a means for transmitting the switch control signal S2 input from the logic unit 107 to the fourth receiving unit 122 via the second transformer 132. The first receiving unit 105 is a means for receiving the watchdog signal S3 input from the third transmitting unit 123 via the third transformer 133 and transmitting it to the logic unit 107. The fourth receiving unit 122 is a means for receiving the driver abnormality signal S4 input from the fourth transmitting unit 124 via the fourth transformer 134 and transmitting it to the logic unit 107.

[0077] The logic unit 107 is a means for exchanging various signals (IN, RST, FLT, OCPOUT) with the ECU 102, and also for exchanging various signals (S1 to S4) with the driving element 112 using the first transmitting unit 103, the second transmitting unit 104, the first receiving unit 105, and the second receiving unit 106.

[0078] Note that when the input signal IN is at a high level, the logic unit 107 generates the switch control signals S1 and S2 so as to set the output signal OUT to a high level, and conversely, when the input signal IN is at a low level, the logic unit 107 generates the switch control signals S1 and S2 so as to set the output signal OUT to a low level. More specifically, the logic unit 107 detects a positive edge (a rising edge from a low level to a high level) of the input signal IN to generate a pulse in the switch control signal S1, and detects a negative edge (a falling edge from a high level to a low level) of the input signal IN to generate a pulse in the switch control signal S2.

[0079] Furthermore, when the reset signal RST is at a low level, the logic unit 107 generates the switch control signals S1 and S2 to disable the generation of the output signal OUT, i.e., to fix the output signal OUT at a low level, and conversely, when the reset signal RST is at a high level, the logic unit 107 generates the switch control signals S1 and S2 to enable the generation of the output signal OUT, i.e., to set the output signal OUT to a logic level corresponding to the input signal IN. Note that if the reset signal RST is maintained at a low level for a predetermined time (for example, 500 [ns]), the logic unit 107 generates the switch control signals S1 and S2 to resume the protection operation by the overcurrent detection unit 128.

[0080] Furthermore, when the semiconductor module 1 is normal, the logic unit 107 turns off the transistor Na and sets the first status signal FLT to an open state (pull-up state by the resistor R1). When an abnormality occurs in the semiconductor module 1 (when a low-voltage abnormality on the control element 111 side, a transformer transmission abnormality of the switch control signals S1 and S2, or an ERRIN signal abnormality is detected), the logic unit 107 turns on the transistor Na and sets the first status signal FLT to a low level. With this configuration, the ECU 102 can grasp the status of the semiconductor module 1 by monitoring the first status signal FLT. Note that a low-voltage abnormality on the control element 111 side can be determined based on the detection result of the first UVLO unit 108, and a transformer transmission abnormality of the switch control signals S1 and S2 can be determined based on the comparison result between the input signal IN (switch control signals S1 and S2) and the watchdog signal S3. Furthermore, an abnormality in the ERRIN signal can be determined based on the output result of the external error detection unit 109.

[0081] Furthermore, when the semiconductor module 1 is normal, the logic unit 107 turns off the transistor Nb and sets the second state signal OCPOUT to an open state (a pulled-up state by the resistor R2), and when an abnormality occurs in the semiconductor module 1 (when a low voltage abnormality on the drive element 112 side or an overcurrent of the motor drive current flowing through the high-side switch SWH is detected), the logic unit 107 turns on the transistor Nb and sets the second state signal OCPOUT to a low level. With this configuration, the ECU 102 can grasp the state of the semiconductor module 1 by monitoring the second state signal OCPOUT. Note that a low voltage abnormality on the drive element 112 side or an overcurrent of the motor drive current flowing through the high-side switch SWH can be determined based on the driver abnormality signal S4.

[0082] The first UVLO unit 108 is means for monitoring whether the first power supply voltage VCC1 is in a low voltage state and transmitting the monitoring result to the logic unit 107.

[0083] The external error detection unit 109 is a means for comparing the voltage input to the ERRIN terminal from the connection node between the resistors R3 and R4 (a divided voltage obtained by resistively dividing the analog voltage to be monitored) with a predetermined threshold voltage, and transmitting the comparison result to the logic unit 107.

[0084] The third receiving unit 121 is a means for receiving a switch control signal S1 input from the first transmitting unit 103 via the first transformer 131 and transmitting it to the set input terminal (S) of the SR flip-flop FF. The fourth receiving unit 122 is a means for receiving a switch control signal S2 input from the second transmitting unit 104 via the second transformer 132 and transmitting it to the reset input terminal (R) of the SR flip-flop FF. The third transmitting unit 123 is a means for transmitting a watchdog signal S3 input from the logic unit 125 to the first receiving unit 105 via the third transformer 133. The fourth transmitting unit 124 is a means for transmitting a driver abnormality signal S4 input from the logic unit 125 to the second receiving unit 106 via the fourth transformer 134.

[0085] The SR flip-flop FF sets its output signal to a high level when triggered by a pulse edge of the switch control signal S1 input to its set input terminal (S), and resets its output signal to a low level when triggered by a pulse edge of the switch control signal S2 input to its reset input terminal (R). That is, the output signal is the same as the input signal IN input from the ECU 102 to the logic unit 107. The output signal is sent from the output terminal (Q) of the SR flip-flop FF to the logic unit 125.

[0086] The logic unit 125 generates a drive signal for the driver unit 126 based on the output signal of the SR flip-flop FF (the same signal as the input signal IN).

[0087] Furthermore, when the logic unit 125 determines that a low voltage abnormality or an overcurrent has occurred based on the detection results of the second UVLO unit 127 and the overcurrent detection unit 128, it transmits this information to the driver unit 126 using an abnormality detection signal, and also transmits this information to the logic unit 107 using a driver abnormality signal S4. With this configuration, even if an abnormality occurs in the drive element 112, the driver unit 126 can quickly perform a protection operation, and the logic unit 107 can perform an abnormality notification operation to the ECU 102 (transition of the second status signal OCPOUT to a low level). Note that the logic unit 125 has a function of automatically recovering from the overcurrent protection operation when a predetermined time has elapsed after the overcurrent protection operation.

[0088] Furthermore, the logic unit 125 outputs the output signal of the SR flip-flop FF as is as the watchdog signal S3 to the third transmission unit 123. In this manner, if the configuration is such that the watchdog signal S3 is returned from the driving element 112 to the control element 111, the logic unit 107 can determine whether or not there is a transformer transmission abnormality by comparing the input signal IN input to the control element 111 with the watchdog signal S3 returned in response from the driving element 112.

[0089] The driver unit 126 controls the on / off of the transistors P1 and N1 based on a drive signal input from the logic unit 125, and outputs an output signal OUT from the connection node between the transistors P1 and N1. The output signal OUT is input to the high-side switch SWH via a drive circuit consisting of transistors Q1 and Q2. The drive circuit adjusts the rise / fall time (slew rate) of the output signal OUT so that the output signal OUT has the driving capability of the high-side switch SWH. When the output signal OUT is at a high level, the high-side switch SWH is turned on, and conversely, when the output signal OUT is at a low level, the high-side switch SWH is turned off.

[0090] The driver unit 126 has a function (active mirror clamp function) of turning on the transistor N2 so as to absorb charge (mirror current) from the gate of the high-side switch SWH via the CLAMP terminal when the voltage level (GND2 reference) of the output signal OUT becomes low. With this configuration, when turning off the high-side switch SWH, the gate potential of the high-side switch SWH can be quickly lowered to low via the transistor N2, regardless of the slew rate set by the above-mentioned drive circuit.

[0091] Furthermore, the driver unit 126 has a function (short-circuit clamp function) of turning on the transistor P2 so as to clamp the gate of the high-side switch SWH to the power supply voltage VCC2 via the CLAMP terminal when the voltage level (GND2 reference) of the output signal OUT becomes high. With this configuration, when the high-side switch SWH is turned on, the gate potential of the high-side switch SWH does not rise to a potential higher than the power supply voltage VCC2.

[0092] Furthermore, when the driver unit 126 determines that a protective operation is necessary based on the abnormality detection signal input from the logic unit 125, it turns off transistors P1 and P2 and transistors N1 and N2, while turning on transistor N3 (a slow-off function). This switch control allows charge to be drawn from the gate of the high-side switch SWH via resistor R5 more slowly than during normal operation during protective operation. This configuration prevents momentary interruptions in the motor current during protective operation, thereby suppressing surges caused by the back electromotive force of the motor coil. The fall time during protective operation can be adjusted arbitrarily by appropriately selecting the resistance value of resistor R5.

[0093] The second UVLO unit 127 is means for monitoring whether the second power supply voltage VCC2 is in a low voltage state and transmitting the monitoring result to the logic unit 125.

[0094] The overcurrent detection unit 128 compares the voltage input to the OCP / DESATIN terminal from the connection node between resistors R7 and R8 (a divided voltage obtained by resistively dividing the anode voltage of diode D1) with a predetermined threshold voltage and transmits the comparison result to the logic unit 125. Note that the larger the motor drive current flowing through the high-side switch SWH, the larger the collector-emitter voltage of the insulated gate bipolar transistor used as the high-side switch SWH. Therefore, the larger the motor drive current flowing through the high-side switch SWH, the higher the anode voltage of diode D1, and ultimately the higher the voltage input to the OCP / DESATIN terminal. Therefore, when the voltage input to OCP / DESATIN (based on GND2) reaches a predetermined threshold (e.g., 0.5 V), the overcurrent detection unit 128 determines that the motor drive current flowing through the high-side switch SWH is in an overcurrent state.

[0095] In this configuration example, a configuration has been described that employs a method (voltage detection method) for detecting the motor drive current by detecting the collector-emitter voltage of the insulated gate bipolar transistor used as the high-side switch SWH. However, the method for detecting the motor drive current is not limited to this. For example, a method (current detection method) may be employed in which the motor drive current flowing through the high-side switch SWH (or a mirror current that behaves in the same way) is passed through a sense resistor to generate a voltage signal, which is then input to the OCP / DESATIN terminal.

[0096] The OCP timer 129 is a means for counting the time that has elapsed since the overcurrent protection operation.

[0097] The first transformer 131 is a DC isolation element for transmitting a switch control signal S1 from the control element 111 to the drive element 112. The second transformer 132 is a DC isolation element for transmitting a switch control signal S2 from the control element 111 to the drive element 112. The third transformer 133 is a DC isolation element for transmitting a watchdog signal S3 from the drive element 112 to the control element 111. The fourth transformer 134 is a DC isolation element for transmitting a driver abnormality signal S4 from the drive element 112 to the control element 111.

[0098] In this way, if the control element 111 and the drive element 112 are configured to exchange not only the switch control signals S1 and S2 but also the watchdog signal S3 and the driver abnormality signal S4, it is possible to appropriately realize not only the on / off control of the high-side switch SWH but also various protection functions.

[0099] Fig. 12 is a detailed diagram of the transmission and reception circuit portion via transformers 131 to 134. As shown in Fig. 12, first transmission unit 103, second transmission unit 104, first reception unit 105, and second reception unit 106 provided on the control element 111 side are all driven by a power supply voltage between VCC1 and GND1, and third reception unit 121, fourth reception unit 122, third transmission unit 123, and fourth transmission unit 124 provided on the drive element 112 side are all driven by a power supply voltage between VCC2 and GND2.

[0100] With this configuration, as mentioned above, both the control element 111 and the drive element 112 can be fabricated using a general low-voltage process (withstand voltage of several volts or more, and several tens of volts or less), eliminating the need to use a dedicated high-voltage process (withstand voltage of several kV), thereby reducing manufacturing costs.

[0101] In addition, in Figure 12, the first receiving unit 105, the second receiving unit 106, the third receiving unit 121, and the fourth receiving unit 122 are depicted as being configured using comparators with hysteresis characteristics, but the presence or absence of hysteresis characteristics is optional.

[0102] Next, the details of the various functions of the semiconductor module 1 will be generally described. [UVLO1 (controller-side low voltage malfunction prevention function)] The semiconductor module 1 is configured such that the controller-side power supply voltage (voltage between VCC1 and GND1) is equal to or lower than a predetermined lower threshold voltage V UVLO1L When the voltage drops below a predetermined upper threshold voltage V, the high-side switch SWH is turned off and the FLT terminal is set to low level. UVLO1H When this occurs, normal operation begins and the FLT terminal is set to open (high level). [UVLO2 (Driver side undervoltage malfunction prevention function)] The semiconductor module 1 is configured such that the driver-side power supply voltage (voltage between VCC2 and GND2) is equal to or lower than a predetermined lower threshold voltage V UVLO2L When the driver-side power supply voltage (voltage between VCC2 and GND2) is equal to or lower than a predetermined upper threshold voltage V UVLO2H When this occurs, normal operation begins and the OCPOUT pin is set to open (high level). [Analog Error Input] The semiconductor module 1 is configured such that the input voltage to the ERRIN terminal is equal to or exceeds a predetermined threshold voltage V ERRDET When the voltage exceeds this threshold, the high-side switch SWH is turned off and the FLT terminal is set to low level. This configuration makes it possible to monitor abnormalities occurring in the peripheral circuits of the semiconductor module 1 and take appropriate protective action, so it can be used, for example, to protect the motor power supply from overvoltage. ERRDET has a predetermined hysteresis (V ERRHYS ) is recommended. [Overcurrent protection] The semiconductor module 1 is configured such that the input voltage to the OCP / DESATIN terminal is equal to or exceeds a predetermined threshold voltage V OCDET When the voltage rises above this level (relative to GND2), the high-side switch SWH is turned off and the OCPOUT pin is set to low level. [Overcurrent protection and automatic recovery] After the overcurrent protection operation, the semiconductor module 1 OCPRLS ) has elapsed, the semiconductor module 1 automatically recovers and sets the OCPOUT terminal to open (high level). The recovery time may be fixedly set within the semiconductor module 1, or may be adjustable from outside the device. [Watchdog Timer] The semiconductor module 1 compares the input signal IN input from the ECU 102 to the control element 111 with the watchdog signal S3 fed back from the drive element 112 to the control element 111, and if the logic of the two signals does not match, it turns off the high-side switch SWH and sets the FLT terminal to a low level. [Slow-off during protection operation] During overcurrent protection operation, the semiconductor module 1 sets the PROOUT terminal to low level and the OUT terminal to open. This control allows the high-side switch SWH to turn off slowly. The slew rate when turned off can be adjusted as desired by appropriately selecting the resistance value of the external resistor R5. [Active Miller Clamp] The semiconductor module 1 is configured such that the gate potential of the high-side switch SWH is a predetermined threshold voltage V AMC When the voltage drops below this level, the CLAMP pin is set to L. This control ensures that the high-side switch SWH is turned off. [Short circuit clamp] Semiconductor module 1 is connected to the CLAMP terminal when the applied voltage is VCC2-V. SCC When this occurs, the CLAMP terminal is set to high level. This control prevents the gate potential of the high-side switch SWH from rising above the second power supply voltage VCC2.

[0103] FIG. 13 is a schematic diagram showing an example of the terminal arrangement of the semiconductor module 1 and the chip arrangement within the sealing resin.

[0104] As shown in Figure 13, in the semiconductor module 1, the package has multiple pins arranged on each of two opposing sides, and as described above, the control element 111, drive element 112, and isolation element 12 are arranged perpendicular to the arrangement direction of the pins (horizontal direction on the paper).

[0105] By adopting such a chip arrangement, pins 11 to 20 connected to control element 111 and pins 1 to 10 connected to drive element 112 can be distributed and arranged on two opposing sides, thereby preventing short-circuiting between pins 11 to 20 and pins 1 to 10 while maintaining the pin spacing at a minimum. Pins 11 to 20 may correspond to first terminal 3 in FIG. 1, and pins 1 to 10 may correspond to second terminal 4 in FIG. 1. Note that, although the chip arrangement in the case of an SOP package format has been taken as an example here, the chip arrangement can be changed appropriately when a package format other than SOP is adopted.

[0106] 13, in the semiconductor module 1 of this configuration example, the control element 111 and the insulating element 12 are mounted on the first die pad 21 as described above, and the drive element 112 is mounted on the second die pad 22 as described above. With this configuration, the power supply systems can be separated from each other, with the first die pad 21 used as a low-voltage side island (GND1 fixed) and the second die pad 22 used as a high-voltage side island (VEE2 fixed). Note that both the first die pad 21 and the second die pad 22 are made of a non-magnetic material (for example, copper), but a magnetic material (for example, iron) may also be used.

[0107] Figure 14 is an example of an external terminal description table. Pin 1 (NC) is a non-connection terminal. Pin 2 (VEE2) is a negative power supply terminal (for example, minimum: -15V). Pin 3 (GND2) is a GND terminal, connected to the emitter of the insulated gate bipolar transistor Tr1 outside the semiconductor module 1. Pin 4 (OCP / DESATIN) is an overcurrent detection terminal. Pin 5 (OUT) is an output terminal. Pin 6 (VCC2) is a positive power supply terminal (for example, maximum: 30V). Pin 7 (CLAMP) is a clamp terminal. Pin 8 (PROOUT) is a slow-off output terminal. Pin 9 (VEE2) is a negative power supply terminal. Pin 10 (NC) is a non-connection terminal. Pin 11 (GND1) is a GND terminal. Pin 12 (IN) is a control input terminal. Pin 13 (RST) is a reset input terminal. Pin 14 (FLT) is the output terminal for the first status signal (the signal for detecting an abnormal state on the controller chip side). Pin 15 (OCPOUT) is the output terminal for the second status signal (the signal for detecting an abnormal state on the driver chip side). Pin 16 (ERRIN) is the error detection terminal. Pin 17 (VCC1) is the power supply terminal (for example, 5V or 3.3V). Pin 18 (NC) and pin 19 (NC) are both non-connection terminals. Pin 20 (GND1) is the GND terminal.

[0108] 15 is an example of an electrical characteristics table for the semiconductor module 1. Unless otherwise specified, the values ​​in this table are those assuming Ta=25°C, VCC1=5V, VCC2=20V, and VEE2=-8V.

[0109] Next, a more detailed description will be given of the configuration and operation of the signal transmission device 200 included in the motor drive device 101. Note that the overall configuration and operation of the motor drive device 101 in which the signal transmission device 200 is mounted have already been explained with reference to the above-mentioned Figures 11 to 15, so below, redundant explanations will be omitted and the explanation will focus on the configuration and operation of the signal transmission device 200. <First embodiment of signal transmission device 200> FIG. 16 is a circuit block diagram showing a first embodiment of a signal transmission device 200. As shown in FIG.

[0110] The signal transmission device 200 of this embodiment includes a logic unit 107, a first transmitter 103, a second transmitter 104, a first transformer 131, a second transformer 132, a third receiver 121, a fourth receiver 122, and an SR flip-flop FF as circuit blocks for transmitting switch control signals S1 and S2 from the primary circuit to the secondary circuit while isolating the ground voltage GND1 of the primary circuit from the ground voltage GND2 of the secondary circuit. All of these circuit blocks are previously described in FIGS. 11 and 12 , but in the signal transmission device 200, the logic unit 107, the third receiver 121, and the fourth receiver 122 are specially configured to prevent malfunctions due to noise and the like. The following description focuses on its distinctive components.

[0111] Logic unit 107 includes inverters 107-1 and 107-2, a first pulse generating unit 107-3, and a second pulse generating unit 107-4.

[0112] The input terminal of inverter 107-1 is connected to the input terminal of input signal IN. The output terminal of inverter 107-1 is connected to the input terminal of inverter 107-2 and also to the input terminal of second pulse generating unit 107-4. The output terminal of inverter 107-2 is connected to the input terminal of first pulse generating unit 107-3.

[0113] The first pulse generating unit 107-3 generates N pulses (N≧2) in the first transformer driving signal S1a in response to positive edges of the input signal IN input via the inverters 107-2 and 107-3. The first transformer driving signal S1a is output to the primary winding of the first transformer 131 via a buffer 103-1 that forms the first transmitting unit 103.

[0114] The second pulse generating unit 107-4 generates N pulses (N≧2) in the second transformer driving signal S2a in response to a positive edge of the inverted input signal INB input from the inverter 107-2 (i.e., a negative edge of the input signal IN). The second transformer driving signal S2a is output to the primary winding of the second transformer 132 via a buffer 104-1 that forms the second transmitting unit 104.

[0115] Thus, in the signal transmission device 200 of the first embodiment, the logic unit 107 functions as a transformer drive signal generation unit that successively generates N pulses in the first transformer drive signal S1a in response to a positive edge at which the input signal IN transitions from low level to high level, and that successively generates N pulses in the second transformer drive signal S2a in response to a negative edge at which the input IN signal transitions from high level to low level.

[0116] The first transformer 131 generates a first induced signal S1b in the secondary winding in response to a first transformer drive signal S1a input to the primary winding.

[0117] The second transformer 132 generates a second induced signal S2b in the secondary winding in response to a second transformer drive signal S2a input to the primary winding.

[0118] The third receiving unit 121 has a first comparator 121-1 that compares the first induced signal S1b with a predetermined threshold voltage to generate a first comparison signal S1c, and a first pulse detecting unit 121-2 that detects that N pulses have been generated consecutively in the first comparison signal S1c and generates a pulse in the first detection signal 1d.

[0119] The fourth receiving unit 122 has a second comparator 122-1 that compares the second induced signal S2b with a predetermined threshold voltage to generate a second comparison signal S2c, and a second pulse detecting unit 122-2 that detects that N pulses have been generated consecutively in the second comparison signal 2c and generates a pulse in the second detection signal 2d.

[0120] The SR flip-flop FF transitions the output signal OUT from a low level to a high level in response to a pulse generated in the first detection signal S1d input to the set input terminal (S), and transitions the output signal OUT from a high level to a low level in response to a pulse generated in the second detection signal S2d input to the reset input terminal (R).

[0121] That is, the switch control signal S1 described above takes various signal forms, such as a first transformer drive signal S1a, a first induced signal S1b, a first comparison signal S1c, and a first detection signal S1d, and is transmitted from the logic unit 107 to the SR flip-flop FF. Similarly, the switch control signal S2 described above takes various signal forms, such as a second transformer drive signal S2a, a second induced signal S2b, a second comparison signal S2c, and a second detection signal S2d, and is transmitted from the logic unit 107 to the SR flip-flop FF. [Structure of semiconductor device] Next, a more detailed description will be given of the structure of the insulating element 12 mounted on the semiconductor module 1. In the following, examples of the structure of the insulating element 12 will be described using semiconductor devices A1 to A4, semiconductor devices B1 to B4, semiconductor devices C1 to C4, semiconductor devices D1 to D2, semiconductor devices E1 to E2, and semiconductor devices F1 to F5, but the structure of the insulating element 12 is not limited to these. <Structure of semiconductor devices A1 to A4> (First embodiment) Fig. 17 is a schematic plan view of a semiconductor device A1 according to an embodiment of the present disclosure. Fig. 18 is a plan view showing a layer in which the low-potential coil 20 is formed in the semiconductor device A1 of Fig. 17. Fig. 19 is a plan view showing a layer in which the high-potential coil 23 is formed in the semiconductor device A1 of Fig. 17. Fig. 20 is a schematic cross-sectional view of the semiconductor device A1 of Fig. 17. Fig. 21 is an enlarged view of a main part of the semiconductor device A1 of Fig. 17. Fig. 22 is an enlarged view of region A in Fig. 19. Fig. 23 is an enlarged view of region B in Fig. 19. Fig. 24 is an enlarged view of region C in Fig. 19.

[0122] 17 to 20, semiconductor device A1 includes a rectangular parallelepiped semiconductor chip 40. Semiconductor chip 40 includes at least one of silicon, a wide bandgap semiconductor, and a compound semiconductor.

[0123] The wide bandgap semiconductor is a semiconductor with a bandgap greater than that of silicon (approximately 1.12 eV). The bandgap of the wide bandgap semiconductor is preferably 2.0 eV or greater. The wide bandgap semiconductor may be silicon carbide (SiC). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0124] In this embodiment, the semiconductor chip 40 includes a silicon semiconductor substrate. The semiconductor chip 40 may be an epitaxial substrate having a layered structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type. The semiconductor chip 40 may also be fixed to ground potential.

[0125] The semiconductor chip 40 has a first main surface 401 on one side, a second main surface 402 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 401 and the second main surface 402. The first main surface 401 and the second main surface 402 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0126] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long sides of the semiconductor chip 40. The first chip sidewall 44A and the second chip sidewall 44B extend along the first direction X and face the second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short sides of the semiconductor chip 40. The third chip sidewall 44C and the fourth chip sidewall 44D extend in the second direction Y and face the first direction X. The chip sidewalls 44A to 44D are made of ground surfaces.

[0127] The semiconductor device A1 includes a first insulating section 50, a second insulating section 7, and a protective layer 8, which are formed in this order on a first main surface 401 of a semiconductor chip 40.

[0128] The first insulating portion 50 has an insulating main surface 54 and insulating side walls 53A to 53D. The insulating main surface 54 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first main surface 401 in a plan view. The insulating main surface 54 extends parallel to the first main surface 401.

[0129] The insulating sidewalls 53A-53D include a first insulating sidewall 53A, a second insulating sidewall 53B, a third insulating sidewall 53C, and a fourth insulating sidewall 53D. The insulating sidewalls 53A-53D extend from the periphery of the insulating main surface 54 toward the semiconductor chip 40 and are continuous with the chip sidewalls 44A-44D. Specifically, the insulating sidewalls 53A-53D are formed flush with the chip sidewalls 44A-44D. The insulating sidewalls 53A-53D form ground surfaces that are flush with the chip sidewalls 44A-44D.

[0130] The second insulating portion 7 is formed on the insulating principal surface 54, and has an insulating principal surface 701 and insulating side walls 702A to 702D. The insulating principal surface 701 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first principal surface 401 in a plan view. The insulating principal surface 701 extends parallel to the first principal surface 401.

[0131] The insulating side walls 702A to 702D include a first insulating side wall 702A, a second insulating side wall 702B, a third insulating side wall 702C, and a fourth insulating side wall 702D. The insulating side walls 702A to 702D extend from the periphery of the insulating principal surface 701 toward the semiconductor chip 40. Specifically, the insulating side walls 702A to 702D are formed inside the insulating side walls 53A to 53D. This forms a step between the insulating side walls 702A to 702D and the insulating side walls 53A to 53D.

[0132] The protective layer 8 is formed on the insulating principal surface 701, and has a protective principal surface 82 and protective side walls 83A to 83D. The protective principal surface 82 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first principal surface 401 in a plan view. The protective principal surface 82 extends parallel to the first principal surface 401.

[0133] The protective sidewalls 83A to 83D include a first protective sidewall 83A, a second protective sidewall 83B, a third protective sidewall 83C, and a fourth protective sidewall 83D. The protective sidewalls 83A to 83D extend from the periphery of the protective main surface 82 toward the semiconductor chip 40. Specifically, the protective sidewalls 83A to 83D are formed inside the insulating sidewalls 702A to 702D. As a result, steps are formed between the protective sidewalls 83A to 83D and the insulating sidewalls 702A to 702D.

[0134] The first insulating section 50 has a multilayer insulating laminate structure including a bottom insulating layer 55, a top insulating layer 56, and multiple (10 in this embodiment) interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 401. The top insulating layer 56 is an insulating layer that forms the insulating main surface 54. The multiple interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the top insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the top insulating layer 56 has a single-layer structure containing silicon nitride. The thickness of the bottom insulating layer 55 may be 0.5 μm or more and 3 μm or less (for example, about 1 μm), and the thickness of the top insulating layer 56 may be 0.2 μm or more and 4 μm or less (for example, about 1 μm).

[0135] Each of the multiple interlayer insulating layers 57 has a stacked structure including a first insulating layer 58 on the side of the bottom insulating layer 55 and a second insulating layer 59 on the side of the top insulating layer 56. The first insulating layer 58 is made of an inorganic insulating layer and may contain, for example, silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, approximately 0.3 μm).

[0136] The second insulating layer 59 is formed on the first insulating layer 58. It contains a different insulating material from the first insulating layer 58. The second insulating layer 59 is made of an inorganic insulating layer different from the first insulating layer 58, and may contain, for example, silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, approximately 2 μm). The thickness of the second insulating layer 59 is preferably greater than the thickness of the first insulating layer 58.

[0137] Furthermore, the first insulating layer 58 may be a compressive stress film, and the second insulating layer 59 may be a tensile stress film. That is, the interlayer insulating layer 57 may have a structure in which compressive stress films and tensile stress films are repeatedly stacked. This allows the first insulating part 50 to be formed while canceling stress at the stacking interface of the interlayer insulating layer 57. As a result, during the manufacturing process of the semiconductor device A1, it is possible to prevent significant warpage deformation from occurring in the semiconductor wafer that serves as the base of the semiconductor chip 40. The compressive stress film may be, for example, a silicon oxide film, and the tensile stress film may be, for example, a silicon nitride film.

[0138] The total thickness TA1 of the first insulating section 50 may be 5 μm or more and 50 μm or less. The total thickness TA1 of the first insulating section 50 and the number of layers of the interlayer insulating layers 57 are arbitrary and are adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be achieved. Furthermore, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layers 57 are arbitrary and are not limited to a specific insulating material.

[0139] The second insulating portion 7 is made of an insulating material having a different dielectric constant from the first insulating layer 58 and the second insulating layer 59, and has a layered structure including, for example, an organic insulating layer 84. In this embodiment, the second insulating portion 7 is made of a single layer of organic insulating layer 84, but may have a laminated structure of multiple organic insulating layers. Examples of the organic insulating layer 84 include a polyimide film, a phenolic resin film, and an epoxy resin film. The total thickness TA2 of the second insulating portion 7 may be 2 μm or more and 100 μm or less. The total thickness TA2 of the second insulating portion 7 is arbitrary and is adjusted according to the desired dielectric strength (dielectric breakdown resistance).

[0140] The semiconductor device A1 includes a first functional device 45. The first functional device 45 includes one or more (in this embodiment, multiple) transformers 15 (voltage transformers). In other words, the semiconductor device A1 is a multi-channel device including multiple transformers 15. The multiple transformers 15 are formed inward of the laminated structure of the first insulating section 50 and the second insulating section 7, spaced apart from the insulating side walls 53A to 53D. The multiple transformers 15 are formed at intervals in the first direction X.

[0141] Specifically, the multiple transformers 15 include a first transformer 15A, a second transformer 15B, a third transformer 15C, and a fourth transformer 15D, which are formed in this order from the insulating side wall 53C side toward the insulating side wall 53D side in a plan view. The first transformer 15A, the second transformer 15B, the third transformer 15C, and the fourth transformer 15D may correspond to the first transformer 131, the second transformer 132, the third transformer 133, and the fourth transformer 134 in FIG. 11, respectively. The multiple transformers 15A to 15D each have a similar structure. The following description will be given using the structure of the first transformer 15A as an example. The structures of the second transformer 15B, the third transformer 15C, and the fourth transformer 15D will be omitted because the description of the structure of the first transformer 15A applies mutatis mutandis.

[0142] 17 to 20, the first transformer 15A includes a low-potential coil 20 and a high-potential coil 23. The low-potential coil 20 is formed in the first insulating section 50. The high-potential coil 23 is formed on the second insulating section 7 so as to face the low-potential coil 20 in the normal direction Z. In this embodiment, the low-potential coil 20 is formed in a region sandwiched between the lowermost insulating layer 55 and the uppermost insulating layer 56 (i.e., multiple interlayer insulating layers 57). The high-potential coil 23 is formed on the insulating main surface 701 of the second insulating section 7. In other words, the high-potential coil 23 faces the semiconductor chip 40 with the low-potential coil 20 sandwiched between them. The low-potential coil 20 and the high-potential coil 23 may be disposed in any position. Furthermore, it is sufficient that the high-potential coil 23 faces the low-potential coil 20 with at least three or more interlayer insulating layers 57 and the second insulating section 7 sandwiched between them.

[0143] The distance D2 between the low-potential coil 20 and the high-potential coil 23 (i.e., the number of layers of the interlayer insulating layers 57 and the thickness of the second insulating section 7) is adjusted as appropriate depending on the dielectric strength and electric field strength between the low-potential coil 20 and the high-potential coil 23. In this embodiment, the low-potential coil 20 is formed on the third interlayer insulating layer 57 counting from the bottom insulating layer 55 side. On the other hand, the high-potential coil 23 is formed on the main insulating surface of the second insulating section 7. Therefore, seven interlayer insulating layers 57 and second insulating sections 7 are interposed between the low-potential coil 20 and the high-potential coil 23.

[0144] The low-potential coil 20 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. As shown in Fig. 18 , the low-potential coil 20 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 that is wound in a spiral shape between the first inner end 24 and the first outer end 25. The first spiral portion 26 is wound in a spiral shape that extends in an elliptical shape (oval shape) in a plan view. The portion that forms the innermost periphery of the first spiral portion 26 defines a first inner region 66 that is elliptical in a plan view.

[0145] The number of turns of the first helical portion 26 may be 3 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 10 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in a direction perpendicular to the helical direction. The first winding pitch of the first helical portion 26 may be 0.1 μm or more and 20 μm or less. The first winding pitch is preferably 1 μm or more and 10 μm or less. The first winding pitch is defined by the distance between two adjacent portions of the first helical portion 26 in a direction perpendicular to the helical direction.

[0146] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the form shown in Fig. 18 etc. The first spiral portion 26 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The first inner region 66 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the first spiral portion 26.

[0147] The low-potential coil 20 may include at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 20 may have a layered structure including a barrier layer and a body layer. The barrier layer defines a recess space in the interlayer insulating layer 57. The body layer is embedded in the recess space defined by the barrier layer. The barrier layer may include at least one of titanium and titanium nitride. The body layer may include at least one of copper, aluminum, and tungsten.

[0148] The high-potential coil 23 is formed to stand on the opposite side of the first insulating portion 50 from the main insulating surface 701 of the second insulating portion 7. The high-potential coil 23 is covered from its top side with a protective layer 8. As shown in FIG. 19 , the high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 that is wound in a spiral shape between the second inner end 27 and the second outer end 28. The second spiral portion 29 is wound in a spiral shape that extends in an elliptical shape (oval shape) in a planar view. In this embodiment, the portion forming the innermost periphery of the second spiral portion 29 defines a second inner region 67 that is elliptical in a planar view. The second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z.

[0149] The number of turns of the second helical portion 29 may be 3 or more and 30 or less. The number of turns of the second helical portion 29 relative to the number of turns of the first helical portion 26 is adjusted according to the voltage value to be boosted. The number of turns of the second helical portion 29 preferably exceeds the number of turns of the first helical portion 26. Of course, the number of turns of the second helical portion 29 may be less than the number of turns of the first helical portion 26 or may be equal to the number of turns of the first helical portion 26.

[0150] The width of the second helical portion 29 may be 0.1 μm or more and 10 μm or less. The width of the second helical portion 29 is preferably 1 μm or more and 10 μm or less. The width of the second helical portion 29 is defined by the width in a direction perpendicular to the helical direction. The width of the second helical portion 29 is preferably equal to the width of the first helical portion 26.

[0151] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 20 μm or less. The second winding pitch is preferably 1 μm or more and 10 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction perpendicular to the helical direction. The second winding pitch is preferably equal to the first winding pitch of the first helical portion 26.

[0152] The winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the form shown in FIG. 19 etc. The second spiral portion 29 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The second inner region 67 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the second spiral portion 29. Furthermore, a portion of the protective layer 8 fills the gaps in the second spiral portion 29.

[0153] The high-potential coil 23 may include at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The high-potential coil 23 may have a laminated structure including a barrier layer and a main body layer. The barrier layer is formed in a flat shape along the insulating main surface 701 of the second insulating portion 7. The main body layer is laminated on the barrier layer. The barrier layer may include at least one of titanium and titanium nitride. The main body layer may include at least one of copper, aluminum, and tungsten.

[0154] 17, the semiconductor device A1 includes a plurality of (12 in this embodiment) low potential terminals 13 and a plurality of (12 in this embodiment) high potential terminals 14. The plurality of low potential terminals 13 are electrically connected to the low potential coils 20 of the corresponding transformers 15A to 15D, respectively. The plurality of high potential terminals 14 are electrically connected to the high potential coils 23 of the corresponding transformers 15A to 15D, respectively.

[0155] The plurality of low potential terminals 13 are formed on the insulating principal surface 701 of the second insulating portion 7. Specifically, the plurality of low potential terminals 13 are formed in an area on the insulating sidewall 53B side at intervals in the second direction Y from the plurality of transformers 15A to 15D, and are arranged at intervals in the first direction X.

[0156] The plurality of low potential terminals 13 include a first low potential terminal 13A, a second low potential terminal 13B, a third low potential terminal 13C, a fourth low potential terminal 13D, a fifth low potential terminal 13E, and a sixth low potential terminal 13F. In this embodiment, two of each of the plurality of low potential terminals 13A to 13F are formed. The number of the plurality of low potential terminals 13A to 13F is arbitrary.

[0157] The first low potential terminal 13A faces the first transformer 15A in the second direction Y in plan view. The second low potential terminal 13B faces the second transformer 15B in the second direction Y in plan view. The third low potential terminal 13C faces the third transformer 15C in the second direction Y in plan view. The fourth low potential terminal 13D faces the fourth transformer 15D in the second direction Y in plan view. The fifth low potential terminal 13E is formed in a region between the first low potential terminal 13A and the second low potential terminal 13B in plan view. The sixth low potential terminal 13F is formed in a region between the third low potential terminal 13C and the fourth low potential terminal 13D in plan view.

[0158] The first low potential terminal 13A is electrically connected to the first inner end 24 of the first transformer 15A (low potential coil 20). The second low potential terminal 13B is electrically connected to the first inner end 24 of the second transformer 15B (low potential coil 20). The third low potential terminal 13C is electrically connected to the first inner end 24 of the third transformer 15C (low potential coil 20). The fourth low potential terminal 13D is electrically connected to the first inner end 24 of the fourth transformer 15D (low potential coil 20).

[0159] The fifth low potential terminal 13E is electrically connected to the first outer end 25 of the first transformer 15A (low potential coil 20) and the first outer end 25 of the second transformer 15B (low potential coil 20). The sixth low potential terminal 13F is electrically connected to the first outer end 25 of the third transformer 15C (low potential coil 20) and the first outer end 25 of the fourth transformer 15D (low potential coil 20).

[0160] That is, the low potential terminals 13A to 13D connected to the first inner terminals 24 of the transformers 15A to 15D are arranged closer to the transformers 15A to 15D than the low potential terminals 13E and 13F connected to the first outer terminals 25 of the transformers 15A to 15D. For example, the first low potential terminal 13A connected to the first inner terminal 24 of the first transformer 15A is arranged closer to the first transformer 15A than the fifth low potential terminal 13E connected to the first outer terminal 25 of the first transformer 15A. The same applies to the relative positions of the second low potential terminal 13B and the fifth low potential terminal 13E relative to the second transformer 15B, the relative positions of the third low potential terminal 13C and the sixth low potential terminal 13F relative to the third transformer 15C, and the relative positions of the fourth low potential terminal 13D and the sixth low potential terminal 13F relative to the fourth transformer 15D.

[0161] The multiple high potential terminals 14 are formed on the insulating main surface 701 of the second insulating portion 7 at intervals from the multiple low potential terminals 13. Specifically, the multiple high potential terminals 14 are formed in an area on the insulating sidewall 53A side at intervals from the multiple low potential terminals 13 in the second direction Y, and are arranged at intervals in the first direction X.

[0162] The multiple high potential terminals 14 are formed in regions close to the corresponding transformers 15A to 15D in a plan view. The high potential terminals 14 being close to the transformers 15A to 15D means that the distance between the high potential terminals 14 and the transformers 15A to 15D in a plan view is less than the distance between the low potential terminals 13 and the high potential terminals 14.

[0163] Specifically, the multiple high potential terminals 14 are formed at intervals along the first direction X so as to face the multiple transformers 15A to 15D along the first direction X in a plan view. More specifically, the multiple high potential terminals 14 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high potential coil 23 and in a region between adjacent high potential coils 23 in a plan view. As a result, the multiple high potential terminals 14 are arranged in a line with the multiple transformers 15A to 15D in the first direction X in a plan view.

[0164] The plurality of high potential terminals 14 include a first high potential terminal 14A, a second high potential terminal 14B, a third high potential terminal 14C, a fourth high potential terminal 14D, a fifth high potential terminal 14E, and a sixth high potential terminal 14F. In this embodiment, two of each of the plurality of high potential terminals 14A to 14F are formed. The number of the plurality of high potential terminals 14A to 14F is arbitrary.

[0165] The first high potential terminal 14A is formed in the second inner region 67 of the first transformer 15A (high potential coil 23) in a plan view. The second high potential terminal 14B is formed in the second inner region 67 of the second transformer 15B (high potential coil 23) in a plan view. The third high potential terminal 14C is formed in the second inner region 67 of the third transformer 15C (high potential coil 23) in a plan view. The fourth high potential terminal 14D is formed in the second inner region 67 of the fourth transformer 15D (high potential coil 23) in a plan view. The fifth high potential terminal 14E is formed in a region between the first transformer 15A and the second transformer 15B in a plan view. The sixth high potential terminal 14F is formed in a region between the third transformer 15C and the fourth transformer 15D in a plan view.

[0166] The first high potential terminal 14A is electrically connected to the second inner end 27 of the first transformer 15A (high potential coil 23). The second high potential terminal 14B is electrically connected to the second inner end 27 of the second transformer 15B (high potential coil 23). The third high potential terminal 14C is electrically connected to the second inner end 27 of the third transformer 15C (high potential coil 23). The fourth high potential terminal 14D is electrically connected to the second inner end 27 of the fourth transformer 15D (high potential coil 23).

[0167] The fifth high potential terminal 14E is electrically connected to the second outer end 28 of the first transformer 15A (high potential coil 23) and the second outer end 28 of the second transformer 15B (high potential coil 23). The sixth high potential terminal 14F is electrically connected to the second outer end 28 of the third transformer 15C (high potential coil 23) and the second outer end 28 of the fourth transformer 15D (high potential coil 23).

[0168] 18 and 19, the semiconductor device A1 includes a first low potential wiring 30, a second low potential wiring 35, a first high potential wiring 33, and a second high potential wiring 34. In this embodiment, a plurality of first low potential wirings 30, a plurality of second low potential wirings 35, a plurality of first high potential wirings 33, and a plurality of second high potential wirings 34 are formed.

[0169] The first low-potential wiring 30 and the second low-potential wiring 35 fix the low-potential coil 20 of the first transformer 15A and the low-potential coil 20 of the second transformer 15B to the same potential. The first low-potential wiring 30 and the second low-potential wiring 35 also fix the low-potential coil 20 of the third transformer 15C and the low-potential coil 20 of the fourth transformer 15D to the same potential. In this embodiment, the first low-potential wiring 30 and the second low-potential wiring 35 fix all the low-potential coils 20 of the transformers 15A to 15D to the same potential.

[0170] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 15A and the high-potential coil 23 of the second transformer 15B to the same potential. The first high-potential wiring 33 and the second high-potential wiring 34 also fix the high-potential coil 23 of the third transformer 15C and the high-potential coil 23 of the fourth transformer 15D to the same potential. In this embodiment, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of the transformers 15A to 15D to the same potential.

[0171] The multiple first low-potential wirings 30 are electrically connected to the corresponding low-potential terminals 13A to 13D and the first inner ends 24 of the corresponding transformers 15A to 15D (low-potential coils 20), respectively. The multiple first low-potential wirings 30 have the same structure. In the following, the structure of the first low-potential wiring 30 connected to the first low-potential terminal 13A and the first transformer 15A will be described as an example. The description of the structure of the first low-potential wiring 30 connected to the first transformer 15A applies mutatis mutandis to the structure of the other first low-potential wirings 30, and will not be repeated here.

[0172] The first low potential wiring 30 includes a through wiring 70, a low potential connection wiring 36, a lead wiring 37, a first connection plug electrode 74, and a second connection plug electrode 75. These current-carrying members are formed within the first insulating section 50. That is, they are formed closer to the first insulating section 50 than the boundary between the first insulating section 50 and the second insulating section 7. The first low potential wiring 30 also includes a first low potential pad wiring 170 and a second low potential pad wiring 171. The first low potential pad wiring 170 and the second low potential pad wiring 171 are formed closer to the second insulating section 7 than the boundary between the first insulating section 50 and the second insulating section 7.

[0173] The through wiring 70, the low-potential connecting wiring 36, the drawing wiring 37, the first connecting plug electrode 74, and the second connecting plug electrode 75 are preferably formed from the same conductive material as the low-potential coil 20, etc. In other words, the through wiring 70, the low-potential connecting wiring 36, the drawing wiring 37, the first connecting plug electrode 74, and the second connecting plug electrode 75 preferably include a barrier layer and a main body layer, similar to the low-potential coil 20, etc.

[0174] On the other hand, it is preferable that the first low-potential pad wiring 170 and the second low-potential pad wiring 171 are each formed from the same conductive material as the high-potential coil 23. In other words, it is preferable that the first low-potential pad wiring 170 and the second low-potential pad wiring 171 each include a barrier layer and a main body layer, similar to the high-potential coil 23, etc.

[0175] The through wiring 70 penetrates the multiple interlayer insulating layers 57 in the first insulating section 50 and is formed in a columnar shape extending along the normal direction Z. In this embodiment, the through wiring 70 is formed in the region between the lowermost insulating layer 55 and the uppermost insulating layer 56 in the first insulating section 50. The through wiring 70 has an upper end on the uppermost insulating layer 56 side and a lower end on the lowermost insulating layer 55 side. The upper end of the through wiring 70 is covered by the uppermost insulating layer 56 and is partially exposed from a through hole 173 formed in the uppermost insulating layer 56. The lower end of the through wiring 70 is formed in the same interlayer insulating layer 57 as the low-potential coil 20.

[0176] In this embodiment, the through wiring 70 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 38. In the through wiring 70, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 38 are each formed from the same conductive material as the low-potential coil 20, etc. In other words, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 38 each include a barrier layer and a main body layer, similar to the low-potential coil 20, etc.

[0177] The first electrode layer 78 forms the upper end of the through wiring 70. The second electrode layer 79 forms the lower end of the through wiring 70. The first electrode layer 78 is formed in an island shape and faces the low potential terminal 13 (first low potential terminal 13A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0178] The plurality of wiring plug electrodes 38 are embedded in the plurality of interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 38 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be electrically connected to one another, and electrically connect the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 38 each have a planar area that is less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0179] The number of stacked wiring plug electrodes 38 is equal to the number of stacked interlayer insulating layers 57. In this embodiment, six wiring plug electrodes 38 are embedded in each interlayer insulating layer 57, but the number of wiring plug electrodes 38 embedded in each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 38 may be formed penetrating the interlayer insulating layers 57.

[0180] The low-potential connecting wire 36 is formed in the first inner region 66 of the first transformer 15A (low-potential coil 20) in the same interlayer insulating layer 57 as the low-potential coil 20. The low-potential connecting wire 36 is formed in an island shape and faces the high-potential terminal 14 (first high-potential terminal 14A) in the normal direction Z. The low-potential connecting wire 36 preferably has a planar area that exceeds the planar area of ​​the wiring plug electrode 38. The low-potential connecting wire 36 is electrically connected to the first inner end 24 of the low-potential coil 20.

[0181] The lead-out wiring 37 is formed in the interlayer insulating layer 57 in a region between the semiconductor chip 40 and the through wiring 70. In this embodiment, the lead-out wiring 37 is formed in the first interlayer insulating layer 57 counting from the bottom insulating layer 55. The lead-out wiring 37 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of the lead-out wiring 37 is located in a region between the semiconductor chip 40 and the lower end of the through wiring 70. The second end of the lead-out wiring 37 is located in a region between the semiconductor chip 40 and the low-potential connecting wiring 36. The wiring portion extends along the first main surface 401 of the semiconductor chip 40 and extends in a strip shape in the region between the first end and the second end.

[0182] The first connection plug electrode 74 is formed in the interlayer insulating layer 57 in a region between the through wiring 70 and the lead-out wiring 37, and is electrically connected to first ends of the through wiring 70 and the lead-out wiring 37. The second connection plug electrode 75 is formed in the interlayer insulating layer 57 in a region between the low potential connection wiring 36 and the lead-out wiring 37, and is electrically connected to second ends of the low potential connection wiring 36 and the lead-out wiring 37.

[0183] The first low-potential pad wiring 170 is formed on the insulating main surface 54 of the first insulating section 50. As shown in FIG. 21 , the first low-potential pad wiring 170 is formed in an island shape on the first insulating section 50. A portion of the first low-potential pad wiring 170 is connected to the through wiring 70 via a through hole 173, and the peripheral portion surrounding the through hole 173 faces the first electrode layer 78 in the normal direction Z, with the top insulating layer 56 sandwiched therebetween. The first low-potential pad wiring 170 is covered with the second insulating section 7, and is thereby formed within the second insulating section 7. Since the first low-potential pad wiring 170 is formed in an island shape, it may also be referred to as a first low-potential pad electrode layer.

[0184] The second low-potential pad wiring 171 is formed on the insulating main surface 701 of the second insulating section 7. That is, in this embodiment, the second low-potential pad wiring 171 is formed in the same layer as the high-potential coil 23. The second low-potential pad wiring 171 may form the above-mentioned low-potential terminal 13. The second low-potential pad wiring 171 is connected to the first low-potential pad wiring 170 via a through-hole 174 formed in the second insulating section 7. As shown in FIG. 21 , the second low-potential pad wiring 171 has a width wider than that of the first low-potential pad wiring 170. Furthermore, as shown in FIG. 21 , the second low-potential pad wiring 171 has an extraction portion 175 extracted from the through-hole 174 to a region that does not overlap with the through-hole 174. The second low-potential pad wiring 171 is formed in the protective layer 8 by being covered with the protective layer 8.

[0185] In addition, the first low potential pad wiring 170 and the second low potential pad wiring 171 may be collectively referred to as low potential wiring that is electrically connected to the low potential coil 20 and extends so as to penetrate the second insulating portion 7 in the thickness direction.

[0186] 18, the plurality of second low potential wirings 35 are electrically connected to the corresponding low potential terminals 13E, 13F and the first outer ends 25 of the low potential coils 20 of the corresponding transformers 15A to 15D. Each of the plurality of second low potential wirings 35 has a structure similar to that of the first low potential wirings 30.

[0187] 19, the plurality of first high-potential wirings 33 are electrically connected to the corresponding high-potential terminals 14A to 14D and the second inner ends 27 of the corresponding transformers 15A to 15D (high-potential coils 23), respectively. The plurality of first high-potential wirings 33 each have a similar structure. The first high-potential wirings 33 may form the above-mentioned high-potential terminals 14. The following description will be given taking as an example the structure of the first high-potential wiring 33 connected to the first high-potential terminal 14A and the first transformer 15A. The description of the structure of the other first high-potential wirings 33 will be omitted, as the description of the structure of the first high-potential wiring 33 connected to the first transformer 15A applies mutatis mutandis.

[0188] The first high-potential wiring 33 is preferably formed from the same conductive material as the high-potential coil 23. That is, the first high-potential wiring 33 preferably includes a barrier layer and a main body layer, similar to the high-potential coil 23. The first high-potential wiring 33 is formed in the second inner region 67 of the high-potential coil 23 on the second insulating portion 7. The first high-potential wiring 33 is formed in an island shape and is electrically connected to the second inner end 27 of the high-potential coil 23. The first high-potential wiring 33 faces the low-potential connection wiring 36 in the normal direction Z, with the second insulating portion 7 and multiple interlayer insulating layers 57 sandwiched therebetween. Furthermore, since the first high-potential wiring 33 is formed in an island shape, it may also be referred to as a first high-potential pad electrode layer.

[0189] The multiple second high-potential wirings 34 are electrically connected to the corresponding high-potential terminals 14E, 14F and the second outer ends 28 of the corresponding transformers 15A to 15D (high-potential coils 23), respectively. The multiple second high-potential wirings 34 each have a similar structure. The second high-potential wirings 34 may form the high-potential terminals 14 described above. The following describes the structure of the second high-potential wiring 34 connected to the fifth high-potential terminal 14E and the first transformer 15A (second transformer 15B) as an example. The description of the structure of the second high-potential wiring 34 connected to the first transformer 15A (second transformer 15B) applies mutatis mutandis to the other second high-potential wirings 34, and will not be repeated here.

[0190] The second high-potential wiring 34 has the same structure as the first high-potential wiring 33, except that it is electrically connected to the second outer ends 28 of the first transformer 15A (high-potential coil 23) and the second outer ends 28 of the second transformer 15B (high-potential coil 23). That is, the second high-potential wiring 34 is formed in an island shape. Since the second high-potential wiring 34 is formed in an island shape, it may be referred to as the second high-potential pad electrode layer.

[0191] The second high-potential wiring 34 is formed around the high-potential coil 23 on the second insulating portion 7. The second high-potential wiring 34 is formed in the region between two adjacent high-potential coils 23 in a plan view and faces the high-potential terminal 14 (the fifth high-potential terminal 14E) in the normal direction Z. The second high-potential wiring 34 faces the low-potential connection wiring 36 across the second insulating portion 7 and the plurality of interlayer insulating layers 57 in the normal direction Z.

[0192] Referring to FIG. 20, it is preferable that the distance D1 between the low-potential terminal 13 and the high-potential terminal 14 exceeds the distance D2 between the low-potential coil 20 and the high-potential coil 23 (D2 < D1). It is preferable that the distance D1 exceeds the sum of the total thickness TA1 of the first insulating portion 50 and the total thickness TA2 of the second insulating portion 7 (TA1 + TA2 < D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.005 or more and 0.5 or less. It is preferable that the distance D1 is 100 μm or more and 1000 μm or less. The distance D2 may be 2 μm or more and less than 120 μm. It is preferable that the distance D2 is 5 μm or more and 50 μm or less. The values of the distance D1 and the distance D2 are arbitrary and are appropriately adjusted according to the insulation withstand voltage to be achieved.

[0193] 19, 20, and 22 to 24, the semiconductor device A1 includes dummy patterns 39 formed on the second insulating part 7 so as to be located around the transformers 15A to 15D in a plan view. In FIGS. 22 to 24, the dummy patterns 39 are indicated by hatching. The dummy patterns 39 include a conductor. The dummy patterns 39 are preferably formed of the same conductive material as the high-potential coil 23. That is, the dummy patterns 39 preferably include a barrier layer and a main body layer, similar to the high-potential coil 23, etc.

[0194] The dummy pattern 39 is formed in a pattern (discontinuous pattern) different from the high-potential coil 23 and the low-potential coil 20, and is independent of the transformers 15A to 15D. In other words, the dummy pattern 39 does not function as the transformers 15A to 15D. The dummy pattern 39 is formed as a shield conductor layer that shields the electric field between the low-potential coil 20 and the high-potential coil 23 in the transformers 15A to 15D and suppresses electric field concentration on the high-potential coil 23.

[0195] In this embodiment, the dummy pattern 39 is routed in dense lines so as to partially cover and partially expose the area surrounding one or more high-potential coils 23 in a plan view. In this embodiment, the dummy pattern 39 is routed at a line density per unit area equal to the line density of the high-potential coils 23. The line density of the dummy pattern 39 being equal to the line density of the high-potential coils 23 means that the line density of the dummy pattern 39 falls within a range of ±20% of the line density of the high-potential coils 23.

[0196] The dummy pattern 39 is preferably formed in a region closer to the high-potential coil 23 than the low-potential terminal 13 in a plan view. The dummy pattern 39 being closer to the high-potential coil 23 in a plan view means that the distance between the dummy pattern 39 and the high-potential coil 23 is less than the distance between the dummy pattern 39 and the low-potential terminal 13.

[0197] The position of the dummy pattern 39 in the normal direction Z is arbitrary and is adjusted according to the electric field strength to be alleviated. For example, the dummy pattern 39 may be located within the first insulating part 50 or on the second insulating part 7. The dummy pattern 39 is preferably formed in a region closer to the high potential coil 23 than to the low potential coil 20 in the normal direction Z. The dummy pattern 39 being closer to the high potential coil 23 in the normal direction Z means that the distance between the dummy pattern 39 and the high potential coil 23 in the normal direction Z is less than the distance between the dummy pattern 39 and the low potential coil 20.

[0198] In this case, it is possible to appropriately suppress electric field concentration on the high-potential coil 23. The shorter the distance between the dummy pattern 39 and the high-potential coil 23 in the normal direction Z, the more it is possible to suppress electric field concentration on the high-potential coil 23. It is preferable that the dummy pattern 39 is formed on the same second insulating part 7 as the high-potential coil 23. In this case, it is possible to further appropriately suppress electric field concentration on the high-potential coil 23.

[0199] The dummy patterns 39 are preferably formed around the high-potential coils 23 so as to be located in the areas between the adjacent high-potential coils 23 in a plan view. In this case, the areas between the adjacent high-potential coils 23 can be utilized to suppress undesired electric field concentration on the high-potential coils 23.

[0200] The dummy pattern 39 is preferably located in the region between the low potential terminal 13 and the high potential coil 23 in a plan view. In this case, undesired conduction between the low potential terminal 13 and the high potential coil 23 due to electric field concentration in the high potential coil 23 can be suppressed. The dummy pattern 39 is preferably located in the region between the low potential terminal 13 and the high potential terminal 14 in a plan view. In this case, undesired conduction between the low potential terminal 13 and the high potential terminal 14 due to electric field concentration in the high potential coil 23 can be suppressed.

[0201] In this embodiment, the dummy pattern 39 is formed along the plurality of high-potential coils 23 in a plan view and is interposed in the region between adjacent plurality of high-potential coils 23. Furthermore, the dummy pattern 39 collectively surrounds the region including the plurality of high-potential coils 23 and the plurality of high-potential terminals 14 in a plan view. Furthermore, the dummy pattern 39 is interposed in the region between the plurality of low-potential terminals 13A to 13F and the plurality of high-potential coils 23 in a plan view. Furthermore, the dummy pattern 39 is interposed in the region between the plurality of low-potential terminals 13A to 13F and the plurality of high-potential terminals 14A to 14F in a plan view.

[0202] The dummy pattern 39 includes a plurality of dummy patterns with different electrical states. The dummy pattern 39 includes a high-potential dummy pattern 86. The high-potential dummy pattern 86 is formed on the second insulating part 7 so as to be positioned around the transformers 15A to 15D in a plan view. The high-potential dummy pattern 86 is formed in a pattern (discontinuous pattern) different from the high-potential coil 23 and the low-potential coil 20, and is independent from the transformers 15A to 15D. In other words, the high-potential dummy pattern 86 does not function as the transformers 15A to 15D.

[0203] In this embodiment, the high-potential dummy pattern 86 is routed in dense lines so as to partially cover and partially expose the area surrounding the high-potential coil 23 in a plan view. In this embodiment, the high-potential dummy pattern 86 is routed at a line density per unit area equal to the line density of the high-potential coil 23. The line density of the high-potential dummy pattern 86 being equal to the line density of the high-potential coil 23 means that the line density of the high-potential dummy pattern 86 falls within a range of ±20% of the line density of the high-potential coil 23.

[0204] The high-potential dummy pattern 86 shields the electric field between the low-potential coil 20 and the high-potential coil 23 in the transformers 15A to 15D, thereby suppressing electric field concentration on the high-potential coil 23. Specifically, the high-potential dummy pattern 86 shields the electric field between the low-potential coil 20 and the high-potential coil 23, thereby moving the electric field leaking above the high-potential coil 23 away from the high-potential coil 23. This suppresses electric field concentration on the high-potential coil 23 caused by the electric field leaking above the high-potential coil 23.

[0205] A voltage that exceeds the voltage applied to the low-potential coil 20 is applied to the high-potential dummy pattern 86. This makes it possible to suppress the voltage drop between the high-potential coil 23 and the high-potential dummy pattern 86, thereby suppressing electric field concentration on the high-potential coil 23. It is preferable that the voltage applied to the high-potential coil 23 is applied to the high-potential dummy pattern 86. In other words, it is preferable that the high-potential dummy pattern 86 be fixed to the same potential as the high-potential coil 23. This reliably suppresses the voltage drop between the high-potential coil 23 and the high-potential dummy pattern 86, thereby appropriately suppressing electric field concentration on the high-potential coil 23.

[0206] The position of the high-potential dummy pattern 86 in the normal direction Z is arbitrary and is adjusted according to the electric field strength to be alleviated. For example, the high-potential dummy pattern 86 may be located within the first insulating part 50 or on the second insulating part 7. The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than the low-potential coil 20 in the normal direction Z. The high-potential dummy pattern 86 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 20.

[0207] In this case, it is possible to appropriately suppress electric field concentration on the high-potential coil 23. The shorter the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z, the more it is possible to suppress electric field concentration on the high-potential coil 23. It is preferable that the high-potential dummy pattern 86 is formed on the same second insulating part 7 as the high-potential coil 23. In this case, it is possible to further appropriately suppress electric field concentration on the high-potential coil 23.

[0208] The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than the low-potential terminal 13 in a plan view. The high-potential dummy pattern 86 being closer to the high-potential coil 23 in a plan view means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 is less than the distance between the high-potential dummy pattern 86 and the low-potential terminal 13.

[0209] The high-potential dummy pattern 86 is preferably formed around the plurality of high-potential coils 23 so as to be located in the region between the plurality of adjacent high-potential coils 23 in a plan view. In this case, the region between the plurality of adjacent high-potential coils 23 can be utilized to suppress undesired electric field concentration on the plurality of high-potential coils 23.

[0210] The high-potential dummy pattern 86 is preferably located in the region between the low-potential terminal 13 and the high-potential coil 23 in a plan view. In this case, undesired conduction between the low-potential terminal 13 and the high-potential coil 23 due to electric field concentration in the high-potential coil 23 can be suppressed. The high-potential dummy pattern 86 is preferably located in the region between the low-potential terminal 13 and the high-potential terminal 14 in a plan view. In this case, undesired conduction between the low-potential terminal 13 and the high-potential terminal 14 due to electric field concentration in the high-potential coil 23 can be suppressed.

[0211] In this embodiment, the high-potential dummy pattern 86 is formed along the multiple high-potential coils 23 in a plan view and is interposed in the region between adjacent multiple high-potential coils 23. Furthermore, the high-potential dummy pattern 86 collectively surrounds the region including the multiple high-potential coils 23 and the multiple high-potential terminals 14 in a plan view. Furthermore, the high-potential dummy pattern 86 is interposed in the region between the multiple low-potential terminals 13A to 13F and the multiple high-potential coils 23 in a plan view. Furthermore, the high-potential dummy pattern 86 is interposed in the region between the multiple low-potential terminals 13A to 13F and the multiple high-potential terminals 14A to 14F in a plan view.

[0212] The high-potential dummy pattern 86 is routed around the high-potential terminals 14E, 14F in the region between the plurality of high-potential coils 23 adjacent to each other in a plan view so as to expose the high-potential terminals 14E, 14F.

[0213] The high-potential dummy pattern 86 is preferably formed in an end shape. In this case, it is possible to prevent a current loop circuit (closed circuit) from being formed in the high-potential dummy pattern 86. This reduces noise caused by the current flowing through the high-potential dummy pattern 86. As a result, it is possible to suppress undesired electric field concentration caused by noise, and at the same time, it is possible to suppress fluctuations in the electrical characteristics of the transformers 15A to 15D.

[0214] The high-potential dummy pattern 86 specifically includes a first high-potential dummy pattern 87 and a second high-potential dummy pattern 88. The first high-potential dummy pattern 87 is formed in a region between the plurality of adjacent transformers 15A to 15D (the plurality of high-potential coils 23) in a planar view. The second high-potential dummy pattern 88 is formed in a region outside the region between the plurality of adjacent transformers 15A to 15D (the plurality of high-potential coils 23) in a planar view.

[0215] Hereinafter, the region between the adjacent first transformer 15A (high-potential coil 23) and second transformer 15B (high-potential coil 23) will be referred to as a first region 89 (see FIG. 22). The region between the second transformer 15B (high-potential coil 23) and third transformer 15C (high-potential coil 23) will be referred to as a second region 90 (see FIG. 23). The region between the third transformer 15C (high-potential coil 23) and fourth transformer 15D (high-potential coil 23) will be referred to as a third region 91 (see FIG. 24).

[0216] In this embodiment, the first high potential dummy pattern 87 is electrically connected to the second high potential wiring 34 (fifth high potential terminal 14E). Specifically, the first high potential dummy pattern 87 includes a first connection portion 92 connected to the second high potential wiring 34. The position of the first connection portion 92 is arbitrary. As a result, the first high potential dummy pattern 87 is fixed to the same potential as the multiple high potential coils 23.

[0217] Specifically, the first high-potential dummy pattern 87 includes a first pattern 93 formed in a first region 89, a second pattern 94 formed in a second region 90, and a third pattern 95 formed in a third region 91. As a result, the first high-potential dummy pattern 87 suppresses the electric field leaking above the high-potential coil 23 in the first region 89, the second region 90, and the third region 91, and suppresses electric field concentration on the adjacent high-potential coils 23.

[0218] In this embodiment, the first pattern 93, the second pattern 94, and the third pattern 95 are integrally formed and fixed to the same potential. The first pattern 93, the second pattern 94, and the third pattern 95 may be separated as long as they are fixed to the same potential.

[0219] 19 and 22, the first pattern 93 is connected to the second high-potential wiring 34 via a first connection portion 92. The first pattern 93 is routed in a dense line shape so as to cover a part of the first region 89 in a plan view. The first pattern 93 is formed in the first region 89 at a distance from the high-potential terminal 14 (fifth high-potential terminal 14E) in a plan view. The first pattern 93 is also formed at a distance from the low-potential connecting wiring 36 in a plan view, and does not face the low-potential connecting wiring 36 in the normal direction Z. This increases the insulation distance between the first pattern 93 and the low-potential connecting wiring 36, thereby increasing the withstand voltage of the first insulating portion 50.

[0220] The first pattern 93 includes a first circumferential line 96, a second circumferential line 97, and a plurality of first intermediate lines 98. The first circumferential line 96 extends in a band shape along the periphery of the high-potential coil 23 of the first transformer 15A. In this embodiment, the first circumferential line 96 is formed in a ring shape having an open end in the first region 89 in plan view. The width of the open end of the first circumferential line 96 is less than the width of the high-potential coil 23 along the second direction Y.

[0221] The width of the first circumferential line 96 may be 0.1 μm or more and 10 μm or less. The width of the first circumferential line 96 is preferably 1 μm or more and 5 μm or less. The width of the first circumferential line 96 is defined by the width in a direction perpendicular to the direction in which the first circumferential line 96 extends. The width of the first circumferential line 96 is preferably equal to the width of the high-potential coil 23. The width of the first circumferential line 96 being equal to the width of the high-potential coil 23 means that the width of the first circumferential line 96 falls within a range of ±20% of the width of the high-potential coil 23.

[0222] The first pitch between the first circumferential line 96 and the high-potential coil 23 (first transformer 15A) may be 0.1 μm or more and 20 μm or less. The first pitch is preferably 1 μm or more and 10 μm or less. The first pitch is preferably equal to the second winding pitch of the high-potential coil 23. The first pitch being equal to the first winding pitch means that the first pitch falls within a range of ±20% of the first winding pitch.

[0223] The second circumferential line 97 extends in a band shape along the periphery of the high-potential coil 23 of the second transformer 15B. In this embodiment, the second circumferential line 97 is formed in a ring shape having an open end in the first region 89 in a plan view. The width of the open end of the second circumferential line 97 is less than the width of the high-potential coil 23 along the second direction Y. The open end of the second circumferential line 97 faces the open end of the first circumferential line 96 along the first direction X.

[0224] The width of the second circumferential line 97 may be 0.1 μm or more and 10 μm or less. The width of the second circumferential line 97 is preferably 1 μm or more and 5 μm or less. The width of the second circumferential line 97 is defined by the width in a direction perpendicular to the direction in which the second circumferential line 97 extends. The width of the second circumferential line 97 is preferably equal to the width of the high-potential coil 23. The width of the second circumferential line 97 being equal to the width of the high-potential coil 23 means that the width of the second circumferential line 97 falls within a range of ±20% of the width of the high-potential coil 23.

[0225] The second pitch between the second circumferential line 97 and the high-potential coil 23 (second transformer 15B) may be 0.1 μm or more and 20 μm or less. The second pitch is preferably 1 μm or more and 10 μm or less. The second pitch is preferably equal to the second winding pitch of the high-potential coil 23. The second pitch being equal to the second winding pitch means that the second pitch falls within a range of ±20% of the second winding pitch.

[0226] The plurality of first intermediate lines 98 extend in a band shape in the region between the first circumferential line 96 and the second circumferential line 97 in the first region 89. The plurality of first intermediate lines 98 include at least one (one in this embodiment) first connecting line 99 that electrically connects the first circumferential line 96 and the second circumferential line 97.

[0227] From the viewpoint of preventing the formation of a current loop circuit, it is preferable that the multiple first intermediate lines 98 include only one first connecting line 99. The position of the first connecting line 99 is arbitrary. At least one of the multiple first intermediate lines 98 has a slit 140 formed therein to interrupt the current loop circuit. The position of the slit 140 is adjusted as appropriate depending on the design of the multiple first intermediate lines 98.

[0228] The multiple first intermediate lines 98 are preferably formed in a band shape extending along the opposing direction of the multiple high-potential coils 23. In this embodiment, the multiple first intermediate lines 98 are each formed in a band shape extending in the first direction X and are formed at intervals in the second direction Y. The multiple first intermediate lines 98 are formed in a stripe shape extending in the first direction X as a whole in a plan view.

[0229] The plurality of first intermediate lines 98 specifically includes a plurality of first lead-out portions 141 and a plurality of second lead-out portions 142. The plurality of first lead-out portions 141 are drawn out in stripes from the first periphery line 96 toward the second periphery line 97. The tip ends of the plurality of first lead-out portions 141 are formed at intervals from the first periphery line 96 toward the second periphery line 97.

[0230] The multiple second lead portions 142 are drawn out in a striped pattern from the second outer periphery line 97 toward the first outer periphery line 96. The tip ends of the multiple second lead portions 142 are formed at intervals from the second outer periphery line 97 toward the first outer periphery line 96. In this embodiment, the multiple second lead portions 142 are formed alternately with the multiple first lead portions 141 at intervals in the second direction Y in a manner that sandwiches one first lead portion 141 therebetween.

[0231] The plurality of second lead portions 142 may sandwich the plurality of first lead portions 141. Furthermore, a group including the plurality of second lead portions 142 may be formed adjacent to a group including the plurality of first lead portions 141. The slits 140, the plurality of first lead portions 141, and the plurality of second lead portions 142 suppress the formation of a current loop circuit in the first pattern 93.

[0232] The width of the first intermediate line 98 in the second direction Y may be 0.1 μm or more and 10 μm or less. The width of the first intermediate line 98 is preferably 1 μm or more and 5 μm or less. The width of the first intermediate line 98 is preferably equal to the width of the high-potential coil 23. The width of the first intermediate line 98 being equal to the width of the high-potential coil 23 means that the width of the first intermediate line 98 falls within a range of ±20% of the width of the high-potential coil 23.

[0233] The third pitch between two adjacent first intermediate lines 98 may be 0.1 μm or more and 20 μm or less. The third pitch is preferably 1 μm or more and 10 μm or less. The third pitch is defined by the distance between adjacent first intermediate lines 98 in the second direction Y. The third pitches are preferably equal to each other. "The third pitches are equal to each other" means that the third pitch falls within a range of ±20% of the third pitch. The third pitch is preferably equal to the second winding pitch of the high-potential coil 23. "The third pitch is equal to the second winding pitch" means that the third pitch falls within a range of ±20% of the second winding pitch.

[0234] 19 and 23, the second pattern 94 is electrically connected to the second high-potential wiring 34 (high-potential terminal 14). In this embodiment, the second pattern 94 is electrically connected to the second high-potential wiring 34 (fifth high-potential terminal 14E) via the second periphery line 97 of the first pattern 93. The second pattern 94 is routed in a dense line shape so as to cover the second region 90.

[0235] The second pattern 94 includes the aforementioned second periphery line 97, third periphery line 143, and multiple second intermediate lines 144. The third periphery line 143 extends in a band shape along the periphery of the high-potential coil 23 of the third transformer 15C. In this embodiment, the third periphery line 143 is formed in a ring shape having an open end in the third region 91 in plan view (see FIG. 24). The width of the open end of the third periphery line 143 is less than the width of the high-potential coil 23 of the third transformer 15C along the second direction Y.

[0236] The width of the third circumferential line 143 may be 0.1 μm or more and 10 μm or less. The width of the third circumferential line 143 is preferably 1 μm or more and 5 μm or less. The width of the third circumferential line 143 is defined by the width in a direction perpendicular to the direction in which the third circumferential line 143 extends. The width of the third circumferential line 143 is preferably equal to the width of the high-potential coil 23. The width of the third circumferential line 143 being equal to the width of the high-potential coil 23 means that the width of the third circumferential line 143 falls within a range of ±20% of the width of the high-potential coil 23.

[0237] The fourth pitch between the third outer circumferential line 143 and the high-potential coil 23 (third transformer 15C) may be 0.1 μm or more and 20 μm or less. The fourth pitch is preferably 1 μm or more and 10 μm or less. The fourth pitch is preferably equal to the second winding pitch of the high-potential coil 23. The fourth pitch being equal to the second winding pitch means that the fourth pitch falls within a range of ±20% of the second winding pitch.

[0238] The multiple second intermediate lines 144 extend in a band shape in the region between the second circumferential line 97 and the third circumferential line 143 in the second region 90. The multiple second intermediate lines 144 include at least one (one in this embodiment) second connection line 145 that electrically connects the second circumferential line 97 and the third circumferential line 143.

[0239] From the viewpoint of preventing the formation of a current loop circuit, it is preferable that the multiple second intermediate lines 144 include only one second connection line 145. The second connection line 145 may have a width greater than the width of the other second intermediate lines 144. The position of the second connection line 145 is arbitrary. At least one of the multiple second intermediate lines 144 has a slit 146 formed therein to interrupt the current loop circuit. The position of the slit 146 is adjusted as appropriate depending on the design of the multiple second intermediate lines 144.

[0240] The second intermediate lines 144 are preferably formed in a strip shape extending along the opposing direction of the high-potential coils 23. In this embodiment, the second intermediate lines 144 are each formed in a strip shape extending in the first direction X and spaced apart in the second direction Y. The second intermediate lines 144 are formed in a strip shape extending in the first direction X as a whole in a plan view.

[0241] Specifically, the plurality of second intermediate lines 144 includes a plurality of third lead-out portions 147 and a plurality of fourth lead-out portions 148. The plurality of third lead-out portions 147 are drawn out in stripes from the second periphery line 97 toward the third periphery line 143. The tip ends of the plurality of third lead-out portions 147 are formed at intervals from the third periphery line 143 toward the second periphery line 97.

[0242] The multiple fourth lead portions 148 are drawn out in stripes from the third outer periphery line 143 toward the second outer periphery line 97. The tip ends of the multiple fourth lead portions 148 are formed at intervals from the second outer periphery line 97 toward the third outer periphery line 143. In this embodiment, the multiple fourth lead portions 148 are formed alternately with the multiple third lead portions 147 at intervals in the second direction Y in a manner that sandwiches one third lead portion 147 therebetween.

[0243] The plurality of fourth lead portions 148 may sandwich the plurality of third lead portions 147. Furthermore, a group including the plurality of fourth lead portions 148 may be formed adjacent to a group including the plurality of third lead portions 147. The slits 146, the plurality of third lead portions 147, and the plurality of fourth lead portions 148 suppress the formation of a current loop circuit in the second pattern 94.

[0244] The width of the second intermediate line 144 in the second direction Y may be 0.1 μm or more and 10 μm or less. The width of the second intermediate line 144 is preferably 1 μm or more and 10 μm or less. The width of the second intermediate line 144 is preferably equal to the width of the high-potential coil 23. The width of the second intermediate line 144 being equal to the width of the high-potential coil 23 means that the width of the second intermediate line 144 falls within a range of ±20% of the width of the high-potential coil 23.

[0245] The fifth pitch between two adjacent second intermediate lines 144 may be 0.1 μm or more and 20 μm or less. The fifth pitch is preferably 1 μm or more and 10 μm or less. The fifth pitch is defined by the distance between adjacent second intermediate lines 144 in the second direction Y. The fifth pitches are preferably equal to each other. The fifth pitch being equal to each other means that the fifth pitch falls within a range of ±20% of the fifth pitch. The fifth pitch is preferably equal to the second winding pitch of the high-potential coil 23. The fifth pitch being equal to the second winding pitch means that the fifth pitch falls within a range of ±20% of the second winding pitch.

[0246] 19 and 24, the third pattern 95 is electrically connected to the second high-potential wiring 34. In this embodiment, the third pattern 95 is electrically connected to the second high-potential wiring 34 via the second pattern 94 and the first pattern 93. The third pattern 95 is routed in a dense line shape so as to cover a part of the third region 91. The third pattern 95 is formed in the third region 91 at a distance from the high-potential terminal 14 (sixth high-potential terminal 14F) in a plan view, and does not face the high-potential terminal 14 in the normal direction Z.

[0247] The third pattern 95 is formed at a distance from the low potential connecting wiring 36 in plan view, and does not face the low potential connecting wiring 36 in the normal direction Z. This increases the insulation distance between the third pattern 95 and the low potential connecting wiring 36 in the normal direction Z, and increases the dielectric strength voltage of the first insulating section 50.

[0248] The third pattern 95 includes the aforementioned third periphery line 143, fourth periphery line 149, and multiple third intermediate lines 150. The fourth periphery line 149 extends in a band shape along the periphery of the high-potential coil 23 of the fourth transformer 15D. In this embodiment, the fourth periphery line 149 is formed in a ring shape having an open end in the third region 91 in a plan view. The width of the open end of the fourth periphery line 149 is less than the width of the high-potential coil 23 of the fourth transformer 15D along the second direction Y. The open end of the fourth periphery line 149 faces the open end of the third periphery line 143 along the first direction X.

[0249] The width of the fourth circumferential line 149 may be 0.1 μm or more and 10 μm or less. The width of the fourth circumferential line 149 is preferably 1 μm or more and 5 μm or less. The width of the fourth circumferential line 149 is defined by the width in a direction perpendicular to the direction in which the fourth circumferential line 149 extends. The width of the fourth circumferential line 149 is preferably equal to the width of the high potential coil 23. The width of the fourth circumferential line 149 being equal to the width of the high potential coil 23 means that the width of the fourth circumferential line 149 falls within a range of ±20% of the width of the high potential coil 23.

[0250] The sixth pitch between the fourth circumferential line 149 and the high-potential coil 23 (fourth transformer 15D) may be 0.1 μm or more and 20 μm or less. The sixth pitch is preferably 1 μm or more and 10 μm or less. The sixth pitch is equal to the second winding pitch of the high-potential coil 23. The sixth pitch being equal to the second winding pitch means that the sixth pitch falls within a range of ±20% of the second winding pitch.

[0251] The plurality of third intermediate lines 150 extend in a band shape in the region between the third circumferential line 143 and the fourth circumferential line 149 in the third region 91. The plurality of third intermediate lines 150 include at least one (one in this embodiment) third connection line 151 that electrically connects the third circumferential line 143 and the fourth circumferential line 149.

[0252] From the viewpoint of preventing the formation of a current loop circuit, it is preferable that the multiple third intermediate lines 150 include only one third connection line 151. The position of the third connection line 151 is arbitrary. At least one of the multiple third intermediate lines 150 has a slit 152 formed therein to interrupt the current loop circuit. The position of the slit 152 is adjusted as appropriate depending on the design of the multiple third intermediate lines 150.

[0253] The third intermediate lines 150 are preferably formed in a strip shape extending along the opposing direction of the high-potential coils 23. In this embodiment, the third intermediate lines 150 are each formed in a strip shape extending in the first direction X and spaced apart in the second direction Y. The third intermediate lines 150 are formed in a stripe shape as a whole in a plan view.

[0254] In this embodiment, the plurality of third intermediate lines 150 includes a plurality of fifth lead-out portions 153 and a plurality of sixth lead-out portions 154. The plurality of fifth lead-out portions 153 are drawn out in stripes from the third circumferential line 143 toward the fourth circumferential line 149. The tip ends of the plurality of fifth lead-out portions 153 are formed at intervals from the fourth circumferential line 149 toward the third circumferential line 143.

[0255] The plurality of sixth lead portions 154 are drawn out in stripes from the fourth outer periphery line 149 toward the third outer periphery line 143. The tip ends of the plurality of sixth lead portions 154 are formed at intervals from the third outer periphery line 143 toward the fourth outer periphery line 149. In this embodiment, the plurality of sixth lead portions 154 are formed alternately with the plurality of fifth lead portions 153 at intervals in the second direction Y in a manner that sandwiches one fifth lead portion 153 therebetween.

[0256] The plurality of sixth lead portions 154 may sandwich the plurality of fifth lead portions 153. Furthermore, a group including the plurality of sixth lead portions 154 may be formed adjacent to a group including the plurality of fifth lead portions 153. The slits 152, the plurality of fifth lead portions 153, and the plurality of sixth lead portions 154 suppress the formation of a current loop circuit in the third pattern 95.

[0257] The width of the third intermediate line 150 in the second direction Y may be 0.1 μm or more and 10 μm or less. The width of the third intermediate line 150 is preferably 1 μm or more and 5 μm or less. The width of the third intermediate line 150 is preferably equal to the width of the high-potential coil 23. The width of the third intermediate line 150 being equal to the width of the high-potential coil 23 means that the width of the third intermediate line 150 falls within a range of ±20% of the width of the high-potential coil 23.

[0258] The seventh pitch between two adjacent third intermediate lines 150 may be 0.1 μm or more and 20 μm or less. The seventh pitch is preferably 1 μm or more and 10 μm or less. The seventh pitch is defined by the distance between adjacent third intermediate lines 150 in the second direction Y. The seventh pitches are preferably equal to each other. The seventh pitches being equal to each other means that the seventh pitch falls within a range of ±20% of the seventh pitch. The seventh pitch is preferably equal to the second winding pitch of the high-potential coil 23. The seventh pitch being equal to the second winding pitch means that the seventh pitch falls within a range of ±20% of the second winding pitch.

[0259] 19, 20 and 22 to 24, in this embodiment, the second high-potential dummy pattern 88 is electrically connected to the high-potential terminal 14 via the first high-potential dummy pattern 87. Specifically, the second high-potential dummy pattern 88 includes a second connection portion 155 connected to the first high-potential dummy pattern 87 (see FIG. 22). The position of the second connection portion 155 is arbitrary. As a result, the second high-potential dummy pattern 88 is fixed to the same potential as the multiple high-potential coils 23.

[0260] The second high-potential dummy pattern 88 suppresses the electric field leaking above the high-potential coil 23 in areas outside the first area 89, the second area 90, and the third area 91, and suppresses electric field concentration on the multiple high-potential coils 23. In this embodiment, the second high-potential dummy pattern 88 collectively surrounds the area including the multiple high-potential coils 23 and the multiple high-potential terminals 14A to 14F in plan view. In this embodiment, the second high-potential dummy pattern 88 is formed in the shape of an oval ring in plan view.

[0261] As a result, the second high potential dummy pattern 88 is located in a region between the plurality of low potential terminals 13A to 13F and the plurality of high potential coils 23 in a plan view. The second high potential dummy pattern 88 is also located in a region between the plurality of low potential terminals 13A to 13F and the plurality of high potential terminals 14A to 14F in a plan view.

[0262] The second high potential dummy pattern 88 includes a plurality of (six in this embodiment) high potential lines 156A, 156B, 156C, 156D, 156E, and 156F. The number of high potential lines is adjusted according to the electric field to be relaxed. The multiple high potential lines 156A to 156F are formed in this order at intervals in a direction away from the multiple high potential coils 23.

[0263] The multiple high potential lines 156A to 156F collectively surround the multiple high potential coils 23 in a plan view. Specifically, the multiple high potential lines 156A to 156F collectively surround an area including the multiple high potential coils 23 and the multiple high potential terminals 14A to 14F in a plan view. In this embodiment, the multiple high potential lines 156A to 156F are formed in an oval ring shape in a plan view.

[0264] Each of the plurality of high potential lines 156A to 156F includes a slit 157 that interrupts the current loop circuit, as shown in Fig. 22. The position of the slit 157 is adjusted as appropriate depending on the design of the plurality of high potential lines 156A to 156F.

[0265] The width of the high potential lines 156A to 156F may be 0.1 μm or more and 10 μm or less. The width of the high potential lines 156A to 156F is preferably 1 μm or more and 5 μm or less. The width of the high potential lines 156A to 156F is defined by the width in a direction perpendicular to the direction in which the high potential lines 156A to 156F extend. The width of the high potential lines 156A to 156F is preferably equal to the width of the high potential coil 23. The width of the high potential lines 156A to 156F being equal to the width of the high potential coil 23 means that the width of the high potential lines 156A to 156F falls within a range of ±20% of the width of the high potential coil 23.

[0266] The eighth pitch between two adjacent high potential lines 156A to 156F may be 0.1 μm or more and 20 μm or less. The eighth pitch is preferably 1 μm or more and 10 μm or less. The eighth pitches are preferably equal to each other. The eighth pitches being equal to each other means that the eighth pitches fall within a range of ±20% of the eighth pitch.

[0267] The ninth pitch between adjacent first high potential dummy patterns 87 and second high potential dummy patterns 88 may be 0.1 μm or more and 20 μm or less. The ninth pitch is preferably 1 μm or more and 10 μm or less. The ninth pitch is preferably equal to the second winding pitch of the high potential coil 23. The ninth pitch being equal to the second winding pitch means that the ninth pitch falls within a range of ±20% of the second winding pitch. The number, width, pitch, etc. of the multiple high potential lines 156A to 156F are arbitrary and are adjusted according to the electric field to be relaxed.

[0268] 19, 20, and 22 to 24, the dummy pattern 39 includes a floating dummy pattern 161 formed in an electrically floating state so as to be located around the transformers 15A to 15D in a plan view. The floating dummy pattern 161 is formed in a pattern (discontinuous pattern) different from the high potential coil 23 and the low potential coil 20, and is independent from the transformers 15A to 15D. In other words, the floating dummy pattern 161 does not function as the transformers 15A to 15D.

[0269] In this embodiment, the floating dummy pattern 161 is routed in a dense line shape so as to partially cover and partially expose the area around the high-potential coil 23 in a plan view. The floating dummy pattern 161 may be formed to have ends or to have no ends.

[0270] The floating dummy pattern 161 is routed at a line density per unit area equal to that of the high-potential coil 23. The line density of the floating dummy pattern 161 being equal to that of the high-potential coil 23 means that the line density of the floating dummy pattern 161 is within a range of ±20% of the line density of the high-potential coil 23.

[0271] Furthermore, the floating dummy patterns 161 are routed at a line density per unit area equal to that of the high-potential dummy patterns 86. The line density of the floating dummy patterns 161 being equal to that of the high-potential dummy patterns 86 means that the line density of the floating dummy patterns 161 is within a range of ±20% of the line density of the high-potential dummy patterns 86.

[0272] The floating dummy pattern 161 shields the electric field between the low-potential coil 20 and the high-potential coil 23 in the transformers 15A to 15D, and suppresses electric field concentration on the high-potential coil 23. Specifically, the floating dummy pattern 161 disperses the electric field leaking above the high-potential coil 23 in a direction away from the high-potential coil 23. This makes it possible to suppress electric field concentration on the high-potential coil 23.

[0273] Furthermore, the floating dummy pattern 161 disperses the electric field leaking above the high-potential dummy pattern 86 around the high-potential dummy pattern 86 in a direction away from the high-potential coil 23 and the high-potential dummy pattern 86. This makes it possible to suppress electric field concentration on the high-potential dummy pattern 86, and at the same time, to appropriately suppress electric field concentration on the high-potential coil 23.

[0274] The position of the floating dummy pattern 161 in the normal direction Z is arbitrary and is adjusted according to the electric field intensity to be alleviated. For example, the floating dummy pattern 161 may be located within the first insulating part 50 or on the second insulating part 7. The floating dummy pattern 161 is preferably formed in a region closer to the high potential coil 23 than to the low potential coil 20 in the normal direction Z. The floating dummy pattern 161 being closer to the high potential coil 23 in the normal direction Z means that the distance between the floating dummy pattern 161 and the high potential coil 23 in the normal direction Z is less than the distance between the floating dummy pattern 161 and the low potential coil 20.

[0275] In this case, it is possible to appropriately suppress electric field concentration on the high-potential coil 23. The shorter the distance between the floating dummy pattern 161 and the high-potential coil 23 in the normal direction Z, the more it is possible to suppress electric field concentration on the high-potential coil 23. It is preferable that the floating dummy pattern 161 is formed on the same second insulating part 7 as the high-potential coil 23. In this case, it is possible to further appropriately suppress electric field concentration on the high-potential coil 23.

[0276] The floating dummy pattern 161 is preferably located in a region between the low potential terminal 13 and the high potential coil 23 in a plan view. In this case, undesired conduction between the low potential terminal 13 and the high potential coil 23 due to electric field concentration in the high potential coil 23 can be suppressed. The floating dummy pattern 161 is preferably located in a region between the low potential terminal 13 and the high potential terminal 14 in a plan view. In this case, undesired conduction between the low potential terminal 13 and the high potential terminal 14 due to electric field concentration in the high potential coil 23 can be suppressed.

[0277] In this embodiment, the floating dummy pattern 161 is formed along the plurality of high-potential coils 23 in a planar view. Specifically, the floating dummy pattern 161 collectively surrounds an area including the plurality of high-potential coils 23 and the plurality of high-potential terminals 14 in a planar view. In this embodiment, the floating dummy pattern 161 collectively surrounds an area including the plurality of high-potential coils 23 and the plurality of high-potential terminals 14 across the high-potential dummy pattern 86 (second high-potential dummy pattern 88) in a planar view.

[0278] As a result, the floating dummy pattern 161 is located in a region between the plurality of low potential terminals 13A to 13F and the plurality of high potential coils 23 in a plan view. The floating dummy pattern 161 is also located in a region between the plurality of low potential terminals 13A to 13F and the plurality of high potential terminals 14A to 14F in a plan view.

[0279] The number of floating lines is arbitrary and is adjusted according to the electric field to be relaxed. In this embodiment, the floating dummy pattern 161 includes a plurality of (six in this embodiment) floating lines 162A, 162B, 162C, 162D, 162E, and 162F. The plurality of floating lines 162A to 162F are formed in this order at intervals in a direction away from the plurality of high potential coils 23.

[0280] The plurality of floating lines 162A to 162F collectively surround the plurality of high-potential coils 23 in plan view. Specifically, the plurality of floating lines 162A to 162F collectively surround an area including the plurality of high-potential coils 23 and the plurality of high-potential terminals 14A to 14F across the high-potential dummy pattern 86 in plan view. In this embodiment, the plurality of floating lines 162A to 162F are formed in an oval ring shape in plan view.

[0281] The width of the floating lines 162A to 162F may be 0.1 μm or more and 10 μm or less. The width of the floating lines 162A to 162F is preferably 1 μm or more and 5 μm or less. The width of the floating lines 162A to 162F is defined by the width in a direction perpendicular to the direction in which the floating lines 162A to 162F extend.

[0282] The tenth pitch between two adjacent floating lines 162A-162F may be 0.1 μm or more and 20 μm or less. The tenth pitch is preferably 1 μm or more and 10 μm or less. The width of the floating lines 162A-162F is preferably equal to the width of the high-potential coil 23. The width of the floating lines 162A-162F being equal to the width of the high-potential coil 23 means that the width of the floating lines 162A-162F falls within a range of ±20% of the width of the high-potential coil 23.

[0283] The 11th pitch between the floating dummy pattern 161 and the high potential dummy pattern 86 (second high potential dummy pattern 88) may be 0.1 μm or more and 20 μm or less. The 11th pitch is preferably 1 μm or more and 10 μm or less. The 11th pitches are preferably equal to each other. The 11th pitches being equal to each other means that the 11th pitch falls within a range of ±20% of the 11th pitch.

[0284] The 11th pitch is preferably equal to the second winding pitch of the high-potential coil 23. The 11th pitch between the floating lines 162A to 162F being equal to the second winding pitch means that the 11th pitch falls within a range of ±20% of the second winding pitch. For clarity, Figures 22 to 24 show an example in which the 11th pitch exceeds the second winding pitch.

[0285] The 12th pitch between the floating dummy pattern 161 and the high-potential dummy pattern 86 is preferably equal to the second winding pitch. The 12th pitch being equal to the second winding pitch means that the 12th pitch is within a range of ±20% of the second winding pitch. The number, width, pitch, etc. of the multiple floating lines 162A-162F are adjusted according to the electric field to be relaxed, and are not limited to specific values.

[0286] Although not shown, the dummy pattern 39 may include a low-potential dummy pattern to which a voltage lower than the voltage applied to the high-potential coil 23 (for example, the voltage applied to the low-potential coil 20) is applied, and a ground-potential dummy pattern fixed to ground potential, in addition to the high-potential dummy pattern 86 and the floating dummy pattern 161. For example, the high-potential dummy pattern 86 and the floating dummy pattern 161 may be replaced with a low-potential dummy pattern and a ground-potential dummy pattern, respectively.

[0287] 20, the semiconductor device A1 includes a second functional device 60 formed on the first main surface 401 of the semiconductor chip 40 in the device region 17. The second functional device 60 is formed using a surface layer portion of the first main surface 401 of the semiconductor chip 40 and / or a region above the first main surface 401 of the semiconductor chip 40, and is covered with a first insulating section 50 (lowermost insulating layer 55). In FIG. 20, the second functional device 60 is simply shown by a dashed line drawn on the surface layer portion of the first main surface 401.

[0288] The second functional device 60 is electrically connected to the low potential terminal 13 via a low potential wiring and to the high potential terminal 14 via a high potential wiring. The second functional device 60 may include at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device. The passive device may include a circuit network in which any two or more types of devices from the passive device, the semiconductor rectifying device, and the semiconductor switching device are selectively combined. The circuit network may form part or all of an integrated circuit.

[0289] The passive device may include a semiconductor passive device. The passive device may include either or both of a resistor and a capacitor. The semiconductor rectifying device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0290] 20, the semiconductor device A1 further includes a seal conductor 16 embedded in the first insulating section 50. The seal conductor 16 is embedded in the first insulating section 50 in a wall shape at a distance from the insulating side walls 53A to 53D in a plan view, and divides the first insulating section 50 into a device region 17 and an outer region 18. The seal conductor 16 prevents moisture and cracks from entering from the outer region 18 to the device region 17.

[0291] The device region 17 is a region including a first functional device 45 (plurality of transformers 15), a second functional device 60, a plurality of low potential terminals 13, a plurality of high potential terminals 14, a first low potential wiring 30, a second low potential wiring 35, a first high potential wiring 33, a second high potential wiring 34, and a dummy pattern 39. The outer region 18 is a region outside the device region 17.

[0292] The seal conductor 16 is electrically isolated from the device region 17. Specifically, the seal conductor 16 is electrically isolated from the first functional device 45 (plurality of transformers 15), the second functional device 60, the plurality of low potential terminals 13, the plurality of high potential terminals 14, the first low potential wiring 30, the second low potential wiring 35, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 39. More specifically, the seal conductor 16 is fixed in an electrically floating state. The seal conductor 16 does not form a current path leading to the device region 17.

[0293] The seal conductor 16 is formed in a strip shape along the insulating side walls 53 to 53D in plan view. In this embodiment, the seal conductor 16 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. As a result, the seal conductor 16 defines a quadrangular (specifically, rectangular) device region 17 in plan view. The seal conductor 16 also defines a quadrangular (specifically, rectangular) outer region 18 surrounding the device region 17 in plan view.

[0294] Specifically, the seal conductor 16 has an upper end on the insulating principal surface 54 side, a lower end on the semiconductor chip 40 side, and a wall extending in a wall shape between the upper and lower ends. In this embodiment, the upper end of the seal conductor 16 is formed at a distance from the insulating principal surface 54 toward the semiconductor chip 40 and is located within the first insulating section 50. In this embodiment, the upper end of the seal conductor 16 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 16 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 16 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 16 is formed at a distance from the semiconductor chip 40 toward the upper end.

[0295] Thus, in this embodiment, the seal conductor 16 is embedded in the first insulating section 50 so as to be located on the semiconductor chip 40 side with respect to the plurality of low potential terminals 13 and the plurality of high potential terminals 14. Furthermore, within the first insulating section 50, the seal conductor 16 faces the first functional device 45 (plurality of transformers 15), the first low potential wiring 30, the second low potential wiring 35, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 39 in a direction parallel to the insulating principal surface 54. Within the first insulating section 50, the seal conductor 16 may face a part of the second functional device 60 in a direction parallel to the insulating principal surface 54.

[0296] The seal conductor 16 includes a plurality of seal plug conductors 19 and one or more (a plurality in this embodiment) seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 19 among the plurality of seal plug conductors 19 forms the upper end portion of the seal conductor 16. The plurality of seal via conductors 65 each form the lower end portion of the seal conductor 16. The seal plug conductor 19 and the seal via conductor 65 are preferably formed from the same conductive material as the low-potential coil 20. In other words, the seal plug conductor 19 and the seal via conductor 65 preferably include a barrier layer and a main body layer, similar to the low-potential coil 20, etc.

[0297] The multiple seal plug conductors 19 are embedded in the multiple interlayer insulating layers 57, respectively, and are each formed in a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 17 in plan view. The multiple seal plug conductors 19 are stacked from the bottom insulating layer 55 to the top insulating layer 56 so as to be connected to each other. The number of stacked multiple seal plug conductors 19 matches the number of stacked multiple interlayer insulating layers 57. Of course, one or more seal plug conductors 19 may be formed penetrating the multiple interlayer insulating layers 57.

[0298] As long as a single annular seal conductor 16 is formed by an assembly of a plurality of seal plug conductors 19, it is not necessary for all of the plurality of seal plug conductors 19 to be formed in an annular shape. For example, at least one of the plurality of seal plug conductors 19 may be formed in an end shape. Also, at least one of the plurality of seal plug conductors 19 may be divided into a plurality of strip-shaped portions with ends. However, in consideration of the risk of moisture or cracks penetrating into the device region 17, it is preferable that the plurality of seal plug conductors 19 be formed in an endless (annular) shape.

[0299] The multiple seal via conductors 65 are each formed in the region between the semiconductor chip 40 and the seal plug conductor 19 in the bottom insulating layer 55. The multiple seal via conductors 65 are connected to the semiconductor chip 40 and also to the seal plug conductor 19. As a result, the seal conductor 16 may be fixed to the ground potential via the seal via conductors 65. The multiple seal via conductors 65 have a planar area smaller than the planar area of ​​the seal plug conductor 19. When a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area equal to or larger than the planar area of ​​the seal plug conductor 19.

[0300] The width of the shield conductor 16 may be 0.1 μm or more and 20 μm or less. The width of the shield conductor 16 is preferably 1 μm or more and 10 μm or less. The width of the shield conductor 16 is defined as the width in a direction perpendicular to the direction in which the shield conductor 16 extends.

[0301] Referring to FIG. 20 , the protective layer 8 is formed on the insulating principal surface 701 of the second insulating portion 7 so as to cover the high-potential coil 23, the low-potential terminal 13, the high-potential terminal 14, the dummy pattern 39, and the seal conductor 16. The protective layer 8 may be referred to as a passivation layer. The protective layer 8 protects the second insulating portion 7, the first insulating portion 50, and the semiconductor chip 40 from above the insulating principal surface 701. The protective layer 8 may be made of an organic insulating layer or may contain a photosensitive resin. The protective layer 8 may contain at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the protective layer 8 contains polyimide. The thickness of the protective layer 8 may be 1 μm or more and 100 μm or less.

[0302] The thickness of protective layer 8 is preferably equal to or greater than the distance D2 between low-potential coil 20 and high-potential coil 23. In this case, the thickness of protective layer 8 is preferably equal to or greater than 5 μm and equal to or less than 50 μm. These structures can prevent protective layer 8 from becoming too thick, and at the same time, protective layer 8 can appropriately increase the dielectric strength voltage on high-potential coil 23.

[0303] The protective layer 8 has a plurality of low-potential terminal openings 188 that expose the plurality of low-potential terminals 13, respectively. The low-potential terminals 13 exposed through the low-potential terminal openings 188 may be referred to as low-potential pads 191. A coating layer containing at least one of palladium and nickel may be formed on the surface of the low-potential pad 191. As shown in FIG. 21 , the low-potential terminal openings 188 expose the lead-out portions 175 of the second low-potential pad wiring 171. That is, the low-potential terminal openings 188 do not face the through-holes 174 in plan view, but are formed at positions offset from the through-holes 174. This can prevent poor connection of the bonding wires 71 to the low-potential terminals 13. For example, when the conductive material of the second low-potential pad wiring 171 is embedded in the through-holes 174, depending on the diameter of the through-holes 174, the upper surface of the embedded second low-potential pad wiring 171 may be recessed at a position overlapping the through-holes 174. However, in this embodiment, a part of the second low potential pad wiring 171 is drawn out onto the flat insulating main surface 701 of the second insulating portion 7 to form a drawn-out portion 175, and this drawn-out portion 175 is exposed from the low potential terminal opening 188. As a result, the exposed portion of the second low potential pad wiring 171 from the low potential terminal opening 188 is flat, allowing the bonding wire 71 to be connected well.

[0304] The protective layer 8 also has a plurality of high potential terminal openings 189 that expose the plurality of high potential terminals 14, respectively. The high potential terminals 14 exposed from the high potential terminal openings 189 may be referred to as high potential pads 192. A coating layer containing at least one of palladium and nickel may be formed on the surface of the high potential pad 192.

[0305] Next, a part of the manufacturing process of semiconductor device A1 will be described with reference to Figures 25A, 25B to 32A, 32B. More specifically, among Figures 25A, 25B to 32A, 32B, the figures with "A" at the end of the figure number show the manufacturing process of region A in Figure 20, and the figures with "B" at the end of the figure number show the manufacturing process of region B in Figure 20.

[0306] In the manufacturing process of the semiconductor device A1, a bottom insulating layer 55 is formed on the semiconductor chip 40 by, for example, a CVD method. Next, a first insulating layer 58 and a second insulating layer 59 are repeatedly stacked to form an interlayer insulating layer 57. In the process of forming the interlayer insulating layer 57, two different inorganic insulating layers 58 and 59 are formed by alternately supplying a source gas for the first insulating layer 58 and a source gas for the second insulating layer 59 into a chamber of a CVD apparatus. Between the process of forming the bottom insulating layer 55 and the process of forming the interlayer insulating layer 57, and after each process of forming the interlayer insulating layer 57, the insulating layers 55 and 57 are selectively etched, and a conductive material is filled in the through holes formed by the etching to form the low-potential coil 20, the first low-potential wiring 30, the second low-potential wiring 35, and the seal conductor 16.

[0307] 25A and 25B, after the formation of the uppermost interlayer insulating layer 57, an uppermost insulating layer 56 is formed so as to cover the interlayer insulating layer 57. Next, the uppermost insulating layer 56 is selectively etched to form a through hole 173 that exposes the through wiring 70.

[0308] Next, as shown in FIGS. 26A and 26B , a seed layer 9 is formed on the top insulating layer 56 by, for example, sputtering. The seed layer 9 is a base conductive layer for growing the first low-potential pad wiring 170 by plating, and is also formed on the upper surface (insulating main surface 54) of the top insulating layer 56 and on the through wiring 70 exposed in the through hole 173. For example, the seed layer 9 may be Cu / Ti, Cu / TiW, or the like. The thickness of the seed layer 9 may be, for example, 0.05 μm or more and 2 μm or less. Next, a resist film 10 is formed on the seed layer 9. Next, the resist film 10 is selectively exposed and developed to form an opening 43 that exposes the portion of the seed layer 9 where the first low-potential pad wiring 170 is to be formed.

[0309] 27A and 27B, a conductive material for the first low potential pad wiring 170 is grown by plating from the seed layer 9 exposed from the opening 43. In this embodiment, Cu is grown by plating from the seed layer 9. As a result, the first low potential pad wiring 170 is formed in the opening 43.

[0310] 28A and 28B, the resist film 10 is removed. After the resist film 10 is removed, the portion of the seed layer 9 that was covered with the resist film 10 (the portion exposed from the first low potential pad wiring 170) is removed.

[0311] Next, as shown in FIGS. 29A and 29B , a second insulating portion 7 (organic insulating layer 84) is formed on the uppermost insulating layer 56 so as to cover the first low-potential pad wiring 170. A known resin film formation method can be used to form the second insulating portion 7. For example, the second insulating portion 7 may be formed by spin coating. Next, the second insulating portion 7 is selectively removed by, for example, photolithography to form a through-hole 174 that exposes the first low-potential pad wiring 170. Next, a seed layer 46 is formed on the second insulating portion 7 by, for example, sputtering. The seed layer 46 is a base conductive layer for plating the second low-potential pad wiring 171 and the high-potential coil 23, and is also formed on the insulating main surface 701 of the second insulating portion 7 and the first low-potential pad wiring 170 exposed in the through-hole 174. For example, the seed layer 46 may be Cu / Ti, Cu / TiW, or the like. The thickness of the seed layer 46 may be, for example, not less than 0.05 μm and not more than 2 μm.

[0312] Next, as shown in FIGS. 30A and 30B , a resist film 47 is formed on the seed layer 46. Next, the resist film 47 is selectively exposed and developed to form an opening 48 that exposes a portion of the seed layer 46 where the second low-potential pad wiring 171 is to be formed, and an opening 49 that exposes a portion of the seed layer 46 where the high-potential coil 23 is to be formed. Next, conductive materials for the second low-potential pad wiring 171 and the high-potential coil 23 are plated from the seed layer 46 exposed from the openings 48 and 49. In this embodiment, Cu is plated from the seed layer 46. As a result, the second low-potential pad wiring 171 is formed in the opening 48, and the high-potential coil 23 is formed in the opening 49.

[0313] Although not shown in Figures 30A and 30B, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 39 may also be formed in the same process as the second low-potential pad wiring 171 and the high-potential coil 23.

[0314] 31A and 31B, the resist film 47 is removed. After the resist film 47 is removed, the portion of the seed layer 46 that was covered with the resist film 47 (the portion exposed from the second low potential pad wiring 171 and the high potential coil 23) is removed.

[0315] Next, as shown in FIGS. 32A and 32B , a protective layer 8 is formed on the insulating main surface 701 of the second insulating portion 7 so as to cover the second low-potential pad wiring 171 and the high-potential coil 23. A known method for forming a resin film can be used to form the protective layer 8. For example, the protective layer 8 may be formed by spin coating. Next, the protective layer 8 is selectively removed by, for example, photolithography, thereby forming a low-potential terminal opening 188 that exposes a portion of the second low-potential pad wiring 171 as a low-potential pad 191. Through the above steps, the semiconductor device A1 can be manufactured.

[0316] As described above, according to this semiconductor device A1, in addition to the first insulating section 50 having a laminated structure of inorganic insulating layers 58 and 59, the second insulating section 7 having an organic insulating layer 84 is formed between the low-potential coil 20 and the high-potential coil 23. Therefore, the withstand voltage between the low-potential coil 20 and the high-potential coil 23 can be achieved by thickening the second insulating section 7. The organic insulating layer 84 allows the second insulating section 7 to be formed thick using only one type of organic insulating material (resin material), without using a laminated structure of multiple different insulating materials like the inorganic insulating layers 58 and 59. For example, as shown in FIGS. 29A and 29B, the second insulating section 7 can be easily thickened by spin coating. As a result, lead time can be shortened and costs can be reduced compared to when the first insulating section 50 is formed thick.

[0317] In the above description, the seal conductor 16 is connected to the semiconductor chip 40 through the seal via conductor 65 and is fixed to the ground potential. On the other hand, as shown in Fig. 33, by omitting the seal via conductor 65, the seal conductor 16 does not need to be fixed to the ground potential.

[0318] 20 and 33, the upper corners of the second insulating portion 7 formed by the intersection of the insulating main surface 701 of the second insulating portion 7 and the insulating side walls 702A to 702D may have a certain angle, or may be rounded so as to have a curved cross-sectional shape. Also, the entire insulating main surface 701 may have a curved shape that bulges out toward the opposite side of the semiconductor chip 40.

[0319] The second insulating section 7 may also have a laminated structure of multiple organic insulating layers. In this case, the multiple organic insulating layers may be made of the same organic insulating material, or may be made of different organic insulating materials. (Second embodiment) 34 is a schematic cross-sectional view of a semiconductor device A2 according to an embodiment of the present disclosure. In the following, structures corresponding to those described above with respect to the semiconductor device A1 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0320] In the semiconductor device A2, a portion of the first low-potential wiring 30 functions as the low-potential terminal 13 of the semiconductor device A2. More specifically, the through wiring 70 (first electrode layer 78) is exposed as a low-potential pad 191. A low-potential terminal opening 190 exposing the low-potential pad 191 is formed penetrating the protective layer 8 and the second insulating portion 7. The low-potential terminal opening 190 may include a first portion 193 formed in the second insulating portion 7 and a second portion 194 formed in the protective layer 8. The second portion 194 is formed with a width greater than that of the first portion 193. This forms a step between the first portion 193 and the second portion 194. The first portion 193 may be formed in a tapered shape in cross section, with its width narrowing toward the low-potential pad 191. On the other hand, the second portion 194 may have a substantially constant width toward the low-potential pad 191.

[0321] Furthermore, the first portion 193 of the low potential terminal opening 190 is formed with a width greater than that of the through hole 173 of the uppermost insulating layer 56. As a result, a step may be formed between the first portion 193 of the low potential terminal opening 190 and the through hole 173.

[0322] As described above, according to the semiconductor device A2, similarly to the semiconductor device A1, in addition to the first insulating section 50 having a laminated structure of inorganic insulating layers 58 and 59, a second insulating section 7 having an organic insulating layer 84 is formed between the low-potential coil 20 and the high-potential coil 23. Therefore, the withstand voltage between the low-potential coil 20 and the high-potential coil 23 can be achieved by thickening the second insulating section 7. As a result, the lead time can be shortened and costs can be reduced compared to when the first insulating section 50 is formed thicker.

[0323] Furthermore, the first low potential pad wiring 170 and the second low potential pad wiring 171 are not formed, and the bonding wire 71 is directly connected to the first low potential wiring 30. Therefore, the steps of forming the first low potential pad wiring 170 and the second low potential pad wiring 171 (FIGS. 26A and 26B to 31A and 31B) can be omitted, thereby further shortening the lead time.

[0324] In the above description, the seal conductor 16 is connected to the semiconductor chip 40 through the seal via conductor 65 and is fixed to the ground potential. However, as shown in Fig. 35, by omitting the seal via conductor 65, the seal conductor 16 does not need to be fixed to the ground potential. (Third embodiment) 36 is a schematic cross-sectional view of a semiconductor device A3 according to an embodiment of the present disclosure. In the following, structures corresponding to those described above with respect to the semiconductor device A1 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0325] In the semiconductor device A3, the protective layer 8 includes a first protective layer 68 and a second protective layer 69. The first protective layer 68 is formed on the insulating principal surface 701 of the second insulating portion 7 so as to cover the high-potential coil 23, the second low-potential pad wiring 171, the first high-potential wiring 33, the dummy pattern 39, and the seal conductor 16. The second protective layer 69 is laminated on the first protective layer 68.

[0326] The first protective layer 68 and the second protective layer 69 may be made of the same organic insulating layer or different types of organic insulating layers. For example, the first protective layer 68 may contain at least one of polyimide, polyamide, and polybenzoxazole, and the second protective layer 69 may be made of the same organic insulating material as the first protective layer 68 or a different type of organic insulating material from the first protective layer 68, among the organic insulating materials exemplified above.

[0327] Furthermore, the thicknesses of the first protective layer 68 and the second protective layer 69 may be the same as or different from each other. In this embodiment, the thickness of the second protective layer 69 is preferably greater than the thickness of the first protective layer 68. By increasing the thickness of the second protective layer 69, it is possible to deepen a recess 179, which will be described later, and therefore to further increase the creepage distance between the high potential terminal 14 and the low potential terminal 13. For example, the thickness of the first protective layer 68 may be 1 μm or more and 100 μm or less, and the thickness of the second protective layer 69 may be 1 μm or more and 100 μm or less.

[0328] A third low-potential pad wiring 176 and a high-potential pad wiring 177 are formed on the main surface of the first protective layer 68. The third low-potential pad wiring 176 and the high-potential pad wiring 177 are preferably formed from the same conductive material as the high-potential coil 23. In other words, the third low-potential pad wiring 176 and the high-potential pad wiring 177 preferably each include a barrier layer and a main body layer, similar to the high-potential coil 23, etc.

[0329] The third low-potential pad wiring 176 is formed on the main surface of the first protective layer 68. That is, in this embodiment, the third low-potential pad wiring 176 is formed in a layer above the high-potential coil 23. Moreover, the third low-potential pad wiring 176 is covered with the second protective layer 69, and is thereby formed within the second protective layer 69. The third low-potential pad wiring 176 may form the above-mentioned low-potential terminal 13. The third low-potential pad wiring 176 is connected to the second low-potential pad wiring 171 via a through-hole 76 formed in the first protective layer 68.

[0330] The high-potential pad wiring 177 is formed on the main surface of the first protective layer 68. That is, in this embodiment, the high-potential pad wiring 177 is formed in a layer above the high-potential coil 23. Moreover, the high-potential pad wiring 177 is formed within the second protective layer 69 by being covered with the second protective layer 69. The high-potential pad wiring 177 may form the above-mentioned high-potential terminal 14. The high-potential pad wiring 177 is connected to the first high-potential wiring 33 via a through-hole 85 formed in the first protective layer 68.

[0331] The third low-potential pad wiring 176 and the high-potential pad wiring 177 may each be formed in an island shape, or, similar to the second low-potential pad wiring 171 shown in FIG. 21, may have an extraction portion (not shown) that is extracted from the through hole 76 and the through hole 85 to an area that does not overlap with the through hole 76 and the through hole 85.

[0332] The protective layer 8 has a plurality of low potential terminal openings 188 that expose the plurality of third low potential pad wirings 176 (low potential terminals 13). The low potential terminals 13 exposed from the low potential terminal openings 188 may be referred to as low potential pads 191.

[0333] The protective layer 8 also has a plurality of high potential terminal openings 189 that expose the plurality of high potential pad wirings 177 (high potential terminals 14). The high potential terminals 14 exposed from the high potential terminal openings 189 may be referred to as high potential pads 192.

[0334] The protective layer 8 also has a concave-convex structure 178 in a region between the low potential terminal opening 188 and the high potential terminal opening 189. The concave-convex structure 178 includes a plurality of recesses 179 recessed from the protective principal surface 82 of the protective layer 8 toward the second insulating portion 7. The concave-convex structure 178 increases the creeping distance along the protective principal surface 82 of the protective layer 8. Therefore, the concave-convex structure 178 suppresses the occurrence of creeping discharge along the protective principal surface 82 of the protective layer 8. In this embodiment, the plurality of recesses 179 penetrate the second protective layer 69 and expose the principal surface of the first protective layer 68. The plurality of recesses 179 have side surfaces formed by the second protective layer 69 from the top to the bottom and a bottom surface formed by the first protective layer 68. Alternatively, the plurality of recesses 179 may penetrate the second protective layer 69, with the bottom reaching partway through the thickness of the first protective layer 68. In this case, the side surfaces of the multiple recesses 179 may have an upper portion formed by the second protective layer 69 and a lower portion formed by the first protective layer 68. Although not shown, the concave-convex structure 178 may be formed so as to surround the high-potential coil 23 in plan view.

[0335] As described above, according to the semiconductor device A3, similarly to the semiconductor device A1, in addition to the first insulating section 50 having a laminated structure of inorganic insulating layers 58 and 59, the second insulating section 7 having the organic insulating layer 84 is formed between the low-potential coil 20 and the high-potential coil 23. Therefore, the withstand voltage between the low-potential coil 20 and the high-potential coil 23 can be achieved by thickening the second insulating section 7. As a result, the lead time can be shortened and costs can be reduced compared to when the first insulating section 50 is formed thicker.

[0336] In addition, an uneven structure 178 is formed on the protective layer 8. This increases the creeping distance along the protective main surface 82 of the protective layer 8 between the high potential terminal 14 and the low potential terminal 13, and also increases the insulation distance between the high potential terminal 14 and the low potential terminal 13. This suppresses the occurrence of creeping discharge in the region between the high potential terminal 14 and the low potential terminal 13, thereby suppressing damage and deterioration of the protective layer 8 between the high potential terminal 14 and the low potential terminal 13. As a result, it is possible to suppress short-circuiting between the high potential terminal 14 and the low potential terminal 13, thereby suppressing further damage and deterioration of the protective layer 8 due to the occurrence of the short-circuit.

[0337] In the above description, the seal conductor 16 is connected to the semiconductor chip 40 through the seal via conductor 65 and is fixed to the ground potential. On the other hand, as shown in Fig. 37, by omitting the seal via conductor 65, the seal conductor 16 does not need to be fixed to the ground potential. (Fourth embodiment) 38 is a schematic cross-sectional view of a semiconductor device A4 according to an embodiment of the present disclosure. In the following, structures corresponding to those described for the semiconductor device A2 and the semiconductor device A3 are denoted by the same reference numerals and will not be described again.

[0338] In the semiconductor device A4, the protective layer 8 of the semiconductor device A2, like the semiconductor device A3 described above, includes a first protective layer 68 and a second protective layer 69. In addition, the protective layer 8 has a concave-convex structure 178 in the region between the low potential terminal opening 190 and the high potential terminal opening 189.

[0339] As described above, according to the semiconductor device A4, similarly to the semiconductor device A1, in addition to the first insulating section 50 having a laminated structure of inorganic insulating layers 58 and 59, the second insulating section 7 having the organic insulating layer 84 is formed between the low-potential coil 20 and the high-potential coil 23. Therefore, the withstand voltage between the low-potential coil 20 and the high-potential coil 23 can be achieved by thickening the second insulating section 7. As a result, the lead time can be shortened and costs can be reduced compared to when the first insulating section 50 is formed thicker.

[0340] Furthermore, the first low potential pad wiring 170 and the second low potential pad wiring 171 are not formed, and the bonding wire 71 is directly connected to the first low potential wiring 30. Therefore, the steps of forming the first low potential pad wiring 170 and the second low potential pad wiring 171 (FIGS. 26A and 26B to 31A and 31B) can be omitted, thereby further shortening the lead time.

[0341] In addition, an uneven structure 178 is formed on the protective layer 8. This increases the creeping distance along the protective main surface 82 of the protective layer 8 between the high potential terminal 14 and the low potential terminal 13, and also increases the insulation distance between the high potential terminal 14 and the low potential terminal 13. This suppresses the occurrence of creeping discharge in the region between the high potential terminal 14 and the low potential terminal 13, thereby suppressing damage and deterioration of the protective layer 8 between the high potential terminal 14 and the low potential terminal 13. As a result, it is possible to suppress short-circuiting between the high potential terminal 14 and the low potential terminal 13, thereby suppressing further damage and deterioration of the protective layer 8 due to the occurrence of the short-circuit.

[0342] In the above description, the seal conductor 16 is connected to the semiconductor chip 40 through the seal via conductor 65 and is fixed to the ground potential. On the other hand, as shown in Fig. 39, by omitting the seal via conductor 65, the seal conductor 16 does not need to be fixed to the ground potential. <Structures of semiconductor devices B1 to B4> (First embodiment) Fig. 40 is a schematic plan view of a semiconductor device B1 according to an embodiment of the present disclosure. Fig. 41 is a plan view showing a layer in which a low-potential coil 520 is formed in the semiconductor device B1 of Fig. 40. Fig. 42 is a plan view showing a layer in which a high-potential coil 523 is formed in the semiconductor device B1 of Fig. 40. Fig. 43 is a schematic cross-sectional view of the semiconductor device B1 of Fig. 40.

[0343] 40 to 43, semiconductor device B1 includes a rectangular parallelepiped semiconductor chip 540. Semiconductor chip 540 includes at least one of silicon, a wide bandgap semiconductor, and a compound semiconductor.

[0344] The wide bandgap semiconductor is a semiconductor with a bandgap greater than that of silicon (approximately 1.12 eV). The bandgap of the wide bandgap semiconductor is preferably 2.0 eV or greater. The wide bandgap semiconductor may be silicon carbide (SiC). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0345] In this embodiment, the semiconductor chip 540 includes a silicon semiconductor substrate. The semiconductor chip 540 may be an epitaxial substrate having a layered structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type. The semiconductor chip 540 may also be fixed to ground potential.

[0346] The semiconductor chip 540 has a first main surface 541 on one side, a second main surface 542 on the other side, and chip sidewalls 544A to 544D connecting the first main surface 541 and the second main surface 542. The first main surface 541 and the second main surface 542 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from the normal direction Z thereof (hereinafter simply referred to as "plan view").

[0347] The chip sidewalls 544A to 544D include a first chip sidewall 544A, a second chip sidewall 544B, a third chip sidewall 544C, and a fourth chip sidewall 544D. The first chip sidewall 544A and the second chip sidewall 544B form the long sides of the semiconductor chip 540. The first chip sidewall 544A and the second chip sidewall 544B extend along the first direction X and face the second direction Y. The third chip sidewall 544C and the fourth chip sidewall 544D form the short sides of the semiconductor chip 540. The third chip sidewall 544C and the fourth chip sidewall 544D extend in the second direction Y and face the first direction X. The chip sidewalls 544A to 544D are composed of ground surfaces.

[0348] The semiconductor device B1 includes a first insulating section 550, a second insulating section 507, and a protective layer 508, which are formed in this order on a first main surface 541 of a semiconductor chip 540.

[0349] The first insulating portion 550 has an insulating main surface 554 and insulating side walls 553A to 553D. The insulating main surface 554 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first main surface 541 in a plan view. The insulating main surface 554 extends parallel to the first main surface 541.

[0350] The insulating side walls 553A-553D include a first insulating side wall 553A, a second insulating side wall 553B, a third insulating side wall 553C, and a fourth insulating side wall 553D. The insulating side walls 553A-553D extend from the periphery of the insulating main surface 554 toward the semiconductor chip 540 and are continuous with the chip side walls 544A-544D. Specifically, the insulating side walls 553A-553D are formed flush with the chip side walls 544A-544D. The insulating side walls 553A-553D form ground surfaces that are flush with the chip side walls 544A-544D.

[0351] The second insulating portion 507 is formed on the insulating principal surface 554, and has an insulating principal surface 501 and insulating side walls 502A to 502D. The insulating principal surface 501 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first principal surface 541 in a plan view. The insulating principal surface 501 extends parallel to the first principal surface 541.

[0352] The insulating side walls 502A to 502D include a first insulating side wall 502A, a second insulating side wall 502B, a third insulating side wall 502C, and a fourth insulating side wall 502D. The insulating side walls 502A to 502D extend from the periphery of the insulating principal surface 501 toward the semiconductor chip 540. Specifically, the insulating side walls 502A to 502D are formed inside the insulating side walls 553A to 553D. As a result, steps are formed between the insulating side walls 502A to 502D and the insulating side walls 553A to 553D.

[0353] The protective layer 508 is formed on the insulating principal surface 501, and has a protective principal surface 582 and protective side walls 583A to 583D. The protective principal surface 582 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first principal surface 541 in a plan view. The protective principal surface 582 extends parallel to the first principal surface 541.

[0354] The protective side walls 583A to 583D include a first protective side wall 583A, a second protective side wall 583B, a third protective side wall 583C, and a fourth protective side wall 583D. The protective side walls 583A to 583D extend from the periphery of the protective main surface 582 toward the semiconductor chip 540. Specifically, the protective side walls 583A to 583D are formed inside the insulating side walls 502A to 502D. As a result, steps are formed between the protective side walls 583A to 583D and the insulating side walls 502A to 502D.

[0355] The first insulating section 550 has a multilayer insulating laminate structure including a bottom insulating layer 555, a top insulating layer 556, and multiple (10 in this embodiment) interlayer insulating layers 557. The bottom insulating layer 555 is an insulating layer that directly covers the first main surface 541. The top insulating layer 556 is an insulating layer that forms the insulating main surface 554. The multiple interlayer insulating layers 557 are insulating layers interposed between the bottom insulating layer 555 and the top insulating layer 556. In this embodiment, the bottom insulating layer 555 has a single-layer structure containing silicon oxide. In this embodiment, the top insulating layer 556 has a single-layer structure containing silicon nitride. The thickness of the bottom insulating layer 555 and the top insulating layer 556 may each be 1 μm or more and 3 μm or less (for example, approximately 2 μm).

[0356] Each of the multiple interlayer insulating layers 557 has a stacked structure including a first insulating layer 558 on the side of the bottom insulating layer 555 and a second insulating layer 559 on the side of the top insulating layer 556. The first insulating layer 558 is made of an inorganic insulating layer and may contain, for example, silicon nitride. The first insulating layer 558 is formed as an etching stopper layer for the second insulating layer 559. The thickness of the first insulating layer 558 may be 0.1 μm or more and 1 μm or less (for example, approximately 0.3 μm).

[0357] Second insulating layer 559 is formed on first insulating layer 558. It contains a different insulating material from first insulating layer 558. Second insulating layer 559 is made of an inorganic insulating layer different from first insulating layer 558, and may contain, for example, silicon oxide. Second insulating layer 559 may have a thickness of 1 μm or more and 3 μm or less (for example, approximately 2 μm). It is preferable that second insulating layer 559 have a thickness greater than that of first insulating layer 558.

[0358] Furthermore, the first insulating layer 558 may be a compressive stress film, and the second insulating layer 559 may be a tensile stress film. That is, the interlayer insulating layer 557 may have a structure in which compressive stress films and tensile stress films are repeatedly stacked. This allows the first insulating part 550 to be formed while canceling stress at the stacking interface of the interlayer insulating layer 557. As a result, in the manufacturing process of the semiconductor device B1, it is possible to prevent a large warpage deformation from occurring in the semiconductor wafer that serves as the base of the semiconductor chip 540. The compressive stress film may be, for example, a silicon oxide film, and the tensile stress film may be, for example, a silicon nitride film.

[0359] The total thickness TB1 of the first insulating section 550 may be 1 μm or more and 20 μm or less. The total thickness TB1 of the first insulating section 550 and the number of layers of the interlayer insulating layers 557 are arbitrary and are adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be achieved. Furthermore, the insulating materials of the bottom insulating layer 555, the top insulating layer 556, and the interlayer insulating layers 557 are arbitrary and are not limited to a specific insulating material.

[0360] Second insulating section 507 is made of an insulating material having a dielectric constant different from that of first insulating layer 558 and second insulating layer 559, and has a layered structure including, for example, organic insulating layer 584. In this embodiment, second insulating section 507 is made of a single layer of organic insulating layer 584, but may have a laminated structure of multiple organic insulating layers. Examples of organic insulating layer 584 include a polyimide film, a phenolic resin film, and an epoxy resin film. Second insulating section 507 may have a total thickness TB2 of 2 μm or more and 100 μm or less. The total thickness TB2 of second insulating section 507 is arbitrary and is adjusted according to the desired dielectric strength voltage (dielectric breakdown resistance).

[0361] The semiconductor device B1 includes a first functional device 545. The first functional device 545 includes one or more (in this embodiment, multiple) transformers 515 (voltage transformers). In other words, the semiconductor device B1 is a multi-channel device including multiple transformers 515. The multiple transformers 515 are formed inward of the laminated structure of the first insulating section 550 and the second insulating section 507, spaced apart from the insulating side walls 553A to 553D. The multiple transformers 515 are formed at intervals in the first direction X.

[0362] Specifically, the multiple transformers 515 include a first transformer 515A, a second transformer 515B, a third transformer 515C, and a fourth transformer 515D, which are formed in this order from the insulating side wall 553C side toward the insulating side wall 553D side in a plan view. The first transformer 515A, the second transformer 515B, the third transformer 515C, and the fourth transformer 515D may correspond to the first transformer 131, the second transformer 132, the third transformer 133, and the fourth transformer 134 in FIG. 11, respectively. The multiple transformers 515A to 515D each have a similar structure. The following description will be given taking the structure of the first transformer 515A as an example. The description of the structure of the first transformer 515A applies mutatis mutandis to the description of the structure of the second transformer 515B, the third transformer 515C, and the fourth transformer 515D, and will be omitted.

[0363] 40 to 43, the first transformer 515A includes a low-potential coil 520 and a high-potential coil 523. The low-potential coil 520 is formed in the first insulating section 550. The high-potential coil 523 is formed on the second insulating section 507 so as to face the low-potential coil 520 in the normal direction Z. In this embodiment, the low-potential coil 520 is formed in a region sandwiched between the lowermost insulating layer 555 and the uppermost insulating layer 556 (i.e., in a plurality of interlayer insulating layers 557). More specifically, the low-potential coil 520 is formed in the interlayer insulating layer 557 in contact with the uppermost insulating layer 556, and its upper surface is in contact with the uppermost insulating layer 556.

[0364] The high-potential coil 523 is formed on the insulating main surface 501 of the second insulating section 507. In other words, the high-potential coil 523 faces the semiconductor chip 540 with the low-potential coil 520 sandwiched between them. The low-potential coil 520 and the high-potential coil 523 may be disposed in any position. The high-potential coil 523 only needs to face the low-potential coil 520 with the second insulating section 507 sandwiched between them.

[0365] The distance D2 between the low-potential coil 520 and the high-potential coil 523 (i.e., the thicknesses of the uppermost insulating layer 556 and the second insulating portion 507) is adjusted as appropriate depending on the dielectric strength and electric field strength between the low-potential coil 520 and the high-potential coil 523. In this embodiment, the low-potential coil 520 is formed in the uppermost interlayer insulating layer 557 counting from the lowermost insulating layer 555 side. On the other hand, the high-potential coil 523 is formed on the insulating main surface 501 of the second insulating portion 507. Therefore, the uppermost insulating layer 556 and the second insulating portion 507 are interposed between the low-potential coil 520 and the high-potential coil 523.

[0366] The low-potential coil 520 is embedded in the interlayer insulating layer 557, penetrating the first insulating layer 558 and the second insulating layer 559. As shown in FIG. 41 , the low-potential coil 520 includes a first inner end 503, a first outer end 525, and a first spiral portion 526 that is wound in a spiral shape between the first inner end 503 and the first outer end 525. The first spiral portion 526 is wound in a spiral shape that extends in an elliptical shape (oval shape) in a plan view. The portion that forms the innermost periphery of the first spiral portion 526 defines a first inner region 566 that is elliptical in a plan view.

[0367] The number of turns of the first helical portion 526 may be 5 or more and 30 or less. The width of the first helical portion 526 may be 0.1 μm or more and 5 μm or less. The width of the first helical portion 526 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 526 is defined by the width in a direction perpendicular to the helical direction. The first winding pitch of the first helical portion 526 may be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions of the first helical portion 526 in a direction perpendicular to the helical direction.

[0368] The winding shape of first spiral portion 526 and the planar shape of first inner region 566 are arbitrary and are not limited to the form shown in Fig. 41 etc. First spiral portion 526 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. First inner region 566 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of first spiral portion 526.

[0369] The low-potential coil 520 may include at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 520 may have a layered structure including a barrier layer and a body layer. The barrier layer defines a recess space in the interlayer insulating layer 557. The body layer is embedded in the recess space defined by the barrier layer. The barrier layer may include at least one of titanium and titanium nitride. The body layer may include at least one of copper, aluminum, and tungsten.

[0370] The high-potential coil 523 is formed to stand on the insulating main surface 501 of the second insulating portion 507 on the side opposite to the first insulating portion 550. The high-potential coil 523 is covered from its top side with a protective layer 508. As shown in FIG. 42 , the high-potential coil 523 includes a second inner end 527, a second outer end 528, and a second spiral portion 529 wound in a spiral shape between the second inner end 527 and the second outer end 528. The second spiral portion 529 is wound in a spiral shape extending in an elliptical (oval) shape in a plan view. In this embodiment, the portion forming the innermost periphery of the second spiral portion 529 defines a second inner region 567 having an elliptical shape in a plan view. The second inner region 567 of the second spiral portion 529 faces the first inner region 566 of the first spiral portion 526 in the normal direction Z.

[0371] The number of turns of the second helical portion 529 may be 5 or more and 30 or less. The number of turns of the second helical portion 529 relative to the number of turns of the first helical portion 526 is adjusted according to the voltage value to be boosted. The number of turns of the second helical portion 529 preferably exceeds the number of turns of the first helical portion 526. Of course, the number of turns of the second helical portion 529 may be less than the number of turns of the first helical portion 526 or may be equal to the number of turns of the first helical portion 526.

[0372] The width of the second spiral portion 529 may be 0.1 μm or more and 10 μm or less. The width of the second spiral portion 529 is preferably 1 μm or more and 5 μm or less. The width of the second spiral portion 529 is defined by the width in a direction perpendicular to the spiral direction. The width of the second spiral portion 529 is preferably equal to the width of the first spiral portion 526.

[0373] The second winding pitch of the second spiral portion 529 may be 0.1 μm or more and 20 μm or less. The second winding pitch is preferably 1 μm or more and 10 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second spiral portion 529 in a direction perpendicular to the spiral direction. The second winding pitch is preferably equal to the first winding pitch of the first spiral portion 526.

[0374] The winding shape of second spiral portion 529 and the planar shape of second inner region 567 are arbitrary and are not limited to the form shown in FIG. 42 etc. Second spiral portion 529 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. Second inner region 567 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of second spiral portion 529. Furthermore, part of protective layer 508 fills the gaps in second spiral portion 529.

[0375] The high-potential coil 523 may include at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The high-potential coil 523 may have a laminated structure including a barrier layer and a body layer. The barrier layer is formed in a flat shape along the insulating main surface 501 of the second insulating portion 507. The body layer is laminated on the barrier layer. The barrier layer may include at least one of titanium and titanium nitride. The body layer may include at least one of copper, aluminum, and tungsten.

[0376] 40, the semiconductor device B1 includes a plurality of (12 in this embodiment) low potential terminals 513 and a plurality of (12 in this embodiment) high potential terminals 514. The plurality of low potential terminals 513 are electrically connected to low potential coils 520 of corresponding transformers 515A to 515D, respectively. The plurality of high potential terminals 514 are electrically connected to high potential coils 523 of corresponding transformers 515A to 515D, respectively.

[0377] The plurality of low potential terminals 513 are formed on the insulating principal surface 501 of the second insulating portion 507. Specifically, the plurality of low potential terminals 513 are formed in an area on the insulating sidewall 553B side at intervals in the second direction Y from the plurality of transformers 515A to 515D, and are arranged at intervals in the first direction X.

[0378] The plurality of low potential terminals 513 include a first low potential terminal 513A, a second low potential terminal 513B, a third low potential terminal 513C, a fourth low potential terminal 513D, a fifth low potential terminal 513E, and a sixth low potential terminal 513F. In this embodiment, two of each of the plurality of low potential terminals 513A to 513F are formed. The number of the plurality of low potential terminals 513A to 513F is arbitrary.

[0379] The first low potential terminal 513A faces the first transformer 515A in the second direction Y in a plan view. The second low potential terminal 513B faces the second transformer 515B in the second direction Y in a plan view. The third low potential terminal 513C faces the third transformer 515C in the second direction Y in a plan view. The fourth low potential terminal 513D faces the fourth transformer 515D in the second direction Y in a plan view. The fifth low potential terminal 513E is formed in a region between the first low potential terminal 513A and the second low potential terminal 513B in a plan view. The sixth low potential terminal 513F is formed in a region between the third low potential terminal 513C and the fourth low potential terminal 513D in a plan view.

[0380] The first low potential terminal 513A is electrically connected to the first inner end 503 of the first transformer 515A (low potential coil 520). The second low potential terminal 513B is electrically connected to the first inner end 503 of the second transformer 515B (low potential coil 520). The third low potential terminal 513C is electrically connected to the first inner end 503 of the third transformer 515C (low potential coil 520). The fourth low potential terminal 513D is electrically connected to the first inner end 503 of the fourth transformer 515D (low potential coil 520).

[0381] The fifth low potential terminal 513E is electrically connected to the first outer end 525 of the first transformer 515A (low potential coil 520) and the first outer end 525 of the second transformer 515B (low potential coil 520). The sixth low potential terminal 513F is electrically connected to the first outer end 525 of the third transformer 515C (low potential coil 520) and the first outer end 525 of the fourth transformer 515D (low potential coil 520).

[0382] That is, the low potential terminals 513A to 513D connected to the first inner terminals 503 of the transformers 515A to 515D are arranged closer to the transformers 515A to 515D than the low potential terminals 513E, 513F connected to the first outer terminals 525 of the transformers 515A to 515D. For example, the first low potential terminal 513A connected to the first inner terminal 503 of the first transformer 515A is arranged closer to the first transformer 515A than the fifth low potential terminal 513E connected to the first outer terminal 525 of the first transformer 515A. The same applies to the relative positions of the second low potential terminal 513B and the fifth low potential terminal 513E relative to the second transformer 515B, the relative positions of the third low potential terminal 513C and the sixth low potential terminal 513F relative to the third transformer 515C, and the relative positions of the fourth low potential terminal 513D and the sixth low potential terminal 513F relative to the fourth transformer 515D.

[0383] The plurality of high potential terminals 514 are formed on the insulating main surface 501 of the second insulating portion 507 at intervals from the plurality of low potential terminals 513. Specifically, the plurality of high potential terminals 514 are formed in an area on the insulating sidewall 553A side at intervals from the plurality of low potential terminals 513 in the second direction Y, and are arranged at intervals in the first direction X.

[0384] The multiple high potential terminals 514 are formed in regions close to the corresponding transformers 515A to 515D in a plan view. The high potential terminals 514 being close to the transformers 515A to 515D means that the distance between the high potential terminals 514 and the transformers 515A to 515D in a plan view is less than the distance between the low potential terminals 513 and the high potential terminals 514.

[0385] Specifically, the multiple high potential terminals 514 are formed at intervals along the first direction X so as to face the multiple transformers 515A to 515D along the first direction X in a plan view. More specifically, the multiple high potential terminals 514 are formed at intervals along the first direction X so as to be located in the second inner region 567 of the high potential coil 523 and in a region between adjacent high potential coils 523 in a plan view. As a result, the multiple high potential terminals 514 are arranged in a line with the multiple transformers 515A to 515D in the first direction X in a plan view.

[0386] The plurality of high potential terminals 514 include a first high potential terminal 514A, a second high potential terminal 514B, a third high potential terminal 514C, a fourth high potential terminal 514D, a fifth high potential terminal 514E, and a sixth high potential terminal 514F. In this embodiment, two of each of the plurality of high potential terminals 514A to 514F are formed. The number of the plurality of high potential terminals 514A to 514F is arbitrary.

[0387] The first high potential terminal 514A is formed in the second inner region 567 of the first transformer 515A (high potential coil 523) in a plan view. The second high potential terminal 514B is formed in the second inner region 567 of the second transformer 515B (high potential coil 523) in a plan view. The third high potential terminal 514C is formed in the second inner region 567 of the third transformer 515C (high potential coil 523) in a plan view. The fourth high potential terminal 514D is formed in the second inner region 567 of the fourth transformer 515D (high potential coil 523) in a plan view. The fifth high potential terminal 514E is formed in a region between the first transformer 515A and the second transformer 515B in a plan view. The sixth high potential terminal 514F is formed in a region between the third transformer 515C and the fourth transformer 515D in a plan view.

[0388] The first high potential terminal 514A is electrically connected to the second inner end 527 of the first transformer 515A (high potential coil 523). The second high potential terminal 514B is electrically connected to the second inner end 527 of the second transformer 515B (high potential coil 523). The third high potential terminal 514C is electrically connected to the second inner end 527 of the third transformer 515C (high potential coil 523). The fourth high potential terminal 514D is electrically connected to the second inner end 527 of the fourth transformer 515D (high potential coil 523).

[0389] The fifth high potential terminal 514E is electrically connected to the second outer end 528 of the first transformer 515A (high potential coil 523) and the second outer end 528 of the second transformer 515B (high potential coil 523). The sixth high potential terminal 514F is electrically connected to the second outer end 528 of the third transformer 515C (high potential coil 523) and the second outer end 528 of the fourth transformer 515D (high potential coil 523).

[0390] 41 and 42, the semiconductor device B1 includes a first low potential wiring 530, a second low potential wiring 535, a first high potential wiring 533, and a second high potential wiring 534. In this embodiment, a plurality of first low potential wirings 530, a plurality of second low potential wirings 535, a plurality of first high potential wirings 533, and a plurality of second high potential wirings 534 are formed.

[0391] The first low potential wiring 530 and the second low potential wiring 535 fix the low potential coil 520 of the first transformer 515A and the low potential coil 520 of the second transformer 515B to the same potential. The first low potential wiring 530 and the second low potential wiring 535 also fix the low potential coil 520 of the third transformer 515C and the low potential coil 520 of the fourth transformer 515D to the same potential. In this embodiment, the first low potential wiring 530 and the second low potential wiring 535 fix all the low potential coils 520 of the transformers 515A to 515D to the same potential.

[0392] The first high-potential wiring 533 and the second high-potential wiring 534 fix the high-potential coil 523 of the first transformer 515A and the high-potential coil 523 of the second transformer 515B to the same potential. The first high-potential wiring 533 and the second high-potential wiring 534 also fix the high-potential coil 523 of the third transformer 515C and the high-potential coil 523 of the fourth transformer 515D to the same potential. In this embodiment, the first high-potential wiring 533 and the second high-potential wiring 534 fix all the high-potential coils 523 of the transformers 515A to 515D to the same potential.

[0393] The multiple first low potential wirings 530 are electrically connected to the corresponding low potential terminals 513A to 513D and the first inner ends 503 of the corresponding transformers 515A to 515D (low potential coils 520), respectively. The multiple first low potential wirings 530 have the same structure. In the following, the structure of the first low potential wiring 530 connected to the first low potential terminal 513A and the first transformer 515A will be described as an example. The description of the structure of the first low potential wiring 530 connected to the first transformer 515A applies mutatis mutandis to the structure of the other first low potential wirings 530, and will not be repeated here.

[0394] First low potential wiring 530 includes first wiring 579 formed closer to first insulating section 550 than the boundary between first insulating section 550 and second insulating section 507, and second wiring 570 formed closer to second insulating section 507 than the boundary between first insulating section 550 and second insulating section 507. First wiring 579 is formed in first insulating section 550, and second wiring 570 is formed in second insulating section 507. First wiring 579 and second wiring 570 are connected to each other at the boundary between first insulating section 550 and second insulating section 507.

[0395] The first wiring 579 includes a low potential connection wiring 536, a lead wiring 537, a relay pad electrode layer 578, a first connection plug electrode 574, and a second connection plug electrode 575. The low potential connection wiring 536, the lead wiring 537, the relay pad electrode layer 578, the first connection plug electrode 574, and the second connection plug electrode 575 are preferably formed from the same conductive material as the low potential coil 520, etc. In other words, the low potential connection wiring 536, the lead wiring 537, the relay pad electrode layer 578, the first connection plug electrode 574, and the second connection plug electrode 575 preferably include a barrier layer and a main body layer, similar to the low potential coil 520, etc.

[0396] The low-potential connecting wire 536 is formed in a first inner region 566 of the first transformer 515A (low-potential coil 520) in the same interlayer insulating layer 557 as the low-potential coil 520. The low-potential connecting wire 536 is formed in an island shape and faces the high-potential terminal 514 (first high-potential terminal 514A) in the normal direction Z. The low-potential connecting wire 536 is electrically connected to the first inner end 503 of the low-potential coil 520.

[0397] The lead-out wiring 537 is formed in the interlayer insulating layer 557 in a region between the semiconductor chip 540 and the second wiring 570. In this embodiment, the lead-out wiring 537 is formed in the first interlayer insulating layer 557 counting from the bottom insulating layer 555. The lead-out wiring 537 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of the lead-out wiring 537 is located in a region between the lower ends of the semiconductor chip 540 and the second wiring 570. The second end of the lead-out wiring 537 is located in a region between the semiconductor chip 540 and the low-potential connecting wiring 536. The wiring portion extends along the first main surface 541 of the semiconductor chip 540 and extends in a strip shape in the region between the first end and the second end.

[0398] The relay pad electrode layer 578 is a portion of the first wiring 579 that is connected to the second wiring 570. The relay pad electrode layer 578 is formed in the same interlayer insulating layer 557 as the low potential coil 520. The relay pad electrode layer 578 is partially exposed from a through hole 504 formed in the uppermost insulating layer 556. The relay pad electrode layer 578 is formed in an island shape, and faces the first end of the lead wiring 537 in the normal direction Z, with the interlayer insulating layer 557 in between.

[0399] The first connection plug electrode 574 is formed in the interlayer insulating layer 557 in a region between the relay pad electrode layer 578 and the lead-out wiring 537, and is electrically connected to first ends of the relay pad electrode layer 578 and the lead-out wiring 537. The second connection plug electrode 575 is formed in the interlayer insulating layer 557 in a region between the low potential connection wiring 536 and the lead-out wiring 537, and is electrically connected to second ends of the low potential connection wiring 536 and the lead-out wiring 537.

[0400] The second wiring 570 includes a pillar wiring 538 and a first low-potential pad wiring 532. The pillar wiring 538 and the first low-potential pad wiring 532 are preferably formed from the same conductive material as the high-potential coil 523. In other words, the pillar wiring 538 and the first low-potential pad wiring 532 preferably each include a barrier layer and a main body layer, similar to the high-potential coil 523, etc.

[0401] The pillar-shaped wiring 538 is formed on the insulating principal surface 554 of the first insulating portion 550. The pillar-shaped wiring 538 extends from the insulating principal surface 554 toward the insulating principal surface 501 of the second insulating portion 507 and penetrates the second insulating portion 507 in the thickness direction. In this embodiment, the pillar-shaped wiring 538 is formed in a pillar shape extending along the normal direction Z. However, since the pillar-shaped wiring 538 penetrates the second insulating portion 507, it may also be called a through wiring. The lower end of the pillar-shaped wiring 538 enters a through hole 504 formed in the uppermost insulating layer 556 and is connected to the relay pad electrode layer 578 within the through hole 504. The pillar-shaped wiring 538 has a width wider than the opening width of the through hole 504. As a result, the pillar-shaped wiring 538 has a peripheral portion 505 that overlaps the uppermost insulating layer 556 around the through hole 504. A peripheral portion 505 of the pillar-shaped wiring 538 faces the relay pad electrode layer 578 across the uppermost insulating layer 556. The pillar-shaped wiring 538 is in direct contact with the relay pad electrode layer 578 and is formed in a region directly above the relay pad electrode layer 578.

[0402] Additionally, the upper end of the columnar wiring 538 is exposed from a through hole 506 formed in the insulating principal surface 501 of the second insulating portion 507. The through hole 506 has a constant depth from the insulating principal surface 501 of the second insulating portion 507 toward the first insulating portion 550. As a result, the top surface 551 of the columnar wiring 538 is formed on the first insulating portion 550 side with respect to the insulating principal surface 501, and a step is formed between the top surface 551 and the insulating principal surface 501.

[0403] The first low-potential pad wiring 532 is formed on the insulating main surface 501 of the second insulating portion 507. That is, in this embodiment, the first low-potential pad wiring 532 is formed in the same layer as the high-potential coil 523. The first low-potential pad wiring 532 may form the above-mentioned low-potential terminal 513. The first low-potential pad wiring 532 is connected to the pillar-shaped wiring 538 via a through-hole 506 formed in the second insulating portion 507. The first low-potential pad wiring 532 has a width wider than that of the pillar-shaped wiring 538. The first low-potential pad wiring 532 may have a planar shape similar to that of the second low-potential pad wiring 171 shown in FIG. 21. That is, the first low-potential pad wiring 532 may have a lead-out portion 552 (not shown) led out from the through-hole 506 to a region not overlapping with the through-hole 506. The lead-out portion 552 may have a shape corresponding to the lead-out portion 175 shown in FIG. 21. The first low-potential pad wiring 532 is covered with the protective layer 508 and is thereby formed within the protective layer 508.

[0404] 41, the plurality of second low potential wirings 535 are electrically connected to the corresponding low potential terminals 513E, 513F and the first outer ends 525 of the low potential coils 520 of the corresponding transformers 515A to 515D. Each of the plurality of second low potential wirings 535 has a similar structure to the first low potential wirings 530.

[0405] 42, the plurality of first high potential wirings 533 are electrically connected to the corresponding high potential terminals 514A-514D and the second inner ends 527 of the corresponding transformers 515A-515D (high potential coils 523). The plurality of first high potential wirings 533 each have a similar structure. The first high potential wirings 533 may form the above-mentioned high potential terminals 514. The following description will be given taking as an example the structure of the first high potential wiring 533 connected to the first high potential terminal 514A and the first transformer 515A. The description of the structure of the other first high potential wirings 533 will be omitted, as the description of the structure of the first high potential wiring 533 connected to the first transformer 515A applies mutatis mutandis.

[0406] The first high-potential wiring 533 is preferably formed from the same conductive material as the high-potential coil 523. That is, the first high-potential wiring 533 preferably includes a barrier layer and a main body layer, similar to the high-potential coil 523. The first high-potential wiring 533 is formed in the second inner region 567 of the high-potential coil 523 on the second insulating portion 507. The first high-potential wiring 533 is formed in an island shape and is electrically connected to the second inner end 527 of the high-potential coil 523. The first high-potential wiring 533 faces the low-potential connection wiring 536 in the normal direction Z, with the second insulating portion 507 and the uppermost insulating layer 556 sandwiched therebetween. Furthermore, since the first high-potential wiring 533 is formed in an island shape, it may also be referred to as a first high-potential pad electrode layer.

[0407] The plurality of second high potential wirings 534 are electrically connected to the corresponding high potential terminals 514E, 514F and the second outer ends 528 of the corresponding transformers 515A to 515D (high potential coils 523), respectively. The plurality of second high potential wirings 534 each have a similar structure. In the following, the structure of the second high potential wiring 534 connected to the fifth high potential terminal 514E and the first transformer 515A (second transformer 515B) will be described as an example. The description of the structure of the second high potential wiring 534 connected to the first transformer 515A (second transformer 515B) applies mutatis mutandis to the structure of the other second high potential wirings 534, and will not be repeated here.

[0408] The second high potential wiring 534 has the same structure as the first high potential wiring 533, except that it is electrically connected to the second outer end 528 of the first transformer 515A (high potential coil 523) and the second outer end 528 of the second transformer 515B (high potential coil 523). That is, the second high potential wiring 534 is formed in an island shape. Because the second high potential wiring 534 is formed in an island shape, it may also be called a second high potential pad electrode layer.

[0409] The second high-potential wiring 534 is formed around the high-potential coil 523 on the second insulating portion 507. The second high-potential wiring 534 is formed in the region between two adjacent high-potential coils 523 in a plan view, and faces the high-potential terminal 514 (the fifth high-potential terminal 514E) in the normal direction Z. The second high-potential wiring 534 faces the low-potential connection wiring 536 across the second insulating portion 507 and the uppermost insulating layer 556 in the normal direction Z.

[0410] Referring to FIG. 43, it is preferable that the distance D1 between the low-potential terminal 513 and the high-potential terminal 514 exceeds the distance D2 between the low-potential coil 520 and the high-potential coil 523 (D2 < D1). It is preferable that the distance D1 exceeds the sum of the total thickness TB1 of the first insulating portion 550 and the total thickness TB2 of the second insulating portion 507 (TB1 + TB2 < D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.005 or more and 0.5 or less. The distance D1 is preferably 100 μm or more and 1000 μm or less. The distance D2 may be 2 μm or more and 120 μm or less. The distance D2 is preferably 5 μm or more and 50 μm or less. The values of the distance D1 and the distance D2 are arbitrary and are appropriately adjusted according to the insulation withstand voltage to be achieved.

[0411] Referring to FIGS. 42 and 43, the semiconductor device B1 includes a dummy pattern 539 formed on the second insulating portion 507 so as to be located around the transformers 515A to 515D in a plan view.

[0412] The dummy pattern 539 may have the same shape as the dummy pattern 39 of the semiconductor device A1. For example, the dummy pattern 539 may include a high-potential dummy pattern 586 having a shape corresponding to the high-potential dummy pattern 86, a first high-potential dummy pattern 587 having a shape corresponding to the first high-potential dummy pattern 87, a second high-potential dummy pattern 588 having a shape corresponding to the second high-potential dummy pattern 88, and a floating dummy pattern 661 having a shape corresponding to the floating dummy pattern 161. In FIG. 55, the high-potential dummy pattern 586, the second high-potential dummy pattern 588, and the floating dummy pattern 661 are shown.

[0413] 43, the semiconductor device B1 includes a second functional device 560 formed on the first main surface 541 of the semiconductor chip 540 in the device region 517. The second functional device 560 is formed using a surface layer portion of the first main surface 541 of the semiconductor chip 540 and / or a region above the first main surface 541 of the semiconductor chip 540, and is covered with a first insulating portion 550 (lowermost insulating layer 555). In FIG. 43, the second functional device 560 is simply shown by a dashed line drawn on the surface layer portion of the first main surface 541.

[0414] The second functional device 560 is electrically connected to the low-potential terminal 513 via a low-potential wiring and to the high-potential terminal 514 via a high-potential wiring. The second functional device 560 may include at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device. The passive device may include a circuit network in which any two or more types of devices from the passive device, the semiconductor rectifying device, and the semiconductor switching device are selectively combined. The circuit network may form part or all of an integrated circuit.

[0415] The passive device may include a semiconductor passive device. The passive device may include either or both of a resistor and a capacitor. The semiconductor rectifying device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0416] 43, the semiconductor device B1 further includes a seal conductor 516 embedded in the first insulating section 550. The seal conductor 516 is embedded in the first insulating section 550 in a wall shape at a distance from the insulating side walls 553A to 553D in a plan view, and divides the first insulating section 550 into a device region 517 and an outer region 518. The seal conductor 516 prevents moisture and cracks from entering from the outer region 518 to the device region 517.

[0417] The device region 517 is a region including a first functional device 545 (plurality of transformers 515), a second functional device 560, a plurality of low potential terminals 513, a plurality of high potential terminals 514, a first low potential wiring 530, a second low potential wiring 535, a first high potential wiring 533, a second high potential wiring 534, and a dummy pattern 539. The outer region 518 is a region outside the device region 517.

[0418] The seal conductor 516 is electrically isolated from the device region 517. Specifically, the seal conductor 516 is electrically isolated from the first functional device 545 (the multiple transformers 515), the second functional device 560, the multiple low potential terminals 513, the multiple high potential terminals 514, the first low potential wiring 530, the second low potential wiring 535, the first high potential wiring 533, the second high potential wiring 534, and the dummy pattern 539. More specifically, the seal conductor 516 is fixed in an electrically floating state. The seal conductor 516 does not form a current path leading to the device region 517.

[0419] The seal conductor 516 is formed in a strip shape along the insulating side walls 553 to 553D in plan view. In this embodiment, the seal conductor 516 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. As a result, the seal conductor 516 defines a quadrangular (specifically, rectangular) device region 517 in plan view. The seal conductor 516 also defines a quadrangular (specifically, rectangular) outer region 518 surrounding the device region 517 in plan view.

[0420] Specifically, the seal conductor 516 has an upper end on the insulating principal surface 554 side, a lower end on the semiconductor chip 540 side, and a wall extending in a wall shape between the upper and lower ends. In this embodiment, the upper end of the seal conductor 516 is formed at a distance from the insulating principal surface 554 toward the semiconductor chip 540 and is located within the first insulating portion 550. In this embodiment, the upper end of the seal conductor 516 is covered by the uppermost insulating layer 556. The upper end of the seal conductor 516 may be covered by one or more interlayer insulating layers 557. The upper end of the seal conductor 516 may be exposed from the uppermost insulating layer 556. The lower end of the seal conductor 516 is formed at a distance from the semiconductor chip 540 toward the upper end.

[0421] Thus, in this embodiment, the seal conductor 516 is embedded in the first insulating section 550 so as to be located on the semiconductor chip 540 side with respect to the plurality of low potential terminals 513 and the plurality of high potential terminals 514. Furthermore, the seal conductor 516 faces the first functional device 545 (plurality of transformers 515), the first low potential wiring 530, the second low potential wiring 535, the first high potential wiring 533, the second high potential wiring 534, and the dummy pattern 539 in the first insulating section 550 in a direction parallel to the insulating principal surface 554. The seal conductor 516 may face a part of the second functional device 560 in the direction parallel to the insulating principal surface 554 in the first insulating section 550.

[0422] The seal conductor 516 includes a plurality of seal plug conductors 519 and one or more (a plurality in this embodiment) seal via conductors 565. The number of seal via conductors 565 is arbitrary. The uppermost seal plug conductor 519 among the plurality of seal plug conductors 519 forms the upper end portion of the seal conductor 516. The plurality of seal via conductors 565 each form the lower end portion of the seal conductor 516. The seal plug conductor 519 and the seal via conductor 565 are preferably formed from the same conductive material as the low potential coil 520. In other words, the seal plug conductor 519 and the seal via conductor 565 preferably include a barrier layer and a main body layer, similar to the low potential coil 520, etc.

[0423] The multiple seal plug conductors 519 are embedded in the multiple interlayer insulating layers 557, respectively, and are each formed in a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 517 in plan view. The multiple seal plug conductors 519 are stacked from the lowermost insulating layer 555 to the uppermost insulating layer 556 so as to be connected to each other. The number of stacked multiple seal plug conductors 519 matches the number of stacked multiple interlayer insulating layers 557. Of course, one or more seal plug conductors 519 may be formed penetrating the multiple interlayer insulating layers 557.

[0424] As long as a single annular seal conductor 516 is formed by an assembly of a plurality of seal plug conductors 519, it is not necessary for all of the plurality of seal plug conductors 519 to be formed in an annular shape. For example, at least one of the plurality of seal plug conductors 519 may be formed in an end-shaped form. Also, at least one of the plurality of seal plug conductors 519 may be divided into a plurality of strip-shaped portions with ends. However, in consideration of the risk of moisture or cracks penetrating into the device region 517, it is preferable that the plurality of seal plug conductors 519 be formed in an endless (annular) form.

[0425] The multiple seal via conductors 565 are each formed in a region between the semiconductor chip 540 and the seal plug conductor 519 in the lowermost insulating layer 555. The multiple seal via conductors 565 are connected to the semiconductor chip 540 and also to the seal plug conductor 519. As a result, the seal conductor 516 may be fixed to the ground potential via the seal via conductors 565. The multiple seal via conductors 565 have a plane area smaller than the plane area of ​​the seal plug conductor 519. When a single seal via conductor 565 is formed, the single seal via conductor 565 may have a plane area equal to or larger than the plane area of ​​the seal plug conductor 519.

[0426] The width of the shield conductor 516 may be 0.1 μm or more and 20 μm or less. The width of the shield conductor 516 is preferably 1 μm or more and 10 μm or less. The width of the shield conductor 516 is defined by the width in a direction perpendicular to the direction in which the shield conductor 516 extends.

[0427] Referring to FIG. 43 , the protective layer 508 is formed on the insulating principal surface 501 of the second insulating portion 507 so as to cover the high-potential coil 523, the low-potential terminal 513, the high-potential terminal 514, and the dummy pattern 539. The protective layer 508 may be referred to as a passivation layer. The protective layer 508 protects the second insulating portion 507, the first insulating portion 550, and the semiconductor chip 540 from above the insulating principal surface 501. The protective layer 508 may be made of an organic insulating layer or may contain a photosensitive resin. The protective layer 508 may contain at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the protective layer 508 contains polyimide. The thickness of the protective layer 508 may be 1 μm or more and 100 μm or less.

[0428] The thickness of protective layer 508 is preferably equal to or greater than distance D2 between low potential coil 520 and high potential coil 523. In this case, the thickness of protective layer 508 is preferably equal to or greater than 5 μm and equal to or less than 50 μm. These structures can prevent protective layer 508 from becoming too thick, and at the same time, protective layer 508 can appropriately increase the dielectric strength voltage on high potential coil 523.

[0429] The protective layer 508 has a plurality of low-potential terminal openings 688 that expose the plurality of low-potential terminals 513, respectively. The low-potential terminals 513 exposed through the low-potential terminal openings 688 may be referred to as low-potential pads 691. A coating layer containing at least one of palladium and nickel may be formed on the surface of the low-potential pad 691. The low-potential terminal openings 688 expose the lead-out portions 552 of the first low-potential pad wiring 532. That is, the low-potential terminal openings 688 do not face the through-holes 506 in plan view, but are formed at positions offset from the through-holes 506. This can prevent poor connection of the bonding wires 71 to the low-potential terminals 513. For example, when the conductive material of the first low-potential pad wiring 532 is embedded in the through-holes 506, depending on the diameter of the through-holes 506, the upper surface of the embedded first low-potential pad wiring 532 may be recessed at a position overlapping the through-holes 506. However, in this embodiment, a part of the first low potential pad wiring 532 is drawn out onto the flat insulating main surface 501 of the second insulating portion 507 to form a drawn-out portion 552, and this drawn-out portion 552 is exposed from the low potential terminal opening 688. As a result, the exposed portion of the first low potential pad wiring 532 from the low potential terminal opening 688 is flat, allowing the bonding wire 71 to be connected well.

[0430] The protective layer 508 also has a plurality of high potential terminal openings 689 that expose the plurality of high potential terminals 514. The high potential terminals 514 exposed from the high potential terminal openings 689 may be referred to as high potential pads 692.

[0431] As described above, according to the semiconductor device B1, the second insulating section 507 made of the organic insulating layer 584 is formed between the low-potential coil 520 and the high-potential coil 523. Therefore, the withstand voltage between the low-potential coil 520 and the high-potential coil 523 can be achieved by thickening the second insulating section 507. The organic insulating layer 584 allows the second insulating section 507 to be formed thick using only one type of organic insulating material (resin material), without using a layered structure made of multiple different insulating materials like the inorganic insulating layers 558 and 559. For example, the second insulating section 507 can be easily thickened by spin coating. As a result, the lead time can be shortened and costs can be reduced compared to when the first insulating section 550 is formed thick.

[0432] Furthermore, because the second insulating section 507 is made of a single organic insulating layer 584, the wiring (columnar wiring 538) penetrating the second insulating section 507 can be easily formed by a single plating growth. In contrast, if the second insulating section 707 has a multilayer wiring structure including multiple inorganic insulating layers like the first insulating section 550, a process of embedding a conductor (similar to the seal conductor 516, for example) into the inorganic insulating layer is required each time an inorganic insulating layer is stacked, and thus, to form the wiring penetrating the second insulating section 507, the same number of processes as the number of layers in the multilayer wiring structure are required. Therefore, in this semiconductor device B1, the lead time for the process of forming the wiring penetrating the second insulating section 507 can also be shortened.

[0433] Meanwhile, between the low-potential coil 520 and the semiconductor chip 540 is a first insulating section 550 made of a multilayer insulating laminated structure including an interlayer insulating layer 557. As a result, when the first functional device 545 (transformer 515) and the second functional device 560 are mounted together, the first insulating section 550 can be used as a space for routing multilayer wiring connected to the second functional device 560. Furthermore, the first insulating section 550 made of an inorganic insulating layer has better flatness than the second insulating section 507 made of an organic insulating layer, and therefore the flatness of the multilayer wiring structure on the semiconductor chip 540 can also be ensured satisfactorily.

[0434] In the above description, the seal conductor 516 is connected to the semiconductor chip 540 through the seal via conductor 565 and is fixed to the ground potential. On the other hand, as shown in Fig. 44, by omitting the seal via conductor 565, the seal conductor 516 does not need to be fixed to the ground potential.

[0435] 43 and 44, the upper corners of second insulating portion 507 formed by the intersection of insulating main surface 501 of second insulating portion 507 and insulating side walls 502A to 502D may have a certain angle or may be rounded so as to have a curved cross-sectional shape. Also, the entire insulating main surface 501 may have a curved shape that bulges out toward the opposite side of semiconductor chip 540.

[0436] Second insulating section 507 may also have a laminated structure of multiple organic insulating layers. In this case, the multiple organic insulating layers may be made of the same organic insulating material, or may be made of different organic insulating materials. (Second embodiment) 45 is a schematic cross-sectional view of a semiconductor device B2 according to an embodiment of the present disclosure. In the following, structures corresponding to those described above with respect to the semiconductor device B1 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0437] In the semiconductor device B2, a part of the first low potential wiring 530 functions as the low potential terminal 513 of the semiconductor device B2. More specifically, the first wiring 579 (relay pad electrode layer 578) is exposed as a low potential pad 691. In this case, unlike the semiconductor device B1, the relay pad electrode layer 578 is not a member that relays current between the columnar wiring 538 and the first low potential wiring 530, and therefore may be referred to as a pad electrode layer, for example.

[0438] A low potential terminal opening 690 exposing a low potential pad 691 is formed by penetrating the protective layer 508 and the second insulating portion 507. The low potential terminal opening 690 may include a first portion 693 formed in the second insulating portion 507 and a second portion 694 formed in the protective layer 508. The second portion 694 is formed with a width greater than that of the first portion 693. This forms a step between the first portion 693 and the second portion 694. The first portion 693 may be formed in a tapered shape in cross section, with its width narrowing toward the low potential pad 691. On the other hand, the second portion 694 may have a substantially constant width toward the low potential pad 691.

[0439] Furthermore, the first portion 693 of the low potential terminal opening 690 is formed with a width greater than the through hole 504 of the uppermost insulating layer 556. As a result, a step may be formed between the first portion 693 of the low potential terminal opening 690 and the through hole 504.

[0440] As described above, according to the semiconductor device B2, similarly to the semiconductor device B1, the second insulating section 507 made of the organic insulating layer 584 is formed between the low-potential coil 520 and the high-potential coil 523. Therefore, the withstand voltage between the low-potential coil 520 and the high-potential coil 523 can be achieved by thickening the second insulating section 507. As a result, the lead time can be shortened and costs can be reduced compared to when the first insulating section 550 is formed thicker.

[0441] Furthermore, between the low-potential coil 520 and the semiconductor chip 540 is a first insulating section 550 made of a multilayer insulating laminated structure including an interlayer insulating layer 557. As a result, when the first functional device 545 (transformer 515) and the second functional device 560 are mounted together, the first insulating section 550 can be used as a space for routing multilayer wiring connected to the second functional device 560. Furthermore, the first insulating section 550 made of an inorganic insulating layer has better flatness than the second insulating section 507 made of an organic insulating layer, and therefore the flatness of the multilayer wiring structure on the semiconductor chip 540 can also be ensured satisfactorily.

[0442] Furthermore, the pillar-shaped wiring 538 and the first low-potential pad wiring 532 are not formed, and the bonding wire 71 is directly connected to the first wiring 579 (first low-potential wiring 530). Therefore, the process of forming the pillar-shaped wiring 538 and the first low-potential pad wiring 532 can be omitted, and the lead time can be further shortened.

[0443] In the above description, the seal conductor 516 is connected to the semiconductor chip 540 through the seal via conductor 565 and is fixed to the ground potential. On the other hand, as shown in Fig. 46, by omitting the seal via conductor 565, the seal conductor 516 does not need to be fixed to the ground potential. (Third embodiment) 47 is a schematic cross-sectional view of a semiconductor device B3 according to an embodiment of the present disclosure. In the following, structures corresponding to those described above with respect to the semiconductor device B1 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0444] In the semiconductor device B3, the protective layer 508 includes a first protective layer 568 and a second protective layer 569. The first protective layer 568 is formed on the insulating principal surface 501 of the second insulating portion 507 so as to cover the high-potential coil 523, the first low-potential pad wiring 532, the first high-potential wiring 533, and the dummy pattern 539. The second protective layer 569 is laminated on the first protective layer 568.

[0445] First protective layer 568 and second protective layer 569 may be made of the same organic insulating layer or different types of organic insulating layers. For example, first protective layer 568 may contain at least one of polyimide, polyamide, and polybenzoxazole, and second protective layer 569 may be made of the same organic insulating material as first protective layer 568 or a different type of organic insulating material from first protective layer 568, among the organic insulating materials exemplified above.

[0446] Furthermore, the thicknesses of first protective layer 568 and second protective layer 569 may be the same as or different from each other. In this embodiment, it is preferable that the thickness of second protective layer 569 is greater than the thickness of first protective layer 568. By increasing the thickness of second protective layer 569, it is possible to deepen recessed portion 679, which will be described later, and therefore it is possible to further increase the creepage distance between high potential terminal 514 and low potential terminal 513. For example, the thickness of first protective layer 568 may be 1 μm or more and 100 μm or less, and the thickness of second protective layer 569 may be 1 μm or more and 100 μm or less.

[0447] A second low-potential pad wiring 676 and a high-potential pad wiring 677 are formed on the main surface of the first protective layer 568. The second low-potential pad wiring 676 and the high-potential pad wiring 677 are preferably formed from the same conductive material as the high-potential coil 523. In other words, the second low-potential pad wiring 676 and the high-potential pad wiring 677 preferably each include a barrier layer and a main body layer, similar to the high-potential coil 523, etc.

[0448] The second low potential pad wiring 676 is formed on the main surface of the first protective layer 568. That is, in this embodiment, the second low potential pad wiring 676 is formed in a layer above the high potential coil 523. Moreover, the second low potential pad wiring 676 is formed within the second protective layer 569 by being covered with the second protective layer 569. The second low potential pad wiring 676 may form the low potential terminal 513 described above. The second low potential pad wiring 676 is connected to the first low potential pad wiring 532 via a through hole 576 formed in the first protective layer 568.

[0449] The high-potential pad wiring 677 is formed on the main surface of the first protective layer 568. That is, in this embodiment, the high-potential pad wiring 677 is formed in a layer above the high-potential coil 523. Moreover, the high-potential pad wiring 677 is covered with the second protective layer 569, and thereby formed within the second protective layer 569. The high-potential pad wiring 677 may form the above-mentioned high-potential terminal 514. The high-potential pad wiring 677 is connected to the first high-potential wiring 533 via a through-hole 585 formed in the first protective layer 568.

[0450] The second low potential pad wiring 676 and the high potential pad wiring 677 may each be formed in an island shape, and like the first low potential pad wiring 532, may have an extraction portion (not shown) that is extracted from the through hole 576 and the through hole 585 to an area that does not overlap with the through hole 576 and the through hole 585.

[0451] The protective layer 508 has a plurality of low potential terminal openings 688 that expose the plurality of second low potential pad wirings 676 (low potential terminals 513). The low potential terminals 513 exposed from the low potential terminal openings 688 may be referred to as low potential pads 691.

[0452] The protective layer 508 also has a plurality of high potential terminal openings 689 that expose the plurality of high potential pad wirings 677 (high potential terminals 514). The high potential terminals 514 exposed from the high potential terminal openings 689 may be referred to as high potential pads 692. A coating layer containing at least one of palladium and nickel may be formed on the surface of the high potential pad 692.

[0453] Furthermore, the protective layer 508 has an uneven structure 678 in a region between the low potential terminal opening 688 and the high potential terminal opening 689. The uneven structure 678 includes a plurality of recesses 679 recessed from the protective principal surface 582 of the protective layer 508 toward the second insulating portion 507. The uneven structure 678 increases the creeping distance along the protective principal surface 582 of the protective layer 508. Therefore, the uneven structure 678 suppresses the occurrence of creeping discharge along the protective principal surface 582 of the protective layer 508. In this embodiment, the plurality of recesses 679 penetrate the second protective layer 569 and expose the principal surface of the first protective layer 568. The recesses 679 have side surfaces formed from the second protective layer 569 from the top to the bottom, and a bottom surface formed from the first protective layer 568. On the other hand, the plurality of recesses 679 may penetrate second protective layer 569, with their bottoms reaching partway through the thickness direction of first protective layer 568. In this case, the side surfaces of the plurality of recesses 679 may have an upper portion formed by second protective layer 569 and a lower portion formed by first protective layer 568. Although not shown, concave-convex structure 678 may be formed so as to surround high-potential coil 523 in plan view.

[0454] As described above, according to the semiconductor device B3, similarly to the semiconductor device B1, the second insulating section 507 made of the organic insulating layer 584 is formed between the low-potential coil 520 and the high-potential coil 523. Therefore, the withstand voltage between the low-potential coil 520 and the high-potential coil 523 can be achieved by thickening the second insulating section 507. As a result, the lead time can be shortened and costs can be reduced compared to when the first insulating section 550 is formed thicker.

[0455] Similarly to the semiconductor device B1, a first insulating section 550 made of a multi-layer insulating laminated structure including an interlayer insulating layer 557 is provided between the low-potential coil 520 and the semiconductor chip 540. This allows the first insulating section 550 to be used as a space for routing multi-layer wiring connected to the second functional device 560 when the first functional device 545 (transformer 515) and the second functional device 560 are mounted together. Furthermore, the first insulating section 550 made of an inorganic insulating layer has better flatness than the second insulating section 507 made of an organic insulating layer, and therefore the flatness of the multi-layer wiring structure on the semiconductor chip 540 can also be ensured satisfactorily.

[0456] Furthermore, an uneven structure 678 is formed on the protective layer 508. This increases the creeping distance along the protective principal surface 582 of the protective layer 508 between the high potential terminal 514 and the low potential terminal 513, and also increases the insulation distance between the high potential terminal 514 and the low potential terminal 513. This suppresses the occurrence of creeping discharge in the region between the high potential terminal 514 and the low potential terminal 513, thereby suppressing damage and deterioration of the protective layer 508 between the high potential terminal 514 and the low potential terminal 513. As a result, it is possible to suppress short-circuiting between the high potential terminal 514 and the low potential terminal 513, thereby suppressing further damage and deterioration of the protective layer 508 due to the occurrence of such short-circuiting.

[0457] In the above description, the seal conductor 516 is connected to the semiconductor chip 540 through the seal via conductor 565 and is fixed to the ground potential. On the other hand, as shown in Fig. 48, by omitting the seal via conductor 565, the seal conductor 516 does not need to be fixed to the ground potential. (Fourth embodiment) 49 is a schematic cross-sectional view of a semiconductor device B4 according to an embodiment of the present disclosure. In the following, structures corresponding to those described for the semiconductor devices B2 and B3 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0458] In the semiconductor device B4, the protective layer 508 of the semiconductor device B2, like the semiconductor device B3 described above, includes a first protective layer 568 and a second protective layer 569. In addition, the protective layer 508 has a concave-convex structure 678 in the region between the low potential terminal opening 690 and the high potential terminal opening 689.

[0459] As described above, according to the semiconductor device B4, similarly to the semiconductor device B1, the second insulating section 507 made of the organic insulating layer 584 is formed between the low-potential coil 520 and the high-potential coil 523. Therefore, the withstand voltage between the low-potential coil 520 and the high-potential coil 523 can be achieved by thickening the second insulating section 507. As a result, the lead time can be shortened and costs can be reduced compared to when the first insulating section 550 is formed thicker.

[0460] Similarly to the semiconductor device B1, a first insulating section 550 made of a multi-layer insulating laminated structure including an interlayer insulating layer 557 is provided between the low-potential coil 520 and the semiconductor chip 540. This allows the first insulating section 550 to be used as a space for routing multi-layer wiring connected to the second functional device 560 when the first functional device 545 (transformer 515) and the second functional device 560 are mounted together. Furthermore, the first insulating section 550 made of an inorganic insulating layer has better flatness than the second insulating section 507 made of an organic insulating layer, and therefore the flatness of the multi-layer wiring structure on the semiconductor chip 540 can also be ensured satisfactorily.

[0461] Furthermore, similar to the semiconductor device B2, the pillar-shaped wiring 538 and the first low-potential pad wiring 532 are not formed, and the bonding wire 71 is directly connected to the first wiring 579 (first low-potential wiring 530). Therefore, the steps of forming the pillar-shaped wiring 538 and the first low-potential pad wiring 532 can be omitted, and the lead time can be further shortened.

[0462] Furthermore, similar to the semiconductor device B3, an uneven structure 678 is formed on the protective layer 508. This increases the creeping distance along the protective principal surface 582 of the protective layer 508 between the high potential terminal 514 and the low potential terminal 513, and also increases the insulation distance between the high potential terminal 514 and the low potential terminal 513. This suppresses the occurrence of creeping discharge in the region between the high potential terminal 514 and the low potential terminal 513, thereby suppressing damage and deterioration of the protective layer 508 between the high potential terminal 514 and the low potential terminal 513. As a result, it is possible to suppress short-circuiting between the high potential terminal 514 and the low potential terminal 513, thereby suppressing further damage and deterioration of the protective layer 508 due to the occurrence of such short-circuiting.

[0463] In the above description, the seal conductor 516 is connected to the semiconductor chip 540 through the seal via conductor 565 and is fixed to the ground potential. However, as shown in Fig. 50, by omitting the seal via conductor 565, the seal conductor 516 does not need to be fixed to the ground potential. <Structure of semiconductor devices C1 to C4> (First embodiment) Fig. 51 is a schematic plan view of a semiconductor device C1 according to an embodiment of the present disclosure. Fig. 52 is a plan view showing a layer in which a low-potential coil 720 is formed in the semiconductor device C1 of Fig. 51. Fig. 53 is a plan view showing a layer in which a high-potential coil 723 is formed in the semiconductor device C1 of Fig. 51. Fig. 54 is a schematic cross-sectional view of the semiconductor device C1 of Fig. 51. Fig. 55 is an enlarged view of a main part of the semiconductor device C1 of Fig. 51.

[0464] 51 to 54, semiconductor device C1 includes a rectangular parallelepiped semiconductor chip 740. Semiconductor chip 740 includes at least one of silicon, a wide bandgap semiconductor, and a compound semiconductor.

[0465] The wide bandgap semiconductor is a semiconductor with a bandgap greater than that of silicon (approximately 1.12 eV). The bandgap of the wide bandgap semiconductor is preferably 2.0 eV or greater. The wide bandgap semiconductor may be silicon carbide (SiC). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0466] In this embodiment, the semiconductor chip 740 includes a silicon semiconductor substrate. The semiconductor chip 740 may be an epitaxial substrate having a layered structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type. The semiconductor chip 740 may also be fixed to ground potential.

[0467] The semiconductor chip 740 has a first main surface 741 on one side, a second main surface 742 on the other side, and chip sidewalls 744A to 744D connecting the first main surface 741 and the second main surface 742. The first main surface 741 and the second main surface 742 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0468] The chip sidewalls 744A to 744D include a first chip sidewall 744A, a second chip sidewall 744B, a third chip sidewall 744C, and a fourth chip sidewall 744D. The first chip sidewall 744A and the second chip sidewall 744B form the long sides of the semiconductor chip 740. The first chip sidewall 744A and the second chip sidewall 744B extend along the first direction X and face the second direction Y. The third chip sidewall 744C and the fourth chip sidewall 744D form the short sides of the semiconductor chip 740. The third chip sidewall 744C and the fourth chip sidewall 744D extend in the second direction Y and face the first direction X. The chip sidewalls 744A to 744D are composed of ground surfaces.

[0469] The semiconductor device C1 includes a first insulating portion 750, a second insulating portion 707, and a protective layer 708, which are formed in this order on a first main surface 741 of a semiconductor chip 740.

[0470] The first insulating portion 750 has an insulating main surface 754 and insulating side walls 753A to 753D. The insulating main surface 754 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first main surface 741 in a plan view. The insulating main surface 754 extends parallel to the first main surface 741.

[0471] The insulating sidewalls 753A-753D include a first insulating sidewall 753A, a second insulating sidewall 753B, a third insulating sidewall 753C, and a fourth insulating sidewall 753D. The insulating sidewalls 753A-753D extend from the periphery of the insulating main surface 754 toward the semiconductor chip 740 and are continuous with the chip sidewalls 744A-744D. Specifically, the insulating sidewalls 753A-753D are formed flush with the chip sidewalls 744A-744D. The insulating sidewalls 753A-753D form ground surfaces that are flush with the chip sidewalls 744A-744D.

[0472] The second insulating portion 707 is formed on the insulating principal surface 754 and has an insulating principal surface 704 and insulating side walls 705A to 705D. The insulating principal surface 704 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first principal surface 741 in a plan view. The insulating principal surface 704 extends parallel to the first principal surface 741.

[0473] The insulating side walls 705A to 705D include a first insulating side wall 705A, a second insulating side wall 705B, a third insulating side wall 705C, and a fourth insulating side wall 705D. The insulating side walls 705A to 705D extend from the periphery of the insulating main surface 704 toward the semiconductor chip 740. Specifically, the insulating side walls 705A to 705D are formed inside the insulating side walls 753A to 753D. This forms a step between the insulating side walls 705A to 705D and the insulating side walls 753A to 753D.

[0474] The protective layer 708 is formed on the insulating principal surface 704 and has a protective principal surface 782 and protective side walls 783A to 783D. The protective principal surface 782 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first principal surface 741 in a plan view. The protective principal surface 782 extends parallel to the first principal surface 741.

[0475] The protective sidewalls 783A-783D include a first protective sidewall 783A, a second protective sidewall 783B, a third protective sidewall 783C, and a fourth protective sidewall 783D. The protective sidewalls 783A-783D extend from the periphery of the protective main surface 782 toward the semiconductor chip 740. Specifically, the protective sidewalls 783A-783D are formed inside the insulating sidewalls 705A-705D. As a result, steps are formed between the protective sidewalls 783A-783D and the insulating sidewalls 705A-705D.

[0476] The first insulating section 750 has a multilayer insulating laminate structure including multiple organic insulating layers. In this embodiment, the first insulating section 750 includes a first organic insulating layer 755 and a second organic insulating layer 756. The second organic insulating layer 756 is a layer that forms the insulating main surface 754 and may be referred to as the uppermost organic insulating layer. On the other hand, the first organic insulating layer 755 is a layer that contacts the first main surface 741 of the semiconductor chip 740 and may be referred to as the lowermost organic insulating layer. Furthermore, one or more organic insulating layers may be interposed between the first organic insulating layer 755 (lowermost organic insulating layer) and the second organic insulating layer 756 (uppermost organic insulating layer).

[0477] First organic insulating layer 755 and second organic insulating layer 756 may be made of the same organic insulating layer or different types of organic insulating layers. For example, first organic insulating layer 755 may contain at least one of polyimide, polyamide, and polybenzoxazole, and second organic insulating layer 756 may be made of the same organic insulating material as first organic insulating layer 755 or a different type of organic insulating material from first organic insulating layer 755, among the organic insulating materials exemplified above.

[0478] Furthermore, the thicknesses of the first organic insulating layer 755 and the second organic insulating layer 756 may be the same or different. In this embodiment, the thickness of the second organic insulating layer 756 is preferably greater than the thickness of the first organic insulating layer 755. For example, the thickness of the first organic insulating layer 755 may be 0.5 μm or more and 30 μm or less, and the thickness of the second organic insulating layer 756 may be 0.5 μm or more and 30 μm or less. The total thickness TC1 of the first insulating section 750 may be 1 μm or more and 60 μm or less. The total thickness TC1 of the first insulating section 750 is arbitrary and is adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be achieved.

[0479] The second insulating section 707 has a layered structure including an organic insulating layer 784. In this embodiment, the second insulating section 707 is made of a single organic insulating layer 784, but may have a laminated structure of multiple organic insulating layers. Examples of the organic insulating layer 784 include a polyimide film, a phenolic resin film, and an epoxy resin film. The total thickness TC2 of the second insulating section 707 may be 2 μm or more and 100 μm or less. The total thickness TC2 of the second insulating section 707 is arbitrary and is adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be achieved.

[0480] The protective layer 708 protects the second insulating portion 707, the first insulating portion 750, and the semiconductor chip 740 from above the insulating main surface 704. The protective layer 708 may be made of an organic insulating layer or may contain a photosensi...

Claims

1. a semiconductor layer having a major surface; a first conductive layer formed on the major surface of the semiconductor layer; a first insulating portion formed on the main surface of the semiconductor layer so as to cover the first conductive layer, the first insulating portion including at least a silicon oxide film; a second insulating portion including a second insulating layer formed on the first insulating portion, having a dielectric constant different from that of the silicon oxide film, and not included in the first insulating portion; a second conductive layer formed on the second insulating portion, facing the first conductive layer with the first insulating portion and the second insulating portion interposed therebetween, and connected to a potential different from that of the first conductive layer; a first pad electrically connected to the first conductive layer; a second pad formed on the second insulating portion, the second conductive layer being positioned between the second pad and the first pad in a first direction parallel to the main surface of the semiconductor layer, and electrically connected to the second conductive layer; a first protective layer formed on the second insulating portion so as to cover the second conductive layer and at least a portion of the second pad; a second protective layer formed on the first protective layer so as to overlap a portion of the second pad and cover the first protective layer in a second direction perpendicular to the main surface of the semiconductor layer.

2. The semiconductor device according to claim 1 , wherein said first insulating portion includes a stack of a silicon nitride film and a silicon oxide film.

3. 3. The semiconductor device according to claim 1, wherein said first pad is formed on said second insulating portion.

4. 4. The semiconductor device according to claim 1, wherein the first protective layer and the second protective layer include an organic insulating layer.

5. The semiconductor device according to claim 4 , wherein the first protective layer and the second protective layer contain different organic insulating materials.

6. 5. The semiconductor device according to claim 4, wherein said organic insulating layer includes at least one of a polyimide film, a phenolic resin film, and an epoxy resin film.

7. 7. The semiconductor device according to claim 1, wherein the second protective layer is an organic insulating layer including at least one of a polyimide film, a phenolic resin film, and an epoxy resin film.

8. the first insulating portion has a thickness of 5 μm or more and 50 μm or less, 8. The semiconductor device according to claim 1, wherein the second insulating portion has a thickness of 2 μm or more and 100 μm or less.

9. 9. The semiconductor device according to claim 1, wherein the distance between said first pad and said second pad is greater than the sum of the thicknesses of said first insulating portion and said second insulating portion.

10. the first conductive layer includes a first coil; 10. The semiconductor device according to claim 1, wherein the second conductive layer includes a second coil.

11. a first current-carrying member connected to the first conductive layer and extending from the first conductive layer to a boundary between the first insulating portion and the second insulating portion; 11. The semiconductor device according to claim 1, further comprising: a second current-carrying member connected to said first current-carrying member and extending from said first current-carrying member onto said second insulating portion.

12. 12. The semiconductor device according to claim 11, wherein the first protective layer has a first opening that exposes a part of the second current-carrying member as the first pad.

13. The semiconductor device according to claim 11 , wherein the first current-carrying member is connected to a ground potential via the semiconductor layer.

14. 14. The semiconductor device according to claim 1, further comprising a seal conductor formed in said first insulating portion so as to surround said first conductive layer.

15. A die pad; The semiconductor device according to claim 10 mounted on the die pad; a package body that encapsulates the die pad and the semiconductor device; a lead terminal electrically connected to the semiconductor device and exposed from the package body.

16. the semiconductor device includes an insulating element for signal transmission that transmits a signal in an insulated state between the first coil and the second coil, The semiconductor module according to claim 15 , further comprising a second semiconductor device electrically connected to the isolation element.

17. 17. The semiconductor module according to claim 16, wherein the second semiconductor device includes a control element electrically connected to one of the first coil and the second coil, and a drive element electrically connected to the other of the first coil and the second coil.

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