Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device including a backside power delivery network (BSPDN) and a method for manufacturing the same.SOLUTION: A semiconductor device includes a substrate 10, an active pattern AP on the top surface of substrate 10, a gate structure intersecting with the active pattern AP on the active pattern AP, a source / drain pattern 160 connected to the active pattern AP on the side of the gate structure, an etch stop layer 172 extending along the upper surface of substrate 10 and the outer surface of source / drain pattern 160, a backside source / drain contact 190 penetrating the substrate 10 and connecting to the source / drain pattern 160, and BS, a backside wiring structure BS connected to the backside source / drain contact 190 on the underside of the substrate 10, and the backside source / drain contact 190 extends along at least a portion of the side of the source / drain pattern 160, and the topmost portion of the backside source / drain contact 190 contacts the etch stop layer 172.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] TECHNICAL FIELD The present invention relates to a semiconductor device including a back side power delivery network (BSPDN) and a method for manufacturing the same. [Background technology]

[0002] In the electronics industry, semiconductor devices have been gaining attention as important elements due to their characteristics such as miniaturization, multi-functionality, and / or low manufacturing costs. Semiconductor devices can be classified into semiconductor memory devices that store logical data, semiconductor logic devices that process logical data, and hybrid semiconductor devices that include both memory and logic elements.

[0003] As the electronics industry advances, the requirements for semiconductor device characteristics are also increasing. For example, there are increasing demands for semiconductor devices with higher reliability, higher speed, and / or more functionality. To meet these requirements, the structures within semiconductor devices are becoming increasingly complex and highly integrated.

[0004] As semiconductor devices become increasingly highly integrated, the widths of the wiring patterns and via patterns that implement the semiconductor devices are gradually decreasing, and as a result, voltage drops (e.g., IR drop) in power delivery networks (PDNs) that supply power voltages to integrated circuits are becoming a significant issue. Summary of the Invention [Problem to be solved by the invention]

[0005] The technical problem to be solved by the present invention is to provide a semiconductor device with improved PPAC (Power, Performance, Area, Cost).

[0006] Another technical problem to be solved by the present invention is to provide a method for manufacturing a semiconductor device with improved PPAC.

[0007] The technical problems of the present invention are not limited to those described above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0008] In order to achieve the above technical object, a semiconductor device according to some embodiments includes a substrate, an active pattern on an upper surface of the substrate, a gate structure on the active pattern and intersecting the active pattern, a source / drain pattern on a side surface of the gate structure and connected to the active pattern, an etching stopper film extending along the upper surface of the substrate and an outer surface of the source / drain pattern, backside source / drain contacts that penetrate the substrate and are connected to the source / drain pattern, and a backside wiring structure on a lower surface of the substrate and connected to the backside source / drain contacts, wherein the backside source / drain contacts extend along at least a portion of the side surface of the source / drain pattern, and a top of the backside source / drain contacts contacts the etching stopper film.

[0009] In order to achieve the above technical object, a semiconductor device according to some embodiments includes a substrate, an active pattern extending in a first direction on an upper surface of the substrate, a gate structure on the active pattern extending in a second direction intersecting the first direction, a source / drain pattern connected to the active pattern on a side surface of the gate structure, an etching stopper film extending along the upper surface of the substrate and an outer surface of the source / drain pattern, a backside wiring structure on a lower surface of the substrate, and a backside source / drain contact connecting the source / drain pattern to the backside wiring structure, wherein the backside source / drain contact includes a first pillar portion penetrating the substrate and contacting a lower surface of the source / drain pattern, and a first wrapping portion protruding from the upper surface of the first pillar portion and extending along at least a portion of a side surface of the source / drain pattern, and the first wrapping portion is in contact with the etching stopper film.

[0010] A semiconductor device according to some embodiments for achieving the above technical object includes a substrate, a plurality of bridge patterns stacked in order on an upper surface of the substrate and spaced apart from each other and extending in a first direction, a gate structure extending in a second direction intersecting the first direction and penetrated by the plurality of bridge patterns, a source / drain pattern on a side surface of the gate structure connected to the plurality of bridge patterns, an etching stop layer extending along the upper surface of the substrate, the side surface of the gate structure, and an outer surface of the source / drain pattern, a backside wiring structure on a lower surface of the substrate, and a backside source / drain contact connecting the source / drain pattern and the backside wiring structure. The source / drain pattern includes a first epitaxial layer and a second epitaxial layer sequentially stacked on the substrate and the plurality of bridge patterns, the impurity concentration of the second epitaxial layer being greater than the impurity concentration of the first epitaxial layer, the backside source / drain contacts include a first pillar portion that penetrates the substrate and contacts the lower surface of the source / drain pattern, and a first wrapping portion that protrudes from the upper surface of the first pillar portion, the first wrapping portion extending along a portion of the side surface of the second epitaxial layer, and the etching stop film extending from the upper surface of the first wrapping portion along another portion of the side surface of the second epitaxial layer.

[0011] Specific details of other embodiments are included in the detailed description and drawings. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is an exemplary layout diagram illustrating a semiconductor device according to some embodiments. [Figure 2] FIG. 2 is a schematic cross-sectional view taken along line AA in FIG. 1. [Figure 3] FIG. 2 is a schematic cross-sectional view taken along line BB in FIG. 1. [Figure 4] FIG. 2 is a schematic cross-sectional view taken along CC in FIG. 1. [Figure 5] FIG. 2 is a schematic cross-sectional view taken along line DD in FIG. 1. [Figure 6] FIG. 6 is an enlarged view for explaining the R1 region in FIG. 5. [Figure 7] 1A and 1B are diagrams illustrating semiconductor devices according to some embodiments. [Figure 8] 1A and 1B are diagrams illustrating semiconductor devices according to some embodiments. [Figure 9] 1A and 1B are diagrams illustrating semiconductor devices according to some embodiments. [Figure 10] 1A and 1B are diagrams illustrating semiconductor devices according to some embodiments. [Figure 11] 1A and 1B are diagrams illustrating semiconductor devices according to some embodiments. [Figure 12] 1A and 1B are diagrams illustrating semiconductor devices according to some embodiments. [Figure 13] 1A and 1B are diagrams illustrating semiconductor devices according to some embodiments. [Figure 14] 1A and 1B are diagrams illustrating semiconductor devices according to some embodiments. [Figure 15] 1A and 1B are diagrams illustrating semiconductor devices according to some embodiments. [Figure 16] 1A and 1B are diagrams illustrating semiconductor devices according to some embodiments. [Figure 17] 1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 18] 1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 19] 1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 20] 1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 21] 1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 22] 1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 23]1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 24] 1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 25] 1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 26] 1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 27] 1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 28] 1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 29] 1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 30] 1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 31] 1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 32] 1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 33] 1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 34] 1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 35] 1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 36] 1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 37] 1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 38]1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 39] 1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 40] 1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 41] 1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 42] 1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 43] 1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 44] 1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 45] 1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 46] 1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. [Figure 47] 1A-1C are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor device according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0013] In this specification, terms such as "first" and "second" are used to describe various elements or components, but these elements or components are not limited by these terms. These terms are used merely to distinguish one element or component from another. Therefore, a first element or component referred to below may of course be a second element or component within the technical concept of the present invention.

[0014] Furthermore, although only an MBCFET (registered trademark) including a multi-bridge channel is shown in this specification as an example of an electronic element included in a semiconductor device, this is merely an example. As other examples, the semiconductor device may include a tunneling transistor (TFT), a vertical FET (VFET), a complementary FET (CFET), or a three-dimensional (3D) transistor. Alternatively, the semiconductor device may include a bipolar junction transistor, a lateral double-diffused transistor (LDMOS), or the like.

[0015] Semiconductor devices according to exemplary embodiments will be described below with reference to FIGS.

[0016] Fig. 1 is an exemplary layout diagram for explaining a semiconductor device according to some embodiments. Fig. 2 is a schematic cross-sectional view taken along line AA in Fig. 1. Fig. 3 is a schematic cross-sectional view taken along line BB in Fig. 1. Fig. 4 is a schematic cross-sectional view taken along line CC in Fig. 1. Fig. 5 is a schematic cross-sectional view taken along line DD in Fig. 1. Fig. 6 is an enlarged view for explaining region R1 in Fig. 5.

[0017] 1 to 6, a semiconductor device according to some embodiments includes a substrate 10, an active pattern AP, a gate structure GS, a gate spacer 140, a gate capping film 150, a source / drain pattern 160, an etching stop film 172, a first interlayer insulating film 174, a second interlayer insulating film 210, a front source / drain contact 180, a front wiring structure FS, a backside source / drain contact 190, and a backside wiring structure BS.

[0018] Substrate 10 may include opposing top and bottom surfaces. In this specification, the top surface of substrate 10 may also be referred to as the frontside of substrate 10, and the bottom surface of substrate 10 may also be referred to as the backside of substrate 10.

[0019] In some embodiments, substrate 10 may comprise an insulating material. For example, substrate 10 may be an insulating substrate comprising at least one of silicon oxide, silicon oxynitride, silicon oxycarbonitride, or a combination thereof.

[0020] In some embodiments, the substrate 10 may include a plurality of base patterns 102 and a field insulating film 105 .

[0021] The base patterns 102 may extend side by side and be spaced apart from each other. For example, the base patterns 102 may each extend elongately in a first direction X and be spaced apart from each other in a second direction Y intersecting the first direction X. In some embodiments, each base pattern 102 may include an insulating material. For example, each base pattern 102 may include at least one of silicon oxide, silicon nitride, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, or a combination thereof, but is not limited thereto.

[0022] Each base pattern 102 may include a first surface 102a and a second surface 102b opposite to each other. The first surface 102a may be included on the front surface of the substrate 10, and the second surface 102b may be included on the back surface of the substrate 10.

[0023] The field insulating film 105 may cover at least a portion of a side surface of each base pattern 102. For example, the field insulating film 105 may fill a space between the base patterns 102 spaced apart along the second direction Y. The field insulating film 105 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, and combinations thereof, but is not limited thereto.

[0024] In some embodiments, the lower surface of the field insulating film 105 can be coplanar with the second surface 102b of each base pattern 102. Although the upper surface of the field insulating film 105 is shown to be higher than the first surface 102a of each base pattern 102 in Figures 3-5, this is merely an example. The upper surface of the field insulating film 105 may be coplanar with the first surface 102a or lower than the first surface 102a.

[0025] Also, although a boundary between the base pattern 102 and the field insulating film 105 is shown, this is merely an example. For example, if the base pattern 102 and the field insulating film 105 comprise the same material, the boundary between the base pattern 102 and the field insulating film 105 may not exist.

[0026] The active pattern AP is formed on the upper surface of the substrate 10. The active pattern AP may extend elongately in a first direction X. A plurality of active patterns AP may extend in the first direction X side by side.

[0027] In some embodiments, the active pattern AP may include a plurality of bridge patterns (e.g., first to fourth bridge patterns 111-114) stacked in sequence on the first surface 102a and spaced apart from one another. The first to fourth bridge patterns 111-114 may be spaced apart from one another in a third direction Z intersecting the first direction X and the second direction Y. Such an active pattern AP may be used as a channel region of an MBCFET (registered trademark) including a multi-bridge channel. The number of bridge patterns included in the active pattern AP is merely an example and is not limited to that shown in the figure.

[0028] The active pattern AP may include an elemental semiconductor material such as silicon (Si) or germanium (Ge). For example, the active pattern AP may include a silicon pattern. Alternatively, the active pattern AP may include a compound semiconductor, such as a IV-IV compound semiconductor or a III-V compound semiconductor. The IV-IV compound semiconductor may be, for example, a binary compound or a ternary compound containing at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound doped with a IV element. The III-V compound semiconductor may be, for example, a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of group III elements aluminum (Al), gallium (Ga), and indium (In) with at least one of group V elements phosphorus (P), arsenic (As), and antimony (Sb).

[0029] In some embodiments, a buffer pattern 104 may be formed between the substrate 10 and the active pattern AP. The buffer pattern 104 may extend in a first direction X along the first surface 102a. The first through fourth bridge patterns 111-114 are sequentially disposed on an upper surface of the buffer pattern 104. Although FIG. 3 shows that the upper surface of the field insulating film 105 is coplanar with the upper surface of the buffer pattern 104, this is merely an example. The upper surface of the field insulating film 105 may be lower than the upper surface of the buffer pattern 104.

[0030] The buffer pattern 104 may include a semiconductor material. For example, the buffer pattern 104 may include a silicon germanium (SiGe) layer. In some embodiments, the buffer pattern 104 may further include a high concentration of impurities. Such a buffer pattern 104 may prevent a punch-through phenomenon within the buffer pattern 104. For example, if the field-effect transistor formed on the buffer pattern 104 is an NFET, the buffer pattern 104 may include a high concentration of p-type impurities. The p-type impurities may include, for example, at least one of B, C, In, Ga, Al, and combinations thereof. For another example, if the field-effect transistor on the buffer pattern 104 is a PFET, the buffer pattern 104 may include a high concentration of n-type impurities. The n-type impurities may include, for example, at least one of P, Sb, As, and combinations thereof.

[0031] The gate structure GS is formed on the substrate 10 and the active pattern AP. The gate structure GS may intersect with the active pattern AP. For example, the gate structure GS may extend elongately in the second direction Y. A plurality of gate structures GS may extend side by side in the second direction Y.

[0032] In some embodiments, the active pattern AP may extend in the first direction X and penetrate the gate structure GS. For example, each of the first to fourth bridge patterns 111-114 may extend in the first direction X and penetrate the gate structure GS. The gate structure GS may surround each of the first to fourth bridge patterns 111-114.

[0033] The gate structure GS may include a gate dielectric layer 120 and a gate electrode 130. The gate dielectric layer 120 and the gate electrode 130 may be sequentially stacked on the active pattern AP.

[0034] The gate dielectric layer 120 is formed on the active pattern AP. For example, the gate dielectric layer 120 may conformally extend along the periphery of each of the first through fourth bridge patterns 111 through 114. The gate dielectric layer 120 may also extend along the top surface of the field insulating layer 105.

[0035] The gate dielectric layer 120 may include at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-k material having a higher dielectric constant than silicon oxide. Examples of the high-k material include hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), lanthanum aluminum oxide (LaAlO3), yttrium oxide (Y2O3), and hafnium oxynitride (HfO x N y ), zirconium oxynitride (ZrO x N y ), lanthanum oxynitride (LaO x N y ), aluminum oxynitride (AlO x N y ), titanium oxynitride (TiO x N y ), strontium titanium oxynitride (SrTiO x N y ), lanthanum aluminum oxynitride (LaAlO x N y ), yttrium oxynitride (YO x N y ) and combinations thereof, but are not limited thereto.

[0036] According to some embodiments, the semiconductor device may include a negative capacitance (NC) field effect transistor (FET) using a negative capacitor. For example, the gate dielectric layer 120 may include a ferroelectric material layer having ferroelectric properties and a paraelectric material layer having paraelectric properties.

[0037] The ferroelectric material layer may have a negative capacitance, and the paraelectric material layer may have a positive capacitance. For example, when two or more capacitors are connected in series and each capacitor has a positive capacitance, the total capacitance is smaller than the capacitance of each individual capacitor. Furthermore, when at least one of the two or more capacitors connected in series has a negative capacitance, the total capacitance may be positive but greater than the absolute value of each individual capacitance.

[0038] When the ferroelectric material layer having a negative capacitance and the paraelectric material layer having a positive capacitance are connected in series, the overall capacitance of the ferroelectric material layer and the paraelectric material layer connected in series can be increased. By utilizing the increased overall capacitance, a transistor including the ferroelectric material layer can have a subthreshold swing (SS) of less than about 60 mV / decade at room temperature.

[0039] The ferroelectric material layer may have ferroelectric properties. The ferroelectric material layer may include at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, for example, hafnium zirconium oxide may be hafnium oxide doped with zirconium (Zr). As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0040] The ferroelectric material film may further include a dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant included in the ferroelectric material film may vary depending on the ferroelectric material included in the ferroelectric material film.

[0041] When the ferroelectric material layer includes hafnium oxide, the dopant included in the ferroelectric material layer may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0042] When the dopant is aluminum (Al), the ferroelectric material film may contain about 3 at % to about 8 at % (atomic %) of aluminum, where the dopant ratio may be the ratio of aluminum to the total of hafnium and aluminum.

[0043] When the dopant is silicon (Si), the ferroelectric material film may contain about 2 at% to about 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material film may contain 2 at% to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may contain 1 at% to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may contain 50 at% to 80 at% zirconium.

[0044] The paraelectric material layer may have paraelectric properties and may include, for example, at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material layer may include, but is not limited to, at least one of hafnium oxide, zirconium oxide, and aluminum oxide.

[0045] The ferroelectric material film and the paraelectric material film may include the same material. The ferroelectric material film may have ferroelectric properties, while the paraelectric material film may not have ferroelectric properties. For example, if the ferroelectric material film and the paraelectric material film include hafnium oxide, the crystalline structure of the hafnium oxide contained in the ferroelectric material film may be different from the crystalline structure of the hafnium oxide contained in the paraelectric material film.

[0046] The ferroelectric material layer may have a thickness that allows it to have ferroelectric properties. The thickness of the ferroelectric material layer may be, for example, 0.5 nm to 10 nm, but is not limited thereto. Since the critical thickness at which ferroelectric properties are exhibited varies depending on the ferroelectric material, the thickness of the ferroelectric material layer may vary depending on the ferroelectric material.

[0047] For example, the gate dielectric layer 120 may include one ferroelectric material layer. For another example, the gate dielectric layer 120 may include a plurality of ferroelectric material layers spaced apart from each other. The gate dielectric layer 120 may have a stacked film structure in which a plurality of ferroelectric material layers and a plurality of paraelectric material layers are alternately stacked.

[0048] The gate electrode 130 is stacked on the gate dielectric layer 120. The gate dielectric layer 120 is interposed between the active pattern AP and the gate electrode 130. The gate electrode 130 is formed by, for example, but not limited to, a replacement process.

[0049] Although the gate electrode 130 is shown as a single layer, this is merely an example, and the gate electrode 130 may be formed by stacking multiple conductive layers. For example, the gate electrode 130 may include a work function adjustment layer that adjusts the work function and a filler conductive layer that fills the space formed by the work function adjustment layer. The work function adjustment layer may include, for example, at least one of TiN, TaN, TiC, TaC, TiAlC, and combinations thereof. The filler conductive layer may include, for example, W or Al.

[0050] The gate spacers 140 may extend in the second direction Y along the side surfaces of the gate electrode 130. In some embodiments, a portion of the gate dielectric film 120 may be interposed between the gate electrode 130 and the gate spacers 140. For example, the gate dielectric film 120 may further extend along the inner side surfaces of the gate spacers 140. Such a gate dielectric film 120 may be formed by, but is not limited to, a replacement process.

[0051] The gate spacer 140 may include, but is not limited to, at least one of an insulating material such as silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonitride, and combinations thereof. For example, the gate spacer 140 may include a silicon nitride film.

[0052] The gate capping layer 150 may extend in the second direction Y along the upper surface of the gate structure GS. Although the upper surface of the gate capping layer 150 is shown to be coplanar with the upper surface of the gate spacer 140, this is merely an example. As another example, the gate capping layer 150 may cover the upper surface of the gate spacer 140.

[0053] The gate capping layer 150 may include, but is not limited to, at least one of an insulating material such as silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonitride, and combinations thereof. For example, the gate capping layer 150 may include a silicon nitride layer.

[0054] The source / drain pattern 160 is formed on at least one side (e.g., both side) of the gate structure GS. The source / drain pattern 160 may be connected to the active pattern AP. For example, each of the first to fourth bridge patterns 111 to 114 may be connected to the source / drain pattern 160 through the gate structure GS. The source / drain pattern 160 may be separated from the gate electrode 130 by a gate dielectric layer 120 and / or a gate spacer 140. The source / drain pattern 160 may serve as a source / drain region of a field effect transistor including the active pattern AP and the gate structure GS.

[0055] In some embodiments, the source / drain pattern 160 may include an epitaxial layer. For example, the source / drain pattern 160 may be formed by an epitaxial growth process. As shown in FIGS. 4 and 5 , the cross section of the source / drain pattern 160 intersecting the first direction X may be hexagonal, but this is merely an example. It goes without saying that the cross section of the source / drain pattern 160 intersecting the first direction X may have various shapes, such as a pentagon or a rhombus, depending on the conditions of the epitaxial growth process.

[0056] In some embodiments, as shown in FIG. 6 , a cross section of the source / drain pattern 160 intersecting the first direction X may include a first side surface 160S1 and a second side surface 160S2. The first side surface 160S1 may extend from a lower surface 160B of the source / drain pattern 160. The first side surface 160S1 forms an obtuse angle with the lower surface 160B of the source / drain pattern 160. That is, the interior angle between the lower surface 160B of the source / drain pattern 160 and the first side surface 160S1 may be greater than 90°. The second side surface 160S2 may extend from an upper surface 160T of the source / drain pattern 160. The second side surface 160S2 forms an obtuse angle with the upper surface 160T of the source / drain pattern 160. That is, the interior angle between the upper surface 160T of the source / drain pattern 160 and the second side surface 160S2 may be greater than 90°.

[0057] When the source / drain pattern 160 is used as a source / drain region of an NFET, the source / drain pattern 160 may contain n-type impurities or impurities for preventing the diffusion of n-type impurities. For example, the source / drain pattern 160 may contain at least one of P, Sb, As, and combinations thereof.

[0058] In some embodiments, the source / drain patterns 160 may include a tensile stress material. For example, if the active patterns AP are silicon (Si) patterns, the source / drain patterns 160 may include a material having a smaller lattice constant than silicon (Si), such as silicon carbide (SiC). The tensile stress material may apply tensile stress to the active patterns AP to improve carrier mobility in the channel region.

[0059] When the source / drain pattern 160 is used as a source / drain region of a PFET, the source / drain pattern 160 may contain p-type impurities or impurities for preventing the diffusion of p-type impurities. For example, the source / drain pattern 160 may contain at least one of B, C, In, Ga, Al, and combinations thereof.

[0060] In some embodiments, the source / drain patterns 160 may include a compressive stress material. For example, if the active patterns AP are silicon patterns, the source / drain patterns 160 may include a material having a larger lattice constant than silicon (Si), such as silicon germanium (SiGe). The compressive stress material may apply compressive stress to the active patterns AP to improve carrier mobility in the channel region.

[0061] In some embodiments, a holder pattern 106 may be formed between the substrate 10 and the source / drain pattern 160. The holder pattern 106 may overlap the source / drain pattern 160 in the third direction Z. The lower surface of the holder pattern 106 may be lower than the lower surface of the buffer pattern 104. For example, as shown in FIG. 2, the lower portion of the holder pattern 106 may protrude from the lower surface of the buffer pattern 104 toward the base pattern 102. In FIGS. 4 and 5, the upper surface of the field insulating film 105 is shown to be coplanar with the upper surface of the holder pattern 106, but this is merely an example. The upper surface of the field insulating film 105 may be lower than the upper surface of the holder pattern 106.

[0062] The holder pattern 106 may include a semiconductor material. For example, the holder pattern 106 may include a silicon germanium (SiGe) layer. In some embodiments, the source / drain patterns 160 may be formed by an epitaxial growth process using the active pattern AP and the holder pattern 106 as a seed layer.

[0063] In some embodiments, the source / drain pattern 160 may include a first epitaxial layer 162 and a second epitaxial layer 164. The first epitaxial layer 162 and the second epitaxial layer 164 may be sequentially stacked on the holder pattern 106 and the active pattern AP. For example, the first epitaxial layer 162 may extend along the top surface of the holder pattern 106, the side surface of the gate spacer 140, and the side surfaces of each of the first to fourth bridge patterns 111 to 114. The second epitaxial layer 164 may be stacked on the first epitaxial layer 162. The first epitaxial layer 162 serves as a seed layer for growing the second epitaxial layer 164.

[0064] The second epitaxial layer 164 may have a higher impurity concentration than the first epitaxial layer 162. As an example, if the source / drain pattern 160 serves as a source / drain region of an NFET, the second epitaxial layer 164 may have a higher n-type impurity concentration than the first epitaxial layer 162. As another example, if the source / drain pattern 160 serves as a source / drain region of a PFET, the second epitaxial layer 164 may have a higher p-type impurity concentration than the first epitaxial layer 162.

[0065] The etch stop layer 172 is formed on the substrate 10, the gate structure GS, and the source / drain pattern 160. For example, the etch stop layer 172 may conformally extend along the profile of the top surface of the field insulating film 105, the side surface of the gate spacer 140, and the outer surface of the source / drain pattern 160.

[0066] The first interlayer insulating film 174 is formed on the etch stop layer 172. The first interlayer insulating film 174 is formed to fill the space above the etch stop layer 172. The second interlayer insulating film 210 is formed on the first interlayer insulating film 174. The second interlayer insulating film 210 is formed to cover the first interlayer insulating film 174 and the gate capping film 150.

[0067] The first interlayer insulating film 174 and the second interlayer insulating film 210 may each include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon carbonitride, silicon oxycarbonitride, and a low-k material having a dielectric constant lower than that of silicon oxide. The low dielectric constant material may include, but is not limited to, at least one of, for example, FOX (Flowable Oxide), TOSZ (Torene Silazene), USG (Undoped Silica Glass), BSG (Borosilica Glass), PSG (PhosphoSilica Glass), BPSG (BoroPhosphoSilica Glass), PETEOS (Plasma Enhanced Tetra Ethyl Orthosilicate), FSG (Fluoride Silicate Glass), CDO (Carbon Doped Silicon Oxide), Xerogel, Aerogel, Amorphous Fluorinated Carbon, OSG (Organo Silicate Glass), Parylene, BCB (bis-benzocyclobutenes), SiLK, polyimide, porous polymeric material, and combinations thereof.

[0068] The first interlayer insulating film 174 and the second interlayer insulating film 210 may have an etching selectivity with respect to the etch stop layer 172. As an example, when the first interlayer insulating film 174 and the second interlayer insulating film 210 each include a silicon oxide film, the etch stop layer 172 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof. The etch stop layer 172 may serve as an etch stop layer in an etching process for forming the front source / drain contacts 180. The front source / drain contacts 180 are formed on the source / drain patterns 160. The front source / drain contacts 180 may extend in the third direction Z to be connected to the source / drain patterns 160. For example, the front source / drain contacts 180 may pass through the second interlayer insulating layer 210, the first interlayer insulating layer 174, and the etch stop layer 172 in this order to directly contact the top of the source / drain patterns 160.

[0069] The width of the front source / drain contacts 180 may decrease toward the source / drain pattern 160. Here, the width refers to the width in a plane (e.g., an XY plane) intersecting the third direction Z. This is because the etching process for forming the front source / drain contacts 180 is performed toward the top surface of the source / drain pattern 160.

[0070] In some embodiments, the front source / drain contacts 180 may include a first silicide film 182 and a first metal film 184 sequentially stacked on the source / drain pattern 160 .

[0071] The first metal film 184 may include a conductive material, for example, a metal material such as cobalt (Co), titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), or cobalt tungsten phosphide (CoWP), but is not limited thereto.

[0072] The first silicide film 182 is interposed between the source / drain pattern 160 and the first metal film 184. The first silicide film 182 is formed when silicon (Si) contained in the source / drain pattern 160 reacts with a metal element (e.g., a metal element contained in the first metal film 184). The first silicide film 182 may include, but is not limited to, a metal silicide such as nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, niobium silicide, or tantalum silicide.

[0073] The front wiring structure FS is formed on the upper surface of the second interlayer insulating film 210. The front wiring structure FS may include a front inter-wire insulating film FID, multi-layer front wiring patterns FM1-FM3 in the front inter-wire insulating film FID, and front via patterns FV1-FV3 interconnecting the front wiring patterns FM1-FM3. The number of layers, number and arrangement of the front inter-wire insulating film FID, front wiring patterns FM1-FM3 and front via patterns FV1-FV3 are merely examples and are not limited to those shown in the figures.

[0074] The front wiring structure FS provides signal and / or power lines for various electronic elements (e.g., field effect transistors including active patterns AP and gate structures GS) formed on the front side of the substrate 10. For example, the first front via pattern FV1 of the front wiring structure FS may be connected to the front source / drain contact 180, thereby electrically connecting the front wiring structure FS to the source / drain pattern 160.

[0075] In some embodiments, a gate contact 185 may be formed on the gate structure GS. The gate contact 185 may be connected to the gate electrode 130 by sequentially passing through the second interlayer insulating film 210, the first interlayer insulating film 174, and the gate capping film 150. The gate contact 185 may connect the gate electrode 130 to the first front wiring pattern FM1. This allows the front wiring structure FS to be electrically connected to the gate electrode 130. Unlike the illustration, in some other embodiments, the gate contact 185 may also connect the gate electrode 130 to the first front via pattern FV1.

[0076] Although not specifically shown in the drawings, the front wiring patterns FM1-FM3 and the front via patterns FV1-FV3 may each include a barrier conductive film and a filling conductive film. The barrier conductive film may include a metal or metal nitride to prevent diffusion of the filling conductive film. The barrier conductive film may include, but is not limited to, at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), platinum (Pt), alloys thereof, and nitrides thereof. The filling conductive film may include, but is not limited to, at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru), and alloys thereof.

[0077] The backside source / drain contacts 190 are formed under the source / drain patterns 160. The backside source / drain contacts 190 may extend in the third direction Z to be connected to the source / drain patterns 160. For example, the backside source / drain contacts 190 may penetrate the substrate 10 and directly contact the bottom of the source / drain patterns 160.

[0078] The back surface source / drain contacts 190 may extend along at least a portion of a side surface of the source / drain pattern 160 intersecting the second direction Y. The top of the back surface source / drain contacts 190 may be in contact with the etching stop film 172. Specifically, the back surface source / drain contacts 190 may include a first pillar portion 190A and a first wrapping portion 190B.

[0079] The first pillar portion 190A may penetrate the substrate 10 and contact the lower surface 160B of the source / drain pattern 160. The width of the first pillar portion 190A may decrease toward the source / drain pattern 160. Here, the width refers to the width in a plane (e.g., the XY plane) intersecting the third direction Z. Although the width of the first pillar portion 190A is shown to be larger than the width of the base pattern 102, this is merely an example. The width of the first pillar portion 190A may be smaller than the width of the base pattern 102.

[0080] 5 and 6, the upper surface of the first pillar portion 190A, which contacts the lower surface 160B of the source / drain pattern 160, is shown to be higher than the top of the first epitaxial layer 162, but this is merely an example. The upper surface of the first pillar portion 190A may be coplanar with the top of the first epitaxial layer 162 or lower than the top of the first epitaxial layer 162. Unlike the illustrations, if the upper surface of the first pillar portion 190A is formed lower than the top of the first epitaxial layer 162, a portion of the first epitaxial layer 162 may be interposed between the first pillar portion 190A and the second epitaxial layer 164.

[0081] In some embodiments, the distance T11 from the top surface of the field insulating film 105 to the top surface of the first pillar 190A may be greater than the thickness T21 of the etch stop film 172 extending along the top surface of the field insulating film 105.

[0082] The first wrapping portion 190B may extend from the first pillar portion 190A. The first wrapping portion 190B may protrude above the top surface of the first pillar portion 190A. The first wrapping portion 190B may extend along at least a portion of a side surface of the source / drain pattern 160 that intersects with the second direction Y. The first wrapping portion 190B may contact at least a portion of a side surface of the source / drain pattern 160 that intersects with the second direction Y.

[0083] The upper surface of the first wrapping portion 190B may be in contact with the etch stop layer 172. For example, the first wrapping portion 190B may extend along a portion of the side surface of the source / drain pattern 160, and the etch stop layer 172 may extend from the upper surface of the first wrapping portion 190B along another portion of the side surface of the source / drain pattern 160.

[0084] In some embodiments, the first wrapping portion 190B may contact at least a portion of a side surface of the second epitaxial layer 164. For example, the first epitaxial layer 162 may not be interposed between the first wrapping portion 190B and the second epitaxial layer 164.

[0085] In some embodiments, the thickness T12 of the first wrapping portion 190B may be greater than the thickness T22 of the etch stop layer 172. For example, as shown in FIG. 6, a portion of the first wrapping portion 190B may protrude beyond the etch stop layer 172 toward the source / drain pattern 160. Alternatively, for example, as shown in FIG. 6, a portion of the first wrapping portion 190B may protrude beyond the etch stop layer 172 toward the first interlayer insulating film 174.

[0086] In some embodiments, the thickness T12 of the first wrapping portion 190B may be smaller than the distance T11 from the top surface of the field insulating film 105 to the top surface of the first pillar 190A.

[0087] 6 , the first wrapping portion 190B may extend along the first side surface 160S1 of the source / drain pattern 160. The first wrapping portion 190B may not extend along the second side surface 160S2 of the source / drain pattern 160. For example, the first wrapping portion 190B may contact the first side surface 160S1 of the source / drain pattern 160, and the etch stop layer 172 may contact the top surface 160T and the second side surface 160S2 of the source / drain pattern 160.

[0088] In some embodiments, the backside source / drain contacts 190 may include a second silicide film 192 and a second metal film 194 sequentially stacked on the source / drain pattern 160 .

[0089] The second metal film 194 may include a conductive material, for example, a metal material such as cobalt (Co), titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), or cobalt tungsten phosphide (CoWP), but is not limited thereto.

[0090] The second silicide film 192 is interposed between the source / drain pattern 160 and the second metal film 194. The second silicide film 192 is formed when silicon (Si) contained in the source / drain pattern 160 reacts with a metal element (e.g., a metal element contained in the second metal film 194). The second silicide film 192 may include, but is not limited to, a metal silicide such as nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, niobium silicide, or tantalum silicide.

[0091] In some embodiments, the second silicide film 192 may extend along the lower surface 160B and the first side surface 160S1 of the source / drain pattern 160.

[0092] The back surface wiring structure BS is formed on the lower surface of the substrate 10. The back surface wiring structure BS may include a back surface inter-wiring insulating film BID, multilayer back surface wiring patterns BM1 to BM3 in the back surface inter-wiring insulating film BID, and back surface via patterns BV1, BV2 interconnecting the back surface wiring patterns BM1 to BM3. The number of layers, the number and arrangement of the back surface inter-wiring insulating film BID, the back surface wiring patterns BM1 to BM3 and the back surface via patterns BV1, BV2 are merely examples and are not limited to those shown in the figures.

[0093] The backside wiring structure BS can provide a power delivery network (PDN) on the backside of the substrate 10 for various electronic devices formed on the frontside of the substrate 10. For example, the first backside wiring pattern BM1 of the backside wiring structure BS can be connected to the backside source / drain contacts 190. The backside wiring structure BS can be connected to an externally supplied power supply voltage (e.g., a source voltage V SS or drain voltage V DD ) can be provided to the source / drain pattern 160 via the back surface wiring patterns BM1 to BM3, the back surface via patterns BV1 and BV2, and the back surface source / drain contacts 190.

[0094] Although not specifically shown in the drawings, the backside wiring patterns BM1 to BM3 and the backside via patterns BV1 and BV2 may each include a barrier conductive film and a filling conductive film. The barrier conductive film may include a metal or metal nitride to prevent diffusion of the filling conductive film. The barrier conductive film may include, but is not limited to, at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), platinum (Pt), alloys thereof, and nitrides thereof. The filling conductive film may include, but is not limited to, at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru), and alloys thereof.

[0095] Semiconductor devices according to some embodiments may have a reduced voltage drop by providing a so-called backside power delivery network (BSPDN). For example, as described above, a backside wiring structure BS providing the power supply network PDN may be disposed on the bottom surface (or backside) of the substrate 10, where integrated circuits (e.g., field-effect transistors) are not disposed. This allows semiconductor devices according to some embodiments to have improved voltage drop and reduced size by minimizing routing crosstalk, compared to when the power supply network PDN is disposed on the top surface (or front side) of the substrate 10.

[0096] In addition, a contact that directly connects the backside power supply network BSPDN to the source / drain region (hereinafter referred to as backside direct contact) has been proposed for connecting the backside power supply network BSPDN to the integrated circuit. The backside direct contact is advantageous in terms of PPAC (Power, Performance, Area, Cost) because it can connect the backside power supply network BSPDN to the integrated circuit via the shortest path.

[0097] However, such a back surface direct contact has a problem in that it is formed from the bottom of the source / drain region, resulting in high contact resistance with the source / drain region. For example, the source / drain region may include a lower epitaxial layer (e.g., the first epitaxial layer 162) containing a low concentration of impurities and an upper epitaxial layer (e.g., the second epitaxial layer 164) containing a high concentration of impurities. However, the back surface direct contact has a relatively large contact area with the lower epitaxial layer, resulting in high contact resistance with the source / drain region.

[0098] In contrast, some embodiments of the semiconductor device have reduced contact resistance by using the backside source / drain contact 190 including the first wrapping portion 190B. Specifically, as described above, the first wrapping portion 190B of the backside source / drain contact 190 may protrude from the top surface of the first pillar portion 190A and contact at least a portion of the side surface of the source / drain pattern 160. The first wrapping portion 190B has a relatively large contact area with the second epitaxial layer 164, thereby forming low contact resistance with the source / drain pattern 160. This may provide a semiconductor device with improved PPAC.

[0099] 7 to 16 are various views illustrating semiconductor devices according to some embodiments. For convenience of explanation, parts that overlap with those described with reference to FIGS. 1 to 6 will be simplified or omitted.

[0100] 7, in a semiconductor device according to some embodiments, the backside source / drain contacts 190 completely cover the side surfaces of the source / drain patterns 160 intersecting with the second direction Y. For reference, FIG. 7 is another schematic cross-sectional view taken along line DD in FIG. 1.

[0101] For example, the first wrapping portion 190B may extend along a first side (160S1 in FIG. 6) and a second side (160S2 in FIG. 6) of the source / drain pattern 160. The first wrapping portion 190B may contact the first side (160S1 in FIG. 6) and the second side (160S2 in FIG. 6) of the source / drain pattern 160, and the etching stop layer 172 may contact a top surface (160T in FIG. 6) of the source / drain pattern 160.

[0102] In some embodiments, the second silicide film 192 may extend along the bottom surface (160B in FIG. 6), the first side surface (160S1 in FIG. 6) and the second side surface (160S2 in FIG. 6) of the source / drain pattern 160.

[0103] 8 to 10, in a semiconductor device according to some embodiments, the source / drain pattern 160 further includes a third epitaxial layer 166. For reference, FIG. 8 is another schematic cross-sectional view taken along line AA in FIG. 1, FIG. 9 is another schematic cross-sectional view taken along line DD in FIG. 1, and FIG. 10 is an enlarged view for explaining region R2 in FIG. 9.

[0104] The third epitaxial layer 166 is interposed between the first epitaxial layer 162 and the backside source / drain contact 190 and between the second epitaxial layer 164 and the backside source / drain contact 190. The backside source / drain contact 190 may be in contact with the third epitaxial layer 166. The third epitaxial layer 166 may be formed by an epitaxial growth process using the first epitaxial layer 162 and the second epitaxial layer 164 as seed layers.

[0105] In some embodiments, the third epitaxial layer 166 may have a higher impurity concentration than the first epitaxial layer 162. As an example, if the source / drain pattern 160 serves as a source / drain region of an NFET, the third epitaxial layer 166 may have a higher n-type impurity concentration than the first epitaxial layer 162. As another example, if the source / drain pattern 160 serves as a source / drain region of a PFET, the third epitaxial layer 166 may have a higher p-type impurity concentration than the first epitaxial layer 162.

[0106] 11 and 12, in a semiconductor device according to some embodiments, one source / drain pattern 160 is connected to both a front source / drain contact 180 and a back source / drain contact 190. For reference, FIG. 11 is another schematic cross-sectional view taken along line AA in FIG. 1, and FIG. 12 is another schematic cross-sectional view taken along line DD in FIG. 1.

[0107] For example, the front source / drain contact 180 may be in direct contact with the top of one of the source / drain patterns 160, and the back source / drain contact 190 may be in direct contact with the bottom of the one of the source / drain patterns 160. The front source / drain contact 180 and the back source / drain contact 190 may overlap in the third direction Z.

[0108] 13, in a semiconductor device according to some embodiments, the front side source / drain contact 180 includes a second pillar portion 180A and a second wrapping portion 180B. For reference, FIG. 13 is another schematic cross-sectional view taken along line DD in FIG.

[0109] The second pillar 180A may contact the top surface of the source / drain pattern 160 (160T in FIG. 6) by sequentially passing through the second interlayer insulating film 210, the first interlayer insulating film 174, and the etch stop film 172. The width of the second pillar 180A may decrease toward the source / drain pattern 160. Here, the width refers to the width in a plane (e.g., the XY plane) intersecting the third direction Z.

[0110] The second wrapping portion 180B may extend from the second pillar portion 180A. The second wrapping portion 180B may protrude below the lower surface of the second pillar portion 180A. The second wrapping portion 180B may extend along a portion of the side surface of the source / drain pattern 160 that intersects with the second direction Y. The second wrapping portion 180B may contact a portion of the side surface of the source / drain pattern 160 that intersects with the second direction Y.

[0111] Although the second wrapping portion 180B is shown separated from the first wrapping portion 190B by the etch stop layer 172, this is merely an example. Contrary to the illustration, the bottom of the second wrapping portion 180B may contact the top of the first wrapping portion 190B.

[0112] In some embodiments, the lower surface of the second wrapping portion 180B may be in contact with the etch stop layer 172. For example, the first wrapping portion 190B may extend along a portion of the side surface of the source / drain pattern 160, the etch stop layer 172 may extend from the upper surface of the first wrapping portion 190B along another portion of the side surface of the source / drain pattern 160, and the second wrapping portion 180B may extend from the upper surface of the etch stop layer 172 along another portion of the side surface of the source / drain pattern 160.

[0113] In some embodiments, the first wrapping portion 190B may contact the second epitaxial layer 164.

[0114] In some embodiments, the thickness of the second wrapping portion 180B may be greater than the thickness of the etch stop layer 172. For example, a portion of the second wrapping portion 180B may protrude beyond the etch stop layer 172 toward the source / drain pattern 160. Or, for example, a portion of the second wrapping portion 180B may protrude beyond the etch stop layer 172 toward the first interlayer insulating film 174.

[0115] In some embodiments, the second wrapping portion 180B may extend along the second side of the source / drain pattern 160 (160S2 in FIG. 6).

[0116] 14, in a semiconductor device according to some embodiments, the source / drain pattern 160 further includes a fourth epitaxial layer 168. For reference, FIG. 14 is another schematic cross-sectional view taken along line DD in FIG.

[0117] The fourth epitaxial layer 168 is interposed between the second epitaxial layer 164 and the front source / drain contacts 180. The front source / drain contacts 180 may contact the fourth epitaxial layer 168. The fourth epitaxial layer 168 may be formed by an epitaxial growth process using the second epitaxial layer 164 as a seed layer.

[0118] In some embodiments, the fourth epitaxial layer 168 may have a higher impurity concentration than the second epitaxial layer 164. As an example, if the source / drain pattern 160 serves as a source / drain region of an NFET, the fourth epitaxial layer 168 may have a higher n-type impurity concentration than the second epitaxial layer 164. As another example, if the source / drain pattern 160 serves as a source / drain region of a PFET, the fourth epitaxial layer 168 may have a higher p-type impurity concentration than the second epitaxial layer 164.

[0119] 15, a semiconductor device according to some embodiments further includes an isolation pattern 107. For reference, FIG. 15 is another schematic cross-sectional view taken along the line AA in FIG.

[0120] The isolation pattern 107 is formed between the backside wiring structure BS and the active pattern AP and / or between the backside wiring structure BS and the gate structure GS. The isolation pattern 107 may overlap the gate structure GS in the third direction Z.

[0121] The isolation pattern 107 may include an insulating material, such as, but not limited to, at least one of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonitride, and combinations thereof.

[0122] In some embodiments, the substrate 10 may include a fin pattern 101. The fin pattern 101 may extend in a first direction X. The fin pattern 101 may include an elemental semiconductor material such as silicon (Si) or germanium (Ge). As an example, the fin pattern 101 may include a silicon pattern. Alternatively, the fin pattern 101 may include a compound semiconductor, such as a IV-IV compound semiconductor or a III-V compound semiconductor.

[0123] In some embodiments, the backside source / drain contact 190 may include a flat portion 194a and a protruding portion 194b. The flat portion 194a may extend along the second surface 102b. The protruding portion 194b may protrude from the flat portion 194a to connect with the source / drain pattern 160. For example, the protruding portion 194b may protrude from the flat portion 194a in the third direction Z to penetrate the substrate 10.

[0124] The isolation pattern 107 cuts the substrate 10 and the backside source / drain contacts 190. For example, the isolation pattern 107 may extend elongately in the second direction Y to cut the fin pattern 101 and the flat portion 194b. In some embodiments, the isolation pattern 107 may contact the upper surface of the backside wiring structure BS and the lower surface of the gate structure GS. A plurality of isolation patterns 107 corresponding to a plurality of gate structures GS may extend side by side and spaced apart from each other. This may provide a plurality of backside source / drain contacts 190 that are isolated from each other.

[0125] 16, in a semiconductor device according to some embodiments, a source / drain pattern 160 further includes a stopper layer 161. For reference, FIG. 16 is another schematic cross-sectional view taken along the line AA in FIG.

[0126] A stopper layer 161 is formed between the substrate 10 and the first epitaxial layer 162. Backside source / drain contacts 190 may pass through the stopper layer 161 to contact the first epitaxial layer 162 and / or the second epitaxial layer 164.

[0127] The stopper layer 161 may include a semiconductor material or an insulating material. For example, the stopper layer 161 may include, but is not limited to, at least one of a silicon germanium (SiGe) layer, a silicon carbide (SiC) layer, a silicon nitride (SiN) layer, or a combination thereof. In some embodiments, the first epitaxial layer 162 may be formed by an epitaxial growth process using the active pattern AP and the stopper layer 161 as a seed layer.

[0128] In some embodiments, a liner layer 108 may be formed between the stopper layer 161 and the substrate 10. For example, the liner layer 108 may conformally extend along the profile of the lower surface of the gate structure GS, the lower surface of the gate spacer 140, and / or the lower surface of the stopper layer 161. The liner layer 108 may include an insulating material, such as, but not limited to, at least one of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonitride, and combinations thereof.

[0129] A method for manufacturing a semiconductor device according to an exemplary embodiment will be described below with reference to FIGS.

[0130] 17 to 43 are views illustrating intermediate stages of a method for manufacturing a semiconductor device according to some embodiments. For convenience of explanation, portions that overlap with the contents described with reference to FIGS. 1 to 14 will be briefly described or omitted.

[0131] 17 to 19, a fin structure FP, a field insulating film 105, a dummy gate DG, and a gate spacer 140 are formed on a base substrate 100. For reference, FIG. 18 is a schematic cross-sectional view taken along line AA in FIG. 17, and FIG. 19 is a schematic cross-sectional view taken along line BB in FIG. 17.

[0132] The base substrate 100 may be bulk silicon or silicon-on-insulator (SOI). Alternatively, the base substrate 100 may be a silicon substrate or may include other materials, such as, but not limited to, silicon germanium, silicon germanium on insulator (SOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. For convenience of explanation, the following description will be given assuming that the base substrate 100 is a silicon substrate.

[0133] The base substrate 100 may include a third surface 100a and a fourth surface 100b opposite to each other. In this specification, the third surface 100a is also referred to as the front side of the base substrate 100, and the fourth surface 100b is also referred to as the back side of the base substrate 100.

[0134] The fin structure FP is formed on the third surface 100a of the base substrate 100. The fin structure FP may extend elongately in the first direction X. A plurality of fin structures FP may extend in the first direction X side by side.

[0135] The fin structure FP may include a fin pattern 101, an active pattern AP and a sacrificial pattern 410.

[0136] The fin pattern 101 may protrude from the third surface 100a of the base substrate 100 and extend in the first direction X. The fin pattern 101 may be formed by etching a portion of the base substrate 100, or may be an epitaxial layer grown on the base substrate 100.

[0137] The active patterns AP and the sacrificial patterns 410 are alternately stacked on the top surface of the fin pattern 101. For example, the fin structure FP may include a plurality of bridge patterns (e.g., first to fourth bridge patterns 111 to 114) and a plurality of sacrificial patterns 410 that are alternately stacked. The first to fourth bridge patterns 111 to 114 may be spaced apart from each other in the third direction Z by the sacrificial patterns 410.

[0138] The sacrificial pattern 410 may have an etching selectivity with respect to the active pattern AP. As an example, if the active pattern AP includes a silicon (Si) layer, the sacrificial pattern 410 may include a silicon germanium (SiGe) layer.

[0139] In some embodiments, the fin structure FP may further include a buffer pattern 104. The buffer pattern 104 is interposed between the fin pattern 101 and the active pattern AP and / or between the fin pattern 101 and the sacrificial pattern 410.

[0140] The base substrate 100 and the fin pattern 101 may have an etching selectivity with respect to the buffer pattern 104. As an example, if the base substrate 100 and the fin pattern 101 each include a silicon (Si) layer, the buffer pattern 104 may include a silicon germanium (SiGe) layer.

[0141] The field insulating film 105 may cover at least a portion of the side surface of the fin pattern 101. For example, the field insulating film 105 may fill the space between the fin patterns 101 spaced apart in the second direction Y.

[0142] The dummy gate DG is formed on the field insulating film 105 and the fin structure FP. The dummy gate DG may intersect with the active pattern AP. For example, the dummy gate DG may extend longitudinally in the second direction Y. A plurality of dummy gates DG may extend side by side in the second direction Y. The dummy gate DG may have an etching selectivity with respect to the active pattern AP. As an example, the dummy gate DG may include polysilicon (poly Si).

[0143] The gate spacers 140 may extend in the second direction Y along the side surfaces of the dummy gates DG.

[0144] Referring to FIG. 20, source / drain recesses 160r are formed in the fin structure FP on the sides of the dummy gate DG.

[0145] For example, a first recess process may be performed on the active pattern AP and the sacrificial pattern 410 using the dummy gate DG and the gate spacer 140 as an etch mask. By performing the first recess process, a portion of the active pattern AP and a portion of the sacrificial pattern 410 may be removed, thereby forming the source / drain recesses 160r.

[0146] Referring to FIG. 21, a holder recess 106r is formed in the fin structure FP below the source / drain recess 160r.

[0147] For example, a second recess process may be performed on the buffer pattern 104 exposed by the source / drain recesses 160r. By performing the second recess process, a portion of the buffer pattern 104 may be removed to form a holder recess 106r. The holder recess 106r may overlap the source / drain recess 160r in the third direction Z.

[0148] In some embodiments, during the second recessing process, a portion of the fin pattern 101 may be removed. For example, the bottom surface of the holder recess 106r may be formed lower than the top surface of the fin pattern 101.

[0149] Referring to FIGS. 21 and 22, a holder pattern 106 is formed to fill the holder recess 106r.

[0150] For example, an epitaxial growth process may be performed using the fin pattern 101 and the buffer pattern 104 as seed layers. The base substrate 100 and the fin pattern 101 may have an etching selectivity with respect to the holder pattern 106. As an example, if the base substrate 100 and the fin pattern 101 each include a silicon (Si) layer, the holder pattern 106 may include a silicon germanium (SiGe) layer.

[0151] 22 and 23, a source / drain pattern 160 is formed to fill the source / drain recess 160r.

[0152] For example, an epitaxial growth process may be performed using the active pattern AP and the holder pattern 106 as a seed layer, thereby forming the source / drain pattern 160 connected to the active pattern AP. Also, the source / drain pattern 160 may overlap with the holder pattern 106 in the third direction Z.

[0153] In some embodiments, the source / drain pattern 160 may include a first epitaxial layer 162 and a second epitaxial layer 164 sequentially stacked on the active pattern AP and the holder pattern 106. The impurity concentration of the second epitaxial layer 164 may be higher than the impurity concentration of the first epitaxial layer 162.

[0154] Referring to FIG. 24, the sacrificial pattern 410 and the dummy gate DG are removed.

[0155] For example, an etch stop layer 172 and a first interlayer insulating film 174 may be sequentially formed on the dummy gate DG, the gate spacers 140, and the source / drain patterns 160. Next, a planarization process is performed on the etch stop layer 172 and the first interlayer insulating film 174 to expose the top surface of the dummy gate DG. Next, the exposed dummy gate DG is removed. As described above, the dummy gate DG may have an etch selectivity with respect to the active pattern AP, and therefore, can be selectively removed. Furthermore, the sacrificial pattern 410 is exposed by removing the dummy gate DG.

[0156] Next, the exposed sacrificial pattern 410 is removed. As described above, the sacrificial pattern 410 may have an etching selectivity with respect to the active pattern AP, and therefore may be selectively removed. As a result, the active pattern AP including the first to fourth bridge patterns 111 to 114 may be formed.

[0157] Referring to FIG. 25, a gate structure GS is formed.

[0158] For example, a gate dielectric layer 120 and a gate electrode 130 may be sequentially stacked on the active pattern AP, thereby forming a gate structure GS that replaces the dummy gate DG and intersects with the active pattern AP.

[0159] In some embodiments, the top of the gate structure GS may be recessed, and then a gate capping film 150 is formed on the top surface of the recessed gate structure GS.

[0160] Referring to FIG. 26, front side source / drain contacts 180 and front side wiring structures FS are formed.

[0161] For example, a second interlayer insulating film 210 may be formed to cover an upper surface of the first interlayer insulating film 174 and an upper surface of the gate capping film 150. Next, a front source / drain contact 180 may be formed to extend in the third direction Z and sequentially penetrate the second interlayer insulating film 210, the first interlayer insulating film 174, and the etch stop film 172. The front source / drain contact 180 may be in direct contact with the source / drain pattern 160.

[0162] In some embodiments, the front source / drain contacts 180 may include a first silicide film 182 and a first metal film 184 sequentially stacked on the source / drain pattern 160 .

[0163] Next, a front wiring structure FS is formed on the upper surface of the second interlayer insulating film 210 and the upper surface of the front source / drain contacts 180. The front wiring structure FS may be electrically connected to the front source / drain contacts 180.

[0164] 27 to 29, a front wiring structure FS is attached on a carrier substrate 500. For reference, FIG. 28 is a schematic cross-sectional view taken along line AA in FIG. 27, and FIG. 29 is a schematic cross-sectional view taken along line DD in FIG. 27.

[0165] For example, a carrier substrate 500 may be attached onto the resultant structure of Fig. 26. After the carrier substrate 500 is attached, the resultant structure of Fig. 26 is inverted, i.e., the fourth surface 100b of the base substrate 100 faces upward. In some embodiments, the front wiring structure FS may be attached onto the carrier substrate 500 by an oxide-oxide bonding process.

[0166] 30 and 31, the base substrate 100 and the fin pattern 101 are removed.

[0167] For example, a grinding process and / or an etching process may be performed on the base substrate 100 and the fin pattern 101. In the process of removing the base substrate 100 and the fin pattern 101, the buffer pattern 104 serves as an etch stop layer. Also, the base substrate 100 and the fin pattern 101 may be selectively removed with respect to the field insulating layer 105, the buffer pattern 104, and the holder pattern 106.

[0168] Referring to Figures 32 and 33, a plurality of base patterns 102 are formed.

[0169] The base patterns 102 fill the areas where the fin patterns 101 have been removed. In some embodiments, each base pattern 102 may include an insulating material, thereby providing a substrate 10 including an insulating material.

[0170] 34 and 35, a first contact hole TH1 is formed in the substrate 10.

[0171] For example, an etching process may be performed on at least a portion of the base pattern 102. The first contact hole TH1 may extend in the third direction Z and penetrate the substrate 10. In addition, the first contact hole TH1 may expose at least a portion of the plurality of holder patterns 106.

[0172] 36 and 37, a second contact hole TH2 is formed in the substrate 10 and the buffer pattern 104.

[0173] For example, the holder pattern 106 exposed by the first contact hole TH1 may be removed. The second contact hole TH2 may extend in the third direction Z and penetrate the substrate 10 and the buffer pattern 104. The second contact hole TH2 may also expose at least a portion of the source / drain patterns 160. In some embodiments, the second contact hole TH2 may expose an upper surface of the first epitaxial layer 162.

[0174] 38 and 39, a lapping recess 172e is formed in the etch stop layer 172. As shown in FIG.

[0175] For example, a third recess process may be performed on the etch stop layer 172 using the second contact hole TH2. By performing the third recess process, a portion of the etch stop layer 172 may be removed to form a lapping recess 172e. The lapping recess 172e may expose at least a portion of a side surface of the source / drain pattern 160. In some embodiments, the lapping recess 172e may expose at least a portion of a side surface of the second epitaxial layer 164.

[0176] In some embodiments, during the third recess process, a portion of the substrate 10, a portion of the source / drain pattern 160, and / or a portion of the first interlayer insulating film 174 may be removed. In this case, the width of the second contact hole TH2 may be greater than the width of the base pattern 102. Alternatively, the thickness of the lapping recess 172e may be greater than the thickness of the etch stop layer 172.

[0177] Referring to FIGS. 40 and 41, a third contact hole TH3 is formed.

[0178] For example, the source / drain patterns 160 exposed by the second contact holes TH2 may be further etched. The third contact holes TH3 may extend in the third direction Z and penetrate the substrate 10 and the buffer pattern 104. The third contact holes TH3 may also expose at least some of the source / drain patterns 160. In some embodiments, the third contact holes TH3 may expose at least some of the top surface of the second epitaxial layer 164.

[0179] Referring to Figures 42 and 43, backside source / drain contacts 190 are formed.

[0180] The backside source / drain contact 190 fills the third contact hole TH3 and the wrapping recess 172e, thereby providing the backside source / drain contact 190 including the first pillar portion 190A and the first wrapping portion 190B.

[0181] In some embodiments, the backside source / drain contacts 190 may include a second silicide film 192 and a second metal film 194 sequentially stacked on the source / drain pattern 160 .

[0182] 2 and 5, a backside wiring structure BS is formed on the backside of the substrate 10. This allows the semiconductor device described with reference to FIGS.

[0183] Although only the use of the holder pattern 106 to form the backside source / drain contacts 190 has been described, this is merely an example, and the holder pattern 106 may be omitted.

[0184] For example, as described with reference to Fig. 15, the backside source / drain contacts 190 may be formed using the isolation pattern 107. In this case, unlike the description with reference to Figs. 30 and 31, only a portion of the base substrate 100 and / or a portion of the fin pattern 101 may be removed.

[0185] Alternatively, for example, as described with reference to FIG. 16, the backside source / drain contacts 190 may be formed using the stopper layer 161. In this case, the stopper layer 161 can prevent the source / drain contacts 190 from being damaged during the process of removing the base substrate 100 and the fin pattern 101 (see FIGS. 30 and 31).

[0186] 44 to 47 are views illustrating intermediate stages for explaining a method for manufacturing a semiconductor device according to some embodiments. For convenience of explanation, portions that overlap with the contents explained with reference to FIGS. 1 to 43 will be briefly explained or omitted. For reference, FIGS. 44 and 45 are views illustrating intermediate stages for explaining the steps after FIGS. 40 and 41.

[0187] Referring to Figures 44 and 45, a third epitaxial layer 166 is formed.

[0188] For example, an epitaxial growth process may be performed using the first epitaxial layer 162 and the second epitaxial layer 164 exposed by the third contact hole TH3 and the lapping recess 172e as a seed layer. In some embodiments, the impurity concentration of the third epitaxial layer 166 may be greater than the impurity concentration of the first epitaxial layer 162.

[0189] 46 and 47, the rear surface source / drain contacts 190 are formed. The formation of the rear surface source / drain contacts 190 is similar to that described with reference to FIGS. 42 and 43, and therefore will not be described in detail below.

[0190] 8 and 9, a backside wiring structure BS is formed on the backside of the substrate 10. This allows the semiconductor device described with reference to FIGS. 8 to 10 to be manufactured.

[0191] Although the present invention has been described above with reference to the accompanying drawings, it should be understood that the present invention is not limited to the above-described embodiments and can be manufactured in various different forms, and that those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, the above-described embodiments should be understood to be illustrative in all respects and not limiting. [Explanation of symbols]

[0192] 10 Substrate 100 Base board 102 Bass Pattern 104 Buffer Patterns 105 Field insulating film 106 holder pattern 111~114 Bridge Pattern 120 Gate dielectric film 130 gate electrode 140 Gate spacer 150 Gate capping film 160 Source / Drain Pattern 162 First epitaxial layer 164 Second epitaxial layer 172 Etching stop film 174 First interlayer insulating film 180 front source / drain contacts 182 First silicide film 184 First metal film 190 Backside source / drain contact 190A First pillar section 190B 1st Wrapping Section 192 Second silicide film 194 Second metal film 210 Second interlayer insulating film AP activity pattern BM1~BM3 rear wiring pattern BS backside wiring structure BV1,BV2 Backside via pattern FM1~FM3 front wiring pattern FS front wiring structure FV1~FV3 Front via pattern GS Gate Structure

Claims

1. A substrate; an active pattern on a top surface of the substrate; a gate structure on the active pattern and intersecting the active pattern; a source / drain pattern connected to the active pattern on a side of the gate structure; an etch stop layer extending along an upper surface of the substrate and an outer surface of the source / drain pattern; a backside source / drain contact that penetrates the substrate and connects to the source / drain pattern; a backside wiring structure on the bottom surface of the substrate, the backside wiring structure being connected to the backside source / drain contacts; the backside source / drain contact extends along at least a portion of a side surface of the source / drain pattern; a top portion of the backside source / drain contact contacts the etch stop layer;

2. the source / drain pattern includes a first epitaxial layer and a second epitaxial layer sequentially stacked on the substrate and the active pattern; 2. The semiconductor device according to claim 1, wherein the impurity concentration of said second epitaxial layer is higher than the impurity concentration of said first epitaxial layer.

3. The semiconductor device of claim 2 , wherein the backside source / drain contacts contact the second epitaxial layer.

4. 2. The semiconductor device according to claim 1, wherein the backside source / drain contact includes a pillar portion that penetrates the substrate and contacts a lower surface of the source / drain pattern, and a wrapping portion that protrudes from an upper surface of the pillar portion and contacts at least a portion of a side surface of the source / drain pattern.

5. 2. The semiconductor device according to claim 1, wherein said backside source / drain contacts include a silicide film and a metal film sequentially stacked on said source / drain patterns.

6. an interlayer insulating film covering the etching stop film; a front surface source / drain contact penetrating the etching stop layer and the interlayer insulating film and connected to the source / drain pattern; 2. The semiconductor device according to claim 1, further comprising a front wiring structure on said interlayer insulating film, said front source / drain contacts being connected to said front wiring structure.

7. The semiconductor device according to claim 6 , wherein the front source / drain contact extends along another part of the side surface of the source / drain pattern.

8. The semiconductor device according to claim 1 , wherein said etching stop film further extends along a side surface of said gate structure.

9. A substrate; an active pattern on an upper surface of the substrate, the active pattern extending in a first direction; a gate structure on the active pattern, the gate structure extending in a second direction intersecting the first direction; a source / drain pattern connected to the active pattern on a side of the gate structure; an etch stop layer extending along an upper surface of the substrate and an outer surface of the source / drain pattern; a backside wiring structure on a bottom surface of the substrate; a backside source / drain contact connecting the source / drain pattern and the backside wiring structure; the backside source / drain contacts include a first pillar portion that penetrates the substrate and contacts a lower surface of the source / drain pattern, and a first wrapping portion that protrudes from an upper surface of the first pillar portion and extends along at least a portion of a side surface of the source / drain pattern; The first wrapping portion contacts the etching stop layer.

10. A substrate; a plurality of bridge patterns sequentially stacked on an upper surface of the substrate, spaced apart from each other and extending in a first direction; a gate structure extending in a second direction intersecting the first direction and penetrated by the plurality of bridge patterns; a source / drain pattern connected to the plurality of bridge patterns on a side of the gate structure; an etch stop layer extending along the top surface of the substrate, the side surfaces of the gate structure, and the outer surfaces of the source / drain pattern; a backside wiring structure on a bottom surface of the substrate; a backside source / drain contact connecting the source / drain pattern and the backside wiring structure; the source / drain pattern includes a first epitaxial layer and a second epitaxial layer sequentially stacked on the substrate and the plurality of bridge patterns; the impurity concentration of the second epitaxial layer is higher than the impurity concentration of the first epitaxial layer; the backside source / drain contact includes a first pillar portion that penetrates the substrate and contacts a lower surface of the source / drain pattern, and a first wrapping portion that protrudes from an upper surface of the first pillar portion; the first wrapping portion extends along a portion of a side surface of the second epitaxial layer; The etching stop film extends from the top surface of the first lapping portion along another part of the side surface of the second epitaxial layer.

Images