Semiconductor device

Abstract

To provide a semiconductor device including an electric field-effect transistor with improved electric characteristics and reliability.SOLUTION: The semiconductor device according to the present invention includes: a substrate including a plurality of active patterns AP1 and AP2; an element isolation film ST disposed between the active patterns AP1 and AP2; a stacked pattern STP disposed on the substrate; a power distribution network layer PDN disposed on a lower surface of the substrate; a first through-via TVI1 penetrating the stacked pattern; and a second through-via TVI2 disposed between the power distribution network layer and the first through via, the second through via penetrating the active patterns AP1 and AP2 and the element isolation film ST.SELECTED DRAWING: Figure 7B

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a field effect transistor. [Background technology]

[0002] The semiconductor device includes an integrated circuit configured with MOS field effect transistors (MOS (Metal Oxide Semiconductor) FETs). As the size and design rules of semiconductor devices continue to shrink, the scale down of MOS field effect transistors is also accelerating.

[0003] As the size of MOS field effect transistors decreases, the operating characteristics of the semiconductor device may deteriorate. Therefore, various researches are being conducted into semiconductor devices and methods for fabricating such devices that have superior performance while overcoming the limitations imposed by the high integration of semiconductor devices. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 11,728,347 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in view of the above-mentioned problems with conventional semiconductor devices, and an object of the present invention is to provide a semiconductor device with improved electrical characteristics and reliability. Another object of the present invention is to provide a method for manufacturing a semiconductor device with improved electrical characteristics and reliability. [Means for solving the problem]

[0006] The semiconductor device according to the present invention, which has been made to achieve the above-mentioned object, comprises a substrate including a plurality of active patterns, an isolation film disposed between the active patterns, a laminated pattern disposed on the substrate, a power transmission network layer disposed on a lower surface of the substrate, a first through via penetrating the laminated pattern, and a second through via disposed between the power transmission network layer and the first through via, wherein the second through via penetrates the active patterns and the isolation film.

[0007] In addition, a semiconductor device according to the present invention, which has been made to achieve the above-mentioned object, comprises a substrate including a logic cell and a tap cell adjacent to the logic cell; a plurality of metal wirings arranged on the substrate, wherein the metal wirings are spaced apart from each other in a first direction and each of the metal wirings extends in a second direction; and a power transmission network layer arranged on a lower surface of the substrate, wherein the tap cell includes through vias connecting some of the metal wirings to the power transmission network layer, the through vias including a first through via and a second through via that are in contact with each other, the second through via penetrating at least a portion of the substrate, and an interface between the first through via and the second through via is closer to the upper surface of the substrate than the lower surface of the substrate.

[0008] In addition, a semiconductor device according to an embodiment of the present invention includes logic cells and tap cells two-dimensionally arranged on a substrate, metal wiring and power wiring on the substrate, and a power transmission network layer on a lower surface of the substrate, each of the logic cells including a channel pattern on an active pattern, an isolation film between the active patterns, source / drain patterns between the channel patterns, and a gate electrode on the channel pattern, each of the tap cells including a through via connecting the metal wiring and the power transmission network layer, and a lower surface of the isolation film being flush with a lower surface of the active pattern. [Effects of the Invention]

[0009] According to the semiconductor device of the present invention, the substrate of the semiconductor device can be removed except for the active patterns by a planarization process. This allows the thickness of the substrate to be reduced. In addition, the first and second through vias of the through vias may be formed individually through different processes and may be formed to have similar heights. This prevents misalignment of the through via with adjacent vias and allows metal material to be easily formed without voids in the through via with a large aspect ratio. Therefore, the semiconductor device can be miniaturized and the electrical characteristics and reliability of the semiconductor device can be improved. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a diagram illustrating a schematic configuration of a semiconductor device according to an embodiment of the present invention; [Figure 2] 1 is a diagram illustrating a schematic configuration of a semiconductor device according to an embodiment of the present invention; [Figure 3] 1 is a diagram illustrating a schematic configuration of a semiconductor device according to an embodiment of the present invention; [Figure 4] 1 is a plan view illustrating a schematic configuration of a semiconductor device according to an embodiment of the present invention; [Figure 5A] FIG. 5 is a cross-sectional view taken along line AA' in FIG. [Figure 5B] FIG. 5 is a cross-sectional view taken along line BB' in FIG. [Figure 5C] FIG. 5 is a cross-sectional view taken along line CC' in FIG. [Figure 5D] FIG. 5 is a cross-sectional view taken along the line DD' in FIG. [Figure 6] 1 is a plan view illustrating a schematic configuration of a semiconductor device according to an embodiment of the present invention; [Figure 7A] FIG. 7 is a cross-sectional view for explaining the semiconductor device according to the embodiment of the present invention, taken along line EE' in FIG. 6. [Figure 7B] 7 is a cross-sectional view for explaining the semiconductor device according to the embodiment of the present invention, taken along line FF' in FIG. 6. FIG. [Figure 8A] FIG. 7 is a cross-sectional view for explaining the semiconductor device according to the embodiment of the present invention, taken along line EE' in FIG. 6. [Figure 8B] 7 is a cross-sectional view for explaining the semiconductor device according to the embodiment of the present invention, taken along line FF' in FIG. 6. FIG. [Figure 9A] FIG. 7 is a cross-sectional view for explaining the semiconductor device according to the embodiment of the present invention, taken along line EE' in FIG. 6. [Figure 9B] 7 is a cross-sectional view for explaining the semiconductor device according to the embodiment of the present invention, taken along line FF' in FIG. 6. FIG. [Figure 10] 1 is a plan view showing the layout relationship of tap cells of a semiconductor device according to an embodiment of the present invention; [Figure 11] 1 is a plan view showing the layout relationship of tap cells of a semiconductor device according to an embodiment of the present invention; [Figure 12A] 7 is a cross-sectional view taken along line EE' in FIG. 6, illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. [Figure 12B] 7 is a cross-sectional view taken along line FF' in FIG. 6, illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. [Figure 13A] 7 is a cross-sectional view taken along line EE' in FIG. 6, illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. [Figure 13B] 7 is a cross-sectional view taken along line FF' in FIG. 6, illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. [Figure 14A] 7 is a cross-sectional view taken along line EE' in FIG. 6, illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. [Figure 14B]7 is a cross-sectional view taken along line FF' in FIG. 6, illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. [Figure 15A] 7 is a cross-sectional view taken along line EE' in FIG. 6, illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. [Figure 15B] 7 is a cross-sectional view taken along line FF' in FIG. 6, illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. [Figure 16A] 7 is a cross-sectional view taken along line EE' in FIG. 6, illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. [Figure 16B] 7 is a cross-sectional view taken along line FF' in FIG. 6, illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0011] Next, specific examples of embodiments for carrying out the semiconductor device according to the present invention will be described with reference to the drawings. Like reference numerals refer to like elements throughout the specification.

[0012] 1 to 3 are diagrams illustrating a schematic configuration of a semiconductor device according to an embodiment of the present invention. Referring to FIG. 1, a Single Height Cell (SHC) is provided. On the substrate 100, a first power wiring (M1_R1) and a second power wiring (M1_R2) are provided. For example, the first power wiring (M1_R1) is a path through which a source voltage VSS or a ground voltage is provided. The second power wiring (M1_R2) is a path through which a drain voltage VDD or a power voltage is provided. A single height cell SHC is defined between the first power wiring (M1_R1) and the second power wiring (M1_R2).

[0013] The single height cell SHC includes a first active region AR1 and a second active region AR2. For example, one of the first active region AR1 and the second active region AR2 is a PMOSFET region. The remaining one of the first active region AR1 and the second active region AR2 is an NMOSFET region. More specifically, the single height cell SHC has a CMOS structure provided between a first power wiring (M1_R1) and a second power wiring (M1_R2). Each of the first active region AR1 and the second active region AR2 has a first width W1 in a first direction D1. The length of the single-height cell SHC in the first direction D1 is defined as a first height HE1. The first height HE1 is substantially the same as the distance (eg, pitch) between the first power wiring (M1_R1) and the second power wiring (M1_R2). The single height cell SHC constitutes one logic cell. As used herein, a logic cell refers to a logic element (eg, AND, OR, XOR, XNOR, inverter, etc.) that performs a specific function. That is, a logic cell includes transistors that form logic elements and wiring that connects the transistors to each other.

[0014] Referring to FIG. 2, a double height cell (DHC) is provided. A first power wiring (M1_R1), a second power wiring (M1_R2), and a third power wiring (M1_R3) are provided on the substrate 100. The second power wiring (M1_R2) is disposed between the first power wiring (M1_R1) and the third power wiring (M1_R3). For example, the third power wiring (M1_R3) is a path through which the source voltage VSS is provided. A double-height cell DHC is defined between the first power wiring (M1_R1) and the third power wiring (M1_R3). The double-height cell DHC includes two first active regions AR1 and two second active regions AR2. The first active region AR1 is adjacent to the first power wiring (M1_R1). Any one of the second active regions AR2 is adjacent to the second power wiring (M1_R2). Another one of the second active regions AR2 is adjacent to the third power wiring (M1_R3). In plan view, the first power wiring (M1_R1) is disposed between the two first active regions AR1.

[0015] The length of the double-height cell DHC in the first direction D1 is defined as a second height HE2. The second height HE2 is approximately twice the first height HE1 of FIG. For example, the first active regions AR1 of the double-height cell DHC are bundled together and operate as one PMOSFET region. Therefore, the channel size of the PMOS transistor of the double-height cell DHC is larger than the channel size of the PMOS transistor of the single-height cell SHC of FIG. For example, the channel size of the PMOS transistor of the double-height cell DHC may be approximately twice the channel size of the PMOS transistor of the single-height cell SHC. This allows the double-height cell DHC to operate at a higher speed than the single-height cell SHC. The double height cell DHC shown in FIG. 2 is defined herein as a multi-height cell. Although not shown in the figure, the multi-height cell may include a triple-height cell whose cell height is approximately three times that of the single-height cell SHC.

[0016] Referring to FIG. 3, a substrate 100 includes a first logic cell LC1, a second logic cell LC2, and a tap cell TC, which are arranged two-dimensionally. A first power wiring (M1_R1) and a second power wiring (M1_R2) are provided on the substrate 100. The first logic cell LC1, the second logic cell LC2, and the tap cell TC are arranged between the first power wiring (M1_R1) and the second power wiring (M1_R2). The first logic cell LC1 and the second logic cell LC2 are spaced apart from each other in the second direction D2. The tap cell TC is disposed between the first logic cell LC1 and the second logic cell LC2. For example, each of the first logic cell LC1 and the second logic cell LC2 is the single height cell SHC described with reference to FIG. An isolation structure DB is provided between the first logic cell LC1 and the tap cell TC, and between the second logic cell LC2 and the tap cell TC, respectively. The isolation structures DB are spaced apart from one another in the second direction D2, and each isolation structure DB extends in the first direction D1. The isolation structure DB electrically isolates the first logic cell LC1, the second logic cell LC2, and the first active region AR1 and the second active region AR2 of the tap cell TC.

[0017] The tap cell TC includes a through via TVI. The through vias TVI are connected to the power transmission network layer described later. For example, the tap cell TC is a cell for applying a voltage to the adjacent first logic cell LC1 and second logic cell LC2 from a power transmission network layer, which will be described later. Alternatively, the tap cell TC is a cell for transmitting a signal to the first logic cell LC1 and the second logic cell LC2. That is, unlike the first logic cell LC1 and the second logic cell LC2, the tap cell TC may not include a logic element. Furthermore, the tap cell TC can apply a voltage to the first logic cell LC1 and the second logic cell LC2 or transmit a signal, but can be a kind of dummy cell that does not perform any circuit function. This allows a voltage or signal to be quickly provided to the first and second logic cells (LC1, LC2) adjacent to the tap cell TC. Therefore, the electrical performance of the semiconductor device is improved. The arrangement of the first logic cell LC1, the second logic cell LC2, and the tap cell TC shown in FIG. 3 is an example, and various arrangements between the first logic cell LC1, the second logic cell LC2, and the tap cell TC can be provided. For example, at least one of the first logic cell LC1 and the second logic cell LC2 may be the multi-height cell described with reference to FIG. Also, multiple tap cells TC may be provided.

[0018] FIG. 4 is a plan view for explaining the schematic configuration of a semiconductor device according to an embodiment of the present invention, and FIGS. 5A to 5D are cross-sectional views taken along lines A-A', B-B', CC', and D-D' in FIG. 4, respectively. Referring to FIG. 4 and FIGS. 5A to 5D, a substrate 100 including a logic cell LC is provided. The logic cell LC is one of the first logic cell LC1 and the second logic cell LC2 described with reference to FIG. For example, the logic cell LC is the single height cell SHC described with reference to FIG.

[0019] Logic transistors that constitute a logic circuit are arranged on the logic cells LC. The substrate 100 may be a semiconductor substrate including silicon, germanium, silicon-germanium, etc., or may be a compound semiconductor substrate. For example, the substrate 100 is a silicon substrate. The substrate 100 includes a first active region AR1 and a second active region AR2. Each of the first and second active regions AR1 and AR2 extends in a second direction D2. For example, the first active region AR1 is an NMOSFET region, and the second active region AR2 is a PMOSFET region. The substrate 100 includes a first active pattern AP1 on the first active region AR1 and a second active pattern AP2 on the second active region AR2. The first and second active patterns AP1 and AP2 are defined by trenches TR formed in the substrate 100. The first and second active patterns AP1 and AP2 extend in a second direction D2.

[0020] According to an embodiment of the present invention, the remainder of the substrate 100 except for the first and second active patterns AP1 and AP2 is removed by a planarization process. As a result, only the first and second active patterns AP1 and AP2 of the substrate 100 remain. That is, the thickness of the first and second active patterns AP1 and AP2 is substantially the same as the thickness of the substrate 100. For example, the upper surface 100U of the substrate 100 corresponds to the upper surfaces of the first and second active patterns AP1 and AP2. The lower surface 100L of the substrate 100 corresponds to the lower surfaces of the first and second active patterns AP1 and AP2. Furthermore, since only the first and second active patterns AP1 and AP2 are left and the remainder of the substrate 100 is removed, the thickness of the substrate 100 is reduced. Therefore, the semiconductor device is miniaturized. An isolation layer ST is provided between the first and second active patterns AP1 and AP2. The element isolation film ST fills the trench TR. The lower surface STL of the isolation film ST is coplanar with the lower surfaces of the first and second active patterns AP1 and AP2. That is, the lower surface STL of the element isolation film ST is located at the same level as the lower surface 100L of the substrate 100. For example, the element isolation film ST includes a silicon oxide film. The isolation film ST does not cover first and second channel patterns CH1 and CH2, which will be described later.

[0021] A first channel pattern CH1 is provided on the first active pattern AP1. A second channel pattern CH2 is provided on the second active pattern AP2. Each of the first channel pattern CH1 and the second channel pattern CH2 includes a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 that are sequentially stacked. The first to third semiconductor patterns (SP1, SP2, SP3) are spaced apart from one another in the vertical direction (for example, the third direction D3). Each of the first to third semiconductor patterns (SP1, SP2, SP3) may include silicon (Si), germanium (Ge), or silicon germanium (SiGe). For example, each of the first to third semiconductor patterns (SP1, SP2, SP3) may include crystalline silicon, and more specifically, single-crystal silicon. Alternatively, the first to third semiconductor patterns (SP1, SP2, SP3) may be stacked nanosheets.

[0022] A plurality of first source / drain patterns SD1 are provided on the first active pattern AP1. A plurality of first recesses RS1 are formed on the first active patterns AP1. Each of the first source / drain patterns SD1 is provided in a first recess RS1. The first source / drain pattern SD1 is a first conductivity type (eg, n-type) impurity region. The first channel pattern CH1 is disposed between the first source / drain patterns SD1 adjacent to each other in the second direction D2. For example, the stacked first to third semiconductor patterns (SP1, SP2, SP3) of the first channel pattern CH1 connect the first source / drain patterns SD1 adjacent to each other in the second direction D2. A plurality of second source / drain patterns SD2 are provided on the second active pattern AP2. A plurality of second recesses RS2 are formed on the second active patterns AP2. Each of the second source / drain patterns SD2 is provided in a second recess RS2. The second source / drain pattern SD2 is a second conductivity type (eg, p-type) impurity region. The second channel pattern CH2 is disposed between the second source / drain patterns SD2 adjacent to each other in the second direction D2. For example, the stacked first to third semiconductor patterns (SP1, SP2, SP3) of the second channel pattern CH2 connect the second source / drain patterns SD2 adjacent to each other in the second direction D2.

[0023] The first and second source / drain patterns SD1 and SD2 are epitaxial patterns formed by a selective epitaxial growth (SEG) process. For example, the top surface of each of the first and second source / drain patterns SD1 and SD2 is higher than the top surface of the third semiconductor pattern SP3. Alternatively, the top surface of at least one of the first and second source / drain patterns SD1 and SD2 may be located at substantially the same level as the top surface of the third semiconductor pattern SP3. For example, the first source / drain pattern SD1 includes the same semiconductor element as the substrate 100 (eg, Si). The second source / drain pattern SD2 includes a semiconductor element (eg, SiGe) having a lattice constant greater than that of the semiconductor element (eg, Si) of the substrate 100. Accordingly, the second source / drain patterns SD2 adjacent to each other in the second direction D2 provide compressive stress to the second channel pattern CH2 therebetween. For example, the sidewalls of the second source / drain pattern SD2 have an embossed shape. That is, the sidewalls of the second source / drain pattern SD2 have a wave-shaped profile. The sidewalls of the second source / drain pattern SD2 protrude toward first to third inner electrodes PO1, PO2, and PO3 of the gate electrode GE, which will be described later.

[0024] A gate electrode GE is provided on the first and second channel patterns CH1 and CH2. Each of the gate electrodes GE crosses the first and second channel patterns CH1 and CH2 and extends in a first direction D1. Each gate electrode GE vertically overlaps the first and second channel patterns CH1 and CH2. The gate electrodes GE are spaced apart from each other in the second direction D2. Each of the gate electrodes GE includes a first inner electrode PO1 between the first and second active patterns (AP1, AP2) and the first semiconductor pattern SP1, a second inner electrode PO2 between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third inner electrode PO3 between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and an outer electrode PO4 on the third semiconductor pattern SP3. The gate electrodes GE are provided on the top surface, bottom surface and both sidewalls of each of the first to third semiconductor patterns (SP1, SP2, SP3). For example, the transistor of the present invention may be a three-dimensional field effect transistor (eg, MBCFET or GAAFET) in which the gate electrode GE three-dimensionally surrounds the channel.

[0025] On the first active region AR1, inner spacers ISP are provided between the first to third inner electrodes PO1, PO2, and PO3 of the gate electrode GE and the first source / drain pattern SD1. Each of the first to third inner electrodes PO1, PO2, and PO3 of the gate electrode GE is spaced apart from the first source / drain pattern SD1 by an inner spacer ISP. The inner spacer ISP can prevent leakage current from the gate electrode GE. A pair of gate spacers GS are provided on both side walls of the outer electrode PO4 of each gate electrode GE. The gate spacer GS extends in a first direction D1 along the gate electrode GE. For example, the gate spacer GS may include at least one of SiCN, SiCON, and SiN. Alternatively, the gate spacer GS may include a multi-layer made of at least two of SiCN, SiCON, and SiN. For example, the gate spacer GS includes a Si-containing insulating material. The gate spacer GS functions as an etching stop film when forming an active contact AC, which will be described later. The active contacts AC are formed in a self-aligned manner by the gate spacers GS.

[0026] On each of the gate electrodes GE, a gate capping pattern GP is provided. Each of the gate capping patterns GP extends in the first direction D1 along the gate electrode GE. The gate capping pattern GP includes a material having etching selectivity with respect to the first and second upper insulating layers 110 and 120 described below. For example, the gate capping pattern GP may include at least one of SiON, SiCN, SiCON, and SiN. A gate insulating film GI is provided between the gate electrode GE and the first channel pattern CH1 and between the gate electrode GE and the second channel pattern CH2. The gate insulating film GI covers the top surface, bottom surface, and both sidewalls of each of the first to third semiconductor patterns (SP1, SP2, SP3). The gate insulating film GI covers the upper surface of the element isolation film ST below the gate electrode GE. For example, the gate insulating film GI may include a silicon oxide film, a silicon oxynitride film, and / or a high-k film. Alternatively, the gate insulating film GI may have a structure in which a silicon oxide film and a high dielectric film are stacked.

[0027] The high dielectric film includes a high dielectric constant material having a higher dielectric constant than a silicon oxide film. By way of example, the high-k material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. According to one embodiment, the semiconductor device of the present invention may include a negative capacitance (NC) FET using a negative capacitor. For example, the gate insulating film GI includes a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0028] The ferroelectric material film has a negative capacitance, and the paraelectric material film has a positive capacitance. For example, if two or more capacitors are connected in series and the capacitance of each capacitor has a positive value, the total capacitance will be less than the capacitance of each individual capacitor. On the other hand, when at least one of the capacitances of two or more capacitors connected in series has a negative value, the total capacitance has a positive value and is greater than the absolute value of each individual capacitance. When a ferroelectric material film having a negative capacitance and a paraelectric material film having a positive capacitance are connected in series, the total capacitance value of the ferroelectric material film and the paraelectric material film connected in series increases. By taking advantage of the increased overall capacitance, a transistor including a ferroelectric material film has a subthreshold swing SS of less than 60 mV / decade at room temperature.

[0029] The ferroelectric material film has ferroelectric properties. For example, the ferroelectric material film may include at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. For example, hafnium zirconium oxide is a material in which hafnium oxide is doped with zirconium (Zr). Alternatively, hafnium zirconium oxide is a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0030] The ferroelectric material film further includes a dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant contained in the ferroelectric material layer varies depending on whether the ferroelectric material layer contains a predetermined ferroelectric material. When the ferroelectric material film includes hafnium oxide, the dopant included in the ferroelectric material film may include at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0031] When the dopant is aluminum (Al), the ferroelectric material film may contain about 3 at % to about 8 at % aluminum. Here, the dopant ratio is the ratio of aluminum to the sum of hafnium and aluminum. When the dopant is silicon (Si), the ferroelectric material film may contain about 2 at % to about 10 at % silicon. When the dopant is yttrium (Y), the ferroelectric material film may contain about 2 at % to about 10 at % of yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may contain about 1 at % to about 7 at % gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may contain about 50 at % to about 80 at % zirconium.

[0032] The paraelectric material film has paraelectric properties. For example, the paraelectric material film may include at least one of silicon oxide and metal oxide having a high dielectric constant. For example, the metal oxide contained in the paraelectric material film may include, but is not limited to, at least one of hafnium oxide, zirconium oxide, and aluminum oxide. The ferroelectric material film and the paraelectric material film may include the same material. A ferroelectric material film has ferroelectric properties, but a paraelectric material film does not necessarily have ferroelectric properties. When the ferroelectric material layer and the paraelectric material layer contain hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric material layer is different from the crystal structure of the hafnium oxide contained in the paraelectric material layer. The ferroelectric material film has a thickness that provides ferroelectric properties. For example, the thickness of the ferroelectric material film is about 0.5 nm to about 10 nm, but is not limited to this. Since the critical thickness at which ferroelectric properties are exhibited varies depending on the ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material. For example, the gate insulating film GI may include one ferroelectric material film. Alternatively, the gate insulating film GI may include a plurality of ferroelectric material films spaced apart from each other. The gate insulating film GI may have a laminated film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0033] A first upper insulating film 110 is provided on a substrate 100 . The first upper insulating film 110 covers the gate spacers GS and the first and second source / drain patterns SD1 and SD2. The upper surface of the first upper insulating film 110 is substantially coplanar with the upper surfaces of the gate capping patterns GP and the gate spacers GS, but is not limited thereto. A second upper insulating layer 120, a third upper insulating layer 130, and a fourth upper insulating layer 140 are sequentially formed on the first upper insulating layer 110. For example, the first to fourth upper insulating films (110, 120, 130, 140) include a silicon oxide film. A pair of isolation structures DB are provided on both sides of the logic cell LC, facing each other in the second direction D2. Each of the isolation structures DB extends parallel to the gate electrode GE in the first direction D1. Each of the isolation structures DB penetrates the first and second upper insulating layers 110 and 120 and extends into the first and second active patterns AP1 and AP2. The isolation structure DB penetrates a portion of each of the first and second active patterns (AP1, AP2). The isolation structure DB electrically isolates the logic cell LC from other adjacent cells (eg, logic cells and tap cells).

[0034] Active contacts AC are provided through the first and second upper insulating layers 110 and 120 and electrically connected to portions of the first and second source / drain patterns SD1 and SD2. In a plan view, each of the active contacts AC has a bar shape extending in the first direction D1. For example, each of the active contacts AC includes a conductive pattern and a barrier pattern surrounding the conductive pattern. The barrier pattern covers the sidewalls and bottom surface of the conductive pattern. A metal-semiconductor compound layer SC is provided between the active contact AC and the first source / drain pattern SD1 or the second source / drain pattern SD2. Each of the active contacts AC is electrically connected to the first and second source / drain patterns SD1 and SD2 through the metal-semiconductor compound layer SC. For example, the metal-semiconductor compound film SC may include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0035] A gate contact GC is provided through the second upper insulating layer 120 and the gate capping pattern GP to be electrically connected to the gate electrode GE. Each of the gate contacts GC includes a conductive pattern and a barrier pattern surrounding the conductive pattern. For example, the gate contact GC has substantially the same structure as the active contact AC. In a plan view, each of the gate contacts GC is disposed so as to overlap the first active region AR1 and the second active region AR2, respectively.

[0036] A first metal layer M1 is provided in the third upper insulating layer 130. For example, the first metal layer M1 includes a first power wiring (M1_R1), a second power wiring (M1_R2), and a first wiring (M1_I). The metal wirings (M1_R1, M1_R2, M1_I) of the first metal layer M1 extend parallel to each other in the second direction D2. The metal wirings (M1_R1, M1_R2, M1_I) of the first metal layer M1 are spaced apart from one another in the first direction D1. The first wiring (M1_I) of the first metal layer M1 is disposed between the first and second power wirings (M1_R1, M1_R2). The first wirings (M1_I) of the first metal layer M1 are spaced apart from each other in the first direction D1. The line width of each of the first wirings (M1_I) is smaller than the line width of each of the first and second power wirings (M1_R1, M1_R2). The first metal layer M1 further includes a first via VI1. The first via VI1 is provided below the metal wiring (M1_R1, M1_R2, M1_I) of the first metal layer M1. The active contact AC, the gate contact GC, and the metal wirings (M1_R1, M1_R2, M1_I) of the first metal layer M1 are electrically connected to each other through the first via VI1.

[0037] A second metal layer M2 is provided in the fourth upper insulating layer 140. The second metal layer M2 includes a plurality of second wirings (M2_I). Each of the second wirings (M2_I) of the second metal layer M2 has a line shape or a bar shape extending in the first direction D1. For example, the second wirings (M2_I) extend parallel to each other in the first direction D1. The second wirings (M2_I) are spaced apart from each other in the second direction D2. The second metal layer M2 includes second vias VI2 provided under each of the second wirings (M2_I). The metal wirings (M1_R1, M1_R2, M1_I) of the first metal layer M1 and the second wiring (M2_I) of the second metal layer M2 are electrically connected to each other through the second via VI2. For example, the second wiring (M2_I) of the second metal layer M2 and the second via VI2 thereunder are both formed in a dual damascene process.

[0038] On the lower surface 100L of the substrate 100, a power transmission network layer PDN is provided. The power transmission network layer PDN includes first and second lower insulating films (160, 170), first and second lower vias (LVI1, LVI2), and first and second lower wirings (LM1, LM2). The first and second lower vias (LV1, LV2) are electrically connected to the first and second lower wirings (LM1, LM2). The first lower via LV1 and the first lower wiring LM1 are disposed in the first lower insulating film 160. A second lower via LV2 and a second lower wiring LM2 are disposed in the second lower insulating film 170. For example, the first lower via LV1 is disposed on the first lower wiring LM1, and the second lower via LV2 is disposed on the second lower wiring LM2. An interlayer insulating film 150 is provided between the substrate 100 and the power transmission network layer PDN. The interlayer insulating film 150 contacts the lower surface 100L of the substrate 100 and the element isolation film ST. For example, the interlayer insulating film 150 and the first and second lower insulating films 160 and 170 include silicon oxide films.

[0039] A back contact BAC is provided that penetrates the interlayer insulating film 150 and the substrate 100 and extends to the first and second source / drain patterns SD1 and SD2. The back contact BAC is connected to a portion of the first and second source / drain patterns SD1 and SD2. The back contact BAC is connected to a first lower via LV1 of the power transmission network layer PDN. The back contact BAC is electrically connected to the first and second lower wirings (LM1, LM2) through the first lower via LV1.

[0040] Figure 6 is a plan view for explaining the schematic configuration of a semiconductor device according to an embodiment of the present invention, and Figures 7A to 9B are cross-sectional views for explaining a semiconductor device according to an embodiment of the present invention, with Figures 7A, 8A, and 9A being cross-sectional views taken along line E-E' in Figure 6, and Figures 7B, 8B, and 9B being cross-sectional views taken along line F-F' in Figure 6. For the sake of simplicity, the following description will omit the description of technical features that overlap with those described with reference to FIG. 4 and FIGS. 5A to 5D, and will focus on differences.

[0041] 6, 7A, and 7D, a substrate 100 including a tap cell TC is provided. The tap cell TC is substantially identical to the tap cell TC described with reference to FIG. It is possible that the logic transistors that constitute the logic circuit are not disposed on the tap cells TC. The substrate 100 includes a first active region AR1 and a second active region AR2. Each of the first and second active regions AR1 and AR2 extends in a second direction D2. For example, the first active region AR1 is an NMOSFET region, and the second active region AR2 is a PMOSFET region. The substrate 100 also includes a first active pattern AP1 on the first active region AR1 and a second active pattern AP2 on the second active region AR2.

[0042] An isolation layer ST is provided adjacent to the first and second active patterns AP1 and AP2. The isolation film ST is disposed on the side surfaces of the first and second active patterns AP1 and AP2. Also, the isolation layer ST is disposed between the first and second active patterns AP1 and AP2 as shown in FIG. 5D. The lower surface STL of the isolation film ST is coplanar with the lower surfaces of the first and second active patterns AP1 and AP2. That is, the lower surface STL of the element isolation film ST is located at the same level as the lower surface 100L of the substrate 100. For example, the element isolation film ST includes a silicon oxide film.

[0043] A stack pattern STP is provided on each of the first and second active patterns AP1 and AP2. Each of the stacked layers STP includes an active layer ACL and a sacrificial layer SAL. The active layers ACL and the sacrificial layers SAL are alternately stacked one on top of the other. For example, the active layers ACL are spaced apart from one another in the vertical direction, and the sacrificial layers SAL are spaced apart from one another in the vertical direction. The active layer ACL contains substantially the same material as the first to third semiconductor patterns (SP1, SP2, SP3) described with reference to FIGS. 5A to 5D. A sacrificial pattern PP is provided on the stack pattern STP. The sacrificial pattern PP covers the upper and side surfaces of the stacked pattern STP and the element isolation film ST. For example, the sacrificial pattern PP comprises polysilicon. A second upper insulating film 120 is provided on the sacrificial pattern PP.

[0044] According to an embodiment, the gate electrode GE described with reference to FIGS. 5A to 5D may be formed by removing the sacrificial layer SAL and the sacrificial pattern PP of the stack pattern STP. That is, since the sacrificial layer SAL and the sacrificial pattern PP remain in the tap cell TC, the gate electrode GE does not need to be provided. Within the tap cell TC, an isolation structure DB is provided. Each of the isolation structures DB extends in a first direction D1. The isolation structures DB are spaced apart from one another in the second direction D2. Each of the isolation structures DB extends through the second upper insulating film 120, the sacrificial pattern PP, and the stack pattern STP into the first and second active patterns AP1 and AP2. According to one embodiment, the centrally located one of the five separation structures DB can be omitted. According to other embodiments, only a pair of isolation structures DB may be provided on either side of the tap cell TC. That is, the isolation structure DB can be provided in various ways within the tap cell TC.

[0045] A through via TVI is provided, extending from the second upper insulating film 120 to the interlayer insulating film 150 on the lower surface 100L of the substrate 100. In plan view, the through via TVI is located at the center of the tap cell TC. The through vias TVI are disposed between the isolation structures DB. That is, the isolation structures DB are disposed on both sides of the through via TVI, but the present invention is not limited to this. The through vias TVI include a first through via TVI1 and a second through via TVI2 located below the first through via TVI1. The first through via TVI1 and the second through via TVI2 contact each other to form an interface TVIF. The first through via TVI1 extends toward the upper surface 100U of the substrate 100 through the second upper insulating film 120, the sacrificial pattern PP, and the stack pattern STP.

[0046] The first through via TVI1 penetrates a portion of the first and second active patterns AP1 and AP2. The first through via TVI1 penetrates a part of the isolation film ST between the first and second active patterns AP1 and AP2. For example, the bottom surface of the first through via TVI1 is located below the top surfaces of the first and second active patterns AP1 and AP2. That is, the bottom surface of the first through via TVI1 is lower than the upper surface 100U of the substrate 100. The first through via TVI1 has a width that decreases from the top to the bottom. For example, the first through via TVI1 has a width that decreases as it approaches the upper surface 100U of the substrate 100. The first through via TVI1 includes a first metal pattern MP1 and a first barrier pattern BP1 in contact with the first metal pattern MP1.

[0047] The first barrier pattern BP1 covers the bottom and side surfaces of the first metal pattern MP1. That is, the first barrier pattern BP1 extends from the side surface of the first metal pattern MP1 onto the bottom surface of the first metal pattern MP1. The first barrier pattern BP1 can prevent or reduce the diffusion of elements constituting the first metal pattern MP1. For example, the first metal pattern MP1 may include at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), and cobalt (Co). The first barrier pattern BP1 may be a metal film including at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), and platinum (Pt), or a metal nitride film including at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0048] The second through via TVI2 penetrates the interlayer insulating film 150 and extends toward the upper surface 100U of the substrate 100. The second through via TVI2 penetrates a portion of the first and second active patterns AP1 and AP2. In addition, the second through via TVI2 penetrates a part of the isolation film ST between the first and second active patterns AP1 and AP2. For example, the top surface of the second through via TVI2 is located below the top surface 100U of the substrate 100 (or the top surfaces of the first and second active patterns AP1 and AP2). Unlike the first through via TVI1, the second through via TVI2 has a width that increases from the top to the bottom. For example, the second through via TVI2 has a width that decreases as it approaches the upper surface 100U of the substrate 100. The second through via TVI2 and the first through via TVI1 contact each other within the substrate 100. As a result, the interface TVIF between the first through via TVI1 and the second through via TVI2 is located within the substrate 100. For example, an interface TVIF between the first through via TVI1 and the second through via TVI2 is adjacent to the upper surface 100U of the substrate 100 between the upper surface 100U and the lower surface 100L of the substrate 100.

[0049] The second through via TVI2 includes a second metal pattern MP2 and a second barrier pattern BP2 in contact with the second metal pattern MP2. The second barrier pattern BP2 covers the top and side surfaces of the second metal pattern MP2. That is, the second barrier pattern BP2 extends on the side surface of the second metal pattern MP2 and onto the top surface of the second metal pattern MP2. As a result, the second barrier pattern BP2 and the first barrier pattern BP1 are in contact with each other. For example, the first metal pattern MP1 and the second metal pattern MP2 are separated from each other by the first barrier pattern BP1 and the second barrier pattern BP2. The second metal pattern MP2 and the second barrier pattern BP2 may include substantially the same material as the first metal pattern MP1 and the first barrier pattern BP1, respectively, but are not limited thereto. For example, the first metal pattern MP1 and the second metal pattern MP2 may include different metal materials.

[0050] A first metal layer M1 is provided in the third upper insulating layer 130. A second metal layer M2 is provided in the fourth upper insulating layer 140. The first metal layer M1 includes a giant via GVI between the first wiring (M1_I) and the through via TVI. The giant via GVI connects the first wiring (M1_I) and the first through via TVI1. In this case, a signal is transmitted to a logic cell adjacent to the tap cell TC through a through via TVI. According to one embodiment, the giant via GVI is connected to at least one of the first and second power wirings (M1_R1, M1_R2) of the first metal layer M1. The giant via GVI connects at least one of the first and second power wirings (M1_R1, M1_R2) to the first through via TVI1. In this case, a voltage is applied to the logic cell adjacent to the tap cell TC through the through via TVI. Furthermore, the through via TVI is electrically connected to the first and second metal layers (M1, M2) through the giant via GVI. Therefore, a signal is transmitted or a voltage is applied to the logic cell adjacent to the tap cell TC through the through via TVI.

[0051] On the lower surface 100L of the substrate 100, a power transmission network layer PDN is provided. The first lower via LV1 of the power transmission network layer PDN is disposed between any one of the through via TVI and the first lower wiring LM1. The first lower via LV1 connects one of the first lower wirings LM1 to the second through via TVI2. Furthermore, the through via TVI is electrically connected to the power transmission network layer PDN through the first lower via LV1. For example, the through vias TVI electrically connect the power transmission network layer PDN to the first and second metal layers (M1, M2).

[0052] 6, 8A, and 8D, a first through via TVI1 of the through vias TVI includes a first metal pattern MP1 and a first barrier pattern BP1. The second through via TVI2 of the through vias TVI includes a second metal pattern MP2 and a second barrier pattern BP2. The first through via TVI1 extends toward the upper surface 100U of the substrate 100 through the second upper insulating film 120, the sacrificial pattern PP, and the stack pattern STP. The first through via TVI1 does not penetrate the first and second active patterns AP1 and AP2, and the isolation film ST between the first and second active patterns AP1 and AP2. For example, the bottom surface of the first through via TVI1 is located at substantially the same level as the top surfaces of the first and second active patterns AP1 and AP2. That is, the bottom surface of the first through via TVI1 is substantially coplanar with the upper surface 100U of the substrate 100. The first barrier pattern BP1 of the first through via TVI1 does not need to extend onto the bottom surface of the first metal pattern MP1. For example, the first barrier pattern BP1 may be provided only on the side surfaces of the first metal pattern MP1. The first barrier pattern BP1 may not be located between the first metal pattern MP1 and the second metal pattern MP2.

[0053] The second through via TVI2 penetrates the interlayer insulating film 150 and extends toward the upper surface 100U of the substrate 100. The second through via TVI2 penetrates the first and second active patterns AP1 and AP2. In addition, the second through via TVI2 penetrates the isolation film ST between the first and second active patterns AP1 and AP2. For example, the top surface of the second through via TVI2 is located on the same plane as the top surface 100U of the substrate 100 (or the top surfaces of the first and second active patterns AP1 and AP2). Unlike the first barrier pattern BP1, the second barrier pattern BP2 of the second through via TVI2 extends onto the top surface of the second metal pattern MP2. For example, the second barrier pattern BP2 is provided on the side and top surfaces of the second metal pattern MP2. The second barrier pattern BP2 is disposed between the first metal pattern MP1 and the second metal pattern MP2. The second barrier pattern BP2 contacts a part of the first metal pattern MP1. The first metal pattern MP1 and the second metal pattern MP2 are separated from each other by a second barrier pattern BP2. The first through via TVI1 and the second through via TVI2 contact each other at substantially the same level as the upper surface 100U of the substrate 100. As a result, the interface TVIF between the first through via TVI1 and the second through via TVI2 is coplanar with the upper surface 100U of the substrate 100.

[0054] Referring to FIGS. 6, 9A, and 9D, the first through via TVI1 includes a first metal pattern MP1 and a first barrier pattern BP1 on a side surface of the first metal pattern MP1. The second through via TVI2 includes a second metal pattern MP2 and a second barrier pattern BP2 on the side of the second metal pattern MP2. The first through via TVI1 extends toward the upper surface 100U of the substrate 100 through the second upper insulating film 120, the sacrificial pattern PP, and a part of the stack pattern STP. For example, the bottom surface of the first through via TVI1 is located within the stack pattern STP. That is, the bottom surface of the first through via TVI1 is higher than the upper surface 100U of the substrate 100. The second through via TVI2 penetrates the interlayer insulating film 150 and extends toward the upper surface 100U of the substrate 100. The second through via TVI2 penetrates the isolation film ST between the first and second active patterns AP1 and AP2. In addition, the second through via TVI2 penetrates the rest of the stack pattern STP. For example, the top surface of the second through via TVI2 is higher than the top surface 100U of the substrate 100 (or the top surfaces of the first and second active patterns (AP1, AP2)).

[0055] The first barrier pattern BP1 of the first through via TVI1 does not need to extend onto the bottom surface of the first metal pattern MP1. Also, the second barrier pattern BP2 of the second through via TVI2 does not have to extend onto the top surface of the second metal pattern MP2. For example, the first barrier pattern BP1 is provided only on the side surfaces of the first metal pattern MP1, and the second barrier pattern BP2 is provided only on the side surfaces of the second metal pattern MP2. That is, the first barrier pattern BP1 and / or the second barrier pattern BP2 may not be located between the first metal pattern MP1 and the second metal pattern MP2. This allows the first metal pattern MP1 and the second metal pattern MP2 to come into contact with each other. The first through via TVI1 and the second through via TVI2 contact each other at a level higher than the upper surface 100U of the substrate 100. As a result, the interface TVIF between the first through via TVI1 and the second through via TVI2 is higher than the upper surface 100U of the substrate 100. For example, the interface TVIF between the first through via TVI1 and the second through via TVI2 is located within the stack pattern STP.

[0056] Referring again to Figures 6 and 7A to 9D, the first through via TVI1 and the giant via GVI are formed on the upper surface 100U of the substrate 100, and the second through via TVI2 and the first lower via LV1 are formed on the lower surface 100L of the substrate 100. For example, after the first through via TVI1 is formed, the second through via TVI2 is formed and they contact each other. That is, the first through via TVI1 and the second through via TVI2 of the through via TVI can be formed individually through different processes. This can prevent the through via TVI from being misaligned with the giant via GVI and / or the first lower via LV1. Furthermore, the difference between the height of the first through via TVI1 in the third direction D3 and the height of the second through via TVI2 in the third direction D3 is small. For example, the height of the first through via TVI1 is about 0.5 to about 2.0 times the height of the second through via TVI2. An interface TVIF between the first through via TVI1 and the second through via TVI2 is disposed so as to be closer to the upper surface 100U of the substrate 100 than to the lower surface 100L. Since the first and second through vias TVI1 and TVI2 are formed to have the same height, a metal material can be easily formed without voids in the through via TVI having a large aspect ratio. Therefore, the electrical characteristics and reliability of the semiconductor device are improved.

[0057] 10 and 11 are plan views showing the layout relationship of tap cells in a semiconductor device according to an embodiment of the present invention. Referring to FIG. 10, a semiconductor device according to an embodiment of the present invention is manufactured based on a designed layout. For example, a layout design tool is used to generate a layout of a semiconductor device. First and second power wirings (M1_R1, M1_R2) are placed on the layout. For example, the first power wiring (M1_R1) defines a path for the drain voltage VDD, and the second power wiring (M1_R2) defines a path for the source voltage VSS. The first and second power wirings (M1_R1, M1_R2) are alternately arranged at a constant pitch along the first direction D1. Each of the first and second power wirings (M1_R1, M1_R2) extends along the second direction D2.

[0058] A logic cell LC, a tap cell TC, and a filler cell FC are provided between the first and second power wirings (M1_R1, M1_R2). The logic cells LC include at least one single-height cell SHC, at least one double-height cell DHC, and at least one triple-height cell THC. The single height cell SHC is substantially the same as that described with reference to FIG. The double height cell DHC and triple height cell THC are substantially the same as those described with reference to FIG. The tap cells TC are arranged apart from the logic cells LC. Each of the tap cells TC is substantially the same as that described with reference to FIG. 6 and FIGS. 7A to 9D. It is also possible that at least one of the tap cells TC is not located between the logic cells LC. It is also possible that at least one of the logic cells LC is not located between the tap cells TC. For example, the tap cells TC may be placed on the remaining area where the logic cells LC are not placed. Each of the filler cells FC is disposed between adjacent logic cells LC. The filler cells FC fill the empty spaces between the logic cells LC. For example, the filler cell FC may be a dummy cell.

[0059] Referring to FIG. 11, first and second power wirings (M1_R1, M1_R2) are arranged on the layout. The first and second power wirings (M1_R1, M1_R2) are arranged at a constant pitch in the first direction D1. Each of the first and second power wirings (M1_R1, M1_R2) extends along the second direction D2. Between the first and second power wirings (M1_R1, M1_R2), a manual element cell and a tap cell TC are provided. The manual element cells include a first manual element cell PC1 and a second manual element cell PC2. The first and second manual element cells PC1 and PC2 are spaced apart from each other in a second direction D2. An isolation structure DB is provided on either side of each of the first and second manual component cells (PC1, PC2). Each of the first and second manual element cells (PC1, PC2) includes a gate electrode GE, an active area AR, and an active contact AC. Each of the first and second manual component cells (PC1, PC2) includes a three-dimensional field effect transistor having a longer channel length than that described with reference to Figures 5A-5D. The tap cell TC is disposed between the first and second manual element cells (PC1, PC2). The tap cell TC is substantially the same as that described with reference to FIG. 6 and FIGS. 7A to 9D. For example, the tap cell TC transmits a signal or applies a voltage to the first and second adjacent manual element cells (PC1, PC2).

[0060] Figures 12A to 16B are figures for explaining a manufacturing method of a semiconductor device according to an embodiment of the present invention, where Figures 12A, 13A, 14A, 15A, and 16A are cross-sectional views taken along line E-E' in Figure 6, and Figures 12B, 13B, 14B, 15B, and 16B are cross-sectional views taken along line F-F'. Referring to Figures 12A and 12B, a substrate 100 including first and second active regions (AR1, AR2) is provided.

[0061] Active layers ACL and sacrificial layers SAL are alternately stacked on the upper surface 100U of the substrate 100. The active layer ACL includes one of silicon (Si), germanium (Ge), and silicon germanium (SiGe), and the sacrificial layer SAL includes another one of silicon (Si), germanium (Ge), and silicon germanium (SiGe). The sacrificial layer SAL includes a material that has an etching selectivity with respect to the active layer ACL. For example, the active layer ACL includes silicon (Si), and the sacrificial layer SAL includes silicon germanium (SiGe). The concentration of germanium (Ge) in each sacrificial layer SAL can be about 10 at % to about 30 at %.

[0062] Mask patterns are formed on the first and second active regions AR1 and AR2 of the substrate 100, respectively. Each of the mask patterns has a line shape or a bar shape extending in the second direction D2. An etching process using the mask pattern is performed to form trenches TR that define the first and second active patterns AP1 and AP2. The first active pattern AP1 is formed on the first active region AR1. The second active pattern AP2 is formed on the second active region AR2. In a plan view, the first and second active patterns AP1 and AP2 have line shapes extending parallel to each other in the second direction D2. A stack pattern STP is formed on each of the first and second active patterns AP1 and AP2. Each of the stacked layers STP includes active layers ACL and sacrificial layers SAL alternately stacked with each other. For example, the stack pattern STP is formed by the etching process that forms the first and second active patterns AP1 and AP2.

[0063] Thereafter, an isolation film ST is formed to fill the trench TR. For example, an insulating film is formed on the upper surface 100U of the substrate 100 to cover the first and second active patterns AP1 and AP2 and the stack pattern STP, and the insulating film is recessed to form the isolation film ST. The stack pattern STP is exposed on the element isolation film ST. More specifically, the stack pattern STP protrudes vertically onto the isolation film ST. The isolation layer ST includes an insulating material such as a silicon oxide layer.

[0064] 13A and 13B, a sacrificial pattern PP is formed on a substrate 100 to cover a stack pattern STP. The sacrificial pattern PP covers the top and side surfaces of the stack pattern STP. The sacrificial pattern PP is in contact with the element isolation film ST. A second upper insulating film 120 is formed on the sacrificial pattern PP. The second upper insulating film 120 includes a silicon oxide film. Thereafter, an isolation structure DB is formed which penetrates the second upper insulating film 120, the sacrificial pattern PP, and the stack pattern STP. The isolation structure DB extends from the second upper insulating layer 120 through the stack pattern STP to the first active pattern AP1. The isolation structure DB includes an insulating material such as silicon oxide or silicon nitride.

[0065] In the case of the logic cell LC described with reference to FIGS. 4 and 5A to 5D, the sacrificial pattern PP is formed in a line shape or a bar shape extending in the first direction D1. The sacrificial pattern PP is used to form the first and second recesses RS1 and RS2 of FIGS. 5A and 5B, and the first and second source / drain patterns SD1 and SD2 are formed in the first and second recesses RS1 and RS2, respectively. Thereafter, the sacrificial pattern PP and the sacrificial layer SAL are selectively removed, and a gate insulating film GI and a gate electrode GE are formed in the space where the sacrificial pattern PP and the sacrificial layer SAL have been removed.

[0066] 14A and 14B, a first through hole TVH1 is formed through the second upper insulating film 120, a portion of the sacrificial pattern PP, and a portion of the stack pattern STP to expose the first and second active patterns AP1 and AP2. The first through-hole TVH1 does not have to be formed in the logic cell LC described with reference to FIGS. 4 and 5A to 5D. The first through holes TVI1 are located between the first and second active patterns AP1 and AP2 and between the isolation structures DB. The first through-hole TVH1 exposes the isolation film ST between the first and second active patterns AP1 and AP2. The width of the first through-hole TVH1 decreases as it approaches the upper surface 100U of the substrate 100.

[0067] A first barrier pattern BP1 is formed on the inner wall of the first through hole TVH1. A first metal pattern MP1 is formed on the first barrier pattern BP1. Forming the first barrier pattern BP1 and the first metal pattern MP1 includes forming a first barrier film that covers the inner wall of the first through hole TVH1 with a uniform thickness, forming a first metal film on the first barrier film, and performing a planarization process on the first metal film to expose the second upper insulating film 120. As a result, the first barrier pattern BP1 is formed from the first barrier film, and the first metal pattern MP1 is formed from the first metal film. As a result, a first through via TVI1 including the first metal pattern MP1 and the first barrier pattern BP1 is formed in the first through hole TVH1.

[0068] 15A and 15B, first and second metal layers M1 and M2 are sequentially formed on the second upper insulating layer 120. As shown in FIG. The first metal layer M1 includes the first and second power wirings (M1_R1, M1_R2), the first wiring (M1_I), and the giant via GVI in the third upper insulating film 130. The second metal layer M2 includes, in the fourth upper insulating film 140, a second wiring (M2_I) and a second via VI2. After the second metal layer M2 is formed, a carrier substrate is bonded onto the fourth upper insulating film 140. The semiconductor device is flipped over using a carrier substrate. As a result, the lower surface 100L of the substrate 100 is positioned at a higher level than the upper surface 100U of the substrate 100. In addition, the lower surface 100L of the substrate 100 is exposed to the outside.

[0069] Thereafter, a planarization process (CMP) is performed on the substrate 100. In the planarization process CMP, the thickness of the substrate 100 is reduced. The planarization process CMP is performed until the lower surface STL of the isolation layer ST is exposed. For example, the planarization process CMP removes the remainder of the substrate 100 except for the first and second active patterns AP1 and AP2. The lower surface STL of the isolation film ST, the lower surfaces of the first and second active patterns AP1 and AP2, and the lower surface 100L of the substrate 100 are located on the same plane. Therefore, the thickness of the substrate 100 is substantially the same as the thickness of each of the first and second active patterns AP1 and AP2. Therefore, the semiconductor device can be made smaller.

[0070] Referring to FIGS. 16A and 16B, an interlayer insulating film is formed on the lower surface of the substrate. A mask pattern is formed on the interlayer insulating film, and a second through hole penetrating the interlayer insulating film and the isolation film is formed by an etching process using the mask pattern. The second through-hole TVH2 does not have to be formed in the logic cell LC described with reference to FIGS. 4 and 5A to 5D. The second through holes TVI1 are located between the first and second active patterns AP1 and AP2 and between the isolation structures DB. The second through hole TVH2 exposes the first barrier pattern of the first through via. The width of the second through-hole TVH2 decreases as it approaches the upper surface 100U of the substrate 100. A second barrier pattern BP2 is formed on the inner wall of the second through hole TVH2. A second metal pattern MP2 is formed on the second barrier pattern BP2. Forming the second barrier pattern BP2 and the second metal pattern MP2 is substantially the same as forming the first barrier pattern BP1 and the first metal pattern MP1. As a result, a second through via TVI2 is formed in contact with the first through via TVI1. For example, the height of the second through via TVI2 is about 0.5 to about 2.0 times the height of the first through via TVI1.

[0071] Referring again to FIGS. 7A and 7B, a power transmission network layer PDN is formed on the interlayer insulating film 150. Forming the power transmission network layer PDN includes forming a first lower insulating film 160, forming a first lower via LV1 and a first lower wiring LM1 in the first lower insulating film 160, forming a second lower insulating film 170 on the first lower insulating film 160, and forming a second lower via LV2 and a second lower wiring LM2 in the second lower insulating film 170. After forming the power transmission network layer PDN, the semiconductor device is turned over again, and the carrier substrate on the fourth upper insulating film 140 is removed.

[0072] According to an embodiment of the present invention, the remainder of the substrate 100 except for the first and second active patterns AP1 and AP2 is removed by a planarization process. Therefore, the thickness of the first and second active patterns AP1 and AP2 is substantially the same as the thickness of the substrate 100. Therefore, the thickness of the substrate 100 is reduced. The first through via TVI1 and the giant via GVI are formed on the upper surface 100U of the substrate 100, and the second through via TVI2 and the first lower via LV1 are formed on the lower surface 100L of the substrate 100. The first through via TVI1 and the second through via TVI2 of the through via TVI are formed individually through different processes and have the same height. This prevents the through via TVI from being misaligned with the giant via GVI and / or the first lower via LV1, while allowing metal material to be easily formed without voids within the through via TVI, which has a large aspect ratio. Therefore, the electrical characteristics and reliability of the semiconductor device are improved.

[0073] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0074] 100 boards 110, 120, 130, 140 (1st to 4th) upper insulating film 150 Interlayer insulating film 160, 170 (first, second) lower insulating film AC Active Contact ACL active layer AP1 and AP2 activity patterns AR1, AR2 (1st, 2nd) active region BAC rear contact BP1, BP2 Barrier Pattern CH1, CH2 (1st, 2nd) channel pattern DHC Double Height Cell DB separation structure GC Gate Contact GE gate electrode GI gate insulating film GP Gate Capping Pattern ISP inner spacer LC1, LC2 (first, second) logic cells LM1, LM2 (1st, 2nd) lower wiring LV1, LV2 (1st, 2nd) bottom via M1, M2 (1st, 2nd) metal layer M1_I First wiring M1_R1, M1_R2, M1_R3 (1st to 3rd) power wiring M2_I 2nd wiring MP1, MP2 metal pattern PDN Power Transmission Network Layer PO1~PO3 (1st~3rd) inner electrode RS1, RS2 (1st, 2nd) recesses SAL sacrificial layer SD1, SD2 (first, second) source / drain patterns SP1~SP3 (1st~3rd) semiconductor patterns ST element separation membrane STP stacking pattern TC Tap Cell TR Trench TVI Through Via TVI1, TVI2 (first and second) through vias VI1, VI2 (1st, 2nd) bottom vias

Claims

1. a substrate including a plurality of active patterns; an isolation layer disposed between the active patterns; a laminated pattern disposed on the substrate; a power transmission network layer disposed on a lower surface of the substrate; a first through via that penetrates the laminated pattern; a second through via disposed between the power transmission network layer and the first through via; The second through via penetrates the active pattern and the isolation film.

2. 2. The semiconductor device of claim 1, wherein the lower surface of the substrate is coplanar with a lower surface of the isolation film.

3. 2. The semiconductor device according to claim 1, wherein the layered pattern includes active layers and sacrificial layers that are alternately layered.

4. further comprising isolation structures on either side of the first through via; 2. The semiconductor device according to claim 1, wherein each of the isolation structures crosses the active pattern.

5. the first through via and the second through via are in contact with each other to form an interface; 2. The semiconductor device according to claim 1, wherein the interface is located between the upper surface and the lower surface of the substrate.

6. the first through via includes a first metal pattern and a first barrier pattern disposed on a side surface of the first metal pattern; The semiconductor device according to claim 1 , wherein the second through via includes a second metal pattern and a second barrier pattern disposed on a side surface of the second metal pattern.

7. the first barrier pattern extends onto a lower surface of the first metal pattern; the second barrier pattern extends onto an upper surface of the second metal pattern; The semiconductor device according to claim 6 , wherein the first barrier pattern and the second barrier pattern are in contact with each other.

8. The semiconductor device of claim 6 , wherein the first metal pattern and the second metal pattern comprise different metal materials.

9. the second barrier pattern extends onto an upper surface of the second metal pattern; The semiconductor device according to claim 6 , wherein the second barrier pattern is in contact with the first metal pattern.

10. a substrate including a logic cell and a tap cell adjacent to the logic cell; a plurality of metal traces disposed on the substrate; wherein the metal wirings are spaced apart from each other in a first direction and extend in a second direction; a power transmission network layer disposed on the lower surface of the substrate; the tap cell includes a through via connecting a portion of the metal wiring to the power transmission network layer; the through vias include a first through via and a second through via that are in contact with each other; the second through via penetrates at least a portion of the substrate; A semiconductor device, characterized in that an interface between the first through via and the second through via is closer to an upper surface of the substrate than to the lower surface of the substrate.

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