Semiconductor device

Abstract

To provide a semiconductor device comprising a switching regulator capable of reducing a voltage noise generated at an output node OUT when transitioning from a Hi-Z state to a lowest frequency operation.SOLUTION: A first control circuit 4 generates a first control signal LGCTL in response to a rise of a feedback voltage FB or assertion of a MINF state signal SMINF. A second control circuit 5 generates a second control signal LGCTLD by which the first control signal LGCTL is delayed, and a third control signal LGDVB thereof. The third control signal LGDVB performs same operation as an inverted signal of the second control signal LGCTLD when the MINF state signal SMINF is negated, and is negated when he MINF state signal SMINF is asserted. A low potential side pre-driver 6 outputs a driving signal LG in response to the second control signal LGCTLD and the third control signal LGDVB, and reduces a slew rate of the driving signal LG when the third control signal LGDVB is negated.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] TECHNICAL FIELD The present disclosure relates to a semiconductor device. [Background technology]

[0002] Switching regulators, which convert DC voltages into other DC voltages by controlling switching elements, have been used in a variety of applications. When switching regulators are classified by function, one type is the step-down switching regulator. Step-down switching regulators convert the input DC voltage into the desired DC voltage by time-dividing it using switching elements and then smoothing it using inductors and capacitors.

[0003] When the load current of a switching regulator is light, the switching regulator performs intermittent operation, intermittently repeating the operation of turning the switch element on and off and then returning to the Hi-Z state. During intermittent operation under light load, the change in output voltage over time is small, so it can take a very long time from when the switch element is turned on and off until the next time the output voltage rises above or falls below the set threshold and the switch element is turned on and off again. Depending on the application in which a switching regulator is used, it is not desirable for the operating frequency of the switching regulator to be very low and uncontrollable, so a minimum frequency operation is provided that operates the switching regulator at the set minimum frequency. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-90271

[0005] [overview] In a step-down switching regulator, when operating at the lowest frequency, the switch element connecting the switch terminal to the low-potential first power supply is turned on to reduce the voltage at the output node, and then the switch element is turned on and off as usual to charge the voltage at the output node to a predetermined voltage. However, when transitioning from the Hi-Z state to the lowest frequency operation, there is a problem in that voltage noise occurs at the output node due to the following process.

[0006] Generally, an inductor connected to a switch terminal has a parasitic capacitor connected in parallel to the inductor. That is, the first electrode of the parasitic capacitor is connected to the switch terminal, and the second electrode is connected to the output node. When a switching regulator transitions from the Hi-Z state to the lowest frequency operation, the voltage of the switch terminal is drawn to the first power supply and drops sharply, and the charge on the parasitic capacitor is discharged, generating voltage noise at the output node.

[0007] In view of the above-described problems discovered by the inventors of the present disclosure, an object of the present disclosure is to provide a semiconductor device including a switching regulator that can reduce voltage noise generated at an output node when transitioning from a Hi-Z state to the lowest frequency operation.

[0008] A semiconductor device according to the present disclosure includes a first switch transistor, a second switch transistor, a state control circuit, a first control circuit, a second control circuit, and a drive circuit. The first switch transistor and the second switch transistor are connected in series between a first power supply having a low potential and a second power supply having a high potential. The state control circuit asserts a first state signal at regular intervals. The first control circuit generates a first control signal in response to an average voltage of a switch terminal, which is a connection point between the first and second switch transistors, becoming higher than a reference voltage or the first state signal being asserted. The second control circuit delays the first control signal to generate a second control signal. The second control circuit further generates a third control signal that operates in the same manner as an inverted signal of the second control signal when the first state signal is negated and is negated when the first state signal is asserted. The drive circuit receives the second control signal and the third control signal, and outputs a drive signal LG, the slew rate of which is switched by the third control signal, to the control electrode of the first switch transistor, wherein the slew rate of the drive signal when the first state signal is asserted is smaller than the slew rate of the drive signal when the first state signal is negated. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a configuration diagram of a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a configuration diagram of a low potential side pre-driver of the semiconductor device according to the embodiment. [Figure 3] FIG. 3 is a configuration diagram of a second control circuit of the semiconductor device according to the embodiment. [Figure 4] FIG. 4 is a configuration diagram of a state control circuit of the semiconductor device according to the embodiment. [Figure 5] FIG. 5 is a configuration diagram of a first control circuit of the semiconductor device according to the embodiment. [Figure 6] FIG. 6 is a state transition diagram of the semiconductor device according to the embodiment. [Figure 7]FIG. 7 is an operational waveform diagram of the semiconductor device according to the embodiment. [Figure 8] FIG. 8 is a configuration diagram of a semiconductor device of a comparative example. [Figure 9] FIG. 9 is a configuration diagram of a low potential side pre-driver of a semiconductor device of a comparative example. [Figure 10] FIG. 10 is an operational waveform diagram of the semiconductor device of the comparative example. [Figure 11] FIG. 11 is a schematic diagram of an element included in an inductor L connected to a semiconductor device of a comparative example. [Figure 12] FIG. 12 is an enlarged operational waveform diagram of the semiconductor device of the comparative example.

[0010] [Detailed explanation] The embodiments will be described with reference to the drawings. In the following description of the drawings, the same or similar parts will be denoted by the same or similar reference numerals, and the description thereof will be omitted. The drawings are schematic.

[0011] Furthermore, the embodiments shown below are merely examples of devices and methods for embodying the technical ideas, and do not specify the materials, shapes, structures, arrangements, etc. of each component part. Various modifications can be made to these embodiments within the scope of the claims.

[0012] [Embodiment] (Configuration of semiconductor device) 1 is a configuration diagram of a semiconductor device according to an embodiment of the present invention, which is a switching regulator 100.

[0013] The switching regulator 100 includes a low-side switch transistor 1, which is a first switch transistor; a high-side switch transistor 2, which is a second switch transistor; a MINF state control circuit 3; a first control circuit 4; and a second control circuit 5. Here, "MINF" stands for minimum frequency, and the "MINF state" refers to the initial state when the switching regulator 100 begins operating at the minimum frequency. The switching regulator 100 also includes a low-side pre-driver 6 and a high-side pre-driver 7, a second power supply terminal TV2, which is an external power supply terminal, a switch terminal T1, and a feedback terminal T2. The switch terminal T1 is the connection point between the low-side switch transistor 1 and the high-side switch transistor 2. The voltage at the second power supply terminal TV2 is a second power supply voltage V2.

[0014] The low-side switch transistor 1 is an n-channel MOS transistor, and has a source connected to a ground electrode GND which is an example of a low-potential first power supply, a drain connected to a switch terminal T1, and a gate which is a control electrode connected to the low-side pre-driver 6. A low-side drive signal LG is input to the gate of the low-side switch transistor 1.

[0015] The high-side switch transistor 2 is an n-channel MOS transistor with a source connected to the switch terminal T1, a drain connected to the second power supply terminal TV2, and a gate connected to the high-side pre-driver 7. A high-side drive signal HG is input to the gate of the high-side switch transistor 2. The low-side switch transistor 1 and the high-side switch transistor 2 are connected in series between the ground electrode GND and the second power supply terminal TV2.

[0016] The MINF state control circuit 3 receives a high-side drive signal HG from the high-side pre-driver 7, and also receives an enable signal EN from a circuit not shown. The enable signal EN is asserted, for example, when it detects that the second power supply voltage V2 has risen above a predetermined voltage, or in accordance with an operating mode set externally to the switching regulator. The MINF state control circuit 3 outputs a MINF state signal SMINF, which is a first state signal, to the first control circuit 4 and the second control circuit 5.

[0017] The first control circuit 4 receives the MINF state signal SMINF from the MINF state control circuit 3, the switch voltage SW from the switch terminal T1, the feedback voltage FB from the feedback terminal T2, and the enable signal EN. The first control circuit 4 outputs a high-side control signal HGCTL to the high-side pre-driver 7, and outputs a low-side control signal LGCTL, which is a first control signal, to the second control circuit 5.

[0018] The second control circuit 5 receives the low potential side control signal LGCTL from the first control circuit 4 and the MINF state signal SMINF from the MINF state control circuit 3. The second control circuit 5 outputs to the low potential side pre-driver 6 a low potential side delay control signal LGCTLD which is a second control signal and a first low potential side drive original signal LGDVB which is a third control signal.

[0019] The low-side pre-driver 6 sets the low-side drive signal LG to high level in response to the low-side delay control signal LGCTLD and the first low-side drive original signal LGDVB input from the second control circuit 5. The low-side pre-driver 6 is a drive circuit that outputs the low-side drive signal LG.

[0020] In response to the high potential side control signal HGCTL input from the first control circuit 4, the high potential side pre-driver 7 sets the high potential side drive signal HG output to the high potential side switch transistor 2 and the MINF state control circuit 3 to high level.

[0021] Generally, an inductor L and a capacitor C are used outside the switching regulator 100 to smooth the voltage of the switch terminal T1. A first end of the inductor L is connected to the switch terminal T1, and a second end is connected to the output node OUT. A first electrode of the capacitor C is connected to the output node OUT, and a second electrode is connected to the ground electrode GND. The voltage of the switch terminal T1 is smoothed by the inductor L and the capacitor C and transmitted to the output node OUT. The output node voltage VOUT is the voltage of the output node OUT. The output node OUT is connected to a feedback terminal T2. A feedback voltage FB, which is the voltage of the feedback terminal T2, is input to the first control circuit 4. The switching regulator 100 sets the output node voltage VOUT to a predetermined voltage by turning on and off the low-side switch transistor 1 and the high-side switch transistor 2 based on the switch voltage SW and the feedback voltage FB to output the switch voltage SW.

[0022] The switching regulator 100 of FIG. 1 operates as follows: The MINF state control circuit 3, which is a state control circuit, asserts the MINF state signal SMINF, which is a first state signal, at regular intervals. The first control circuit 4 generates the low-side control signal LGCTL, which is a first control signal, in response to the average voltage of the switch terminal T1, which is the connection point between the first and second switch transistors 1 and 2, becoming higher than the reference voltage or the MINF state signal SMINF being asserted. The second control circuit 5 delays the low-side control signal LGCTL, which is the first control signal, to generate the low-side delayed control signal LGCTLD, which is a second control signal. The second control circuit 5 also generates the first low-side drive original signal LGDVB, which is a third control signal. The first low-side drive original signal LGDVB operates in the same manner as the inverted signal of the low-side delayed control signal LGCTLD when the MINF state signal SMINF is negated and is negated when the MINF state signal SMINF is asserted.

[0023] A low-side delay control signal LGCTLD and a first low-side drive original signal LGDVB are input to the low-side pre-driver 6, which is a drive circuit. The low-side pre-driver 6 outputs a low-side drive signal LG, the slew rate of which is switched by the first low-side drive original signal LGDVB, to the gate, which is the control electrode of the first switch transistor 1. The slew rate of the low-side drive signal LG when the MINF state signal SMINF is asserted is smaller than the slew rate of the low-side drive signal LG when the MINF state signal SMINF is negated.

[0024] 2 is a configuration diagram of the low-side pre-driver 6 of the switching regulator 100. The low-side pre-driver 6 includes p-channel MOS transistors 61, 63, 64, and 65, and n-channel MOS transistors 62, 66, 67, and 68. The p-channel MOS transistors 65 and 63 are the first drive transistor and the second drive transistor, respectively, and the n-channel MOS transistor 68 is the third drive transistor.

[0025] The source of the p-channel MOS transistor 61 is connected to the third power supply VCC, and the source of the n-channel MOS transistor 62 is connected to the ground electrode GND. The p-channel MOS transistor 61 and the n-channel MOS transistor 62 each have a gate to which the low potential side delay control signal LGCTLD is input, and a drain from which the second low potential side drive original signal LGDV2B is output.

[0026] The p-channel MOS transistors 63, 64, and 65 have their sources, which are first main electrodes, connected to the third power supply VCC, and the n-channel MOS transistors 66, 67, and 68 have their sources, which are first main electrodes, connected to the ground electrode GND. The p-channel MOS transistor 63 has its gate, which is its control electrode, input with the second low potential side drive original signal LGDV2B, and the p-channel MOS transistors 64 and 65 have their gates, which are their control electrodes, input with the first low potential side drive original signal LGDVB. The n-channel MOS transistors 66, 67, and 68 have their gates, which are their control electrodes, input with the second low potential side drive original signal LGDV2B. The low potential side drive signal LG is output from the drains, which are second main electrodes, of the p-channel MOS transistors 63, 64, and 65 and the drains, which are second main electrodes, of the n-channel MOS transistors 66, 67, and 68.

[0027] The ratio of the gate widths or the current driving capabilities of the p-channel MOS transistors 63, 64, and 65 is set to, for example, 1:1:2. The ratio of the gate widths or the current driving capabilities of the n-channel MOS transistors 66, 67, and 68 is set to, for example, 1:1:2.

[0028] FIG. 3 is a configuration diagram of the second control circuit 5 of the switching regulator 100. The second control circuit 5 includes an inverter 51, a two-input NOR 52, and inverter groups 53 and 54. The inverter 51 inverts the low-side control signal LGCTL input to its input terminal and outputs the low-side inverted control signal LGCTLB. The two-input NOR 52 performs an inverted OR operation on the MINF state signal SMINF and the low-side inverted control signal LGCTLB to output the inverted OR signal NORO. The inverter group 53 inverts and buffers the inverted OR signal NORO using three inverters to output the first low-side drive original signal LGDVB. In other words, the second control circuit 5 generates the first low-side drive original signal LGDVB, which is the third control signal, by performing an OR operation on the inverted signal of the low-side control signal LGCTL, which is the first control signal, and the MINF state signal SMINF, which is the first state signal. The second control circuit 5 may generate the first low potential side drive original signal LGDVB by a logic circuit logically equivalent to that shown in Fig. 3. The inverter group 54 inverts and delays the low potential side inverted control signal LGCTLB using three inverter stages, and outputs the low potential side delayed control signal LGCTLD.

[0029] The operation of the second control circuit 5 in FIG. 3 and the low-side pre-driver 6 in FIG. 2 will be described with reference to FIGS. 1 to 3. When the MINF state signal SMINF is negated to a low level, the second control circuit 5 inverts and buffers the low-side control signal LGCTL and outputs the first low-side driver original signal LGDVB. When the low-side control signal LGCTL transitions from a low level to a high level, the first low-side driver original signal LGDVB transitions from a high level to a low level, a first time TD1 after the transition of the low-side control signal LGCTL. When the first low-side driver original signal LGDVB input to the gates of the low-side pre-driver 6 goes low, the p-channel MOS transistors 64 and 65 turn on, setting the low-side drive signal LG to a high level. When the low-side drive signal LG goes high, the low-side switch transistor 1 turns on, setting the switch voltage SW, which is the voltage at the switch terminal T1, to the voltage of the ground electrode GND, which is a low level.

[0030] The second control circuit 5 delays the low-side control signal LGCTL and outputs the low-side delay control signal LGCTLD. The p-channel MOS transistor 61 and n-channel MOS transistor 62 of the low-side pre-driver 6 invert the low-side delay control signal LGCTLD input to their gates and output the second low-side driver original signal LGDV2B. The p-channel MOS transistor 63 of the low-side pre-driver 6 turns on when the second low-side driver original signal LGDV2B input to its gate goes low, causing the low-side drive signal LG to go high. The delay amount of the inverter group 54 of the second control circuit 5 is set so that the second low-side driver original signal LGDV2B transitions at a timing delayed by a first time TD1 from the transition of the low-side control signal LGCTL. In other words, the first low-side driver original signal LGDVB and the second low-side driver original signal LGDV2B transition at substantially the same timing when the low-side control signal LGCTL transitions.

[0031] When the first low potential side drive original signal LGDVB and the second low potential side drive original signal LGDV2B simultaneously transition from high level to low level, the p-channel MOS transistors 63, 64, and 65 of the low potential side pre-driver 6 are simultaneously turned on. When the p-channel MOS transistors 63, 64, and 65 are turned on and the low potential side drive signal LG is set to high level, the low potential side switch transistor 1 is turned on and the switch voltage SW is set to low level.

[0032] When the low potential side control signal LGCTL transitions from high to low while the MINF state signal SMINF is at low level, the operation is as follows: The first low potential side drive original signal LGDVB and the second low potential side drive original signal LGDV2B transition from low to high simultaneously, and the p-channel MOS transistors 63, 64, and 65 of the low potential side pre-driver 6 are simultaneously turned off. Also, the n-channel MOS transistors 66, 67, and 68 of the low potential side pre-driver 6 are simultaneously turned on, and the low potential side drive signal LG is set to low level.

[0033] On the other hand, when the MINF state signal SMINF is asserted to a high level, the first low potential side drive original signal LGDVB is fixed to a high level, and the p-channel MOS transistors 64 and 65 of the low potential side pre-driver 6 are turned off. When the low potential side control signal LGCTL transitions from a low level to a high level, the second low potential side drive original signal LGDV2B of the low potential side pre-driver 6 transitions from a high level to a low level, and the p-channel MOS transistor 63 is turned on. Then, the p-channel MOS transistor 63 sets the low potential side drive signal LG to a high level, the low potential side switch transistor 1 is turned on, and the switch voltage SW is set to a low level.

[0034] The gate width or current drive capability of the p-channel MOS transistor 63 is, for example, ¼ of the total gate width or current drive capability of the p-channel MOS transistors 63, 64, and 65. The slew rate when the p-channel MOS transistor 63 is turned on and the low-side drive signal LG goes high is smaller than the slew rate when the p-channel MOS transistors 63, 64, and 65 are turned on simultaneously. As the slew rate when the low-side drive signal LG goes high is reduced, the slew rate when the switch voltage SW goes low is also reduced.

[0035] In other words, the slew rate when the low potential side drive signal LG goes to high level and the slew rate when the switch voltage SW goes to low level are smaller when the MINF state signal SMINF is asserted than when it is negated.

[0036] 4 is a configuration diagram of the MINF state control circuit 3 of the switching regulator 100. The MINF state control circuit 3 has an oscillator circuit 31 and a counter circuit 32. When the enable signal EN is at a high level, the oscillator circuit 31 generates an oscillation signal OSC that transitions from a low level to a high level and back to a low level at a fixed oscillation period TOSC, and outputs the oscillation signal OSC to the counter circuit 32. The counter circuit 32 counts the number of transitions of the oscillation signal OSC that occur while the high-side drive signal HG is at a low level, and when the number of transitions exceeds a threshold for transitioning to the MINF state, it asserts the MINF state signal SMINF at a high level.

[0037] The threshold number of transitions to the MINF state is the number of times equivalent to the period calculated as the reciprocal of the minimum frequency. For example, if the minimum frequency is 200 kHz and the oscillation period TOSC of the oscillation signal OSC is 100 ns, the period TPMINF at which the MINF state signal SMINF becomes high level is 5 us, and the threshold number of transitions of the oscillation signal OSC at which the state transitions to the MINF state is 50.

[0038] When the high potential side drive signal HG goes high, the counter circuit 32 resets and restarts the count of the number of transitions of the oscillation signal OSC, and also negates the MINF state signal SMINF by going low.

[0039] 5 is a configuration diagram of the first control circuit 4 of the switching regulator 100. The first control circuit 4 includes comparators 41 and 42 and an output control circuit 43.

[0040] The comparator 41 receives a reference voltage REF, which is a reference voltage, from a reference voltage generating circuit (not shown), a feedback voltage FB from a feedback terminal T2, and an enable signal EN, and outputs a feedback determination signal FBCOMP to an output control circuit 43. When the enable signal EN is at a high level, the comparator 41 compares the feedback voltage FB with the reference voltage REF, and when the feedback voltage FB is lower than the reference voltage REF, the comparator 41 sets the feedback determination signal FBCOMP to a high level. When the enable signal EN is at a low level, the comparator 41 sets the feedback determination signal FBCOMP to a low level.

[0041] The comparator 42 receives the switch voltage SW from the switch terminal T1, the voltage of the ground electrode GND, and an enable signal, and outputs a determination signal ZCOMP to the output control circuit 43. When the enable signal EN is at a high level, the comparator 42 compares the switch voltage SW with the voltage of the ground electrode GND. When the switch voltage SW and the voltage of the ground electrode GND are substantially equal, the comparator 42 determines that the current of the inductor L is 0 A and sets the determination signal ZCOMP to a high level. When the enable signal EN is at a low level, the comparator 42 sets the determination signal ZCOMP to a low level.

[0042] The output control circuit 43 receives the MINF state signal SMINF from the MINF state control circuit 3, the feedback determination signal FBCOMP from the comparator 41, the determination signal ZCOMP from the comparator 42, and the enable signal EN. The output control circuit 43 outputs a low-side control signal LGCTL to the second control circuit 5, and outputs a high-side control signal HGCTL to the high-side pre-driver 7.

[0043] FIG. 6 is a state transition diagram of the switching regulator 100. Using the state transition diagram of FIG. 6, the operation performed by the switching regulator 100 under the control of the MINF state control circuit 3 and the output control circuit 43 will be explained. The state transition diagram shows the portion related to the minimum frequency operation performed under a light load. In FIG. 6, the low potential side switch transistor 1 is referred to as "L SW Tr." and the high potential side switch transistor 2 is referred to as "H SW Tr."

[0044] When a drop in the second power supply voltage V2 is detected or a stop command is input from an external device, the enable signal EN changes to low level from the All State, which indicates all states. When the enable signal EN changes to low level, the switching regulator 100 transitions to the Disable State, which is a stopped state. In the Disable State, the MINF state control circuit 3 in FIG. 4, the comparators 41 and 42, and the output control circuit 43 in FIG. 5 stop operating, and the low-side control signal LGCTL and the high-side control signal HGCTL are fixed to low level. Then, the low-side drive signal LG and the high-side drive signal HG are fixed to low level, turning off both the low-side switch transistor 1 and the high-side switch transistor 2, and the switch terminal T1 becomes Hi-Z.

[0045] In the Disable state, when a rise in the second power supply voltage V2 is detected or an operation command is input from the outside, the enable signal EN changes to high level. When the enable signal EN changes to high level, the switching regulator 100 transitions to a Hi-Z state in which the MINF state control circuit 3 in FIG. 4 and the comparators 41 and 42 and the output control circuit 43 in FIG. 5 are in operation and the switch terminal T1 is in Hi-Z.

[0046] The lowest frequency operation starts from this Hi-Z state, and ends by returning to the Hi-Z state. The state transition during the lowest frequency operation is explained below.

[0047] When the load current of the switching regulator 100 is small, the change in the output node voltage VOUT is small, so the state in which the feedback voltage FB in Figure 5 remains equal to or higher than the reference voltage REF continues. When the switching regulator 100 remains in the Hi-Z state and the number of transitions measured by the MINF state control circuit 3 exceeds the threshold number for transitioning to the MINF state, the MINF state signal SMINF becomes high level. When the MINF state signal SMINF becomes high level, the switching regulator 100 transitions to the MINF state.

[0048] In the MINF state, the low-side control signal LGCTL goes high, the low-side drive signal LG goes high, the low-side switch transistor 1 turns on, and the switch voltage SW is pulled down to the voltage of the ground electrode GND. The output node voltage VOUT, which is smoothed from the switch voltage SW by the inductor L and capacitor C, also drops.

[0049] When the output node voltage VOUT drops, the feedback voltage FB in FIG. 5 drops, and when the feedback voltage FB becomes lower than the reference voltage REF, the comparator 41 sets the feedback determination signal FBCOMP to a high level, and the switching regulator 100 transitions to the HON state.

[0050] In the HON state, the high-side control signal HGCTL in Fig. 1 goes high, the high-side drive signal HG goes high, and in the MINF state control circuit 3 in Fig. 4, the counter circuit 32 is reset and the MINF state signal SMINF goes low. When the high-side drive signal HG goes high, the high-side switch transistor 2 turns on, and the switch voltage SW rises to the second power supply voltage V2. The output node voltage VOUT, which is smoothed by the inductor L and capacitor C from the switch voltage SW, also rises.

[0051] When the output node voltage VOUT rises, the feedback voltage FB in FIG. 5 rises, and when the feedback voltage FB becomes equal to or higher than the reference voltage REF, the comparator 41 sets the feedback determination signal FBCOMP to a low level, and the switching regulator 100 transitions to the LON state.

[0052] In the LON state, the high-side control signal HGCTL in FIG. 1 goes low, the high-side drive signal HG goes low, and the high-side switch transistor 2 turns off. Then, the low-side control signal LGCTL goes high, the low-side drive signal LG goes high, and the low-side switch transistor 1 turns on, and the switch voltage SW is pulled down to the voltage of the ground electrode GND. The output node voltage VOUT, which is the switch voltage SW smoothed by the inductor L and capacitor C, also drops. In parallel, the comparator 42 in FIG. 5 compares the switch voltage SW with the voltage of the ground electrode GND.

[0053] When the switch voltage SW becomes substantially equal to the voltage of the ground electrode GND, the comparator 42 determines that the current flowing from the inductor L via the low-side switch transistor 1 has become 0 A, and sets the determination signal ZCOMP to high level. When the determination signal ZCOMP becomes high level, the switching regulator 100 returns to the Hi-Z state.

[0054] When the load current of the switching regulator 100 is small, the above-described Hi-Z state is changed in order from the MINF state, the HON state, and the LON state, and then the state is returned to the Hi-Z state, and the change is repeated. This type of change is called the minimum frequency operation.

[0055] FIG. 7 is an operational waveform diagram of the switching regulator 100. The horizontal axis of FIG. 7 represents time, and the vertical axis represents voltage. The state notation "state" indicates the state in the state transition diagram of FIG. 6. The waveform of the first low potential side drive original signal LGDVB is indicated by a dashed line, and waveforms other than the first low potential side drive original signal LGDVB are indicated by solid lines. The operational waveform diagram of FIG. 7 is an operational waveform diagram for transitioning from the Hi-Z state to the MINF state.

[0056] At time t0, the switching regulator 100 is in a Hi-Z state. The low-potential side drive signal LG is at a low level, the high-potential side drive signal HG (not shown in FIG. 7) is at a low level, and the switch terminal T1 is in a Hi-Z state.

[0057] At time t1, when the number of transitions of the oscillation signal OSC (not shown in FIG. 7) exceeds the threshold number of transitions to the MINF state, the switching regulator 100 transitions to the MINF state, and the MINF state signal SMINF goes high.

[0058] In the MINF state, the low-side control signal LGCTL goes high, and the low-side delay control signal LGCTLD (not shown in FIG. 7) goes high at a timing delayed by a first time TD1 in the second control circuit 5 of FIG. 3. Because the MINF state signal SMINF is high, the first low-side driver original signal LGDVB generated by the second control circuit 5 of FIG. 3 remains high. In the low-side pre-driver 6 of FIG. 2, when the low-side delay control signal LGCTLD goes high, the second low-side driver original signal LGDV2B goes low, turning on the p-channel MOS transistor 63. Because the first low-side driver original signal LGDVB is high, the p-channel MOS transistors 64 and 65 are off. The low-side drive signal LG transitions to a high level when the p-channel MOS transistor 63 turns on. The slew rate of the low potential side drive signal LG is smaller than when the p-channel MOS transistors 64 and 65 are on because the p-channel MOS transistors 64 and 65 are off.

[0059] When the voltage of the low-side drive signal LG increases, the low-side switch transistor 1 turns on, and the switch voltage SW goes low. Because the slew rate of the low-side drive signal LG decreases, the slew rate of the switch voltage SW also decreases. The slew rate of the switch voltage SW is, for example, 1 MV / us. When the switching regulator 100 transitions from the Hi-Z state to the lowest frequency operation, the slew rate of the switch voltage SW decreases, thereby suppressing the voltage noise generated in the output node voltage VOUT to, for example, 19.7 mV.

[0060] Here, to facilitate understanding of the features of the present invention, a semiconductor device of a comparative example will be described.

[0061] 8 is a configuration diagram of a semiconductor device of a comparative example. The semiconductor device of FIG. 8 is a switching regulator 200. The switching regulator 200 differs from the switching regulator 100 according to the embodiment shown in FIG. 1 in the following respects. The switching regulator 200 of FIG. 8 uses a first control circuit 94 having a different configuration from the first control circuit 4, does not use a second control circuit 5, and uses a low-side pre-driver 96 having a different configuration from the low-side pre-driver 6. The low-side pre-driver 96 receives a low-side control signal LGCTL from the first control circuit 94.

[0062] 9 is a configuration diagram of the low-side pre-driver 96 of the switching regulator 200. The low-side pre-driver 96 differs from the low-side pre-driver 6 shown in FIG. 2 in the following respects: The low-side control signal LGCTL is inverted by a p-channel MOS transistor 961 and an n-channel MOS transistor 962 to generate a low-side drive original signal LGDVB. The low-side drive original signal LGDVB is input to the gates of p-channel MOS transistors 963, 964, and 965 and the gates of n-channel MOS transistors 966, 967, and 968. The low-side drive signal LG is output from the drains of the p-channel MOS transistors 963, 964, and 965 and the drains of the n-channel MOS transistors 966, 967, and 968.

[0063] The ratio of the gate widths or current driving capabilities of the p-channel MOS transistors 963, 964, and 965 is set to, for example, 1:1:2. The ratio of the gate widths or current driving capabilities of the n-channel MOS transistors 966, 967, and 968 is set to, for example, 1:1:2.

[0064] When the low potential side control signal LGCTL goes high, the low potential side drive original signal LGDVB goes low, the p-channel MOS transistors 963, 964, 965 are simultaneously turned on, and the low potential side drive signal LG goes high.

[0065] Fig. 10 is an operational waveform diagram of the switching regulator 200 of the comparative example. The horizontal axis of Fig. 10 represents time, and the vertical axis represents voltage. The state notation "state" indicates a state in the state transition diagram of Fig. 6. The operational waveform diagram of Fig. 10 is an operational waveform diagram of a transition from the Hi-Z state to the MINF state.

[0066] At time t0, the switching regulator 200 is in the Hi-Z state. The low-potential side drive signal LG and the high-potential side drive signal HG (not shown in Fig. 10) are at low level, and the switch terminal T1 is in the Hi-Z state.

[0067] At time t1, when the number of transitions of the oscillation signal OSC (not shown in FIG. 10) exceeds the threshold number of transitions to the MINF state, the switching regulator 200 transitions to the MINF state, and the MINF state signal SMINF goes high.

[0068] In the MINF state, the low-side control signal LGCTL (not shown in FIG. 10) goes high, and in the low-side pre-driver 96 of FIG. 9, the low-side drive source signal LGDVB goes low, turning on p-channel MOS transistors 963, 964, and 965. The p-channel MOS transistors 963, 964, and 965 are simultaneously turned on, causing the low-side drive signal LG to transition to a high level. The slew rate when the low-side drive signal LG goes high is greater than when the p-channel MOS transistors 64 and 65 are off. When the voltage of the low-side drive signal LG rises, the low-side switch transistor 1 turns on, and the switch voltage SW goes low.

[0069] 11 is a schematic diagram of elements included in an inductor L connected to a switching regulator 200 of the comparative example. The inductor L includes an intrinsic inductor L0, a parasitic resistor Rp connected in series with the intrinsic inductor L0, and a parasitic capacitor Cp connected in parallel with the intrinsic inductor L0 and the parasitic resistor Rp.

[0070] 12 is an operational waveform diagram showing enlarged operational waveforms of the switch voltage SW, the inductor current IL flowing through the inductor L, and the output node voltage VOUT of the switching regulator 200 of the comparative example. The horizontal axis in Fig. 12 represents time. The vertical axis of the operational waveforms of the switch voltage SW and the output node voltage VOUT represents voltage, and the vertical axis of the operational waveform of the inductor current IL represents current.

[0071] At time t1, the switching regulator 200 transitions from the Hi-Z state to the MINF state. When the low-side drive signal LG goes high and the switch voltage SW goes low, the parasitic capacitor Cp, which is connected in parallel to the intrinsic inductor L0 and the parasitic resistor Rp, is discharged, causing the inductor current IL to rapidly increase negative. This noise in the inductor current IL propagates to the output node voltage VOUT as voltage noise. The magnitude of the voltage noise depends on the magnitude of the noise in the inductor current IL, which in turn depends on the slew rate of the switch voltage SW. Therefore, the voltage noise can be reduced by reducing the slew rate of the switch voltage SW.

[0072] Returning to the explanation of FIG. 10, in the switching regulator 200 of the comparative example, the slew rate of the low-side drive signal LG is large, and therefore the slew rate of the switch voltage SW is also large. The slew rate of the switch voltage SW is, for example, 3.9 MV / us. When the switching regulator 200 transitions from the Hi-Z state to the lowest frequency operation, the large slew rate of the switch voltage SW causes the voltage noise generated in the output node voltage VOUT to increase to 134.3 mV. In contrast, in the switching regulator 100, the slew rate of the switch voltage SW is, for example, 1 MV / us, and the voltage noise generated in the output node voltage VOUT is, for example, 19.7 mV, which can be kept lower than that of the switching regulator 200 of the comparative example.

[0073] (Effects of the embodiment) In the switching regulator 100, when transitioning from the Hi-Z state to the lowest frequency operation, the MINF state signal SMINF is asserted, fixing the p-channel MOS transistors 64 and 65 of the low-side pre-driver 6 to the off state. In response to the low-side control signal LGCTL going high, the low-side pre-driver 6 sets the low-side drive signal LG to the high level. By turning on the p-channel MOS transistor 63 while the p-channel MOS transistors 64 and 65 are off, the slew rate of the low-side drive signal LG becomes smaller than when the p-channel MOS transistors 63, 64, and 65 are simultaneously turned on. According to the switching regulator 100, when transitioning to the lowest frequency operation, the slew rate when the low-side drive signal LG goes high is reduced, thereby reducing the slew rate of the switch voltage SW and reducing voltage noise generated in the output node voltage VOUT.

[0074] When the MINF state signal SMINF is negated, the switching regulator 100 synchronizes the transition timings of the first and second low potential side drive original signals LGDVB and LGDV2B due to the delay of the inverter group 54. In states other than the MINF state, the first and second low potential side drive original signals LGDVB and LGDV2B operate at the same timing, which causes the p-channel MOS transistors 63, 64, and 65 to turn on simultaneously, allowing the low potential side drive signal LG to operate at a desired slew rate.

[0075] [Other embodiments] Although the embodiments of the present disclosure have been described, they are presented as examples and are not intended to limit the scope of the invention. This novel embodiment can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions described in the claims and their equivalents.

[0076] For example, in the switching regulator 100 of the present disclosure described above, the second control circuit 5 outputs the first low potential side drive original signal LGDVB, which is low active, to the gates of the p-channel MOS transistors 64 and 65 of the low potential side pre-driver 6. However, an inverter 69 may be added to the low potential side pre-driver 6, and the second control circuit 5 may output the third low potential side drive original signal LGDV, which is high active, and the signal inverted by the inverter 69 may be input to the gates of the p-channel MOS transistors 64 and 65.

[0077] (Addendum) The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0078] (Appendix 1) The semiconductor device includes a first switch transistor 1, a second switch transistor 2, a state control circuit 3, a first control circuit 4, a second control circuit 5, and a drive circuit 6. The first switch transistor 1 and the second switch transistor 2 are connected in series between a ground electrode GND, which is an example of a low-potential first power supply, and a high-potential second power supply TV2. The state control circuit 3 asserts a first state signal SMINF at regular intervals. The first control circuit 4 generates a first control signal LGCTL in response to the average voltage of a switch terminal T1, which is the connection point between the first and second switch transistors 1 and 2, becoming higher than a reference voltage or the first state signal SMINF being asserted. The second control circuit 5 delays the first control signal LGCTL to generate a second control signal LGCTLD. The second control circuit 5 further generates a third control signal LGDVB that operates in the same manner as an inverted signal of the second control signal LGCTLD when the first state signal SMINF is negated and is negated when the first state signal SMINF is asserted.

[0079] The drive circuit 6 receives the second control signal LGCTLD and the third control signal LGDVB as inputs, and outputs a drive signal LG, whose slew rate is switched by the third control signal LGDVB, to the control electrode of the first switch transistor 1. The slew rate of the drive signal LG when the first state signal SMINF is asserted is smaller than the slew rate of the drive signal LG when the first state signal SMINF is negated. Because the slew rate of the drive signal LG when the first state signal SMINF is asserted is smaller, the semiconductor device 100 can reduce the slew rate of the switch voltage SW and reduce voltage noise generated in the output node voltage VOUT.

[0080] (Appendix 2) In the semiconductor device described in Supplementary Note 1, the drive circuit 6 includes a first drive transistor 65, a second drive transistor 63, and a third drive transistor 68. The first drive transistor 65 receives the voltage of the third power supply VCC at its first main electrode, receives the third control signal LGDVB at its control electrode, and outputs the drive signal LG from its second main electrode. The second drive transistor 63 receives the voltage of the third power supply VCC at its first main electrode, receives an inverted signal of the second control signal LGCTLD at its control electrode, and outputs the drive signal LG from its second main electrode. The third drive transistor 68 receives the voltage of the ground electrode GND at its first main electrode, receives an inverted signal of the second control signal LGCTLD at its control electrode, and outputs the drive signal LG from its second main electrode. When the third control signal LGDVB is input to its gate, the first drive transistor 65 is turned off when the first state signal SMINF is asserted, thereby reducing the slew rate of the drive signal LG. Furthermore, when the first state signal SMINF is negated, the first drive transistor 65 can be turned on simultaneously with the second drive transistor 63, and the drive signal LG can be operated at a desired slew rate.

[0081] (Appendix 3) In the semiconductor device described in Supplementary Note 2, the current driving capability of the second driving transistor 63 is smaller than the current driving capability of the first driving transistor 65. In the MINF state, the semiconductor device 100 can reduce the slew rate of the switch voltage SW, and can efficiently reduce voltage noise generated in the output node voltage VOUT.

[0082] (Appendix 4) In the semiconductor device described in any one of Supplementary Notes 1 to 3, the second control circuit 5 generates the third control signal LGDVB by a logic circuit equivalent to the logical sum of an inverted signal of the first control signal LGCTL and the first state signal SMINF. This logic circuit enables the third control signal LGDVB to perform the same operation as an inverted signal of the second control signal LGCTLD when the first state signal SMINF is negated, and to be negated when the first state signal SMINF is asserted.

[0083] (Appendix 5) In the semiconductor device described in any one of Supplementary Notes 1 to 4, the delay amount of the second control signal LGCTLD relative to the first control signal LGCTL is set so that the timing at which the third control signal LGDVB operates and the timing at which the inverted signal of the second control signal LGCTLD operates substantially coincide. By having the third control signal LGDVB and the inverted signal of the second control signal LGCTLD operate at the same timing, the p-channel MOS transistors 63, 64, and 65 of the low-side pre-driver 6 are turned on simultaneously, and the low-side drive signal LG can operate at a desired slew rate.

[0084] (Appendix 6) In the semiconductor device described in any one of Supplementary Notes 1 to 5, a first end of an inductor L is connected to a switch terminal T1 outside the semiconductor device, a first electrode of a capacitor C is connected to a second end of the inductor, and a second electrode of the capacitor C is connected to a ground electrode GND. A first electrode of the capacitor C is connected to a feedback terminal T2. A voltage of the first electrode of the capacitor C is input to a first control circuit 4. By connecting the inductor L and the capacitor C to the switch terminal T1, the semiconductor device 100 can generate a smoothed output node voltage VOUT and can effectively reduce voltage noise generated in the output node voltage VOUT by a parasitic capacitor Cp of the inductor L. [Explanation of symbols]

[0085] 1 Low-side switch transistor 2 High-side switch transistor 3 MINF state control circuit 4. First control circuit 5 Second control circuit 6 Low-voltage side pre-driver 7 High-potential side pre-driver 31 Oscillator Circuit 32 Counter circuit 41, 42 Comparator 43 Output control circuit 51, 69 Inverter 53, 54 Inverter group 61, 63, 64, 65 p-channel MOS transistor 62, 66, 67, 68 n-channel MOS transistor 100 Semiconductor device, particularly switching regulator C capacitor Cp Parasitic capacitor EN Enable signal FB Feedback voltage GND ground electrode HG High potential side drive signal HGCTL High-potential side control signal IL Inductor current L inductor L0 intrinsic inductor LG Low potential side drive signal LGCTL Low potential side control signal LGDV2B Second low potential side drive source signal LGDVB First low potential side driver signal NORO Inverted OR signal OSC Oscillator signal OUT output node REF Reference voltage Rp parasitic resistance SMINF MINF state signal SW Switch voltage t0, t1 time T1 switch terminal T2 feedback terminal TD1 First Hour TOSC oscillation period TV2 2nd power terminal V2 Second power supply voltage VCC 3rd power supply VOUT Output node voltage ZCOMP judgment signal

Claims

1. a first switch transistor and a second switch transistor connected in series between a first power supply of a low potential and a second power supply of a high potential; a state control circuit that asserts a first state signal at regular intervals; a first control circuit that generates a first control signal in response to an average voltage of a switch terminal that is a connection point between the first switch transistor and the second switch transistor becoming higher than a reference voltage or in response to the first state signal being asserted; a second control circuit that delays the first control signal to generate a second control signal, and that generates a third control signal that operates in the same manner as an inverted signal of the second control signal when the first state signal is negated and is negated when the first state signal is asserted; a drive circuit that receives the second control signal and the third control signal and outputs a drive signal, the slew rate of which is switched in response to the third control signal, to a control electrode of the first switch transistor; Equipped with The semiconductor device, wherein the slew rate of the drive signal when the first state signal is asserted is smaller than the slew rate when the first state signal is negated.

2. The drive circuit a first drive transistor having a first main electrode to which a voltage of a third power supply is input, a control electrode to which the third control signal is input, and a second main electrode to which the drive signal is output; a second drive transistor having a first main electrode to which the voltage of the third power supply is input, a control electrode to which an inverted signal of the second control signal is input, and a second main electrode to which the drive signal is output; a third drive transistor having a first main electrode to which the voltage of the first power supply is input, a control electrode to which an inverted signal of the second control signal is input, and a second main electrode to which the drive signal is output; Including, The semiconductor device according to claim 1 .

3. the current driving capability of the second driving transistor is smaller than the current driving capability of the first driving transistor; The semiconductor device according to claim 2 .

4. The second control circuit includes: generating the third control signal by a logic circuit equivalent to a logical sum of an inverted signal of the first control signal and the first state signal; The semiconductor device according to claim 2 .

5. a delay amount of the second control signal relative to the first control signal, The timing at which the third control signal operates is set to substantially coincide with the timing at which the inverted signal of the second control signal operates. The semiconductor device according to claim 4 .

6. Outside the semiconductor device, a first end of an inductor connected to the switch terminal; a first electrode of a capacitor connected to the second end of the inductor and to a feedback terminal; a second electrode of the capacitor connected to the first power supply; The voltage of the first electrode of the capacitor is input to the first control circuit. The semiconductor device according to claim 1 .

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