Method of manufacturing semiconductor device and inspection method for semiconductor device

Abstract

To provide a method of manufacturing a chip of which the avalanche resistance is high, and an inspection method for a semiconductor device.SOLUTION: A semiconductor device comprises a semiconductor substrate having a first principal surface and a plurality of chip regions formed within a plane of the semiconductor substrate, and a field effect transistor is formed in each of the plurality of chip regions. In a method of manufacturing a semiconductor device, the step of inspecting chip regions includes the steps of: acquiring a breakdown voltage of the field effect transistor for each chip region; approximating the dependency of the breakdown voltage on positions of chip regions disposed side by side along a first axis parallel to the first principal surface with a first high-order function; calculating a first derivative by once differentiating the first high-order function at the positions; and determining a quality of the chip regions disposed side by side along the first axis based on the first derivative. In the step of the determination on the basis of the first derivative, a chip region at a position where a value of the first derivative is larger than a first determinative value is determined as a defect.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a method for inspecting a semiconductor device. [Background technology]

[0002] A semiconductor device with a superjunction structure is disclosed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-165065 Summary of the Invention [Problem to be solved by the invention]

[0004] When a plurality of chip regions are formed within the surface of a semiconductor substrate, the avalanche resistance may vary among the chip regions.

[0005] An object of the present disclosure is to provide a method for manufacturing a semiconductor device and a method for inspecting a semiconductor device that enable the manufacture of chips with high avalanche resistance. [Means for solving the problem]

[0006] A manufacturing method of a semiconductor device disclosed herein is a manufacturing method of a semiconductor device including a field effect transistor, the semiconductor device having a semiconductor substrate having a first main surface and a plurality of chip regions formed within the surface of the semiconductor substrate, with a field effect transistor formed in each of the plurality of chip regions, the method comprising the steps of: acquiring a breakdown voltage of the field effect transistor for each of the chip regions; approximating the dependence of the breakdown voltage on the position of the chip regions aligned along a first axis parallel to the first main surface with a first higher-order function; differentiating the first higher-order function once with respect to the position to calculate a first derivative; and judging the pass / fail of the chip regions aligned along the first axis based on the first derivative, wherein the step of making the judgment based on the first derivative includes judging that the chip regions positioned where the value of the first derivative is greater than a first judgment value are defective. [Effects of the Invention]

[0007] According to the present disclosure, chips with high avalanche resistance can be manufactured. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a diagram showing a chip area of ​​the semiconductor device according to the embodiment. [Figure 3] FIG. 3 is a cross-sectional view showing a chip region of the semiconductor device according to the embodiment. [Figure 4] FIG. 4 is a flow diagram showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 5] FIG. 5 is a cross-sectional view (part 1) showing a step of forming a chip region. [Figure 6] FIG. 6 is a cross-sectional view (part 2) showing the step of forming the chip region. [Figure 7] FIG. 7 is a cross-sectional view (part 3) showing the step of forming the chip region. [Figure 8] FIG. 8 is a flow diagram showing the steps of inspecting the chip area. [Figure 9] FIG. 9 is a diagram showing the distribution of variations in breakdown voltage. DETAILED DESCRIPTION OF THE INVENTION

[0009] The embodiments for carrying out the invention are described below.

[0010] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described. In the following description, identical or corresponding elements will be assigned the same reference numerals, and the same description will not be repeated. In the following description, an XYZ Cartesian coordinate system is used, but this coordinate system is defined for the purpose of explanation and does not limit the orientation of the silicon carbide semiconductor device. The XY plane view is referred to as a planar view, and the +Z direction from an arbitrary point may be referred to as upward, upper side, or top, and the -Z direction may be referred to as downward, lower side, or bottom.

[0011] [1] A method for manufacturing a semiconductor device according to one embodiment of the present disclosure includes a semiconductor substrate having a first main surface and a plurality of chip regions formed within the semiconductor substrate, each of which includes a field-effect transistor. The method includes the steps of: acquiring a breakdown voltage of the field-effect transistor for each of the chip regions; approximating the dependency of the breakdown voltage on the position of the chip regions aligned along a first axis parallel to the first main surface using a first higher-order function; calculating a first derivative by differentiating the first higher-order function once with respect to the position; and determining whether the chip regions aligned along the first axis are defective based on the first derivative. The determining step includes determining whether the chip regions aligned along the first axis are defective if the value of the first derivative is greater than a first determination value. In this case, chip regions including field-effect transistors with low breakdown voltages can be extracted and removed from the plurality of chip regions aligned along the first axis. This allows the manufacture of chips with high avalanche resistance.

[0012] [2] In [1], the first judgment value may be determined based on an average value of the first derivative calculated for each of the plurality of chip regions aligned along the first axis, thereby improving the sensitivity of detecting defective products.

[0013] [3] In [2], the step of determining based on the first derivative may include determining that the chip region at a position where the ratio of the value of the first derivative to the average value is greater than 5% is defective, thereby improving the sensitivity of detecting defective products.

[0014] [4] In any of [1] to [3], for each of the chip regions having different positions on a second axis parallel to the first main surface and perpendicular to the first axis, a step of approximating with the first higher-order function, a step of calculating the first derivative, and a step of making a judgment based on the first derivative may be performed. In this case, it is possible to judge whether the chip region is defective at different positions on the second axis.

[0015] [5] In any of [1] to [4], the method may further include the steps of: approximating the dependency of the breakdown voltage on the position of the chip regions aligned along a second axis parallel to the first main surface and perpendicular to the first axis with a second higher-order function; calculating a second derivative by differentiating the second higher-order function once with respect to the position; and determining the pass / fail of the chip regions based on the second derivative, wherein the determining based on the second derivative may include determining that the chip regions at positions where the value of the second derivative is greater than a second determination value are defective. In this case, chip regions including field-effect transistors with low breakdown voltages can be extracted and removed from the multiple chip regions aligned along the second axis. This allows the manufacture of chips with high avalanche resistance.

[0016] [6] In [5], the step of approximating with the second higher-order function, the step of calculating the second derivative, and the step of determining may be performed for each of the chip areas whose positions on the first axis are different. In this case, it can be determined whether or not the chip area is defective at different positions on the first axis.

[0017] [7] In any of [1] to [6], the breakdown voltage may be a drain-source voltage when the drain current of the field-effect transistor is 1 mA. In this case, the breakdown voltage is easy to obtain.

[0018] [8] In any of [1] to [7], the first axis may be parallel to an orientation flat provided on the semiconductor substrate. In this case, a chip region including a field-effect transistor with a low breakdown voltage can be extracted and removed from a plurality of chip regions aligned parallel to the orientation flat.

[0019] [9] Another aspect of the present disclosure provides a semiconductor device inspection method for a semiconductor device including a field-effect transistor, the semiconductor device including a semiconductor substrate having a first main surface and multiple chip regions formed within the semiconductor substrate, each of the multiple chip regions including a field-effect transistor. The method includes the steps of: acquiring a breakdown voltage of the field-effect transistor for each of the multiple chip regions; approximating the dependency of the breakdown voltage on the position of the chip regions aligned along a first axis parallel to the first main surface using a first higher-order function; calculating a first derivative by differentiating the first higher-order function once with respect to the position; and determining whether the chip regions aligned along the first axis are defective based on the first derivative. The determining step based on the first derivative includes determining as defective any chip region where the value of the first derivative is greater than a first determination value. In this case, chip regions including field-effect transistors with low breakdown voltages can be extracted and removed from the multiple chip regions aligned along the first axis. This allows for the manufacture of chips with high avalanche resistance.

[0020] [Details of the embodiments of the present disclosure] [Configuration of Semiconductor Device] An embodiment of the present disclosure relates to a so-called vertical MOS (Metal Oxide Semiconductor) field effect transistor (FET) using silicon carbide. FIG. 1 is a diagram showing a semiconductor device 200 according to the embodiment. FIG. 2 is a diagram showing a chip region 100 of the semiconductor device 200 according to the embodiment. FIG. 3 is a cross-sectional view showing the chip region 100 of the semiconductor device 200 according to the embodiment. FIG. 3 corresponds to a cross-sectional view taken along line III-III in FIG. 2.

[0021] As shown in FIG. 1, a semiconductor device 200 according to the embodiment has a plurality of chip regions 100. The plurality of chip regions 100 are arranged in an array. For example, the planar shape of each chip region 100 is rectangular. Each chip region 100 has a common configuration. A dicing region is provided between adjacent chip regions 100. A plurality of chips are obtained by dividing along the dicing region.

[0022] As shown in FIGS. 2 and 3, the chip region 100 has a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, and a drain electrode .

[0023] The silicon carbide substrate 10 is an example of a semiconductor substrate. When the silicon carbide substrate 10 is used, an excellent breakdown voltage can be easily obtained. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The first main surface 1 and the second main surface 2 are parallel to the XY plane. The first main surface 1 is in the +Z direction as viewed from the second main surface 2. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide epitaxial layer 40 includes the first main surface 1. The silicon carbide single crystal substrate 50 includes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 include, for example, hexagonal silicon carbide of polytype 4H. Silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen (N) and has n-type conductivity (first conductivity type).

[0024] The silicon carbide epitaxial layer 40 includes a drift region 11, a body region 12, a source region 13, and a contact region 18.

[0025] Drift region 11 contains n-type impurities such as nitrogen or phosphorus (P) and has n-type conductivity. Drift region 11 is provided on silicon carbide single crystal substrate 50. An electric field relaxation region may be provided in drift region 11. The electric field relaxation region has p-type conductivity (second conductivity type).

[0026] The body region 12 contains p-type impurities such as aluminum (Al) and has p-type conductivity. The body region 12 is provided on the drift region 11. The lower end surface of the body region 12 contacts the upper end surface of the drift region 11.

[0027] The source region 13 contains n-type impurities such as nitrogen or phosphorus and has n-type conductivity. The source region 13 is provided on the body region 12. The source region 13 is separated from the drift region 11 by the body region 12. The source region 13 includes the first main surface 1.

[0028] A plurality of gate trenches 5 defined by side surfaces 3 and bottom surfaces 4 are provided on the first main surface 1. The gate trenches 5 extend, for example, along the Y axis. The plurality of gate trenches 5 are provided at regular intervals along the X axis. The side surfaces 3 penetrate the source region 13, the body region 12, and part of the drift region 11, and reach the drift region 11. The bottom surfaces 4 are continuous with the side surfaces 3. The bottom surfaces 4 are located in the drift region 11. The bottom surfaces 4 are, for example, parallel to the first main surface 1 and the second main surface 2. The side surfaces 3 are inclined with respect to a plane including the bottom surfaces 4.

[0029] The contact region 18 contains p-type impurities such as aluminum and has p-type conductivity. The contact region 18 penetrates the source region 13 and the body region 12 and is in contact with the drift region 11. The contact region 18 includes the first main surface 1. In a plan view perpendicular to the first main surface 1, the contact region 18 is located between adjacent gate trenches 5 along the X-axis.

[0030] The gate insulating film 81 includes, for example, silicon dioxide. The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 contacts the side surface 3 and the bottom surface 4. The gate insulating film 81 contacts the drift region 11 at the bottom surface 4. The gate insulating film 81 contacts the source region 13, the body region 12, and the drift region 11 at the side surface 3. The gate insulating film 81 may contact the source region 13 at the first main surface 1.

[0031] The gate electrode 82 is formed of, for example, polysilicon containing conductive impurities. The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is disposed inside the gate trench 5. The gate electrode 82 faces the side surface 3 and the bottom surface 4. A portion of the gate electrode 82 may face the first main surface 1. The gate electrode 82 extends along the Y axis.

[0032] The interlayer insulating film 83 includes, for example, silicon dioxide. The interlayer insulating film 83 covers the gate electrode 82. The interlayer insulating film 83 is in contact with the gate insulating film 81 and the gate electrode 82. The interlayer insulating film 83 electrically insulates the gate electrode 82 from the source electrode 60. A part of the interlayer insulating film 83 may be provided inside the gate trench 5. The upper surface of the interlayer insulating film 83 may be flat. The upper surface of the interlayer insulating film 83 may be a curved surface whose curvature changes continuously. The upper surface of the interlayer insulating film 83 may be a curved surface that is convex in the +Z direction above the gate trench 5.

[0033] Contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81 at regular intervals along the X-axis. The contact holes 90 are arranged such that the gate trench 5 is located between adjacent contact holes 90 along the X-axis. The contact holes 90 extend along the Y-axis. Through the contact holes 90, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81.

[0034] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 has a contact electrode 61 and a source wiring 62. The contact electrode 61 is provided in the contact hole 90. The contact electrode 61 is in contact with the source region 13 and the contact region 18 on the first main surface 1. The contact electrode 61 is formed of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be formed of a material containing, for example, titanium (Ti), aluminum, and silicon. The contact electrode 61 forms an ohmic junction with the source region 13 and the contact region 18. The source wiring 62 covers the upper surface and side surfaces of the interlayer insulating film 83 and the upper surface of the contact electrode 61. The source wiring 62 is in contact with the interlayer insulating film 83 and the contact electrode 61. The source wiring 62 is formed of a material containing, for example, aluminum.

[0035] The chip region 100 has a gate runner 63. The gate runner 63 is formed simultaneously with the source electrode 60 and is made of the same material as the source electrode 60. The gate runner 63 is electrically connected to the gate electrode 82.

[0036] The chip region 100 has a passivation film 87. The passivation film 87 covers the upper surface of the source electrode 60. An opening 121 is formed in the passivation film 87, exposing a portion of the source electrode 60. The opening 121 is formed between two gate runners 63 adjacent to each other along the Y axis. A plating film 86 for the source is formed in the opening 121. The plating film 86 is, for example, a nickel plating film. An opening 122 is formed in the passivation film 87, exposing a portion of the gate pad 65 connected to the gate runner 63. A plating film for the gate is formed in the opening 122. An opening 123 may be formed in the passivation film 87, in addition to the openings 121 and 122.

[0037] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 at the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is formed of a material containing nickel silicide, for example. The drain electrode 70 may be formed of a material containing titanium, aluminum, and silicon. The drain electrode 70 is in ohmic contact with the silicon carbide single crystal substrate 50.

[0038] [Method for manufacturing semiconductor device] Next, a method for manufacturing the semiconductor device 200 will be described. Fig. 4 is a flow diagram showing a method for manufacturing the semiconductor device 200 according to the embodiment. As shown in Fig. 4, the method for manufacturing the semiconductor device 200 according to the embodiment includes a step S1 of forming the chip region 100 and a step S2 of inspecting the chip region 100.

[0039] A description will now be given of step S1 of forming the chip region 100. Figures 5 to 7 are cross-sectional views showing step S1 of forming the chip region 100.

[0040] First, as shown in Fig. 5, a silicon carbide single crystal substrate 50 is prepared. Next, a silicon carbide epitaxial layer 40 is formed on the silicon carbide single crystal substrate 50. For example, the silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen and has n-type conductivity. For example, the silicon carbide epitaxial layer 40 can be formed by epitaxial growth with the addition of n-type impurities such as nitrogen.

[0041] 6, ions are implanted into the silicon carbide epitaxial layer 40 to form the body region 12, the source region 13, and the contact region 18. The remaining portion of the silicon carbide epitaxial layer 40 becomes the drift region 11.

[0042] 7, a plurality of gate trenches 5 are formed. Next, a gate insulating film 81, a gate electrode 82, and an interlayer insulating film 83 are formed. Next, contact holes 90 are formed in the gate insulating film 81 and the interlayer insulating film 83.

[0043] Next, the source electrode 60, the gate pad 65, the drain electrode 70, the passivation film 87, and the plating film 86 are formed (see FIGS. 1 and 2). The plating film 86 can be formed by, for example, electroless plating. In this manner, a plurality of chip regions 100 in which field-effect transistors are formed can be formed.

[0044] A description will be given of step S2 of inspecting the chip region 100. Step S2 of inspecting the chip region 100 is performed after step S1 of forming the chip region 100.

[0045] Fig. 8 is a flow chart showing step S2 of inspecting chip region 100. Fig. 9 is a diagram showing the distribution of variations in breakdown voltage VB. In Fig. 9, the X axis is parallel to the orientation flat provided on silicon carbide substrate 10.

[0046] First, in step S21, the breakdown voltage VB of the field effect transistor is obtained for each chip region 100. The breakdown voltage VB is the drain-source voltage when a predetermined drain current flows when the gate-source voltage is zero. The voltage applied between the drain and source may be gradually increased from zero when the gate-source voltage is zero, and the drain-source voltage measured when the drain current reaches a predetermined drain current may be taken as the breakdown voltage VB. The predetermined drain current is, for example, 1 mA. In this case, the breakdown voltage VB is easy to obtain.

[0047] In step S21, for multiple chip regions 100 whose position along the Y axis is 5 (see region A1 in FIG. 9), the breakdown voltage VB of the field-effect transistor may be obtained for each chip region 100. That is, the breakdown voltages VB(1,5), VB(2,5), VB(3,5), VB(4,5), VB(5,5), VB(6,5), VB(7,5), VB(8,5), and VB(9,5) may be obtained. The breakdown voltage VB(a,b) indicates the breakdown voltage VB at the position a along the X axis and the position b along the Y axis. In the example shown in FIG. 9, a is any value from 1 to 9, and b is any value from 1 to 9.

[0048] Next, in step S22, the dependency of the breakdown voltage VB on the position of the multiple chip regions 100 aligned along the X axis is approximated by a high-order function. The X axis is parallel to an orientation flat provided on the silicon carbide substrate 10. In this case, among the multiple chip regions 100 aligned parallel to the orientation flat, chip regions 100 including field-effect transistors with low breakdown voltages VB can be extracted and removed. The X axis is an example of a first axis. The high-order function is an example of a first high-order function. The high-order function is, for example, a quadratic function. The high-order function may be a cubic or higher order function.

[0049] Next, in step S23, a first derivative is calculated by differentiating the high-order function calculated in step S22 once at the position of the chip region 100. The first derivative is an example of a first derivative.

[0050] Next, in step S24, the pass / fail of the multiple chip regions 100 aligned along the X-axis is determined based on the first derivative calculated in step S23. In step S24, the chip regions 100 at positions where the value of the first derivative is greater than a determination value are determined to be defective. The determination value is an example of a first determination value. In step S24, the chip regions 100 at positions where the ratio of the value of the first derivative to the determination value is greater than 5% may be determined to be defective. In this case, the sensitivity of defective product detection is improved. The determination value may be determined based on the average value of the first derivative values ​​calculated for each of the multiple chip regions 100 at position 5 along the Y-axis. In this case, the sensitivity of defective product detection is improved. The determination value may be determined based on the average value of the first derivative values ​​calculated for all chip regions 100 included in the same semiconductor device 200.

[0051] Next, in step S25, the chip regions 100 determined to be defective in step S24 are designated as removal targets, and the process ends. The chip regions 100 designated as removal targets are removed after being diced along the dicing region.

[0052] In the trench-type MOSFET using silicon carbide described above (see FIG. 3 ), a field relaxation region is provided directly below or on both sides of the gate trench 5 to reduce electric field concentration in the gate insulating film 81 at the bottom surface 4 of the gate trench 5 during avalanche operation. The field relaxation region contains p-type impurities and has p-type conductivity. The breakdown voltage of the field relaxation region varies depending on the width of the field relaxation region in the unit transistor cell and the concentration of the p-type impurities. The breakdown voltage of the field relaxation region also varies depending on the concentration of n-type impurities and the film thickness of the drift region 11 adjacent to the field relaxation region. As a result, the breakdown voltage VB of the field-effect transistor varies within the plane of the silicon carbide substrate 10.

[0053] The electric field relaxation region is formed, for example, by ion implantation into the silicon carbide epitaxial layer 40 using an implantation mask and activation annealing performed after the ion implantation. During activation annealing, the silicon carbide substrate 10 becomes hot. For this reason, the implantation mask is formed by depositing a film of a heat-resistant inorganic material such as silicon oxide or polysilicon and opening the inorganic material by reactive ion etching using a resist mask. The width of the opening in the implantation mask made of inorganic material is likely to vary within the surface of the silicon carbide substrate 10 due to warpage of the silicon carbide substrate 10 and the coverage of the resist mask. As a result, the breakdown voltage VB of the field-effect transistor varies within the surface of the silicon carbide substrate 10.

[0054] As a result, the surface of silicon carbide substrate 10 includes chip region 100 including a field-effect transistor with a low breakdown voltage VB. In this case, when the field-effect transistor in the inductive load circuit is turned off, the energy stored in the inductive load is concentrated in chip region 100 including the field-effect transistor with a low breakdown voltage VB. This accelerates the heat generation in chip region 100 where the energy is concentrated, and the avalanche resistance decreases. The decrease in avalanche resistance becomes more pronounced as the cell pitch becomes smaller.

[0055] When removing chip regions 100 with low avalanche resistance, a method can be considered in which an avalanche action is generated for each chip region 100 to destroy the field-effect transistors with low avalanche resistance. In this case, particles scattered from the destroyed field-effect transistors may contaminate other field-effect transistors or damage the inspection equipment.

[0056] According to the manufacturing method of the semiconductor device 200 according to the embodiment, first, in step S21, the breakdown voltage VB of the field-effect transistor is obtained for each chip region 100. Next, in step S22, the dependency of the breakdown voltage VB on the position of the multiple chip regions aligned along the X-axis is approximated by a high-order function. Next, in step S23, the high-order function calculated in step S22 is differentiated once with respect to the position of the chip region 100 to calculate a first derivative. Next, in step S24, the pass / fail of the multiple chip regions 100 aligned along the X-axis is determined based on the first derivative calculated in step S23. In step S24, chip regions 100 positioned where the value of the first derivative is greater than a determination value are determined to be defective. In this case, chip regions 100 including field-effect transistors with low breakdown voltages VB can be extracted and removed from the multiple chip regions 100 aligned along the X-axis. This allows the manufacture of chips with high avalanche resistance.

[0057] In the above-described step S2 of inspecting the chip areas 100, the pass / fail determination has been described for multiple chip areas 100 at position 5 along the Y axis, but the present disclosure is not limited to this. For example, the pass / fail determination may be performed for multiple chip areas 100 at positions 1, 2, 3, 4, 6, 7, 8, and 9 along the Y axis. In other words, in the step S2 of inspecting the chip areas 100, steps S22 to S27 may be performed for each chip area 100 at a different position along the Y axis.

[0058] In the above-described step S2 of inspecting the chip regions 100, the pass / fail judgment has been described for multiple chip regions 100 aligned along the X axis, but the present disclosure is not limited to this. For example, the pass / fail judgment may be performed for multiple chip regions 100 aligned along an axis tilted at a first angle with respect to the X axis. The first angle may be 90°. In other words, the pass / fail judgment may be performed for multiple chip regions 100 aligned along the Y axis (see region A2 in FIG. 9). The first angle may be greater than 0° and less than 90°.

[0059] In the above step S2 of inspecting chip regions 100, the case where 65 chip regions 100 are arranged on silicon carbide substrate 10 has been described. However, the number of chip regions 100 is not limited to 65.

[0060] Although the embodiments have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0061] 1 First main surface 2 Second main surface 3. Aspects 4 Bottom 5. Gate trench 10 Silicon carbide substrate 11 Drift Region 12 Body Region 13 Source Region 18 Contact Area 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 Source electrode 61 Contact electrode 62 Source wiring 63 Gate Runner 65 Gate Pad 70 drain electrode 81 Gate insulating film 82 gate electrode 83 Interlayer insulating film 86 Plating film 87 Passivation Film 90 Contact Holes 100 chip area 121 Opening 122 Opening 123 Opening 200 Semiconductor device VB Breakdown voltage

Claims

1. A method for manufacturing a semiconductor device including a field effect transistor, comprising: The semiconductor device includes a semiconductor substrate having a first main surface and a plurality of chip regions formed within the surface of the semiconductor substrate; the field effect transistor is formed in each of the plurality of chip regions, obtaining a breakdown voltage of the field effect transistor for each of the chip regions; approximating the dependence of the breakdown voltage on the position of the chip regions aligned along a first axis parallel to the first main surface with a first higher-order function; differentiating the first higher-order function once with respect to the position to calculate a first derivative; determining whether the chip regions aligned along the first axis are good or bad based on the first derivative; and the step of determining based on the first derivative includes determining that the chip region at a position where the value of the first derivative is greater than a first determination value is defective. A method for manufacturing a semiconductor device.

2. the first determination value is determined based on an average value of the values ​​of the first derivative calculated for each of the plurality of chip regions arranged along the first axis; The method for manufacturing a semiconductor device according to claim 1 .

3. the step of determining based on the first derivative includes determining that the chip region at a position where the ratio of the value of the first derivative to the average value is greater than 5% is defective. The method for manufacturing a semiconductor device according to claim 2 .

4. performing a step of approximating the first high-order function, a step of calculating the first derivative, and a step of determining based on the first derivative for each of the chip regions that differ in position along a second axis that is parallel to the first main surface and perpendicular to the first axis; The method for manufacturing a semiconductor device according to any one of claims 1 to 3.

5. approximating, by a second higher-order function, the dependency of the breakdown voltage on the position of the chip regions aligned along a second axis parallel to the first main surface and perpendicular to the first axis; differentiating the second higher-order function once with respect to the position to calculate a second derivative; determining whether the chip area is good or bad based on the second derivative; and the step of determining based on the second derivative includes determining that the chip region at a position where the value of the second derivative is greater than a second determination value is defective. The method for manufacturing a semiconductor device according to any one of claims 1 to 3.

6. performing the step of approximating with the second higher-order function, the step of calculating the second derivative, and the step of determining for each of the chip regions having different positions on the first axis; The method for manufacturing a semiconductor device according to claim 5 .

7. The breakdown voltage is the drain-source voltage when the drain current of the field effect transistor is 1 mA. The method for manufacturing a semiconductor device according to any one of claims 1 to 3.

8. the first axis is parallel to an orientation flat provided on the semiconductor substrate; The method for manufacturing a semiconductor device according to any one of claims 1 to 3.

9. A method for testing a semiconductor device including a field effect transistor, comprising: The semiconductor device includes a semiconductor substrate having a first main surface and a plurality of chip regions formed within the surface of the semiconductor substrate; the field effect transistor is formed in each of the plurality of chip regions, obtaining a breakdown voltage of the field effect transistor for each of the chip regions; approximating the dependence of the breakdown voltage on the position of the chip regions aligned along a first axis parallel to the first main surface with a first higher-order function; differentiating the first higher-order function once with respect to the position to calculate a first derivative; determining whether the chip regions aligned along the first axis are good or bad based on the first derivative; and the step of determining based on the first derivative includes determining that the chip region at a position where the value of the first derivative is greater than a first determination value is defective. A method for inspecting a semiconductor device.

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