Monitoring circuit and register control device

Abstract

To provide a monitoring circuit capable of suppressing increases in both a mounting area and cost.SOLUTION: A monitoring circuit (2) includes a first arithmetic circuit (21) configured so as to calculate a first CRC value being a CRC value of data to be written in a register (3), second arithmetic circuits (22_1 to 22_n) configured so as to calculate a second CRC value being a CRC value of a register value of the register, storage circuits (23_1 to 23_n) configured so as to store the first CRC value, and comparator circuits (24_1 to 24_n) configured so as to compare the first CRC value stored in the storage circuits with the second CRC value.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a monitoring circuit configured to monitor soft errors in a register and a register control device including the monitoring circuit. [Background technology]

[0002] A semiconductor integrated circuit device such as a power supply IC (Integrated Circuit) includes a register (see, for example, Patent Document 1). The semiconductor integrated circuit device operates according to various settings stored in the register. Therefore, by changing the various settings stored in the register, the operation of the semiconductor integrated circuit device can be changed.

[0003] When radiation such as cosmic rays passes through or strikes a semiconductor integrated circuit device, electron-hole pairs are generated, which can invert the value held in a register, resulting in a soft error.

[0004] When a soft error occurs in a register, the operation of the semiconductor integrated circuit device can change unintentionally. Therefore, highly reliable semiconductor integrated circuit devices such as in-vehicle semiconductor integrated circuit devices require a monitoring circuit configured to monitor soft errors in the register. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-158289

[0006] [overview] The simplest monitoring method is to have two registers and constantly compare the values ​​held in the paired registers.

[0007] However, this method requires twice as many registers, which is quite disadvantageous in terms of mounting area and cost.

[0008] The monitoring circuit according to the present disclosure comprises a first arithmetic circuit configured to calculate a first CRC value, which is a CRC value of data to be written to a register; a second arithmetic circuit configured to calculate a second CRC value, which is a CRC value of a register value of the register; a memory circuit configured to store the first CRC value; and a comparison circuit configured to compare the first CRC value stored in the memory circuit with the second CRC value.

[0009] A register control device according to the present disclosure includes a monitoring circuit having the above configuration, the register, and a control circuit configured to write data to the register, the control circuit configured to perform control based on the output of the monitoring circuit. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram illustrating a configuration of a register control device according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a diagram illustrating a modified example of the register control device according to the embodiment of the present disclosure.

[0011] [Detailed explanation] 1 is a diagram showing the configuration of a register control device according to an embodiment of the present disclosure. The register control device 1 shown in FIG. 1 includes a monitoring circuit 2, a register 3, and a control circuit 4.

[0012] The monitoring circuit 2 monitors soft errors in the register 3. The register 3 has n addresses, and stores data (e.g., 8-bit data) at each address. n is a natural number equal to or greater than 2. The control circuit 4 is configured, for example, with a CPU (Central Processing Unit) or the like, and writes data to and reads data from the register 3. The control circuit 4 also performs control based on the output of the monitoring circuit 2. For example, when the output of the monitoring circuit 2 indicates the occurrence of a soft error in the register 3, the control circuit 4 can update the soft error register of the register 3 to an error and notify a system (not shown) such as an MCU of the soft error.

[0013] The monitoring circuit 2 includes a first arithmetic circuit 21, second arithmetic circuits 22_1 to 22_n, memory circuits 23_1 to 23_n, comparison circuits 24_1 to 24_n, and an OR circuit 25.

[0014] The first arithmetic circuit 21 calculates a first CRC value, which is a CRC (Cyclic Redundancy Check) value for data to be written to the register 3. Because soft errors caused by radiation such as cosmic rays result in at most one-bit data corruption, in this embodiment, parity values ​​are used as both the first CRC value and a second CRC value, which will be described later. That is, in this embodiment, both the first CRC value and a second CRC value, which will be described later, are parity values. When both the first CRC value and a second CRC value, which will be described later, are parity values, the first CRC value and a second CRC value, which will be described later, can be calculated using only exclusive logic. Note that the first CRC value and a second CRC value, which will be described later, may each be a CRC value other than a parity value.

[0015] The first arithmetic circuit 21 is a circuit common to all addresses of the register 3. Therefore, every time the control circuit 4 writes data to the register 3, the control circuit 4 supplies the first arithmetic circuit 21 with the same data as the data written to the register 3. The first arithmetic circuit 21 outputs a first CRC value to the storage circuits 23_1 to 23_n.

[0016] The second arithmetic circuits 22_1 to 22_n, the storage circuits 23_1 to 23_n, and the comparison circuits 24_1 to 24_n are provided for each address of the register 3.

[0017] The second arithmetic circuits 22_1 to 22_n constantly calculate second CRC values ​​which are CRC values ​​of the register values ​​of the register 3. The second arithmetic circuit 22_k constantly calculates second CRC values ​​which are CRC values ​​of data written to the kth address of the register 3 (the register value written to the kth address). The control circuit 4 reads the data to be written to each address in the register 3 from the register 3, and supplies the data written to the kth address of the register 3 (the register value written to the kth address) to the second arithmetic circuit 22_k. Here, k is any natural number between 1 and n.

[0018] The storage circuits 23_1 to 23_n store the first CRC value. The storage circuits 23_1 to 23_n store the first CRC value output from the first arithmetic circuit 21 at the timing when they receive a trigger signal from the control circuit 4. When the control circuit 4 writes data to the kth address in the register 3, the control circuit 4 outputs a trigger signal to the storage circuit 23_k. That is, the storage circuit 23_k stores the first CRC value calculated by the first arithmetic circuit 21 when the control circuit 4 writes data to the kth address in the register 3.

[0019] The comparison circuits 24_1 to 24_n constantly compare the first CRC values ​​stored in the respective storage circuits 23_1 to 23_n with the second CRC values ​​calculated by the respective second arithmetic circuits 22_1 to 22_n. That is, the comparison circuit 24_k constantly compares the first CRC value stored in the storage circuit 23_k with the second CRC value calculated by the second arithmetic circuit 22_k, and outputs "0" indicating that a soft error has not occurred if the comparison results in a match, and outputs "1" indicating that a soft error has occurred if the comparison results in a mismatch.

[0020] The OR circuit 25 generates a logical sum of the outputs of the comparison circuits 24_1 to 24_n and outputs the logical sum to the control circuit 4.

[0021] <Other> The above-described embodiments should be considered to be illustrative in all respects and not restrictive. The technical scope of the present disclosure is indicated by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0022] For example, the register control device 1 shown in Fig. 1 may be modified into the register control device 1 shown in Fig. 2. The register control device 1 shown in Fig. 2 differs from the register control device 1 shown in Fig. 1 in that the monitoring circuit 2 does not include the OR circuit 25, but is otherwise similar to the register control device 1 shown in Fig. 1. In the register control device 1 shown in Fig. 2, the outputs of the comparison circuits 24_1 to 24_n are supplied to a control circuit 4.

[0023] <Additional Notes> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0024] The monitoring circuit (2) of the present disclosure has a configuration (first configuration) including a first arithmetic circuit (21) configured to calculate a first CRC value, which is the CRC value of data to be written to a register (3), second arithmetic circuits (22_1 to 22_n) configured to calculate a second CRC value, which is the CRC value of the register value of the register, memory circuits (23_1 to 23_n) configured to store the first CRC value, and comparison circuits (24_1 to 24_n) configured to compare the first CRC value stored in the memory circuits with the second CRC value.

[0025] According to the monitoring circuit of the first configuration, there is no need to have twice as many registers, so it is possible to suppress increases in both the mounting area and costs.

[0026] In the monitoring circuit of the first configuration, the first CRC value and the second CRC value may each be a parity value (second configuration).

[0027] The monitoring circuit of the first or second configuration may have a configuration (third configuration) including the second arithmetic circuit, the memory circuit, and the comparison circuit for each address of the register.

[0028] The monitoring circuit of the third configuration may be configured (fourth configuration) to include an OR circuit (25) configured to generate a logical sum of the outputs of the plurality of comparison circuits provided for each address of the register.

[0029] The monitoring circuit of any one of the first to fourth configurations may have a configuration (fifth configuration) in which the first arithmetic circuit is common to all addresses of the register.

[0030] The register control device (1) of the present disclosure comprises a monitoring circuit of any one of the first to fifth configurations, the register, and a control circuit (4) configured to write data to the register, and the control circuit is configured to perform control based on the output of the monitoring circuit (sixth configuration). [Explanation of symbols]

[0031] 1 Register control device 2 Monitoring circuit 3 Registers 4 Control Circuit 21 1st calculation circuit 22_1~22_n Second arithmetic circuit 23_1~23_n Memory circuit 24_1~24_n Comparison circuit 25 OR Circuit

Claims

1. a first arithmetic circuit configured to calculate a first CRC value, the first CRC value being a CRC value of the data to be written to the register; a second arithmetic circuit configured to calculate a second CRC value, the second CRC value being a CRC value of the register value of the register; a storage circuit configured to store the first CRC value; a comparison circuit configured to compare the first CRC value stored in the storage circuit with the second CRC value; A monitoring circuit comprising:

2. 2. The monitoring circuit of claim 1, wherein the first CRC value and the second CRC value are each a parity value.

3. 2. The monitoring circuit according to claim 1, further comprising: the second arithmetic circuit, the memory circuit, and the comparison circuit for each address of the register.

4. 4. The monitoring circuit according to claim 3, further comprising an OR circuit configured to generate a logical sum of the outputs of the plurality of comparison circuits provided for each address of the register.

5. 2. The monitoring circuit according to claim 1, further comprising: said first arithmetic circuit being common to all addresses of said register.

6. A monitoring circuit according to any one of claims 1 to 5; the register; a control circuit configured to write data to the register; Equipped with The control circuit is configured to perform control based on the output of the monitoring circuit.

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