Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device and a manufacturing method thereof that can improve mounting reliability.SOLUTION: A semiconductor device includes: a semiconductor chip; leads spaced apart from the semiconductor chip; a conductive member electrically connecting at least one terminal of the semiconductor chip and the leads; and an encapsulant having a first main surface, a second main surface spaced apart from the first main surface, and a side surface located between the first main surface and the second main surface, and encapsulating the semiconductor chip and the conductive member.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Patent Document 1 (Japanese Patent Laid-Open Publication No. 2005-191240) discloses a semiconductor device having a recessed portion.

[0003] Patent document 2 (JP 2014-007287 A) discloses a method for manufacturing a semiconductor device, which includes a step of removing a portion of each of the first lead, the second lead, and the tie bar using a first blade having a first width that is wider than the width of the tie bar. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-191240 [Patent Document 2] Japanese Patent Application Laid-Open No. 2014-007287 Summary of the Invention [Problem to be solved by the invention]

[0005] Examples of non-leaded packages include QFN (Quad Flat No-lead package), DFN (Dual Flat No-lead package), and SON (Small Outline Non-leaded package). The mounting strength of conventional non-leaded packages after soldering is lower than that of, for example, QFP (Quad Flat Package). Therefore, non-leaded packages are unsuitable for products that require high mounting strength, such as those for automotive applications.

[0006] Therefore, it is necessary to provide a semiconductor device and a manufacturing method thereof that can improve mounting reliability. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment includes a lead. The lead has a first surface exposed from the outer surface of the encapsulant and a second surface spaced apart from the first surface and connected to the encapsulant. The lead also has a third surface located between the first and second surfaces and connected to the encapsulant, and a fourth surface located between the first and second surfaces and exposed from the outer surface of the encapsulant. The fourth surface includes a first side surface that is flush with a side surface of the encapsulant, a second side surface that connects to the first side surface and extends toward the third surface relative to the first side surface, and a third side surface that connects to the second side surface and the first surface and extends toward the first surface relative to the first surface. When viewed from a cross section perpendicular to the first surface and the first side surface, there is a region in which the distance from the second surface to a plane that includes the first surface and is parallel to the first surface increases toward the first side surface.

[0008] A method for manufacturing a semiconductor device according to one embodiment includes preparing a lead frame. The lead frame has a first lead, a portion of which is provided in a first device region and has a first protrusion protruding in a first direction. The lead frame also has a second lead, a portion of which is provided in a second device region and has a second protrusion protruding in the first direction. The lead frame also has tie bars connected to the first and second leads and spaced apart from the first and second device regions. The first direction is the thickness direction of the lead frame. [Effects of the Invention]

[0009] According to the embodiment, it is possible to provide a semiconductor device and a manufacturing method thereof that can improve mounting reliability. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a cross-sectional view showing a state in which the semiconductor device shown in FIG. 1 is mounted on a mounting surface of a mounting substrate via a bonding material. [Figure 3] FIG. 3 is a perspective plan view showing the internal structure of the semiconductor device with the sealing body removed. [Figure 4] FIG. 4 is an enlarged cross-sectional view showing a state in which the semiconductor device is mounted on the mounting surface of a mounting board via a bonding material. [Figure 5] FIG. 5 is an enlarged cross-sectional view showing a state in which a semiconductor device is mounted on a mounting surface of a mounting board via a bonding material when the upper surfaces of the leads are flat. [Figure 6] FIG. 6 is an enlarged cross-sectional view showing the semiconductor device shown in FIG. 1 placed on a mounting substrate. [Figure 7] FIG. 7 is an explanatory diagram that schematically shows the configuration of the appearance inspection process. [Figure 8] FIG. 8 is an explanatory diagram of a case where an appearance inspection step is performed in the configuration of another semiconductor device shown in FIG. [Figure 9] FIG. 9 is an explanatory diagram showing the assembly flow of a semiconductor device. [Figure 10] FIG. 10 is a plan view showing the structure of a lead frame prepared in the lead frame preparation step. [Figure 11] FIG. 11 is an enlarged cross-sectional view taken along line AA in FIG. [Figure 12] FIG. 12 is an explanatory diagram that schematically shows the configuration of a lead frame manufacturing process. [Figure 13] FIG. 13 is an enlarged plan view showing a state in which a semiconductor chip and a plurality of leads are electrically connected via wires. [Figure 14] FIG. 14 is an enlarged cross-sectional view taken along line AA in FIG. [Figure 15] FIG. 15 is an explanatory diagram that schematically shows the configuration of the wire bonding process. [Figure 16]FIG. 16 is a cross-sectional view showing a state in which a sealing body is formed in the device region of the lead frame shown in FIG. [Figure 17] FIG. 17 is a cross-sectional view showing a state in which a lead frame is placed in a molding die in the sealing step. [Figure 18] FIG. 18 is an enlarged cross-sectional view showing a state in which the lead frame shown in FIG. 16 has been cut to expose the lower surface side of the tie bar. [Figure 19] FIG. 19 is an enlarged cross-sectional view showing the dicing region and its periphery shown in FIG. 16 in a further enlarged manner. [Figure 20] FIG. 20 is an enlarged cross-sectional view showing the dicing region and its periphery shown in FIG. 18 in a further enlarged manner. [Figure 21] FIG. 21 is an enlarged cross-sectional view showing the periphery of a dicing region before cutting when the lead frame does not have a protruding portion. [Figure 22] FIG. 22 is an enlarged cross-sectional view showing a state in which the lead frame has no protrusions and has been cut to expose the lower surface side of the tie bar. [Figure 23] FIG. 23 is a plan view showing the lower surface side of the lead frame. [Figure 24] FIG. 24 is an enlarged cross-sectional view showing a state in which a metal film is formed on the exposed surfaces of the leads and die pad shown in FIG. [Figure 25] FIG. 25 is an enlarged plan view showing a state in which the lead frame shown in FIG. 23 is divided into individual device regions after a metal film is formed on the lead frame. [Figure 26] FIG. 26 is an enlarged cross-sectional view showing a state in which the lead frame shown in FIG. 24 is fixed to a dicing tape and separated into individual pieces. [Figure 27] FIG. 27 is an enlarged cross-sectional view showing the dicing region and its periphery in FIG. 26 in a further enlarged manner. DETAILED DESCRIPTION OF THE INVENTION

[0011] (Explanation of the description format, basic terms and usage in this application) In this application, the description of the embodiments will be divided into multiple sections, etc., for convenience, as necessary. However, unless otherwise expressly stated, these are not mutually independent and separate, and regardless of the order of description, they are each part of a single example, one being a partial detail of the other, or a partial or complete modification, etc. Furthermore, as a general rule, repeated explanations of similar parts will be omitted. Furthermore, each component in the embodiments is not essential unless otherwise expressly stated, there is a theoretical limit to the number, or it is clearly not essential from the context.

[0012] Similarly, in the description of embodiments, when a material, composition, etc. is described as "X consisting of A," this does not exclude elements other than A, unless otherwise expressly stated or clearly indicated by the context. For example, when referring to a component, it means "X containing A as its primary component." For example, a "silicon component" does not necessarily refer to pure silicon, but also includes SiGe (silicon-germanium) alloys and other multi-component alloys containing silicon as the primary component, as well as components containing other additives. Furthermore, unless otherwise expressly stated, gold plating, Cu layer, nickel plating, etc., include not only pure components but also components containing gold, Cu, nickel, etc. as their primary components.

[0013] Furthermore, even when a specific number or quantity is mentioned, unless otherwise specified, unless it is theoretically limited to that number, or unless it is clearly not the case from the context, the number may be greater than that specific number or less than that specific number.

[0014] Furthermore, in each drawing of the embodiment, the same or similar parts are indicated by the same or similar symbols or reference numbers, and descriptions thereof will not be repeated as a general rule.

[0015] In the accompanying drawings, hatching may be omitted even in cross sections if it would be too complicated or if the distinction from voids is clear. In relation to this, background contour lines may be omitted even in the case of holes that are closed in plan view if it is clear from the description, etc. Furthermore, hatching or dot patterns may be added even in cases where the drawing is not a cross section to clearly indicate that the hole is not a void or to clearly indicate the boundary of the area.

[0016] The technology described in the following embodiments can be applied to various package-type semiconductor devices in which the leads are exposed on the underside of the encapsulant. In this embodiment, as an example, an embodiment applied to a QFN-type semiconductor device in which multiple leads, which are external terminals, are exposed from the encapsulant on the underside (mounting surface) of the encapsulant will be described.

[0017] <Semiconductor device> First, an outline of the configuration of a semiconductor device 1 of this embodiment will be described. The semiconductor device 1 of this embodiment includes a die pad (chip mounting portion, tab) 2 (see FIGS. 1 and 2) and a semiconductor chip 3 (see FIGS. 1 and 2) mounted on the die pad 2 via a die bond material DB (see FIGS. 1 and 2). The semiconductor device 1 also includes a plurality of leads (terminals, external terminals) 4 arranged around the semiconductor chip 3 (die pad 2) and a plurality of wires (conductive members) 5 (see FIGS. 1 and 2). The plurality of wires 5 electrically connect a plurality of pads (electrodes, bonding pads) PD (see FIGS. 1 and 2) of the semiconductor chip 3 to the plurality of leads 4, respectively. A plurality of suspension leads TL are connected to the die pad 2. The semiconductor device 1 also includes an encapsulant (resin body) 6 that encapsulates the semiconductor chip 3, the plurality of wires 5, and portions of the plurality of leads 4.

[0018] First, the structure of the semiconductor device 1 will be described. The planar shape of the sealing body (resin body) 6 is rectangular. In this embodiment, the sealing body 6 is, for example, square. The sealing body 6 has an upper surface (main surface) 6a, a lower surface (main surface, back surface, mounting surface) 6b (see FIG. 1) opposite the upper surface 6a, and a side surface 6c located between the upper surface 6a and the lower surface 6b. In the example shown in FIG. 1, the side surface 6c is perpendicular to the upper surface 6a and the lower surface 6b.

[0019] 1, in the semiconductor device 1, a plurality of leads 4 are arranged along each side (side surface 6c) of the sealing body 6. Each of the plurality of leads 4 is made of a metal material. In this embodiment, the plurality of leads 4 is made of, for example, copper (Cu), or a laminated metal member in which a metal film SD made of, for example, nickel (Ni) is formed on the surface of a base material made of copper (Cu).

[0020] As shown in FIG. 1 , the lead 4 has a bottom surface 4b, a top surface 4a, a side surface 4d, and a side surface 4e. The bottom surface 4b is exposed from the outer surface of the sealing body 6. The top surface 4a is spaced apart from the bottom surface 4b and connected to the sealing body 6. The side surface 4d is located between the bottom surface 4b and the top surface 4a and connected to the sealing body 6. The side surface 4e is located between the bottom surface 4b and the top surface 4a and exposed from the outer surface of the sealing body 6. The bottom surface 4b may be substantially parallel to the bottom surface 6b. Here, "exposed from the outer surface of the sealing body 6" means that the lead is located outside the sealing body 6 beyond the outer surface of the sealing body 6. Even if the lead is covered by something other than the sealing body 6 and cannot be seen from the outside, it is said to be exposed from the outer surface of the sealing body 6 if it is located outside the sealing body 6 beyond the outer surface of the sealing body 6 beyond the outer surface of the sealing body 6.

[0021] The side surface 4e of the lead 4 includes a side surface 41a, a side surface 41b, and a side surface 41c. The side surface 41a is flush with the side surface 6c of the encapsulant 6. The side surface 41b is connected to the side surface 41a and extends toward the side surface 4d relative to the side surface 41a. The side surface 41c is connected to the side surface 41a and the bottom surface 4b and extends toward the top surface 6a of the encapsulant 6 relative to the bottom surface 4b. The side surface 41a may be substantially flush with the side surface 6c of the encapsulant 6. As shown in FIG. 1, the side surface 41b and the side surface 41c form a step portion 10 having a step.

[0022] In this embodiment, when viewed from a cross section perpendicular to the bottom surface 4b and the side surface 41a, there is a region 41e in which the height h1 of the lead 4 increases toward the side surface 41a. Here, the height h1 of the lead 4 refers to the distance from the top surface 4a to a reference plane. That is, there is a region 41e in which the distance from the top surface 4a to the reference plane increases toward the side surface 41a. In FIG. 1, the reference plane is a plane that includes the bottom surface 4b and is parallel to the bottom surface 4b. In the example shown in FIG. 1, the top surface 4a includes a region 41f that is substantially parallel to the bottom surface 4b. Furthermore, the region 41e is inclined with respect to the region 41f. That is, the region 41e is an inclined plane. Furthermore, the region 41f is located closer to the side surface 4d than the region 41e. It is preferable that the distance from the side surface 41b to a plane that includes the bottom surface 4b and is parallel to the bottom surface 4b be longer than half the distance from the region 41f to a plane that includes the bottom surface 4b and is parallel to the bottom surface 4b. The upper surface 4a preferably includes an area that is parallel to the lower surface 4b.

[0023] 1, the bottom surface 4b and side surface 4e of the lead 4 are exposed from the outer surface of the sealing body 6. The bottom surface 4b, side surface 41b, and side surface 41c are covered with a metal layer SD. The metal layer SD is a plated film formed by, for example, a plating method, and is made of, for example, a solder material, and functions as a bonding material when the lead 4 is bonded to a terminal on the mounting board, which will be described later.

[0024] The metal film SD (solder material) of this embodiment is made of so-called lead-free solder, which is substantially free of lead (Pb), such as tin (Sn) only, tin-bismuth (Sn-Bi), or tin-copper-silver (Sn-Cu-Ag). Here, lead-free solder refers to solder containing 0.1 wt% or less of lead (Pb), a limit stipulated by the RoHS (Restriction of Hazardous Substances) Directive. Hereinafter, when solder material or solder components are described in this embodiment, they refer to lead-free solder unless otherwise specified.

[0025] As shown in FIG. 1, a step 10 is formed by side surfaces 41b and 41c on the periphery of the lower surface (mounting surface) of the semiconductor device 1. The step 10 is continuously formed around the entire periphery of the lower surface of the semiconductor device 1. In the example shown in FIG. 2, each of the leads 4 includes a side surface 41b that is continuous with the side surface 41a and is located between the lower surface 4b and the upper surface 4a. A side surface 41c is located inside the side surface 41a and is continuous with the lower surface 4b and the side surface 41b. The sealing body 6 includes a step surface 6f that is continuous with the side surface 6c and is located between the lower surface 6b and the upper surface 6a. A side surface 6e is located inside the side surface 6c and is continuous with the lower surface 6b and the step surface 6f. As will be described in detail later, this configuration improves visibility during inspection after mounting. It also improves mounting strength.

[0026] 2, the side surface 41a of the lead 4 is exposed without being covered by the metal film SD. The reason why the side surface 41a is exposed from the metal film SD in this manner stems from the manufacturing method of the semiconductor device 1, and details will be explained when explaining the manufacturing method of the semiconductor device.

[0027] Next, as shown in FIG. 1 , the lower surface 2b of the die pad (chip mounting portion, tab) 2 is exposed from the sealing body 6 at the lower surface 6b of the sealing body 6. In other words, the semiconductor device 1 is an exposed-die-pad (exposed-tab) semiconductor device. The die pad 2 is made of a metal material with a higher thermal conductivity than the sealing body 6. In this embodiment, the die pad 2 is made of, for example, copper (Cu) or a laminated metal film in which a metal film SD made of, for example, nickel (Ni) is formed on the surface of a copper (Cu) substrate. In this manner, the exposed-die-pad semiconductor device can expose a metal member (die pad 2) such as copper (Cu) that has a higher thermal conductivity than the sealing body 6. Therefore, the exposed-die-pad semiconductor device can improve the heat dissipation performance of the package compared to a semiconductor device in which the die pad 2 is not exposed. In the example shown in FIGS. 1 and 2 , a metal film SD that functions as a bonding material during mounting is formed on the lower surface 2b of the die pad 2, covering the lower surface of the substrate. The metal film SD is a plating film (solder film) formed by, for example, a plating method, as described above.

[0028] As shown in FIG. 3, one end of the suspension lead TL (sealing portion TL1) is connected to (integrally formed with) the die pad 2, and the other end (exposed portion TL2) is exposed from the sealing body 6 at the corner 6k. That is, the suspension lead of this embodiment is a so-called I-suspension type. Since the suspension lead TL is integrally formed with the die pad 2, the suspension lead TL is made of the same metal material as the die pad 2. In this embodiment, the exposed die pad type semiconductor device is made of, for example, copper (Cu) or a laminated metal film in which a metal film (not shown) made of, for example, nickel (Ni) is formed on the surface of a copper (Cu) base material. In addition, a metal film (not shown) that functions as a bonding material during mounting is formed on the underside of the exposed portion of the suspension lead TL, covering the underside of the base material. The metal film SD is a solder film formed by, for example, plating, as described above.

[0029] In other words, the semiconductor device 1 has a step portion 10 formed continuously around the peripheral portion of the lower surface 6b of the sealing body, and at the step portion 10, multiple leads 4 and multiple suspension leads TL are exposed from the sealing body 6.

[0030] By exposing a portion of the suspension lead TL from the sealing body 6 in this manner, when the semiconductor device 1 is mounted on a mounting board described later, the exposed portion of the suspension lead TL can be joined to a terminal of the mounting board. This improves the mounting strength of the semiconductor device 1. However, as a modified example, a structure in which the exposed portion of the suspension lead TL is not provided as shown in FIG. 1 can be used.

[0031] Next, the internal structure of the semiconductor device 1 will be described. As shown in Fig. 3, the top surface (chip mounting surface) 2a of the die pad 2 has a quadrilateral (fourth side) planar shape. In this embodiment, the top surface 2a of the die pad 2 is, for example, a square. In the example shown in Fig. 3, the outer size (planar size) of the die pad 2 is larger than the outer size (planar size of the back surface 3b) of the semiconductor chip 3. In this way, by mounting the semiconductor chip 3 on the die pad 2 having an area larger than its outer size and exposing the bottom surface 2b of the die pad 2 from the sealing body 6, heat dissipation can be improved.

[0032] 3, a semiconductor chip 3 is mounted on the die pad 2. The semiconductor chip 3 is mounted in the center of the die pad 2. As shown in FIG. 1, the semiconductor chip 3 is mounted on the die pad 2 via a die bond material (adhesive) DB, with the back surface 3b facing the upper surface 2a of the die pad 2. That is, the semiconductor chip 3 is mounted by a so-called face-up mounting method, in which the surface (back surface 3b) opposite to the front surface (main surface) 3a on which the multiple pads PD are formed faces the chip mounting surface (upper surface 2a). This die bond material DB is an adhesive material used when die-bonding the semiconductor chip 3. In this embodiment, for example, an epoxy-based thermosetting resin containing metal particles made of silver (Ag) or the like is used as the die bond material DB.

[0033] As shown in FIG. 3, the semiconductor chip 3 mounted on the die pad 2 has a rectangular planar shape. In this embodiment, the planar shape of the semiconductor chip 3 is, for example, a square. Also, as shown in FIG. 1, the semiconductor chip 3 has a front surface (main surface, upper surface) 3a, a back surface (main surface, lower surface) 3b opposite the front surface 3a, and a side surface 3c located between the front surface 3a and the back surface 3b. As shown in FIGS. 1 and 3, a plurality of pads (bonding pads) PD are formed on the front surface 3a of the semiconductor chip 3. In this embodiment, the plurality of pads PD are formed along each side of the front surface 3a. Although not shown, a plurality of semiconductor elements (circuit elements) are formed on the main surface of the semiconductor chip 3 (more specifically, a semiconductor element formation region provided on the top surface of the base material (semiconductor substrate) of the semiconductor chip 3). The plurality of pads PD are electrically connected to the semiconductor elements via wiring (not shown) formed in a wiring layer disposed inside the semiconductor chip 3 (more specifically, between the front surface 3a and the semiconductor element formation region, not shown).

[0034] The semiconductor chip 3 (more specifically, the substrate of the semiconductor chip 3) is made of, for example, silicon (Si). An insulating film covering the substrate and wiring of the semiconductor chip 3 is formed on the surface 3a, and the surfaces of the multiple pads PD are exposed from the insulating film at openings formed in the insulating film. The pads PD are made of metal, and in this embodiment, are made of, for example, aluminum (Al) or an alloy layer mainly containing aluminum (Al).

[0035] As shown in FIG. 3 , a plurality of leads 4 made of, for example, copper (Cu), the same material as the die pad 2, are arranged around the semiconductor chip 3 (specifically, around the die pad 2). A plurality of pads (bonding pads) PD formed on the front surface 3 a of the semiconductor chip 3 are electrically connected to the leads 4 via a plurality of wires (conductive members) 5. The wires 5 are made of, for example, gold (Au), and a portion (for example, one end) of the wires 5 is bonded to the pads PD, and another portion (for example, the other end) is bonded to a bonding region on the top surface 4 a of the leads 4. Although not shown, a plating film is formed on the surface of the bonding region of the leads 4 (specifically, the surface of a plating film made of nickel (Ni)). The plating film is made of, for example, silver (Ag) or gold (Au). Forming a plating film made of silver (Ag) or gold (Au) on the surface of the bonding region (wire bonding region) of the leads 4 (inner lead portion) can improve the bonding strength with the gold (Au) wires 5.

[0036] 1, the lead 4 has an upper surface (wire bonding surface) 4a that is sealed by the sealing body 6, and a lower surface (mounting surface) 4b that is located opposite the upper surface 4a and is exposed at the lower surface 6b of the sealing body 6. The lead 4 also has a side surface 41a on the outer periphery. As described above, the lead 4 also has a side surface 41b that is continuous with the side surface 41a and is located between the lower surface 4b and the upper surface 4a. Furthermore, inside the side surface 41a, the lead 4 has a side surface 41c that is continuous with the lower surface 4b and the side surface 41b.

[0037] 3, a plurality of suspension leads TL are connected (coupled) to the die pad 2. One end of each of the suspension leads TL is connected to a corner of the die pad 2, which is rectangular in plan view. The other end of each of the suspension leads TL extends toward a corner 6k of the sealing body 6 and is exposed from the sealing body 6 at the corner 6k. Extending the suspension leads TL toward the corner 6k of the sealing body 6 allows the suspension leads TL to be arranged without interfering with the arrangement of the leads 4 arranged along each side (each main side) of the sealing body 6. This allows the number of leads 4, i.e., the number of terminals of the semiconductor device 1, to be increased. Furthermore, a portion of the suspension leads TL (sealing portion TL1) is half-etched from the underside, and the underside is sealed by the sealing body 6. This allows the suspension leads TL and the sealing body 6 to be firmly fixed together, preventing the suspension leads TL from falling off the sealing body 6.

[0038] Next, the mounting structure of the semiconductor device will be described. As shown in FIG. 2, a mounting substrate (motherboard, wiring board) 20 has an upper surface (mounting surface) 20a on which electronic components are mounted, and the semiconductor device 1 is mounted on the upper surface 20a. A plurality of lands (terminals) 21, which are terminals on the mounting substrate, are arranged on the upper surface 20a. In the example shown in FIG. 2, the mounting substrate 20 includes a plurality of lands (terminals for lead connection) 21a and lands (terminals for die pad connection) 21b. As shown in FIG. 4, the lead 4 has a side surface 41c connecting the side surface 41b and the lower surface 4b, which serves as a trigger for the bonding material 24 to wet up to the side surface 41b. Each of the plurality of leads 4 and the plurality of lands 21a is bonded via the bonding material 24. One surface of the bonding material 24 is bonded to the lower surface 4b, the side surface 41b, and the side surface 41c of the lead 4, and the other surface of the bonding material 24 is bonded to the exposed surface of the land 21a. That is, in this step, the leads 4 and the lands 21a are electrically connected to each other via the bonding material 24. The bonding material 24 is, for example, solder.

[0039] Next, the main features and effects of the semiconductor device of this embodiment will be described. FIG. 5 is an enlarged cross-sectional view showing a semiconductor device mounted on the mounting surface of a mounting board via a bonding material when the upper surface of the lead is flat. To improve the mounting reliability of semiconductor devices, there is a demand for increasing the volume of solder used to secure the terminals. One method for increasing the volume of solder used to secure the terminals is to increase the height h2 of the step portion 10. However, in the example shown in FIG. 5 , increasing the height h2 of the step portion 10 reduces the thickness t2 of the lead 4 from the upper surface 4a to the side surface 41b. This could result in breakage of the lead 4 due to stress from a cutting tool or the like during the half-dicing process described below. For this reason, it is difficult to increase the height h2 of the step portion 10 in the structure shown in FIG. 5 . Another method is to increase the height h2 of the step portion 10 while simultaneously increasing the thickness t1 of the lead 4 from the upper surface 4a to the lower surface 4b. In this case, the thickness t2 of the lead 4 from the upper surface 4a to the side surface 41b increases, but this could result in an increase in the size of the semiconductor device.

[0040] As shown in FIG. 4 , the semiconductor device according to this embodiment includes a region 41e in which the height h1 of the lead 4 increases toward the side surface 41a. Because the height h1 of the lead 4 increases by the presence of region 41e, the thickness t2 of the lead 4 from the top surface 4a to the side surface 41b does not decrease even if the height h2 of the step portion 10 is increased. Since the thickness t2 of the lead 4 from the top surface 4a to the side surface 41b does not decrease, the lead 4 is prevented from breaking due to stress from a cutting tool or the like during the half-dicing process described below. Furthermore, since the height h1 of the step portion 10 can be increased, the volume of the solder securing the terminals can be increased. This increases the tolerance for plastic deformation of the solder before breakage. As a result, the mounting reliability of the semiconductor device can be improved. Furthermore, since the volume of the solder securing the terminals can be increased without increasing the thickness t1 of the lead from the top surface 4a to the bottom surface 4b where the wire is connected, the semiconductor device can be miniaturized. Furthermore, in conventional non-lead type packages, almost no plating film is formed on the cut surfaces of the leads that serve as external terminals, making it difficult for solder fillets to form when the package is mounted on a mounting substrate. On the other hand, the semiconductor device according to this embodiment is provided with a step portion 10, and the height h1 of the step portion 10 can be increased, thereby increasing the area on which the plating film is formed. This makes it easier for solder fillets to form when the package is mounted on a mounting substrate. As a result, the mounting strength of the semiconductor device is increased.

[0041] <Method for mounting semiconductor devices> Next, a method for mounting a semiconductor device will be described.

[0042] In this embodiment, first, the mounting substrate 20 is prepared (substrate preparation step). The upper surface 20a is covered with an insulating film (solder resist film) 22. The insulating film 22 has openings formed at positions overlapping with the plurality of lands 21. The plurality of lands 21 are exposed from the insulating film 22 through the openings formed at the positions overlapping with the plurality of lands 21.

[0043] Next, as shown in FIG. 6, bonding material 23 is disposed (applied) on each of the lands 21 provided on the upper surface 20a of the mounting substrate 20 (bonding material disposing step). In the example shown in FIG. 6, the bonding material 23 is a solder material called cream solder (or paste solder). Cream solder contains a solder component that serves as a conductive bonding material and a flux component that activates the surface of the joint. Cream solder is in a paste state at room temperature. The bonding material can be applied by, for example, screen printing. In this step, the bonding material 23 is disposed on each of the lands 21. In the example shown in FIG. 1, the multiple leads 4, the die pad 2, and the multiple suspension leads TL are exposed on the lower surface 6b of the sealing body 6. The multiple leads 4, the die pad 2, and the multiple suspension leads TL are each connected to the lands 21 of the mounting substrate 20. For this reason, in this step, the bonding material 23 is applied to each of the lands 21 shown in FIG. 6.

[0044] 6, the semiconductor device 1 is placed on the upper surface 20a of the mounting substrate 20 (package mounting process). In this process, the positions of the terminals of the semiconductor device 1 are aligned with the positions of the lands 21 on the mounting substrate 20, and the semiconductor device 1 is placed on the upper surface 20a, which is the mounting surface of the mounting substrate 20. More specifically, in this process, the die pad 2 of the semiconductor device 1 is placed on the lands 21b of the mounting substrate 20, and the multiple leads 4 are placed on the multiple lands 21a.

[0045] Next, a heat treatment is performed with the semiconductor device 1 placed on the mounting substrate 20, and as shown in Fig. 2, the leads 4 and the lands 21a are each bonded via the bonding material 24 (reflow process). The bonding material 24 shown in Fig. 2 is a conductive member (solder material) formed by integrating the solder component contained in the bonding material 23 shown in Fig. 6 with the solder component of the metal film SD. In this process, the leads 4 and the lands 21a are electrically connected via the bonding material 24.

[0046] Furthermore, on the land 21b, which is a die pad connection terminal, one surface of the bonding material 24 is bonded to the underside 2b of the die pad 2, and the other surface of the bonding material 24 is bonded to the exposed surface of the land 21b. That is, in this step, a heat dissipation path is formed that connects the die pad 2 to the mounting substrate 20. Furthermore, when the die pad 2 is used as a terminal for supplying a reference potential, for example, the die pad 2 and the land 21b are electrically connected via the bonding material 24 in this step.

[0047] In this process, when the bonding material 23 shown in FIG. 6 is heated, the flux component contained in the bonding material 23 flows out, activating the exposed surfaces of the metal film SD and the lands 21. This makes the solder component contained in the bonding material 23 more likely to wet the metal film SD and the lands 21. Further heating causes the melting point of the solder component to be reached, causing the solder component to melt. At this time, the metal film SD and the lands 21 are in a state where they are more likely to wet the solder (high solder wettability), so the solder component wets and spreads over the exposed surfaces of the lands 21 and the surfaces on which the metal film SD is formed. As a result, as shown in FIG. 2, the bonding material 24 wets and spreads over the entire exposed surface of the lands 21. The bonding material 24 also wets and spreads over the entire lower surface 2b, which is the exposed surface of the die pad 2. The bonding material 24 also wets and spreads over the lower surface 4b and the step portion 10 of the exposed surface of the leads 4. Meanwhile, as shown in FIG. 6, the metal film SD is not formed on the side surface 4c, so the bonding material 24 shown in FIG. 2 does not easily wet and spread over the side surface 4c. In particular, when the bonding material 24 is made of lead-free solder, the wettability tends to be lower than that of so-called lead solder, so the bonding material 24 does not easily wet onto the side surface 4c on which the metal film SD is not formed.

[0048] Here, the mounting strength of the semiconductor device 1 will be described. After being mounted on the mounting substrate 20, the semiconductor device 1 is subjected to a temperature cycle load in the usage environment. The temperature cycle load is a load that occurs when the environmental temperature of a mounting structure in which the semiconductor device 1 is mounted on the mounting substrate 20 changes repeatedly. An example of the temperature cycle load is stress that occurs due to differences in the linear expansion coefficients of the components that make up the mounting structure. This stress tends to concentrate on the periphery of the mounting surface of the semiconductor device 1. Therefore, in order to extend the temperature cycle life (the number of temperature cycles that can be endured until the connection is damaged by the temperature cycle load), it is preferable to improve the strength of the connection between the leads 4 and the lands 21 that are arranged on the periphery of the mounting surface.

[0049] Therefore, when viewed from a cross section perpendicular to the bottom surface 4b and the side surface 41a, the semiconductor device 1 of this embodiment has a region 41e in which the height h1 of the lead 4 increases toward the side surface 41a. The height h1 of the lead 4 refers to the distance from the top surface 4a to a plane that includes and is parallel to the bottom surface 4b. This allows the stepped portion 10, where plating is present, to be enlarged. This allows the thickness of the bonding material 24 to be increased directly below the side surface 4c, where stress generated by temperature cycles is most likely to concentrate. As a result, the strength of the bond between the lead 4 and the land 21a is improved, thereby improving the connection reliability of the semiconductor device 1. Furthermore, the semiconductor device 1 includes a side surface 41c that is continuous with the bottom surface 4b and the side surface 41b of the lead 4. This allows the bonding material 24 to be bonded at multiple intersecting surfaces, thereby improving the bonding strength between the bonding material 24 and the lead 4. Furthermore, providing the stepped portion 10 on the bottom surface 4b of the lead 4 increases the contact area between the bonding material 24 and the lead 4, thereby improving the bonding strength between the lead 4 and the bonding material 24. The bonding material 24 also functions as a stress buffer, so that an increased amount of the bonding material 24 can improve the connection reliability of the semiconductor device 1.

[0050] In particular, when miniaturizing the semiconductor device 1, the dimensions of each lead 4 become smaller, and the area of ​​the lower surface 4b, which is the mounting surface, also becomes smaller. According to this embodiment, even if the area of ​​the lower surface 4b of the lead 4 becomes smaller due to miniaturization, a decrease in mounting strength can be suppressed by providing the step portion 10. In other words, by improving the mounting strength of the lead 4, the area of ​​the lower surface 4b of the lead 4 can be reduced, and therefore the semiconductor device 1 can be miniaturized.

[0051] Furthermore, in this embodiment, the hanging leads TL are formed integrally with the die pad 2, so there is no need to electrically connect the hanging leads TL and the lands 21. However, by fixing the hanging leads TL and the lands 21 via the bonding material 24, the connection strength between the semiconductor device 1 and the mounting board 20 can be improved. Note that, in order to make the bonding material 24 wet up onto the hanging leads TL, it is necessary to form a metal film SD on the hanging leads TL and also to bring the metal film SD into contact with the bonding material 23 in the reflow process. The lead 4 shown in FIG. 2 has a side surface 41c that connects the side surface 41b and the lower surface 4b, which acts as a trigger for the bonding material 24 to wet up to the side surface 41b.

[0052] After this step, if any residue of the flux component contained in the bonding material 23 shown in FIG. 6 remains, a cleaning step is carried out as necessary to remove the residue.

[0053] Next, the appearance of the semiconductor device 1 mounted on the mounting substrate 20 is inspected (inspection process). In this process, the connection between the semiconductor device 1 and the mounting substrate 20, i.e., the bonding state by the bonding material 24, is particularly inspected. In this process, the appearance of the connection state can be inspected visually, for example, from the top surface side of the semiconductor device 1 (the top surface 6a side of the sealing body 6), but from the viewpoint of performing the inspection efficiently, it is preferable to perform the inspection using image processing.

[0054] For example, inspection can be performed using an inspection device (visual inspection device) 30 shown schematically in FIG. 7. FIG. 7 is an explanatory diagram showing a schematic configuration of a visual inspection process for a mounting structure. FIG. 8 is an explanatory diagram showing a case where the visual inspection process is performed for another semiconductor device configuration shown in FIG. 7. The inspection device 30 includes a light irradiation unit 31 that irradiates light onto the inspection target portion, an imaging unit 32 that detects and captures the light reflected from the inspection target portion, and a control unit 33 electrically connected to the imaging unit 32. The control unit 33 includes, for example, an image processing unit that processes (image processing) data obtained by the imaging unit 32, and a judgment unit that evaluates the image-processed data and makes a pass / fail judgment. As described above, in this process, the bonding state of the bonding material 24 is particularly inspected. Therefore, the light irradiation unit 31 is disposed on the upper surface side of the semiconductor device 1 (the upper surface 6a side of the sealing body 6), and light is irradiated toward the bonding material 24. The imaging unit 32 is also disposed on the upper surface side of the semiconductor device 1 (on the side of the upper surface 6a of the sealing body 6), and detects light reflected by the bonding material 24 and captures an image.

[0055] 8, when no protrusion is provided on the upper surface 4a, the step 10 needs to be formed low, and as a result, the thickness of the bonding material 24 disposed between the step 10 and the land 21 becomes small.

[0056] 7, in the semiconductor device 1 of this embodiment, the protrusion is provided on the upper surface 4a, so the step portion 10 can be formed high. As a result, the thickness of the bonding material 24 disposed between the step portion 10 and the land 21 can be increased.

[0057] 7, when the exposed surface of the bonding material 24 is flat or has a slightly recessed fillet shape, the reflection direction of the light irradiated onto the bonding material 24 becomes more stable. Furthermore, when the thickness of the bonding material 24 disposed between the step portion 10 and the land 21 is increased, the amount of reflected light reaching the imaging unit 32 increases, enabling accurate determination processing.

[0058] As described above, according to this embodiment, the bonding strength of the bonding portion formed by the bonding material 24 is improved, thereby extending the temperature cycle life of the semiconductor device 1. In other words, the reliability of the semiconductor device 1 can be improved. Furthermore, as shown in FIG. 7 , according to this embodiment, the exposed surface of the bonding material 24 is flat or has a slightly recessed fillet shape, so that defects during mounting can be detected more easily. As a result, the mounting reliability of the semiconductor device 1 can be further improved.

[0059] <Method of manufacturing a semiconductor device> Next, we will explain a method for manufacturing the semiconductor device 1. The semiconductor device 1 of this embodiment is manufactured in accordance with the assembly flow shown in FIG.

[0060] 1. Lead frame preparation process; First, in the lead frame preparation step shown in Fig. 9, a lead frame (base material) 40 as shown in Fig. 10 is prepared. Fig. 11 is an enlarged cross-sectional view taken along line AA in Fig. 10.

[0061] The multiple leads 4 include leads 42 and 43. The lead frame 40 prepared in this process includes leads 42 at least partially provided in the device region (product formation region) 40a and leads 43 at least partially provided in another device region 40a. The leads 42 have protruding portions 42a protruding in the thickness direction of the lead frame 40. Here, the thickness direction of the lead frame 40 is direction D shown in FIG. 11. Direction D is perpendicular to a plane parallel to region 41f. As shown in FIG. 11, the protruding portions 42a protrude from region 41f toward direction D. That is, the portion of the lead 42 extending in direction D from a plane parallel to region 41f (the dotted line portion in FIG. 11) is the protruding portion 42a of the lead 42. The protruding portion 42a includes region 41e. The lead 43 has protruding portions 43a protruding in the same direction as the protruding portion 42a of the lead 42, i.e., in the thickness direction of the lead frame 40. That is, as shown in FIG. 11, the protruding portion 43a protrudes from the region 41f toward the direction D. That is, the portion of the lead 43 that protrudes in the direction D from a plane parallel to the region 41f (the dotted line portion in FIG. 11) is the protruding portion 43a of the lead 43. The protruding portion 43a includes the region 41e. The lead frame 40 has a tie bar 40tb that connects the leads 42 and 43. The tie bar 40tb is provided spaced apart from each device region 40a. In the example shown in FIG. 10, the tie bar is provided in the dicing region 40c. In the example shown in FIG. 10, the tie bar is not formed in the device region (product formation region) 40a. Here, a pre-manufactured lead frame may be used in the preparation step.

[0062] The manufacturing method of the lead frame 40 is not particularly limited, but may be press processing. By using press processing, the processing strength can be increased. Furthermore, by changing the design of the receiving portion of the die on the back side of the trench processing portion and the punch die, processing with a high degree of freedom in shape can be achieved with high precision. As shown in FIG. 12, the lead frame 40 is placed on a receiving die 81. A punch 82 is used to form protrusions 42a, 43a, and trench portion 40hf in the lead frame 40.

[0063] The lead frame 40 is made of metal, and in this embodiment, it is made of, for example, copper (Cu), or a laminated metal film in which a metal film (not shown) made of, for example, nickel (Ni) is formed on the surface of a base material made of copper (Cu).

[0064] In the example shown in FIG. 10, dicing regions 40c are provided between the device regions 40a, surrounding the periphery of each device region 40a. These dicing regions 40c are regions that are cut in the singulation process (see FIG. 19), which will be described later. As shown in FIG. 10, the dicing regions 40c are formed so as to surround the periphery of the plurality of leads 4. In addition, tie bars 40tb are arranged in the dicing regions 40c so as to surround the periphery of the device region 40a. The tie bars 40tb are formed integrally with the plurality of leads 4 and the outer frame (frame body) 40b.

[0065] 10, a die pad 2 having a rectangular shape in plan view is formed in the center of each device region 40a. Hanging leads TL are connected to the four corners of the die pad 2, respectively, and are arranged to extend toward the corners of the device region 40a. A plurality of leads 4 are formed around the die pad 2, each between the hanging leads TL. The leads 4 are each connected to a tie bar 40tb that is arranged outside the leads 4 relative to the die pad 2.

[0066] In other words, the lead frame 40 includes a tie bar 40tb, a die pad 2, multiple suspension leads TL, and multiple leads 4. In a plan view, the die pad 2 is disposed inside the tie bar 40tb. The multiple suspension leads TL connect the die pad 2 and the tie bar 40tb. The multiple leads 4 are disposed between the die pad 2 and the tie bar 40tb.

[0067] 10, the lead frame 40 has a plurality of device regions 40a adjacent to each other. Each device region 40a is provided with a plurality of leads 4. Tie bars 40tb are provided between the device regions 40a, and the plurality of leads 4 are connected to the tie bars 40tb.

[0068] As shown in FIGS. 10 and 11, when viewed from a cross section perpendicular to the bottom surface 4b and side surface 4d, there is a region 41e in which the height h1 of the lead 42 increases toward the tie bar 40tb. The height h1 of the lead 42 is the distance from the top surface 4a to a plane that includes the bottom surface 4b and is parallel to the bottom surface 4b (see FIG. 4). When viewed from a cross section perpendicular to the bottom surface 4b and side surface 4d, there is a region 41e in which the height h1 of the lead 43 increases toward the tie bar 40tb. The height h1 of the lead 43 is the distance from the top surface 4a to a plane that includes the bottom surface 4b and is parallel to the bottom surface 4b (see FIG. 4). As shown in FIG. 11, the leads 42 and 43 have a region 41f in which the height h1 is constant.

[0069] 11, the lead frame 40 has a trench portion 40hf on the side opposite to the side facing the direction D. In other words, the lead frame 40 has the trench portion 40hf on the side opposite to the side from which the protrusions 42a and 43a protrude. The method for forming the trench portion 40hf is not particularly limited, and examples thereof include mold processing and half-etching.

[0070] As shown in FIG. 11, the tie bars 40tb and portions of the leads 4 disposed within the dicing region 40c between the device regions 40a are formed as trench portions 40hf. In other words, the tie bars 40tb and portions of the leads 4 are partially removed from the lower surface of the lead frame. By forming trench portions 40hf within the dicing region 40c in this manner, the amount of metal material to be cut in the singulation process can be reduced. This reduces metal burrs and other defects that occur during the cutting process, improving the reliability of the semiconductor device.

[0071] 2.Semiconductor chip mounted; Next, in the semiconductor chip mounting step shown in FIG. 9, the semiconductor chip 3 is mounted on the die pad 2 via the die bond material DB as shown in FIG.

[0072] 14, the semiconductor chip 3 is mounted in a so-called face-up mounting manner, in which the back surface 3b (the surface opposite to the front surface 3a on which the multiple pads PD are formed) of the semiconductor chip 3 faces the top surface 2a of the die pad 2. Also, as shown in FIG. 13, the semiconductor chip 3 is mounted in the center of the die pad 2 so that each side of the front surface 3a is arranged along each side of the die pad 2.

[0073] In this process, the semiconductor chip 3 is mounted via a die bond material DB, which is, for example, an epoxy-based thermosetting resin. The die bond material DB is a paste material that has fluidity before being hardened (thermosetting). When a paste material is used as the die bond material DB in this manner, the die bond material DB is first applied to the die pad 2, and then the back surface 3b of the semiconductor chip 3 is bonded to the upper surface 2a of the die pad 2. After bonding, the die bond material DB is hardened (for example, by heat treatment), and the semiconductor chip 3 is fixed to the die pad 2 via the die bond material DB, as shown in FIG.

[0074] In this step, the die bond material DB and the semiconductor chip 3 are placed on the die pad 2 provided in each device region 40a, respectively. Then, the semiconductor chip 3 is mounted on each device region 40a.

[0075] In this embodiment, a paste material made of a thermosetting resin is used for the die bond material DB, but various modifications are possible. For example, instead of a paste material, an adhesive material that is a tape material (film material) with adhesive layers on both sides may be attached to the back surface 3b of the semiconductor chip 3 in advance, and the semiconductor chip 3 may be mounted on the die pad 2 via the tape material.

[0076] 3.Wire bonding process; Next, in the wire bonding step shown in FIG. 9, the pads PD of the semiconductor chip 3 and the leads 4 are electrically connected via wires (conductive members) 5, respectively, as shown in FIGS.

[0077] In this process, for example, the lead frame 40 having the semiconductor chip 3 mounted on the die pad 2 of each device region 40a is placed on a heat stage (lead frame heating table) not shown. Then, the pads PD of the semiconductor chip 3 and the leads 4 are electrically connected via wires 5. In this embodiment, the wires 5 are connected by a so-called nail head bonding method, in which the wires 5 are supplied through a capillary not shown and bonded using a combination of ultrasonic waves and thermocompression bonding.

[0078] A plating film made of, for example, silver (Ag) or gold (Au) is formed on a portion (a bonding region arranged at the tip of the inner lead portion) of the lead 4. A portion of the wire 5 is electrically connected to the lead 4 via a plating film made of silver (Ag) or gold (Au). The wire 5 is made of metal, and in this embodiment, it is made of, for example, gold (Au).

[0079] In this embodiment, after connecting a part (end) of the wire 5 to the pad PD of the semiconductor chip 3, the other part of the wire 5 is connected to the bonding region of the lead 4 (a part of the upper surface of the lead 4). In this embodiment, the wire is connected by the so-called normal bonding method. The bonding region is located on the opposite side of the lower surface 4b. This allows a sufficient load to be applied when bonding the wire 5 to the lead 4, thereby improving the bonding strength.

[0080] In this process, wires 5 are bonded to the leads 4 provided in each device region 40a. As a result, in each device region 40a, the semiconductor chip 3 and the leads 4 are electrically connected via the wires 5.

[0081] The bonding area may be located in an area 41f where the height h1 is constant, which can further improve the bonding strength.

[0082] 15, a frame clamper 90 used in the wire bonding process has a shape corresponding to the upper surface 4a of the lead 4. For example, if the upper surface 4a of the lead 4 has an inclined portion, the frame clamper 90 also has an inclined portion corresponding to the upper surface 4a of the lead 4.

[0083] 4. Sealing process; In the encapsulation process, a encapsulant is formed to encapsulate the semiconductor chip and conductive members so that at least a portion of the leads and at least a portion of the leads are exposed from the outer surface of the encapsulant. In the encapsulation process, a encapsulant is formed to encapsulate the semiconductor chip and conductive members so that at least a portion of the protruding portions of the leads and at least a portion of the protruding portions of the leads are connected to the encapsulant. Here, "encapsulating" refers to covering all outer surfaces of the object to be encapsulated. Furthermore, the term "encapsulating with a encapsulant" includes not only cases where the entire outer surface of the object is covered only with the encapsulant, but also cases where the entire outer surface of the object is covered with both the encapsulant and other components. As shown in FIGS. 16 and 17 , in this embodiment, a encapsulant (encapsulant) 6 is formed to encapsulate a portion of each of the semiconductor chip 3, the plurality of wires 5, and the plurality of leads 4.

[0084] In this process, as shown in Fig. 16, the sealing body 6 is formed so that at least a portion of each of the leads 4 provided in each device region 40a is exposed. In this embodiment, the sealing body 6 is formed so that the lower surface 2b of the die pad 2 provided in each device region 40a is exposed. In this process, for example, the sealing body 6 is formed by a so-called transfer molding method in which, with the lead frame 40 sandwiched between molding dies 50 shown in Fig. 17, softened resin is injected into the molding dies 50 and then hardened.

[0085] The molding die 50 includes an upper die (die) 51 disposed above the lead frame 40, and a lower die (die) 52 disposed below the lead frame 40. The upper die 51 includes a clamping surface (die surface, pressing surface, surface) 51a that presses the lead frame 40, and a cavity (recessed portion) 51b formed inside the clamping surface 51a. The lower die 52 includes a clamping surface (die surface, pressing surface, surface) 52a that is disposed opposite the clamping surface 51a and presses the lead frame 40. In this embodiment, since a QFN type package is manufactured, no cavity is formed inside the clamping surface 52a of the lower die 52.

[0086] In the sealing process, sealing resin is pressure-filled into cavity 51b to seal a portion of each of semiconductor chip 3 (FIG. 16), the plurality of wires 5 (FIG. 16), and the plurality of leads 4 (FIG. 16). Then, the resin supplied to cavity 51b is thermally cured to form sealing body 6.

[0087] 16 and 17, a resin film (film material) 53 is disposed between the lead frame 40 and the lower die 52. A pressing force is applied to the lower surface (rear surface side, mounting surface side) of the lead frame 40 from the clamp surface 52a of the lower die 52 via the resin film 53. Therefore, as shown in FIG. 16, the lower surfaces 4b of the leads 4 and the lower surface 2b of the die pad 2 are likely to adhere to the resin film 53. By adhering the resin film 53, it is possible to prevent the sealing resin from getting around to the lower surfaces 4b of the leads 4 and the lower surface 2b of the die pad 2. In other words, the lower surfaces 4b of the leads 4 and the lower surface 2b of the die pad 2 can be exposed.

[0088] In this embodiment, the sealing body 6 is formed to collectively seal the multiple device regions 40a. In other words, as shown in FIG. 17 , in the sealing process, the lead frame 40 is placed in the molding die 50 so that the multiple device regions 40a of the lead frame 40 fit into one cavity 51b. A semiconductor package in which the sealing body 6 is formed to collectively cover the multiple device regions 40a arranged in a matrix (array) is called a MAP (Multi Array Package) type semiconductor device. A sealing method that collectively seals the multiple device regions 40a is called a block molding method. In a MAP type semiconductor device, the spacing between the device regions 40a can be reduced, thereby increasing the effective area of ​​one lead frame 40. This increases the number of products that can be manufactured from one lead frame 40. Increasing the effective area of ​​one lead frame 40 in this way improves the efficiency of the manufacturing method. In particular, when several tens of products are manufactured from one lead frame 40, the increased effective area significantly improves manufacturing efficiency.

[0089] 16, in this step, the sealing resin wraps around and adheres to areas that are not in close contact with the molding die 50 or the resin film. Therefore, when the trench portion 40hf is formed, the sealing body 6 is formed in the trench portion 40hf. In other words, in this step, the trench portion 40hf is sealed with resin.

[0090] 5. Half dicing process (first cutting process); In the half dicing process, a blade having a first width greater than the width of the tie bar is inserted into the lead frame 40 from the bottom surface 4b of the lead frame 40 (i.e., the side opposite to the side where the protruding portions of the leads 4 protrude), thereby removing a portion of the lead frame including the tie bar 40tb. Furthermore, if the lead frame 40 prepared in the lead frame preparation process has a trench portion 40hf, the half dicing process removes a portion of the lead frame 40 including the tie bar 40tb and a portion of the sealing body formed in the trench portion. Specifically, a blade BD1 having a first width greater than the width of the tie bar 40tb is inserted into the lead frame 40 from the bottom surface 4b of the lead frame 40, thereby removing a portion of the lead frame 40 including the tie bar 40tb and a portion of the sealing body formed in the trench portion.

[0091] In the half dicing process shown in FIG. 9, the resin (sealing body 6) embedded in the lower surface side (back surface side, mounting surface side) of trench portion 40hf is removed as shown in FIG. 18. This exposes tie bar 40tb and the lower surface side (back surface side, mounting surface side) of tie bar 40tb. FIG. 18 is an enlarged cross-sectional view showing the state in which cutting has been performed on the lead frame shown in FIG. 16 to expose the lower surface sides of the tie bars. FIG. 19 is an enlarged cross-sectional view showing a further enlargement of the dicing region and its periphery shown in FIG. 16. FIG. 20 is an enlarged cross-sectional view showing a further enlargement of the dicing region and its periphery shown in FIG. 18. FIG. 23 is a plan view showing the lower surface side of the lead frame.

[0092] In this process, as shown in Figure 18, cutting is performed using a blade (rotary blade) BD1 to remove the resin embedded in the underside of the trench portion 40hf. The blade BD1 is an annular (ring-shaped) or disk-shaped cutting jig, and multiple abrasive grains are attached to the cutting portion located on the periphery of the circle. Then, by pressing the cutting portion of the blade BD1 to which multiple abrasive grains are attached against the workpiece, the workpiece can be cut and removed.

[0093] In this process, the side surfaces (lower surfaces, middle surfaces) 41b of the leads 4, as described with reference to FIG. 1, are exposed. Therefore, as shown in FIG. 19, the width W1 of the blade BD1 used in this process, i.e., the cutting width in this half-dicing process, is wider (larger) than the width W2 of the tie bar 40tb. The lower surfaces 4b of the leads 42 and 43 are each part of the lower surface of the lead frame 40. By inserting the blade BD1 into the area enclosed by the dotted line in FIG. 19 from the lower surface of the lead frame 40, a part of the lead frame 40 including the tie bar 40tb and a part of the sealing body 6 formed in the trench portion 40hf are removed. Specifically, the lead frame 40 and sealing body 6 overlapping the area enclosed by the dotted line in FIG. 19 are removed by cutting. The shape of the lead frame 40 after the half-dicing process is shown in FIG. 20. As shown in FIG. 20, the side surfaces 41b of the leads 4 connected to both sides of the tie bar 40tb can be exposed. In other words, in this process, a groove is formed along the dicing region 40c by cutting with the blade BD1, thereby forming a step portion 10 in each of the multiple leads 4. In the example shown in FIG. 19, the width W1 of the blade BD1 is larger than the width of the sealing body 6 formed in the trench portion 40hf. Therefore, as shown in FIGS. 19 and 20, the width of the trench portion 40hf after cutting is larger than the width of the trench portion 40hf before cutting. Also, in the example shown in FIG. 19, the insertion depth h3 of the blade BD1 is smaller than the height (depth) of the sealing body 6 formed in the trench portion 40hf. Therefore, as shown in FIGS. 19 and 20, the height (depth) of the trench portion 40hf after cutting, which corresponds to the height h2 of the step portion 10, is larger than the height (depth) of the trench portion 40hf before cutting.

[0094] Furthermore, from the viewpoint of reliably removing the resin adhering to the underside of the trench portion 40hf, it is preferable to remove a part of the tie bar 40tb and a part of the lead 4 adjacent to the tie bar 40tb by cutting. Therefore, it is preferable that the width W1 of the blade BD1 shown in FIG. 19 is thicker (larger) than the width (groove width) W4 of the trench portion 40hf shown in FIG.

[0095] Furthermore, in this process, the leads 4 are not separated from the tie bar 40tb. In other words, in this process, portions of the lower surface (rear surface, mounting surface) of each of the leads 4 and the tie bar 40tb are removed while portions of the upper surface of each are left. By connecting the leads 4 to the tie bar 40tb, a metal film can be easily formed using electroplating in the plating process described below.

[0096] 21 and 22, if the lead 4 does not have a protrusion, forming the trench portion 40hf deeply may reduce the thickness t2 of the lead 4 from the upper surface 4a to the side surface 41b. Therefore, when forming the trench portion 40hf by cutting in the half-dicing process, the lead 4 may be broken due to stress from a cutting tool or the like. Therefore, if the lead 4 does not have a protrusion, it is difficult to increase the insertion depth h3 of the blade BD1. Because the insertion depth h3 of the blade BD1 is equal to the height h2 of the step portion 10, reducing the insertion depth h3 results in a shallower trench portion 40hf.

[0097] On the other hand, as shown in FIG. 20, the lead 42 (lead 4) of this embodiment has a protrusion 42a. Furthermore, the lead 43 (lead 4) has a protrusion 43a. Specifically, the height of the tie bar 40tb from a plane parallel to the lower surface 4b is greater than the thickness t1 (see FIG. 4) of the lead 4 from the plane parallel to the lower surface 4b to the region 41f. Furthermore, the height h1 (see FIG. 4) of the lead 4 from the plane parallel to the lower surface 4b to the region 41e is greater than the thickness t1 of the lead 4 from the plane parallel to the lower surface 4b to the region 41f. Therefore, even if the trench portion 40hf is formed deep in the tie bar 40tb and the lead 4 adjacent to the tie bar 40tb, the thickness t1 of the lead 4 from the upper surface 4a to the side surface 41b is prevented from becoming smaller. That is, because the lead 4 has the protrusions 42a and 43a, the thickness t1 of the lead 4 from the upper surface 4a to the side surface 41b does not decrease even if the insertion depth h3 of the blade BD1 is increased. Therefore, when forming the trench portion 40hf by cutting in the half-dicing process, the lead 4 is less likely to break due to stress from a cutting tool or the like. The insertion depth h3 of the blade BD1 is equal to the height h2 of the step portion 10, so increasing the insertion depth h3 allows for the formation of a deep trench portion 40hf. Because a deep trench portion 40hf can be formed, a larger amount of bonding material can be used. This increases the plastic deformation tolerance of the bonding material. As a result, the mounting reliability of the semiconductor device is improved. Furthermore, because the lead 4 of this embodiment has protrusions, the width of the trench portion 40hf can be increased. This increases the plastic deformation tolerance of the bonding material. As a result, the mounting reliability of the semiconductor device is further improved. Furthermore, since the lead 4 of this embodiment has a protrusion, even if the trench portion 40hf is formed deep, electrical continuity between the terminals can be ensured and a shape that allows electrical plating can be maintained. Also, since the lead 4 of this embodiment has a protrusion, even if the width of the trench portion 40hf is increased, electrical continuity between the terminals can be ensured and a shape that allows electrical plating can be maintained.

[0098] Next, the detailed flow of this process will be described. In this process, first, lead frame 40 on which sealing body 6 has been formed is fixed to a frame (ring frame) via tape (dicing tape). At this time, cutting is performed from the lower surface side (back surface side, mounting surface side) of lead frame 40, so as shown in Fig. 16, the upper surface 6a of sealing body 6 is adhered to the tape, and lead frame 40 is fixed so that the lower surface side (back surface side, mounting surface side) of lead frame 40 faces upward.

[0099] Next, a blade BD1 shown in FIG. 18 is rotated and moved along the dicing region 40c of the lead frame 40. As a result, as shown in FIG. 23, step portions 10 are formed along the periphery of each lead 4 along the dicing region 40c. Marks 40m are formed on the outer frame of the lead frame 40 to serve as alignment marks when cutting with the blade BD1 (see FIG. 18). Two marks 40m are provided for each dicing line (dicing region 40c). One of the two marks 40m is provided on an extension of the dicing line (dicing region 40c), and the other is provided at a position that does not overlap with the extension of the dicing line. Providing the marks 40m on the extension of the dicing line improves alignment accuracy, allowing the step portions 10 shown in FIG. 23 to be formed with high precision. However, in the half-dicing process, the outer frame of the lead frame 40 is also cut. Therefore, the marks 40m located on the extension of the dicing line are removed in this process. Therefore, as an alignment mark used in the singulation process described later, a mark 40m is provided at a position that does not overlap with the extension of the dicing line.

[0100] Furthermore, the depth of the groove formed in this step, i.e., the depth of the step portion 10 shown in FIG. 22, is preferably as follows. That is, from the viewpoint of improving the mounting strength of the semiconductor device 1 (see FIG. 3) or from the viewpoint of easily detecting defects during mounting of the semiconductor device 1, the deeper the step portion 10, the better. Therefore, in this step, cutting is preferably performed to a depth greater than half the distance from the region 41f on the upper surface 4a of the lead 4 to the lower surface 4b. However, it is preferable that the multiple leads 4 are connected to the tie bar 40tb at least until the plating step described below is completed. Therefore, from the viewpoint of preventing breakage of the connection between the leads 4 and the tie bar 40tb until the plating step is completed, it is preferable that the thickness of the tie bar 40tb is thick. Taking these factors into consideration, it is particularly preferable that the depth of the step portion 10 be greater than half the distance from the region 41f on the upper surface 4a of the lead 4 to the lower surface 4b. For example, when the total thickness of the lead 4 is about 0.2 mm, the depth of the step portion 10 is preferably greater than 0.1 mm.

[0101] Furthermore, in this process, the blade BD1 is caused to travel along the dicing region 40c, and therefore, as shown in FIG. 23, the lower surface (rear surface side, mounting surface side) of a portion (exposed portion TL2) of the hanging lead TL is exposed in this process. By exposing a portion (exposed portion TL2) of the hanging lead TL in this half-dicing process, a metal film can be formed on the exposed surface of the hanging lead TL in a plating process described later. As a result, the portion (exposed portion TL2) of the hanging lead TL can be connected to the land of the mounting board 20 via the bonding material 24, thereby improving the mounting strength of the semiconductor device 1. Furthermore, according to this embodiment, the process of forming the step portion 10 in the lead 4 and the process of exposing a portion of the hanging lead TL can be performed simultaneously. Therefore, an increase in the number of manufacturing steps due to exposing the hanging lead TL can be prevented.

[0102] Furthermore, since the lower surface of the lead frame is cut during the half-dicing process, a lead frame without the trench portion 40hf shown in FIG. 11 can be used as a modification of this embodiment. However, when cutting metal material, as the amount of metal material cut increases, the possibility of generating metal chips and metal burrs also increases. Therefore, from the perspective of suppressing the generation of metal chips and metal burrs, it is preferable to preliminarily provide the trench portion 40hf as shown in FIG. 11 to reduce the amount of metal material cut. This reduces the processing resistance of the cutting blade. As a result, the cutting width and depth can be increased without degrading the processing quality.

[0103] Furthermore, when the spacing between adjacent device regions 40a is wide, another variation of the half dicing process is to run the dicing blade twice between each of the device regions 40a, thereby forming step portions 10 on adjacent leads 4 sandwiching the tie bar 40tb therebetween. In this case, the resin covering the tie bar 40tb remains between the step portions 10.

[0104] However, from the viewpoint of improving manufacturing efficiency, it is preferable to shorten the arrangement intervals of adjacent device regions 40a and form step portions 10 collectively for adjacent leads 4 sandwiching a tie bar 40tb, as in the example shown in Fig. 20. In other words, in the half dicing step, it is preferable to expose the lower surfaces of the tie bars 40tb from the sealing body 6. This allows the cutting processing time in the half dicing step to be shortened.

[0105] 6. Plating process; In the plating step, a metal layer is formed on the exposed surface of the lead frame that is exposed from the outer surface of the encapsulant.

[0106] In this embodiment, as the plating step shown in Fig. 9, a metal film SD is formed on the exposed surfaces of the leads 4 and the die pad 2 as shown in Fig. 24. Fig. 24 is an enlarged cross-sectional view showing a state in which a metal film has been formed on the exposed surfaces of the leads and the die pad shown in Fig. 18.

[0107] In this process, the lead frame 40, which is the workpiece to be plated, is placed in a plating tank 60 containing a plating solution 61. At this time, the workpiece is connected to a cathode 62 in the plating tank 60. The outer frame 40d of the lead frame 40 is electrically connected to the cathode 62. Then, for example, a DC voltage is applied between the cathode 62 and an anode 63, which is also placed in the plating tank 60, to form a metal film SD on the exposed surface of the metal member connected to the outer frame 40d of the lead frame 40. That is, in this embodiment, the metal film SD is formed by a so-called electrolytic plating method.

[0108] As described above, the metal film SD of this embodiment is made of so-called lead-free solder that is substantially free of lead (Pb), such as tin (Sn) only, tin-bismuth (Sn-Bi), or tin-copper-silver (Sn-Cu-Ag). Therefore, the plating solution 61 used in this plating process is an electrolytic plating solution containing metal salts such as Sn2+ or Bi3+. In the following description, Sn-Bi alloy metal plating will be used as an example of lead-free solder plating, but Bi can be replaced with metals such as Cu or Ag.

[0109] In this embodiment, as described above, the plating process is performed in a state in which the leads 4 are electrically connected to the outer frame 40d via the tie bars 40tb. The die pad 2 is also electrically connected to the outer frame 40d via the tie bars 40tb and the suspension leads TL (see FIG. 24). Therefore, when a voltage is applied between the anode 63 and the cathode 62 while the lead frame 40 is immersed in the plating solution 61, electricity flows between the two electrodes (between the anode 63 and the cathode 62). Since the outer frame 40d of the lead frame 40 is electrically connected to the cathode 62 as described above, Sn2+ and Bi3+ in the plating solution 61 are deposited in a predetermined ratio on the exposed surfaces of the leads 4 and the die pad 2 shown in FIG. 24, forming a metal film SD.

[0110] 20, in this embodiment, a half dicing step is performed before the plating step, and step portions 10 are formed in each lead 4 as shown in FIG. 24, and the step portions 10 are exposed from the sealing body 6. Therefore, in this plating step, the metal film SD can be reliably formed on the exposed surfaces of the step portions 10. The thickness of the metal film SD can be changed depending on the product specifications, but for example, a film of about 10 μm to 20 μm is formed.

[0111] In addition to electrolytic plating, electroless plating is another method for forming a metal film by plating. However, electrolytic plating is preferred because the quality of the metal film SD can be easily controlled by controlling the current during metal film formation. Electrolytic plating is also preferred because the time required to form the metal film SD can be shorter than that required for electroless plating.

[0112] 7. Singulation process (second cutting process); In the singulation process, the tie bars are cut using a blade having a second width narrower than the width of the trench portion, thereby separating each device region. In this embodiment, a blade having a second width wider than the tie bars is used.

[0113] In the singulation step shown in Fig. 9, tie bars 40tb (see Fig. 26) connected to dicing region 40c are cut as shown in Fig. 25, and the plurality of device regions 40a are divided into individual pieces. Fig. 25 is an enlarged plan view showing a state in which a metal film is formed on the lead frame shown in Fig. 23 and then the lead frame is singulated into individual device regions. Fig. 26 is an enlarged cross-sectional view showing a state in which the lead frame shown in Fig. 10 is fixed to a dicing tape and singulated. Fig. 27 is an enlarged cross-sectional view further enlarging the periphery of the dicing region of Fig. 26.

[0114] In this process, first, lead frame 40 on which sealing body 6 (see FIG. 26) has been formed is fixed to a frame (ring frame) via tape (dicing tape). At this time, cutting is performed from the lower surface side (back surface side, mounting surface side) of lead frame 40, so as shown in FIG. 26, upper surface 6a of sealing body 6 is adhered to the tape, and lead frame 40 is fixed so that the lower surface side (back surface side, mounting surface side) faces upward.

[0115] Next, a blade (rotary blade) BD2 shown in FIGS. 26 and 27 is rotated and moved along the dicing region 40c of the lead frame 40. Specifically, the rotating blade (rotary blade) BD2 is inserted into the groove formed by the half-dicing process (first cut process), and the blade BD2 is moved along the dicing region 40c of the lead frame 40. This removes (cuts) the tie bars 40tb and portions of the encapsulation body formed directly above the tie bars 40tb (portions overlapping with the tie bars 40tb), separating adjacent device regions 40a. The blade BD2 is similar to the blade BD1 shown in FIG. 19 except for its cutting width. The blade BD2 is a cutting jig with an annular (ring-shaped) or disc-shaped side surface, and a plurality of abrasive grains are attached to the cutting portion located around the periphery of the circle. The cutting portion of the blade BD2, to which the abrasive grains are attached, is pressed against the workpiece to cut and remove the workpiece.

[0116] 26, the width W3 of the blade BD2, i.e., the cutting width in this singulation process, is larger (greater) than the width W2 of the tie bar 40tb and smaller (smaller) than the width W1 of the blade BD1 shown in FIG. 19. In other words, the width W3 is larger (greater) than the width W2 of the tie bar 40tb and smaller (smaller) than the groove width (width W2 shown in FIG. 19) of the groove (step portion 10) formed in the half-dicing process. To cite an example of specific dimensions, the width W2 of the tie bar 40tb is, for example, 0.16 mm, the width W1 of the blade BD1 is, for example, 0.90 mm, and the width W3 of the blade BD2 is, for example, 0.30 mm. By cutting the tie bar 40tb using the blade BD2 having the width W3 that is larger than the width W2 and smaller than the width W1 as described above, the tie bar 40tb can be reliably removed while leaving the step portion 10.

[0117] In this step, when cutting is performed from the lower surface 4b side of the lead 4, the side surface 41a that is not covered with the metal film SD (exposed from the metal film SD) is exposed as shown in Fig. 26. However, according to this embodiment, the side surface 4e that constitutes the step portion 10 is covered with the metal film SD, and therefore the mounting strength of the obtained semiconductor device 1 (see Fig. 3) can be improved.

[0118] As described above, the lead frame 40 of this embodiment has two marks 40m provided for each dicing line (dicing region 40c). Therefore, in the half dicing process described above, one of the two marks 40m is removed, but in this process, the mark 40m provided at a position that does not overlap with the extension of the dicing line can be used as an alignment mark.

[0119] After this process, necessary inspections and tests such as visual inspection and electrical test are carried out, and only those that pass are the finished semiconductor device 1. Then, the semiconductor device 1 is shipped or mounted on a mounting board (not shown).

[0120] <Modification> The invention made by the inventor of the present application has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the spirit of the invention.

[0121] For example, in the above embodiment, a so-called QFN type semiconductor device has been described in which a plurality of leads 4 are arranged along each side of a quadrilateral sealing body 6, and the lower surfaces of the leads 4 are exposed at the lower surface of the sealing body 6. However, applicable package forms are not limited to QFN. For example, the present invention can be applied to a SON type semiconductor device in which a plurality of leads 4 are arranged along the opposing long sides of a sealing body that is rectangular in plan view. The present invention can also be applied to a DFN type semiconductor device.

[0122] As a modification of the dicing blade used in the half-dicing process described in the above embodiment, a blade with a V-shaped or trapezoidal cutting edge may be used. Furthermore, if the trench portion 40hf is pre-formed, the half-dicing process may not be performed. In this case, a process of removing only the resin without removing the lead frame may be included. If the trench portion 40hf is pre-formed, the step portion 10 is already formed, so there is no need to remove the lead frame. On the other hand, since resin is formed in the trench portion 40hf by the sealing process, it is necessary to remove the resin to expose the metal surface. Here, not removing the lead frame includes not substantially removing the lead frame.

[0123] Furthermore, in the above embodiment, the pads (electrodes, bonding pads) PD of the semiconductor chip 3 and the leads (terminals, external terminals) 4 are electrically connected via wires 5 serving as conductive members. However, as a modified example, the pads PD of the semiconductor chip 3 and the leads 4 may be electrically connected via bump electrodes BM. The semiconductor device 71 is mounted by a so-called flip-chip connection method such that the surface 3a on which the pads PD of the semiconductor chip 3 are formed faces the upper surfaces 4a of the multiple leads 4. [Explanation of symbols]

[0124] 1. Semiconductor device 2 die pad 2a Top side 2b Bottom side 3. Semiconductor chips 3a surface 3b back side 3c side 4 Lead 4a Top side 4b Bottom side 4c side 4d side 4e side 5 wire 6 Encapsulation body 6a Top side 6b Bottom side 6c side 6e side 6f step surface 6k corner 10 Step 20 Mounting board 20a top surface 21 rand 21a Land 21b Land 22 insulating film 23 Bonding material 24 Bonding material 30 Inspection equipment 31 Light irradiation unit 32 Imaging unit 33 Control Unit 40 Lead Frame 40a Device Area 40c dicing area 40hf trench section 40tb tie bar 41a side 41b Side 41c side 41e area 41f area 42 Lead 42a Protrusion 43 Lead 43a Protrusion 50 molding die 51 Upper mold 51a Clamping surface 51b cavity 52 Lower mold 52a Clamping surface 53 Resin film 81 Mold 82 Punch 90 Frame clamper

Claims

1. A semiconductor chip; a lead spaced apart from the semiconductor chip; a conductive member that electrically connects at least one terminal of the semiconductor chip and the lead; a sealing body having a first main surface, a second main surface spaced apart from the first main surface, and a side surface located between the first main surface and the second main surface, and sealing the semiconductor chip and the conductive member; the lead has a first surface exposed from the outer surface of the encapsulant, a second surface spaced apart from the first surface and connected to the encapsulant, a third surface between the first surface and the second surface and connected to the encapsulant, and a fourth surface between the first surface and the second surface and exposed from the outer surface of the encapsulant; the fourth surface includes a first side surface that is flush with the side surface of the encapsulant, a second side surface that is connected to the first side surface and extends toward the third surface relative to the first side surface, and a third side surface that is connected to the second side surface and the first surface and extends toward the first main surface relative to the first surface; When viewed from a cross section perpendicular to the first surface and the first side surface, there is a region in which the distance from the second surface to a surface that includes the first surface and is parallel to the first surface increases as the distance approaches the first side surface.

2. The semiconductor device according to claim 1 , wherein said second surface includes a region that is parallel to said first surface.

3. 3. The semiconductor device according to claim 2, wherein the region of the second surface parallel to the first surface is located closer to the third surface than the region in which the distance from the second surface to a surface that includes the first surface and is parallel to the first surface becomes longer as the region approaches the first side when viewed from a cross section perpendicular to the first surface and the first side.

4. 4. The semiconductor device according to claim 3, wherein a distance from the second side surface to a plane that includes the first surface and is parallel to the first surface is longer than half a distance from the region of the second surface that is parallel to the first surface to a plane that includes the first surface and is parallel to the first surface.

5. Further, the metal layer is provided, The semiconductor device according to claim 4 , wherein the metal layer covers the first surface, the second side surface, and the third side surface.

6. (a) preparing a lead frame having a first lead, a portion of which is provided in a first device region and has a first protrusion protruding in a first direction, a second lead, a portion of which is provided in a second device region and has a second protrusion protruding in the first direction, and a tie bar connected to the first lead and the second lead and spaced apart from the first device region and the second device region; (b) mounting a first semiconductor chip on the first device region and a second semiconductor chip on the second device region; (c) forming an encapsulant that encapsulates the first semiconductor chip and the second semiconductor chip so that the lower surfaces of the first leads and the lower surfaces of the second leads are exposed from the outer surface of the encapsulant and the first protruding portions of the first leads and the second protruding portions of the second leads are connected to the encapsulant; (d) removing a portion of the lead frame including the tie bar by inserting a blade having a first width greater than a width of the tie bar into the lead frame from a lower surface of the lead frame; (e) separating the first device region and the second device region by cutting the tie bar with a blade having a second width narrower than the first width; the lower surface of the first lead and the lower surface of the second lead are each a part of the lower surface of the lead frame; The method for manufacturing a semiconductor device, wherein the first direction is a thickness direction of the lead frame.

7. 7. The method for manufacturing a semiconductor device according to claim 6, wherein said first lead and said second lead have regions with a constant height.

8. In the step (a), the lead frame has a trench portion on a side opposite to a side from which the protruding portion protrudes, 7. The method for manufacturing a semiconductor device according to claim 6, wherein in the step (d), a blade having a first width greater than the width of the tie bar is inserted into the lead frame from the underside of the lead frame, thereby removing a portion of the lead frame including the tie bar and a portion of the sealing body formed in the trench portion.

9. Before the step (c), the method further includes the step of: (b1) electrically connecting the first lead and at least one terminal of the first semiconductor chip via a first conductive member, and electrically connecting the second lead and at least one terminal of the second semiconductor chip via a second conductive member; 7. The method for manufacturing a semiconductor device according to claim 6, wherein in the step (c), the sealing body is formed to seal the first semiconductor chip, the second semiconductor chip, the first conductive member, and the second conductive member so that the lower surfaces of the first leads and the lower surfaces of the second leads are exposed from the outer surface of the sealing body and the first protrusions of the first leads and the second protrusions of the second leads are connected to the sealing body.

10. 7. The method for manufacturing a semiconductor device according to claim 6, further comprising, after the step (d) and before the step (e), a step (f) of forming a metal layer on an exposed surface of the lead frame exposed from the outer surface of the sealing body.

Images