Semiconductor device and data storage system including the same

Abstract

To provide a semiconductor device and the like having an improved integration degree.SOLUTION: A semiconductor device includes: a plate layer 101; a gate electrode 130 including lower gate electrodes, memory gate electrodes, and upper gate electrodes that are laminated along a Z direction perpendicular to a top face of the plate layer; a channel structure CH that penetrates the gate electrodes and extends along the Z direction; first contact plugs MC1 that are electrically coupled to the upper gate electrodes, respectively; second contact plugs MC2 that penetrate one or some of the gate electrodes from above and are electrically coupled to the memory gate electrodes and the lower gate electrodes, respectively; gate separation regions that penetrate the whole of the gate electrode, extend along a Y direction perpendicular to the Z direction, and are spaced apart in an X direction perpendicular to the Z, Y directions; and first upper separation regions that penetrate the upper gate electrodes between the gate separation regions and extend in the Y direction. The respective first contact plugs are in contact with at least one of the first upper separation regions and the second contact plugs are spaced apart from the first upper separation regions.SELECTED DRAWING: Figure 2a

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a data storage system including the same. [Background technology]

[0002] In data storage systems requiring data storage, semiconductor devices capable of storing high-capacity data are in demand. Accordingly, methods for increasing the data storage capacity of semiconductor devices have been studied. For example, as one method for increasing the data storage capacity of semiconductor devices, a semiconductor device including memory cells arranged three-dimensionally instead of two-dimensionally has been proposed. Summary of the Invention [Problem to be solved by the invention]

[0003] One of the technical problems to be solved by the present invention is to provide a semiconductor device with improved integration density.

[0004] One of the technical problems that the present invention aims to solve is to provide a data storage system including semiconductor devices with increased integration density. [Means for solving the problem]

[0005] A semiconductor device according to an exemplary embodiment includes a plate layer; gate electrodes stacked in first to third regions at a distance from each other along a first direction perpendicular to an upper surface of the plate layer, the gate electrodes including a lower gate electrode, a memory gate electrode, and an upper gate electrode stacked in sequence on the plate layer; a channel structure penetrating the gate electrodes and extending in the first direction in the first region; first contact plugs penetrating at least one of the upper gate electrodes from above and electrically connected to the upper gate electrodes, respectively, in the second region; second contact plugs penetrating a portion of the gate electrodes including the upper gate electrode from above and electrically connected to the memory gate electrode and the lower gate electrode, respectively, in the third region; the gate electrode includes gate isolation regions that penetrate the entire gate electrode, extend along a second direction perpendicular to the first direction, and are spaced apart from each other in a third direction perpendicular to the first and second directions; a first upper isolation region that penetrates the upper gate electrode between the gate isolation regions in the first and second regions and extends in the second direction; and a second upper isolation region that is connected to an end of the first upper isolation region at a boundary between the second and third regions and extends in the third direction through the upper gate electrode, the first contact plugs being arranged in at least one line shape across the first upper isolation region along the third direction perpendicular to the first and second directions, and each of the first contact plugs may be in contact with at least one side of the first upper isolation region along the third direction.

[0006] a gate electrode including a lower gate electrode, a memory gate electrode, and an upper gate electrode stacked sequentially on the plate layer and spaced apart from each other along a first direction perpendicular to an upper surface of the plate layer; a channel structure extending through the gate electrode along the first direction; first contact plugs electrically connected to the upper gate electrode; second contact plugs electrically connected to the memory gate electrode and the lower gate electrode from above and passing through a portion of the gate electrode; a gate isolation region extending through the entire gate electrode along a second direction perpendicular to the first direction and spaced apart from a third direction perpendicular to the first and second directions; and a first upper isolation region extending in the second direction through the upper gate electrode between the gate isolation regions, wherein each of the first contact plugs contacts at least one of the first upper isolation regions, and the second contact plugs are spaced apart from the first upper isolation region.

[0007] A data storage system according to an exemplary embodiment includes a semiconductor memory device including a first semiconductor structure including a circuit element, a second semiconductor structure disposed on one side of the first semiconductor structure, and an input / output pad electrically connected to the circuit element, and a controller electrically connected to the semiconductor memory device via the input / output pad and controlling the semiconductor memory device, wherein the second semiconductor structure includes a plate layer, gate electrodes stacked on the plate layer at a distance from each other along a first direction perpendicular to an upper surface of the plate layer, the gate electrodes including a first gate electrode and a second gate electrode on the first gate electrode, and a gate electrode stacked on the first gate electrode along the first direction. and second contact plugs disposed on one side of the first contact plugs in a second direction perpendicular to the first direction, extending through the first contact plugs along the first direction, and electrically connected to the second gate electrodes, respectively. The first contact plugs may be arranged in columns along a third direction perpendicular to the first and second directions, the number of columns being the same as the number of the second gate electrodes, and the second contact plugs may be arranged in a different form from the first contact plugs. [Effects of the Invention]

[0008] The first contact plugs are arranged to be divided by the first upper isolation region, thereby providing a semiconductor device with improved integration and a data storage system including the same.

[0009] The various yet significant advantages and effects of the present invention are not limited to the above, but can be more easily understood in the course of describing specific embodiments of the present invention. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a schematic plan view of a semiconductor device according to an exemplary embodiment; [Figure 2a] 1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 2b]1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 2c] 1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 3a] 1 is a partially enlarged view showing a partial area of ​​a semiconductor device according to an exemplary embodiment; [Figure 3b] 1 is a partially enlarged view showing a partial area of ​​a semiconductor device according to an exemplary embodiment; [Figure 3c] 1 is a partially enlarged view showing a partial area of ​​a semiconductor device according to an exemplary embodiment; [Figure 4a] 1 is a plan view of a semiconductor device according to an exemplary embodiment; [Figure 4b] 1 is a plan view of a semiconductor device according to an exemplary embodiment; [Figure 5a] 1 is a plan view of a semiconductor device according to an exemplary embodiment; [Figure 5b] 1 is a plan view of a semiconductor device according to an exemplary embodiment; [Figure 6a] 1 is a plan view of a semiconductor device according to an exemplary embodiment; [Figure 6b] 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 7] 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 8] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 9a] 1A to 1C are schematic plan views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 9b] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 10] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 11] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 12]1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 13] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 14] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 15] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 16] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 17] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 18a] 1A to 1C are schematic plan views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 18b] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 19] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 20] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 21] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 22] 1 is a diagram that schematically illustrates a data storage system including a semiconductor device according to an exemplary embodiment; [Figure 23] 1 is a perspective view that schematically illustrates a data storage system including a semiconductor device according to an exemplary embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

[0012] Fig. 1 is a schematic plan view of a semiconductor device according to an exemplary embodiment, and Figs. 2a to 2c are schematic cross-sectional views of the semiconductor device according to an exemplary embodiment, showing cross sections along cutting lines I-I', II-II', and III-III' in Fig. 1, respectively.

[0013] 3a to 3c are enlarged partial views showing enlarged portions of a semiconductor device according to an exemplary embodiment, and FIGS. 3a to 3c respectively show enlarged portions of area "A" in FIG. 2a, area "B" in FIG. 2b, and area "C" in FIG. 2c.

[0014] 1 to 3c, the semiconductor device 100 may include first and second semiconductor structures S1 and S2 stacked one above the other. The first semiconductor structure S1 may include a memory cell region, and the second semiconductor structure S2 may include a peripheral circuit region. In some embodiments, the second semiconductor structure S2 may be disposed below the first semiconductor structure S1. FIG. 1 shows a planar layout of the main components of the first semiconductor structure S1.

[0015] The first semiconductor structure S1 may include first to third regions R1, R2, and R3. The first semiconductor structure S1 includes a plate layer 101, a gate electrode 130 stacked on the plate layer 101 to form a gate structure GS, an interlayer insulating layer 120 stacked alternately with the gate electrode 130 to form the gate structure GS, a channel structure CH disposed to penetrate the gate structure GS in the first region R1, a gate isolation region MS extending to penetrate the gate structure GS in the first to third regions R1, R2, and R3, and first and second upper gate electrodes 130U1 disposed in the upper part of the gate electrode 130. , 130U2, a first contact plug MC1 connected to the first and second upper gate electrodes 130U1, 130U2 and extending vertically in the second region R2, a second contact plug MC2 connected to the memory gate electrode 130M and the bottom gate electrode 130L and extending vertically in the third region R3, and first and second dummy vertical structures DH1, DH2 disposed around the first and second contact plugs MC1, MC2. The first semiconductor structure S1 may further include a contact insulating layer 160 surrounding the first and second contact plugs MC1, MC2, a stud 180, a cell wiring line 185, a first bonding via 195, a first bonding metal layer 198, a first bonding insulating layer 199, and a cell region insulating layer 190.

[0016] In the first semiconductor structure S1, the first region R1 may be a region where a channel structure CH is disposed, i.e., a region where a memory cell is disposed. The second and third regions R2 and R3 may correspond to regions for electrically connecting the gate electrode 130 to the second semiconductor structure S2. The second and third regions R2 and R3 may be sequentially disposed from the first region R1 at least at one end of the first region R1 in at least one direction, e.g., the x-direction. The second region R2 may be disposed with a first contact plug MC1 and a first dummy vertical structure DH1, and the third region R3 may be disposed with a second contact plug MC2 and a second dummy vertical structure DH1. Depending on the explanation, the first to third regions R1, R2, and R3 may also be referred to as regions of the semiconductor device 100 or the plate layer 101, rather than regions of the first semiconductor structure S1.

[0017] The plate layer 101 has a plate shape and can function as at least a part of a common source line of the semiconductor device 100. The plate layer 101 can include a conductive material. For example, the plate layer 101 can include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor can include silicon, germanium, or silicon-germanium. The plate layer 101 can further include impurities. The plate layer 101 can be provided as a polycrystalline semiconductor layer, such as a polycrystalline silicon layer, or an epitaxial layer.

[0018] The gate electrodes 130 may be stacked vertically on the plate layer 101 and spaced apart from one another to form a gate structure GS together with the interlayer insulating layer 120. The gate structure GS may include first to fourth stack structures GS1, GS2, GS3, and GS4 stacked vertically. However, the number of stack structures forming the gate structure GS may vary depending on the embodiment. For example, in some embodiments, the gate structure GS may be composed of less than four, five or more stack structures, or a single stack structure. The number of gate electrodes 130 forming each of the first to fourth stack structures GS1, GS2, GS3, and GS4 may be the same or different.

[0019] The gate electrode 130 may include first and second upper gate electrodes 130U1 and 130U2 forming a string select transistor and an erase transistor, a memory gate electrode 130M forming a plurality of memory cells, and a bottom gate electrode 130L forming a ground select transistor. The number of memory gate electrodes 130M may be determined depending on the capacity of the semiconductor device 100. The first upper gate electrode 130U1 may form an erase transistor, and the second upper gate electrode 130U2 may form a string select transistor. The second upper gate electrode 130U2 may be disposed between the first upper gate electrode 130U1 and the memory gate electrode 130M. In some embodiments, the first upper gate electrode 130U1 may be omitted. In some embodiments, the bottom gate electrode 130L may also include a gate electrode forming an erase transistor. Depending on the embodiment, the number of gate electrodes 130 forming the first and second upper gate electrodes 130U1 and 130U2 and the bottom gate electrode 130L may vary. Some of the gate electrodes 130, for example, the memory gate electrode 130M adjacent to the second upper gate electrode 130U2 and / or the lower gate electrode 130L, may be dummy gate electrodes. In the claims, the gate electrodes 130 excluding the first and second upper gate electrodes 130U1 and 130U2 may be referred to as first gate electrodes, and the first and second upper gate electrodes 130U1 and 130U2 may also be referred to as second gate electrodes.

[0020] 1, the gate electrodes 130 may be arranged to be separated from each other in the y direction by gate isolation regions MS that extend continuously in the first to third regions R1, R2, and R3. The gate electrodes 130 between a pair of gate isolation regions MS may form one memory block, but the scope of the memory block is not limited thereto.

[0021] The gate electrodes 130 may be stacked vertically and spaced apart from each other in the first to third regions R1, R2, and R3. The gate electrodes 130 may have a stacked shape without forming a stepped shape in the second and third regions R2 and R3. Thus, a portion of the first contact plug MC1 and the second contact plug MC2 may penetrate at least one gate electrode 130 from above and be connected to the gate electrode 130. An end of the gate electrode 130 in the x-direction may be located outside the third region R3.

[0022] 3a and 3b, each gate electrode 130 may include a gate barrier layer 132 and a gate conductive layer 135. The gate barrier layer 132 may cover the upper and lower surfaces of the gate conductive layer 135 and may also cover a portion of the side surfaces. The gate barrier layer 132 may expose the gate conductive layer 135 at the side surfaces of the gate electrode 130 that contact the gate isolation region MS, and may cover the gate conductive layer 135 at the side surfaces that contact the channel structure CH, the first and second dummy vertical structures DH1 and DH2, and the contact insulating layer 160. In some embodiments, the gate barrier layer 132 may at least partially extend along the lower surfaces of the first and second contact plugs MC1 and MC2.

[0023] The gate electrode 130 may include a conductive material such as a metallic material or a semiconductor material. For example, the gate barrier layer 132 may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof, and the gate conductive layer 135 may include tungsten (W).

[0024] The interlayer insulating layers 120 may be disposed between the gate electrodes 130. Similar to the gate electrodes 130, the interlayer insulating layers 120 may be disposed to extend in the x-direction and spaced apart from each other in a direction perpendicular to the top surface of the plate layer 101. The interlayer insulating layers 120 may include an insulating material such as silicon oxide or silicon nitride. In an embodiment, the thickness of each of the interlayer insulating layers 120 may vary.

[0025] The channel structures CH may extend in the z-direction through the gate electrode 130 and be connected to the plate layer 101. Each channel structure CH may form one memory cell string and may be spaced apart from each other while forming rows and columns on the plate layer 101 in the first region R1. The channel structures CH may be arranged in a lattice pattern in the xy plane or in a staggered pattern in one direction. The channel structures CH may have a pillar shape and have sloping sides that become narrower as they approach the plate layer 101. The channel structures CH may be arranged in the y-direction between a pair of gate isolation regions MS, for example, 32 in number, but the number of channel structures CH and the corresponding arrangement may vary depending on the embodiment.

[0026] The channel structure CH may include first to fourth channel portions CH1, CH2, CH3, and CH4, which are vertically stacked. The first to fourth channel portions CH1, CH2, CH3, and CH4 may penetrate first to fourth gate structures GS1, GS2, GS3, and GS4 of the gate structure GS, respectively. The first to fourth channel portions CH1, CH2, CH3, and CH4 may be connected to each other, and may have a shape in which the width of the upper surface of the lower channel portion is greater than the width of the lower surface of the upper channel portion at the connected region or interface. The channel structure CH may have a bent portion at the interface between the first to fourth channel portions CH1, CH2, CH3, and CH4 due to the difference in width. The lower end of the first channel portion CH1 may be located within the plate layer 101.

[0027] Each of the channel structures CH may include a channel layer 140 disposed in a channel hole, a channel dielectric layer 145, a channel-buried insulating layer 147, and a channel pad 149. The channel layer 140, the channel dielectric layer 145, and the channel-buried insulating layer 147 may be connected to each other among the first to fourth channel portions CH1, CH2, CH3, and CH4.

[0028] 3c, the channel layer 140 may be formed in an annular shape surrounding the inner channel buried insulating layer 147. Within the plate layer 101, the channel layer 140 may be exposed from the channel dielectric layer 145 and may contact the plate layer 101, and may be electrically connected to the plate layer 101. The channel layer 140 may include a semiconductor material such as polycrystalline silicon or single crystalline silicon.

[0029] The channel dielectric layer 145 may be disposed between the gate electrode 130 and the channel layer 140. Although not specifically illustrated, the channel dielectric layer 145 may include a tunneling layer, a charge storage layer, and a blocking layer, which are sequentially stacked on the channel layer 140. The tunneling layer may tunnel charges to the charge storage layer and may include, for example, silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or a combination thereof. The charge storage layer may be a charge trap layer or a floating gate conductive layer. The blocking layer may include silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof. In an exemplary embodiment, at least a portion of the channel dielectric layer 145 may extend horizontally along the gate electrode 130. The channel pad 149 may be disposed only on an upper end of the upper fourth channel portion CH4. The channel pad 149 may include, for example, doped polycrystalline silicon.

[0030] The gate isolation regions MS may be arranged to extend in the x direction through the gate electrode 130. As shown in FIG. 1, the gate isolation regions MS may be arranged parallel to one another. However, the arrangement and number of the gate isolation regions MS are not limited to those shown in FIG. 1. For example, in some embodiments, the gate isolation regions MS may be further arranged in a discontinuous manner in the first to third regions R1, R2, and R3.

[0031] As shown in FIG. 2b, the gate isolation region MS may be connected to the plate layer 101 by penetrating the gate electrode 130 stacked on the plate layer 101. The gate isolation region MS may have a shape in which its width decreases toward the plate layer 101 due to a high aspect ratio. The gate isolation region MS may have bent portions corresponding to the first and fourth channel portions CH1, CH2, CH3, and CH4. Although not specifically shown in FIG. 1, the gate isolation region MS may have a bent side along the y direction in a plan view. The gate isolation region MS may include an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0032] As shown in FIG. 1, the first upper isolation region SS1 may extend in the x-direction between a pair of gate isolation regions MS. The first upper isolation region SS1 may be disposed in the first and second regions R1 and R2. The first upper isolation region SS1 may penetrate the first and second upper gate electrodes 130U1 and 130U2 of the gate electrode 130. As shown in FIG. 1, the first upper isolation region SS1 may divide each of the first and second upper gate electrodes 130U1 and 130U2 into eight layers along the y-direction between the pair of gate isolation regions MS. However, in an exemplary embodiment, the number of first upper isolation regions SS1 disposed between the pair of gate isolation regions MS may vary.

[0033] 1 and 2b, the first upper isolation region SS1 may be disposed between the first contact plugs MC1. The first upper isolation region SS1 may be interposed between adjacent first contact plugs MC1 in the y direction to space the first contact plugs MC1 apart. The first upper isolation region SS1 may penetrate the first contact plugs MC1 constituting the first to seventh columns CL1, CL2, CL3, CL4, CL5, CL6, and CL7 in the y direction. The side surfaces of the first upper isolation region SS1 in the y direction may be in contact with the first contact plugs MC1.

[0034] 1 and 2c, the first upper isolation region SS1 may be disposed to partially cut a portion of the channel structure CH. The first upper isolation region SS1 may extend partially through a portion of the channel structure CH, thereby contacting the channel layer 140. In an exemplary embodiment, the relative arrangement of the first upper isolation region SS1 and the channel structure CH partially penetrated thereby in the plan view of FIG. 1 may be variously changed.

[0035] 1, the second upper isolation region SS2 may be connected to an end of the first upper isolation region SS1 at the boundary between the second region R2 and the third region R3 and may extend in the y direction. The second upper isolation region SS2 may be disposed at the same level as the first upper isolation region SS1 and have the same depth. The width of the second upper isolation region SS2 may be the same as or different from the width of the first upper isolation region SS1. The first and second upper isolation regions SS1 and SS2 divide each of the first and second upper gate electrodes 130U1 and 130U2 into eight electrodes, to which separate electrical signals may be applied.

[0036] The first and second upper isolation regions SS1 and SS2 may include an insulating material, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0037] The first and second contact plugs MC1 and MC2 may be physically and electrically connected to the gate electrode 130. The first contact plug MC1 may be connected to the first and second upper gate electrodes 130U1 and 130U2 in a second region R2 adjacent to the first region R1. The second contact plug MC2 may be connected to the memory gate electrode 130M and the lower gate electrode 130L in a third region R3 outside the second region R2.

[0038] 1, the first contact plugs MC1 may be arranged in first to seventh columns CL1, CL2, CL3, CL4, CL5, CL6, and CL7 along the y direction in a plan view. Each of the first contact plugs MC1 in the first to seventh columns CL1, CL2, CL3, CL4, CL5, CL6, and CL7 may have a line shape with a first upper isolation region SS1 interposed therebetween. However, in embodiments, the specific shape of the line shape, such as width and degree of corner rounding, may be variously changed. The first to seventh columns CL1, CL2, CL3, CL4, CL5, CL6, and CL7 may be spaced apart from one another in the x direction.

[0039] The first contact plugs MC1 in the same column among the first to seventh columns CL1, CL2, CL3, CL4, CL5, CL6, and CL7 may extend to the same depth, and the first contact plugs MC1 in different columns may have different depths. For example, the first contact plugs MC1 in the first column CL1 may be connected to the uppermost first upper gate electrode 130U1, and the first contact plugs MC1 in the second column CL2 may be connected to the underlying first upper gate electrode 130U1. The number of columns may be the same as the number of first and second upper gate electrodes 130U1 and 130U2. The number of first contact plugs MC1 in each of the first to seventh columns CL1, CL2, CL3, CL4, CL5, CL6, and CL7 may be one more than the number of first upper isolation regions SS1.

[0040] The first contact plugs MC1 may be connected to the first and second upper gate electrodes 130U1 and 130U2 by penetrating at least one of the first and second upper gate electrodes 130U1 and 130U2, except for the first contact plug MC1 connected to the uppermost first upper gate electrode 130U1. The first contact plugs MC1 may be electrically isolated from the first and second upper gate electrodes 130U1 and 130U2 by the contact insulating layer 160.

[0041] At least one of the first side surfaces of each of the first contact plugs MC1 along the y direction may be in contact with the first upper isolation region SS1. In a plan view, each of the first contact plugs MC1 arranged between adjacent first upper isolation regions SS1 along the y direction may be in contact with all of the adjacent first upper isolation regions SS1. Outer surfaces of the first side surfaces of the first contact plugs MC1 located at both ends along the y direction of each of the first to seventh columns CL1, CL2, CL3, CL4, CL5, CL6, and CL7 may be covered with the contact insulating layer 160. A second side surface of each of the first contact plugs MC1 along the x direction may be covered with the contact insulating layer 160.

[0042] The second contact plugs MC2 are disposed in the third region R3 and may have a different shape and be arranged in a different pattern from the first contact plugs MC1 in a plan view. The second contact plugs MC2 may have a circular or elliptical shape in a plan view and be spaced apart from each other in the x and y directions, as shown in FIG. 1. The second contact plugs MC2 may be arranged in a grid or staggered pattern.

[0043] The second contact plugs MC2 may be spaced apart by at least a portion of the gate electrode 130. A gate electrode 130 may be interposed between adjacent second contact plugs MC2. Each side of the second contact plug MC2 may be covered with a contact insulating layer 160. The second contact plug MC2 may penetrate all of the first and second upper gate electrodes 130U1 and 130U2 and be connected to the memory gate electrode 130M and the lower gate electrode 130L, respectively. The number of second contact plugs MC2 disposed between a pair of gate isolation regions MS may be equal to or greater than the number of the memory gate electrodes 130M and the lower gate electrodes 130L.

[0044] The first contact plug MC1 may have a width of a first length L1 in the x-direction and a width of a second length L2 in the y-direction. For example, the second length L2 may be equal to or greater than the first length L1, but is not limited to this. The second length L2 may be, for example, in the range of about 400 nm to 550 nm. The second contact plug MC2 may have a diameter or width of a third length L3. The third length L3 may be equal to or greater than the second length L2. However, in exemplary embodiments, the relative sizes of the first contact plug MC1 and the second contact plug MC2 may vary.

[0045] The first and second contact plugs MC1 and MC2 may extend in the z-direction only from the top to the gate electrode 130 to which they are electrically connected. The first and second contact plugs MC1 and MC2 may be connected by partially recessing the gate electrode 130 from the top. However, the depth by which the first and second contact plugs MC1 and MC2 recess the gate electrode 130 may vary depending on the embodiment. Each of the first and second contact plugs MC1 and MC2 may have a shape that extends horizontally from the top end.

[0046] 3a and 3b, each of the first and second contact plugs MC1 and MC2 may include a contact barrier layer 172 and a contact conductive layer 175 on the contact barrier layer 172. The contact barrier layer 172 may cover the upper surface, the lower surface, and part of the side surfaces of the contact conductive layer 175. For example, in the first contact plug MC1, the contact barrier layer 172 may cover all of the side surfaces of the contact conductive layer 175 in the y direction and may cover the side surfaces in the x direction that do not contact the first upper isolation region SS1. In the side surfaces of the first contact plug MC1 that contact the first upper isolation region SS1, the contact conductive layer 175 may be exposed from the contact barrier layer 172 and be in direct contact with the first upper isolation region SS1.

[0047] The first and second contact plugs MC1 and MC2 may include at least one of a conductive material, such as tungsten (W), copper (Cu), aluminum (Al), and alloys thereof. For example, the contact barrier layer 172 may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof, and the contact conductive layer 175 may include tungsten (W).

[0048] The contact insulating layer 160 may be disposed on a portion of each side of the first contact plug MC1 and on each side of the second contact plug MC2. The lower end of the contact insulating layer 160 may be located at a higher level than the lower ends of the first and second contact plugs MC1 and MC2, but is not limited to this. The contact insulating layer 160 may include an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0049] The first dummy vertical structures DH1 may be arranged spaced apart from each other in rows and columns on the plate layer 101 in the second region R2. As shown in FIG. 1, the first dummy vertical structures DH1 may be arranged in a staggered pattern, partially overlapping the first contact plugs MC1 in a plan view.

[0050] The second dummy vertical structures DH2 may be spaced apart from each other and arranged in rows and columns on the plate layer 101 in the third region R3. As shown in FIG. 1, the second dummy vertical structures DH2 may be arranged in a regular pattern around the second contact plug MC2. The second dummy vertical structures DH2 may be arranged in a different pattern from the first dummy vertical structures DH1. However, in some embodiments, the arrangement of the first and second dummy vertical structures DH1 and DH2 may be the same, and the specific patterns may vary.

[0051] The first and second dummy vertical structures DH1 and DH2 may have a circular, elliptical, or similar shape in a plan view. The first and second dummy vertical structures DH1 and DH2 may have a pillar shape penetrating the gate electrode 130 and may have sloping side surfaces that become narrower toward the plate layer 101 according to the aspect ratio. The first and second dummy vertical structures DH1 and DH2 may have the same diameter, and the diameters of the first and second dummy vertical structures DH1 and DH2 may be larger than the diameter of the channel structure CH, but are not limited thereto. In some embodiments, the second dummy vertical structure DH2 may have a larger diameter than the first dummy vertical structure DH1.

[0052] The first and second dummy vertical structures DH1 and DH2 may include regions protruding from their side surfaces toward the gate electrode 130. The first and second dummy vertical structures DH1 and DH2 may have bent portions corresponding to the first and fourth channel portions CH1, CH2, CH3, and CH4. The first dummy vertical structure DH1 may contact a portion of the side surface of the first contact plug MC1 along the x-direction.

[0053] The first and second dummy vertical structures DH1 and DH2 may not include a conductive layer and may include an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0054] The cell region insulating layer 190 may be disposed to cover the gate structure GS. The cell region insulating layer 190 may include multiple insulating layers depending on the embodiment. The cell region insulating layer 190 may be made of an insulating material, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0055] The stud 180 and the cell wiring line 185 may constitute a cell wiring structure electrically connected to the memory cell. The stud 180 may penetrate a portion of the cell region insulating layer 190 to be connected to the channel structure CH and first and second contact plugs MC1 and MC2, and electrically connected to the channel layer 140 and the gate electrode 130. The stud 180 may have a plug shape, and the cell wiring line 185 may have a line shape, but is not limited thereto. The stud 180 and the cell wiring line 185 may include a metal, for example, tungsten (W), copper (Cu), aluminum (Al), etc.

[0056] The first bonding via 195, the first bonding metal layer 198, and the first bonding insulating layer 199 may form a first bonding structure of the first semiconductor structure S1. The first bonding via 195 may be disposed on the cell wiring line 185, and the first bonding metal layer 198 may be connected to the first bonding via 195. The top surface of the first bonding metal layer 198 may be exposed to the top surface of the first substrate structure S1. The first bonding metal layer 198 may be bonded to and connected to a second bonding metal layer 298 of the second substrate structure S2. The first bonding via 195 and the first bonding metal layer 198 may include a conductive material, such as copper (Cu). The first bonding insulating layer 199 may form a dielectric-dielectric bond with the second bonding insulating layer 299 of the second substrate structure S2. The first bonding insulating layer 199 may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0057] The peripheral circuit region PERI may include a substrate 201, source / drain regions 205 and an element isolation layer 210 in the substrate 201, a circuit element 220 disposed on the substrate 201, a peripheral region insulating layer 290, a circuit contact plug 270, a circuit wiring line 280, a second bonding via 295, a second bonding metal layer 298, and a second bonding insulating layer 299.

[0058] The substrate 201 may have a bottom surface extending in the x- and y-directions. An active region may be defined in the substrate 201 by an isolation layer 210. A source / drain region 205 containing impurities may be disposed in a portion of the active region. The substrate 201 may include a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The substrate 201 may be provided as a bulk wafer or an epitaxial layer.

[0059] The circuit elements 220 may include planar transistors. Each circuit element 220 may include a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. On both sides of the circuit gate electrode 225, source / drain regions 205 may be disposed in the substrate 201 as source / drain regions.

[0060] The peripheral region insulating layer 290 may be disposed on the lower surface of the substrate 201 to cover the circuit elements 220. The peripheral region insulating layer 290 may include multiple insulating layers formed in different process steps. The peripheral region insulating layer 290 may be made of an insulating material.

[0061] The circuit contact plugs 270 and the circuit wiring lines 280 may form a circuit wiring structure electrically connected to the circuit elements 220 and the source / drain regions 205. The circuit contact plugs 270 may have a cylindrical shape, and the circuit wiring lines 280 may have a line shape. An electrical signal may be applied to the circuit elements 220 through the circuit contact plugs 270 and the circuit wiring lines 280. In a region not shown, the circuit contact plugs 270 may also be connected to the circuit gate electrodes 225. The circuit wiring lines 280 may be connected to the circuit contact plugs 270 and may be arranged in multiple layers. The circuit contact plugs 270 and the circuit wiring lines 280 may include a conductive material, such as tungsten (W), copper (Cu), or aluminum (Al), and each may further include a diffusion barrier layer. In an exemplary embodiment, the number of layers of the circuit contact plugs 270 and the circuit wiring lines 280 may vary.

[0062] The second bonding via 295, the second bonding metal layer 298, and the second bonding insulating layer 299 constitute a second bonding structure and may be disposed under a portion of the lowest circuit wiring line 280. The second bonding via 295 may have a cylindrical shape, and the second bonding metal layer 298 may have a pad shape or a relatively short line shape having a circular shape on a planar surface. The lower surface of the second bonding metal layer 298 may be exposed to the lower surface of the second substrate structure S2. The second bonding via 295 and the second bonding metal layer 298 may provide an electrical connection path with the first semiconductor structure S1. In an exemplary embodiment, a portion of the second bonding metal layer 298 may not be connected to the circuit wiring line 280 and may be disposed solely for bonding. The second bonding via 295 and the second bonding metal layer 298 may include a conductive material, such as copper (Cu).

[0063] The second bonding insulating layer 299 may be disposed to a predetermined thickness from the lower surface of the peripheral region insulating layer 290. The second bonding insulating layer 299 may be a layer for dielectric-dielectric bonding with the first bonding insulating layer 199 of the first semiconductor structure S1. The second bonding insulating layer 299 may also function as a diffusion barrier layer for the second bonding metal layer 298 and may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0064] The first and second semiconductor structures S1 and S2 may be bonded by bonding the first bonding metal layer 198 to the second bonding metal layer 298 and bonding the first bonding insulating layer 199 to the second bonding insulating layer 299. The bonding between the first bonding metal layer 198 and the second bonding metal layer 298 may be, for example, copper (Cu)-copper (Cu) bonding, and the bonding between the first bonding insulating layer 199 and the second bonding insulating layer 299 may be, for example, dielectric-dielectric bonding such as SiCN-SiCN bonding. The first and second semiconductor structures S1 and S2 may be bonded by hybrid bonding including copper (Cu)-copper (Cu) bonding and dielectric-dielectric bonding.

[0065] The first and second semiconductor structures S1 and S2 may be packaged with the first semiconductor structure S1 located on the bottom as shown in FIGS. 2a to 2c, or alternatively, may be packaged upside down with the second semiconductor structure S2 located on the bottom.

[0066] 4a and 4b are plan views of a semiconductor device according to an example embodiment.

[0067] 4a, in the semiconductor device 100a, the first contact plugs MC1a may be arranged in the form of a plurality of lines with first upper isolation regions SS1 interposed therebetween along the y direction between pairs of gate isolation regions MS. The first contact plugs MC1a may be arranged in two lines with first upper isolation regions SS1 interposed therebetween in each of the first to seventh columns CL1, CL2, CL3, CL4, CL5, CL6, and CL7. The distance L4 between the two lines, the degree of corner rounding in a plan view, and the like may be variously modified in various embodiments.

[0068] In this embodiment, the first upper isolation region SS1 that is disposed at the center along the y direction in a plan view among the first upper isolation region SS1 can be prevented from contacting the first contact plug MC1a.

[0069] 4b, in the semiconductor device 100b, the first contact plugs MC1b may be arranged in four lines with the first upper isolation region SS1 interposed therebetween in each of the first to seventh columns CL1, CL2, CL3, CL4, CL5, CL6, and CL7. In this embodiment, the first contact plugs MC1b may be described as having a rectangular or elliptical shape. One side of each of the first contact plugs MC1b along the y direction may contact the first upper isolation region SS1, and the other side may be spaced apart from the first upper isolation region SS1.

[0070] The first upper isolation regions SS1 may be arranged alternately along the y direction in a plan view, with the first upper isolation regions SS1 in contact with the first contact plugs MC1b and the first upper isolation regions SS1 not in contact with the first contact plugs MC1b.

[0071] Thus, in an exemplary embodiment, the first contact plugs MC1a, MC1b may be arranged in the shape of multiple lines along the y direction between a pair of gate isolation regions MS, and the number of the multiple lines may be varied in various ways in the embodiment.

[0072] 5a and 5b are plan views of a semiconductor device according to an example embodiment.

[0073] 5a, in the semiconductor device 100c, the first contact plugs MC1c adjacent to the gate isolation regions MS in the y direction can be in contact with the gate isolation regions MS. In each of the first to seventh columns CL1, CL2, CL3, CL4, CL5, CL6, and CL7, the two first contact plugs MC1c located at both ends in the y direction can be in contact with the gate isolation regions MS.

[0074] 5b, in the semiconductor device 100d, some of the first contact plugs MC1d adjacent to the gate isolation regions MS in the y-direction may be in contact with the gate isolation regions MS, and other parts may be spaced apart from the gate isolation regions MS. In each of the first to seventh columns CL1, CL2, CL3, CL4, CL5, CL6, and CL7, the first contact plugs MC1d located at one end in the y-direction may be in contact with the gate isolation regions MS, and the first contact plugs MC1d located at the other end may be spaced apart from the gate isolation regions MS.

[0075] As described above, in the exemplary embodiment, the first contact plugs MC1c and MC1d may have a structure formed by patterning across a plurality of memory blocks.

[0076] 6a and 6b are a plan view and a cross-sectional view of a semiconductor device according to an exemplary embodiment, with FIG. 6b showing a cross section taken along line IV-IV' in FIG. 6a.

[0077] 6a and 6b, in the semiconductor device 100e, the arrangement of the first and second dummy vertical structures DH1 and DH2 may be different from that of the embodiment of FIGS. 1 to 3c. The first dummy vertical structure DH1 may be arranged so as not to overlap with the first contact plug MC1. As a result, as shown in FIG. 6b, the first dummy vertical structure DH1 may be arranged spaced apart from the first contact plug MC1 in a cross-sectional view. The second dummy vertical structures DH2 may be arranged in a regular pattern, for example, a hexagonal shape, between and together with the second contact plugs MC2.

[0078] In this manner, in the exemplary embodiment, the arrangements of the first and second dummy vertical structures DH1 and DH2 can be varied independently of each other. In the exemplary embodiment, the arrangements of the first and second dummy vertical structures DH1 and DH2 in FIG. 1 and the arrangements of the first and second dummy vertical structures DH1 and DH2 in this embodiment can be combined with each other independently.

[0079] FIG. 7 is a cross-sectional view of a semiconductor device according to an exemplary embodiment.

[0080] 7, in the semiconductor device 100f, the second semiconductor structure S2 may be disposed below the first semiconductor structure S1. The second semiconductor structure S2 may further include a fourth region R4, and may further include a through via TH, first and second horizontal conductive layers 102 and 104, a horizontal insulating layer 110, and a substrate insulating layer 121 disposed in the fourth region R4. In the semiconductor device 100f, the first semiconductor structure S1 may have a structure formed on the second semiconductor structure S2 rather than a structure bonded to the second semiconductor structure S2. As a result, the first and second semiconductor structures S1 and S2 may not include the above-mentioned bonding structure.

[0081] The fourth region R4 may be a region where the gate electrode 130 does not extend. In the fourth region R4, sacrificial insulating layers 118 and interlayer insulating layers 120 may be alternately stacked on the plate layer 101. The through vias TH may extend into the second semiconductor structure S2 through the stacked structure of the sacrificial insulating layers 118 and the interlayer insulating layers 120. However, in some embodiments, the through vias TH may be arranged to penetrate an insulating region formed after the sacrificial insulating layer 118 is removed.

[0082] The through vias TH may electrically connect the cell wiring lines 185 and the circuit wiring lines 280. The through vias TH may be electrically isolated from the plate layer 101 by the substrate insulating layer 121. The through vias TH may have bent portions corresponding to the first and fourth channel portions CH1, CH2, CH3, and CH4 (see FIG. 2c) of the channel structure CH. However, in some embodiments, the through vias TH may not have the bent portions and may extend at a constant slope from the top to the bottom.

[0083] The first and second horizontal conductive layers 102 and 104 may be sequentially stacked on the upper surface of the plate layer 101 in the first region R1. The first and second horizontal conductive layers 102 and 104 may form a common source structure together with the plate layer 101 and function as a common source line of the semiconductor device 100f. The first horizontal conductive layer 102 may be directly connected to the channel layer 140 under the channel structure CH.

[0084] The first and second horizontal conductive layers 102 and 104 may include a semiconductor material, such as polycrystalline silicon. In this case, at least the first horizontal conductive layer 102 may be a layer doped with impurities of the same conductivity type as the plate layer 101. The second horizontal conductive layer 104 may be a doped layer or a layer containing impurities diffused from the first horizontal conductive layer 102.

[0085] The horizontal insulating layer 110 may be disposed on the plate layer 101 at the same level as the first horizontal conductive layer 102 in at least a portion of the second to fourth regions R2, R3, and R4. The horizontal insulating layer 110 may include first and second horizontal insulating layers alternately stacked on the plate layer 101. The horizontal insulating layer 110 may be a layer that remains after a portion of it is replaced by the first horizontal conductive layer 102 during the manufacturing process of the semiconductor device 100f.

[0086] The horizontal insulating layer 110 may include silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. The first horizontal insulating layer and the second horizontal insulating layer may include different insulating materials.

[0087] The substrate insulating layer 121 may be disposed in the fourth region R2 to penetrate the plate layer 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104. The substrate insulating layer 121 may include an insulating material, such as silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.

[0088] Figures 8 to 21 are schematic plan views and cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment, where Figures 9a and 18a show plan views corresponding to Figure 1, and Figures 8, 9b, 10 to 17, 18b, 19, and 21 each show cross sections corresponding to Figure 2a.

[0089] 8, a manufacturing process for a first substrate structure S1 can be started. Sacrificial insulating layers 118 and interlayer insulating layers 120 can be alternately stacked on a base substrate SUB to form a mold structure PS and a vertical sacrificial structure VS penetrating the mold structure PS, thereby forming a part of a cell region insulating layer 190.

[0090] The base substrate SUB is a layer that is removed in a subsequent process and may be a semiconductor substrate such as a silicon (Si) wafer. A first mold stack structure PS1 of the mold structure PS is formed first, and then a portion of the vertical sacrificial structure VS penetrating the first mold stack structure PS1 is formed. A second mold stack structure PS2 is then formed, and a portion of the vertical sacrificial structure VS penetrating the second mold stack structure PS2 is also formed. Third and fourth mold stack structures PS3 and PS4 and portions of the vertical sacrificial structure VS may be formed in the same manner.

[0091] The sacrificial insulating layer 118 may be a layer that will be replaced by the gate electrode 130 (see FIG. 2a) through a subsequent process. The sacrificial insulating layer 118 may be made of a different material from the interlayer insulating layer 120 and may be formed of a material that can be etched with etching selectivity to the interlayer insulating layer 120 under specific etching conditions. For example, the interlayer insulating layer 120 may be made of at least one of silicon oxide and silicon nitride, and the sacrificial insulating layer 118 may be made of a different material from the interlayer insulating layer 120, selected from silicon, silicon oxide, silicon carbide, and silicon nitride. In an embodiment, the interlayer insulating layers 120 may not all have the same thickness. The thicknesses and number of layers constituting the interlayer insulating layer 120 and the sacrificial insulating layer 118 may be variously changed from those shown in the drawings.

[0092] The vertical sacrificial structures VS may be formed at positions corresponding to the channel structure CH, the first and second dummy vertical structures DH1 and DH2, and the gate isolation regions MS in FIG. 2a. The vertical sacrificial structures VS may be formed to have the same size as the channel structure CH. The vertical sacrificial structures VS may include, but are not limited to, carbon (C).

[0093] 9a and 9b, a mask layer ML having first and second openings OP1 and OP2 may be formed on the cell region insulating layer 190.

[0094] The mask layer ML may include a hard mask layer and a photoresist layer. The hard mask layer may include, for example, polycrystalline silicon. The first opening OP1 may be formed in a trench shape extending in the y direction in a region corresponding to the first contact plug MC1 of FIG. 2a. The second opening OP2 may be formed in a circular, elliptical, or similar shape in a region corresponding to the second contact plug MC2 of FIG. 2a. When patterning the mask layer ML, the underlying cell region insulating layer 190 may be partially removed, but is not limited to this.

[0095] Referring to FIG. 10, the mold structure PS may be etched using the mask layer ML to form first and second contact openings OP1' and OP2', and the mask layer ML may then be removed.

[0096] The first and second contact openings OP1' and OP2' may be formed by extending from the first and second openings OP1 and OP2 of the mask layer ML, respectively. The first and second contact openings OP1' and OP2' may be formed by repeatedly performing a plurality of etching processes that etch the mold structure PS to a predetermined depth. In FIG. 10, the sacrificial insulating layer 118 is shown exposed through the bottom surfaces of the first and second contact openings OP1' and OP2', but this is not limited thereto, and the interlayer insulating layer 120 thereover may also be partially left.

[0097] Referring to FIG. 11, a preliminary contact insulating layer 160P and a contact sacrificial layer 129 may be formed in the first and second contact openings OP1' and OP2'.

[0098] The preliminary contact insulating layer 160P may be conformally formed to cover the sidewalls and bottom surfaces of the first and second contact openings OP1′ and OP2′. For example, the preliminary contact insulating layer 160P may be formed using an atomic layer deposition (ALD) or chemical vapor deposition (CVD) process.

[0099] The contact sacrificial layer 129 may be formed on the preliminary contact insulating layer 160P to fill the first and second contact openings OP1′ and OP2′. The contact sacrificial layer 129 may include a different material from the preliminary contact insulating layer 160P, for example, carbon (C).

[0100] Referring to FIG. 12, portions of the vertical sacrificial structures VS may be removed to form channel structures CH.

[0101] In the first region R1, a mask layer exposing only a region corresponding to the channel structure CH may be formed, and the exposed vertical sacrificial structure VS may be removed to form a channel hole. At least a portion of the channel dielectric layer 145, the channel layer 140, the channel buried insulating layer 147, and the channel pad 149 may be sequentially deposited in the channel hole to form the channel structure CH.

[0102] The channel dielectric layer 145 may be formed to have a uniform thickness using an ALD or CVD process. All or a portion of the channel dielectric layer 145 may be formed in this step, and a portion extending perpendicular to the plate layer 101 along the channel structure CH may be formed in this step. The channel layer 140 may be formed on the channel dielectric layer 145 in the channel hole. A channel-filled insulating layer 147 is formed to fill the channel hole and may be made of an insulating material. The channel pad 149 may be made of a conductive material, for example, polycrystalline silicon.

[0103] Referring to FIG. 13, portions of the vertical sacrificial structure VS may be removed to form first and second dummy vertical structures DH1 and DH2.

[0104] In the second and third regions R2 and R3, a mask layer is formed to expose regions corresponding to the first and second dummy vertical structures DH1 and DH2, and the exposed vertical sacrificial structures VS are removed to form dummy holes. A process of partially removing the mold structure PS around the dummy holes to expand the dummy holes may be performed. An insulating material may be filled into the expanded dummy holes to form the first and second dummy vertical structures DH1 and DH2.

[0105] Referring to FIG. 14, the sacrificial insulating layer 118 may be removed to form the gate electrode 130.

[0106] After forming a portion of the cell region insulating layer 190, vertical holes may be formed by removing the vertical sacrificial structures VS at positions corresponding to the gate isolation regions MS of Figure 1. By partially removing the mold structure PS around the vertical holes and expanding the vertical holes so that they are connected to each other, trench-shaped openings corresponding to the gate isolation regions MS may be formed.

[0107] The sacrificial insulating layer 118 exposed through the opening can be removed by, for example, wet etching, selectively removing the sacrificial insulating layer 118 with respect to the interlayer insulating layer 120, the channel structure CH, the first and second dummy vertical structures DH1 and DH2, and the preliminary contact insulating layer 160P.

[0108] The gate electrode 130 may be formed by depositing a conductive material in the area where the sacrificial insulating layer 118 has been removed. The conductive material may include metal, polycrystalline silicon, or a metal silicide material. In the gate electrode 130, the gate conductive layer 135 (see FIG. 3a) may be formed after the gate barrier layer 132 (see FIG. 3a) is formed. In some embodiments, a portion of the channel dielectric layer 145 (see FIG. 3c) may be formed before the gate electrode 130 is formed. This may result in the formation of a gate structure GS including first to fourth stacked structures GS1, GS2, GS3, and GS4. After the gate electrode 130 is formed, an insulating material may be deposited in the opening to form a gate isolation region MS.

[0109] Referring to FIG. 15, the contact sacrificial layer 129 may be removed to form first and second contact openings OP1'', OP2''.

[0110] After removing a portion of the cell region insulating layer 190 on the contact sacrificial layer 129 so that the contact sacrificial layer 129 is exposed, the exposed contact sacrificial layer 129 can be selectively removed relative to the preliminary contact insulating layer 160P.

[0111] Referring to FIG. 16, a portion of the preliminary contact insulating layer 160P may be removed to form the contact insulating layer 160.

[0112] The preliminary contact insulating layer 160P exposed through the first and second contact openings OP1″ and OP2″ may be partially removed from the bottom surfaces of the first and second contact openings OP1″ and OP2″. To this end, a separate spacer layer may be formed on the sidewalls of the first and second contact openings OP1″ and OP2″, but this is not limitative. When the preliminary contact insulating layer 160P is removed, the exposed gate electrode 130 may also be partially recessed from the top surface. As a result, the contact insulating layer 160 disposed only on the sidewalls of the first and second contact openings OP1″ and OP2″ may be formed.

[0113] Referring to FIG. 17, a conductive material may be deposited in the first and second contact openings OP1'' and OP2'' to form first and second contact plugs MC1 and MC2.

[0114] The first and second contact plugs MC1 and MC2 may be formed together by depositing a conductive material in the first and second contact openings OP1″ and OP2″. The first and second contact plugs MC1 and MC2 may be physically connected to the gate electrode 130.

[0115] Referring to FIGS. 18a and 18b, first and second trenches TR1 and TR2 may be formed through the first and second upper gate electrodes 130U1 and 130U2.

[0116] The first and second trenches TR1 and TR2 may be formed by removing a portion of the gate electrode structure GS to penetrate the first and second upper gate electrodes 130U1 and 130U2 in regions corresponding to the first and second upper isolation regions SS1 and SS2 of Fig. 1. The first and second trenches TR1 and TR2 may be formed to extend while cutting a portion of the channel structure CH in the first region R1.

[0117] Referring to FIG. 19, an insulating material may be deposited in the first and second trenches TR1 and TR2 to form first and second upper isolation regions SS1 and SS2, and a stud 180 and a cell wiring line 185 may be formed.

[0118] The first and second upper isolation regions SS1 and SS2 may be formed by filling the first and second trenches TR1 and TR2 with an insulating material and performing a planarization process.

[0119] The stud 180 may be formed by forming a stud hole that penetrates the cell region insulating layer 190 to expose the channel structure CH and the first and second contact plugs MC1 and MC2, and then filling the stud hole with a conductive material. The cell wiring line 185 may be formed on the stud 180.

[0120] Referring to FIG. 20, a first bonding structure is formed to form a first semiconductor structure S1, a second semiconductor structure S2 is formed, and then the first semiconductor structure S1 and the second semiconductor structure S2 can be bonded together.

[0121] The first bonding via 195 and the first bonding metal layer 198 constituting the first bonding structure may be formed by further forming a cell region insulating layer 190 on the cell wiring line 185, forming a first bonding insulating layer 199, partially removing the first bonding insulating layer 199, and depositing a conductive material thereon. An upper surface of the first bonding metal layer 198 may be exposed from the cell region insulating layer 190. Thus, a first semiconductor structure S1 may be prepared.

[0122] The second semiconductor structure S2 can be prepared by forming a circuit element 220, a circuit wiring structure, and a second bonding structure on the substrate 201.

[0123] An isolation layer 210 may be formed in a substrate 201, and a circuit gate dielectric layer 222 and a circuit gate electrode 225 may be sequentially formed on the substrate 201. The isolation layer 210 may be formed, for example, by a shallow trench isolation (STI) process. The circuit gate dielectric layer 222 and the circuit gate electrode 225 may be formed using ALD or CVD. The circuit gate dielectric layer 222 may be formed of silicon oxide, and the circuit gate electrode 225 may be formed of at least one of, but not limited to, polysilicon or a metal silicide layer. A spacer layer 224 and source / drain regions 205 may be formed on both sidewalls of the circuit gate dielectric layer 222 and the circuit gate electrode 225. Depending on the embodiment, the spacer layer 224 may be composed of multiple layers. The source / drain regions 205 may be formed by an ion implantation process.

[0124] The circuit contact plug 270 of the circuit wiring structure and the second bonding via 295 of the second bonding structure may be formed by partially forming a peripheral region insulating layer 290, etching away a portion of the peripheral region insulating layer 290, and then filling the peripheral region insulating layer 290 with a conductive material. The circuit wiring line 280 of the circuit wiring structure and the second bonding metal layer 298 of the second bonding structure may be formed by, for example, depositing a conductive material and then patterning the deposited conductive material. The second bonding metal layer 298 may be formed such that its lower surface is exposed through the second bonding insulating layer 299.

[0125] The peripheral region insulating layer 290 may be composed of a plurality of insulating layers. Part of the peripheral region insulating layer 290 may be formed in each step of forming the circuit wiring structure and the second bonding structure. Through this step, the second semiconductor structure S2 may be prepared.

[0126] The first semiconductor structure S1 and the second semiconductor structure S2 can be connected by bonding the first bonding metal 198 and the second bonding metal layer 298 with pressure. At the same time, the first bonding insulating layer 199 and the second bonding insulating layer 299 can also be bonded with pressure. The second semiconductor structure S2 can be inverted onto the first semiconductor structure S1 so that the second bonding metal layer 298 faces downward, and then bonding can be performed. The bonding can also be performed by attaching another carrier substrate to one side of the second semiconductor structure S2, for example, one side of the substrate 201.

[0127] Referring to FIG. 21, the base substrate SUB may be removed to expose the channel layer 140.

[0128] In the bonding structure of the first semiconductor structure S1 and the second semiconductor structure S2, the base substrate SUB may be removed, and a portion of the exposed channel dielectric layer 145 (see FIG. 3c) may be removed to expose the channel layer 140.

[0129] 2a, the semiconductor device 100 of FIG. 2a can be manufactured by forming a plate layer 101 connected to the channel layer 140. In some embodiments, the plate layer 101 may be formed as a conformal layer along the upper ends of the channel structure CH and the upper ends of the first and second dummy vertical structures DH1 and DH2.

[0130] FIG. 22 is a diagram that schematically illustrates a data storage system including a semiconductor device according to an exemplary embodiment.

[0131] 22 , a data storage system 1000 may include a semiconductor device 1100 and a controller 1200 electrically coupled to the semiconductor device 1100. The data storage system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the data storage system 1000 may be a solid state drive device (SSD) device, a Universal Serial Bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0132] The semiconductor device 1100 may be a nonvolatile memory device, for example, a NAND flash memory device as described above with reference to FIGS. 1 to 7. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In an exemplary embodiment, the first structure 1100F may be disposed adjacent to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, first and second upper gate lines UL1 and UL2, first and second lower gate lines LL1 and LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0133] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may vary depending on the embodiment.

[0134] In an exemplary embodiment, the upper transistors UT1 and UT2 may comprise string select transistors, and the lower transistors LT1 and LT2 may comprise ground select transistors. The lower gate lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be a gate electrode of the memory cell transistor MCT, and the upper gate lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

[0135] In an exemplary embodiment, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string selection transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used in an erase operation that erases data stored in the memory cell transistor MCT using the GIDL phenomenon.

[0136] The common source line CSL, the first and second gate lower lines LL1 and LL2, the word line WL, and the first and second gate upper lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 via a first connecting line 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 via a second connecting line 1125 extending from the first structure 1100F to the second structure 1100S.

[0137] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 can be controlled by a logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 via an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 can be electrically connected to the logic circuit 1130 via an input / output connecting wiring 1135 extending to the second structure 1100S within the first structure 1100F.

[0138] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. Depending on the embodiment, the data storage system 1000 may include multiple semiconductor devices 1100, in which case the controller 1200 may control multiple semiconductor devices 1100.

[0139] The processor 1210 can control the overall operation of the data storage system 1000, including the controller 1200. The processor 1210 can operate according to predetermined firmware and can control the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 can include a NAND interface 1221 that processes communication with the semiconductor device 1100. Control commands for controlling the semiconductor device 1100, data to be written to the memory cell transistors MCT of the semiconductor device 1100, data to be read from the memory cell transistors MCT of the semiconductor device 1100, etc. can be transferred via the NAND interface 1221. The host interface 1230 can provide a communication function between the data storage system 1000 and an external host. When a control command is received from the external host via the host interface 1230, the processor 1210 can control the semiconductor device 1100 in response to the control command.

[0140] FIG. 23 is a perspective view that schematically illustrates a data storage system including a semiconductor device according to an exemplary embodiment.

[0141] 23, a data storage system 2000 may include a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor packages 2003 and the DRAM 2004 may be connected to the controller 2002 by a wiring pattern 2005 formed on the main board 2001.

[0142] The main board 2001 may include a connector 2006 including a plurality of pins for coupling with an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. In an exemplary embodiment, the data storage system 2000 may communicate with the external host via any one of interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). In an exemplary embodiment, the data storage system 2000 may operate using power supplied from the external host via the connector 2006. The data storage system 2000 may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0143] The controller 2002 can record data to or read data from the semiconductor package 2003 , which can improve the operating speed of the data storage system 2000 .

[0144] The DRAM 2004 can be a buffer memory for reducing the speed difference between the semiconductor package 2003, which is a data storage space, and an external host. The DRAM 2004 included in the data storage system 2000 can also operate as a type of cache memory and can provide space for temporarily storing data in control operations for the semiconductor package 2003. When the data storage system 2000 includes the DRAM 2004, the controller 2002 can further include a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

[0145] The semiconductor package 2003 may include first and second semiconductor packages 2003a and 2003b spaced apart from each other. The first and second semiconductor packages 2003a and 2003b may each include a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages 2003a and 2003b may include a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on a lower surface of each of the semiconductor chips 2200, a connecting structure 2400 that electrically connects the semiconductor chip 2200 and the package substrate 2100, and a molding layer 2500 that covers the semiconductor chip 2200 and the connecting structure 2400 on the package substrate 2100.

[0146] The package substrate 2100 may be a printed circuit board including upper package pads 2130. Each semiconductor chip 2200 may include input / output pads 2210. The input / output pads 2210 may correspond to the input / output pads 1101 in FIG. 22. Each semiconductor chip 2200 may include the semiconductor device described above with reference to FIGS. 1 to 7.

[0147] In an exemplary embodiment, the connecting structure 2400 may be a bonding wire that electrically connects the I / O pad 2210 and the package upper pad 2130. Therefore, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other using a bonding wire, and may be electrically connected to the package upper pad 2130 of the package substrate 2100. According to an embodiment, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other using a connecting structure including a through silicon via (TSV), instead of the connecting structure 2400 using a bonding wire.

[0148] In an exemplary embodiment, the controller 2002 and the semiconductor chip 2200 may be included in one package. In an exemplary embodiment, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate other than the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other by wiring formed on the interposer substrate.

[0149] The present invention is not limited by the above-described embodiments and the accompanying drawings, but is limited by the scope of the appended claims. Therefore, within the scope of the technical idea of ​​the present invention described in the claims, various substitutions, modifications, and changes and combinations of embodiments may be made by a person skilled in the art, and these also fall within the scope of the present invention. [Explanation of symbols]

[0150] CH Channel structure DH1, DH2 Dummy vertical structures GS Gate structure MC1, MC2 Contact plug MS gate isolation region SS1, SS2 upper isolation region 101 plate layer 120 interlayer insulating layer 130 Gate electrode 132 Gate barrier layer 135 Gate conductive layer 140 Channel layer 145 Channel dielectric layer 147 Channel buried insulating layer 149 channel pad 160 contact insulating layer 172 Contact barrier layer 175 Contact conductive layer 180 stud 185 cell wiring line 190 Cell area insulating layer

Claims

1. a plate layer; In the first to third regions, gate electrodes are stacked apart from each other along a first direction perpendicular to an upper surface of the plate layer, the gate electrodes including a lower gate electrode, a memory gate electrode, and an upper gate electrode stacked in sequence from the plate layer; a channel structure extending in the first direction through the gate electrode in the first region; first contact plugs, each of which penetrates at least one of the upper gate electrodes from above in the second region and is electrically connected to the upper gate electrodes; second contact plugs, which penetrate a portion of the gate electrode including the upper gate electrode from above in the third region and are electrically connected to the memory gate electrode and the lower gate electrode, respectively; In the first to third regions, gate isolation regions penetrate the entire gate electrode, extend along a second direction perpendicular to the first direction, and are spaced apart from each other in a third direction perpendicular to the first and second directions; a first upper isolation region extending in the second direction between the gate isolation regions and penetrating the upper gate electrode in the first and second regions; a second upper isolation region connected to an end of the first upper isolation region at a boundary between the second region and the third region, penetrating the upper gate electrode and extending in the third direction; the first contact plugs are arranged in the shape of at least one line along the third direction with the first upper isolation region interposed therebetween; Each of the first contact plugs contacts at least one of the side surfaces of the first upper isolation region along the third direction.

2. 2. The semiconductor device according to claim 1, wherein the first contact plugs arranged between the first upper isolation regions adjacent to each other along the third direction contact all of the adjacent first upper isolation regions.

3. the first contact plugs are arranged in at least one row along the third direction; 2 . The semiconductor device according to claim 1 , wherein the number of the first contact plugs in the at least one column is one more than the number of the first upper isolation regions between the gate isolation regions adjacent in the third direction.

4. each of the first contact plugs includes a contact barrier layer and a contact conductive layer on the contact barrier layer; The semiconductor device according to claim 1 , wherein the contact conductive layer contacts the side surface of the first upper isolation region along the third direction.

5. The semiconductor device of claim 1 , wherein the first upper isolation region partially penetrates a portion of the channel structure.

6. The semiconductor device according to claim 1 , wherein an end of said gate electrode along said second direction is located outside said third region.

7. a plate layer; Gate electrodes are stacked apart from each other along a first direction perpendicular to an upper surface of the plate layer, and include a lower gate electrode, a memory gate electrode, and an upper gate electrode stacked in sequence on the plate layer; a channel structure extending along the first direction through the gate electrode; first contact plugs electrically connected to the upper gate electrodes; second contact plugs that penetrate a portion of the gate electrode from above and are electrically connected to the memory gate electrode and the lower gate electrode, respectively; gate isolation regions that penetrate the entire gate electrode, extend along a second direction perpendicular to the first direction, and are spaced apart from each other in a third direction perpendicular to the first and second directions; a first upper isolation region extending in the second direction between the gate isolation regions and penetrating the upper gate electrode; each of the first contact plugs contacts at least one of the first upper isolation regions; The second contact plug is spaced apart from the first upper isolation region.

8. 8. The semiconductor device according to claim 7, wherein said upper gate electrode is a gate electrode of a string select transistor and an erase transistor.

9. The semiconductor device of claim 8 , wherein the number of the first contact plugs arranged between the first upper isolation regions adjacent in the third direction is the same as the number of the upper gate electrodes.

10. a semiconductor memory device including a first semiconductor structure including a circuit element, a second semiconductor structure disposed on one surface of the first semiconductor structure, and an input / output pad electrically connected to the circuit element; a controller electrically connected to the semiconductor memory device through the input / output pad and controlling the semiconductor memory device; The second semiconductor structure is a plate layer; gate electrodes stacked on the plate layer and spaced apart from each other along a first direction perpendicular to an upper surface of the plate layer, the gate electrodes including a first gate electrode and a second gate electrode on the first gate electrode; first contact plugs extending in the first direction and electrically connected to the second gate electrodes; second contact plugs disposed on one side of the first contact plugs in a second direction perpendicular to the first direction, extending through the second gate electrodes along the first direction and electrically connected to the first gate electrodes; the first contact plugs are arranged in columns along a third direction perpendicular to the first and second directions, the number of the columns being equal to the number of the second gate electrodes; The data storage system, wherein the second contact plugs are arranged in a different manner than the first contact plugs.

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