Semiconductor device

Abstract

To provide a transistor that includes an oxide semiconductor and that enables a high-speed operation, and to provide a method of manufacturing the same, or to provide a highly-reliable semiconductor device that includes the transistor, and to provide a method of manufacturing the same.SOLUTION: Provided is a semiconductor device that includes: a channel formation region; and a source region and a drain region provided so as to sandwich the channel formation region therebetween, and that have a lower resistance than the channel formation region. Each of the channel formation region, the source region, and the drain region has an oxide semiconductor layer including a crystalline region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The disclosed invention relates to a semiconductor device and a manufacturing method thereof.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to a general category of semiconductor devices, including electro-optical devices, light-emitting displays, semiconductor circuits, and electronic equipment. be. [Background technology]

[0003] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is The transistor is used in integrated circuits (ICs) and image display devices (also known simply as display devices). It is widely applied to semiconductor electronic devices such as transistors. Silicon-based semiconductor materials are known as suitable semiconductor thin films, but oxides are also used as other materials. Semiconductors are in the spotlight.

[0004] For example, zinc oxide and In-Ga-Zn-O oxides are used as oxide semiconductors. The technology for fabricating a transistor and using it as a switching element for pixels of a display device is described in Patent Document 1 and This is disclosed in Patent Document 2.

[0005] In Patent Document 3, in a staggered transistor using an oxide semiconductor, A highly conductive buffer layer is formed between the source and drain regions and the source and drain electrodes. an oxide semiconductor containing nitrogen; and a source electrode and a drain electrode. Techniques for reducing contact resistance have been disclosed.

[0006] In Non-Patent Document 1, a channel region, a source region, and a drain region are formed by self-alignment. A top-gate amorphous oxide semiconductor transistor is disclosed. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Patent Document 3] Japanese Patent Application Laid-Open No. 2010-135774 [Non-patent literature]

[0008] [Non-Patent Document 1] Jae Chul Park et al., “High performance amorphous oxide thin film transistors with self-aligned top-gate structure” IEDM2009, pp191-194 Summary of the Invention [Problem to be solved by the invention]

[0009] As semiconductor devices, including transistors, become more sophisticated, there is a demand for high-speed transistor operation. In view of this, in one embodiment of the present invention, a transistor including an oxide semiconductor and capable of high-speed operation is Another object of the present invention is to provide a semiconductor device including the transistor and a manufacturing method thereof. An object of the present invention is to provide a semiconductor device with high performance and a manufacturing method thereof. [Means for solving the problem]

[0010] In one embodiment of the disclosed invention, a channel formation region and a pair of thin films provided so as to sandwich the channel formation region are provided. and a source region and a drain region, which are regions having a lower resistance than a channel formation region, The channel forming region, the source region, and the drain region are each made of an oxide semiconductor containing a crystalline region. More specifically, the semiconductor device may have the following configuration: .

[0011] Another aspect of the present invention is a crystalline semiconductor device including a source region, a drain region, and a channel formation region. an oxide semiconductor layer, a gate insulating layer provided over a channel formation region, and a gate insulating layer a gate electrode provided on the channel forming region, and a source region and a drain region The region is a crystalline region of a semiconductor device that contains nitrogen.

[0012] Another embodiment of the present invention is a semiconductor device including a source region, a drain region, and a channel formation region. a crystalline oxide semiconductor layer; a gate insulating layer provided on a channel formation region; and a gate insulating a gate electrode provided on a channel forming region via a layer; an insulating layer provided on the semiconductor layer and the gate electrode, and an opening provided in the insulating layer; a source electrode and a drain electrode in contact with the source region and the drain region, respectively; The source region and the drain region are crystalline regions containing nitrogen in the semiconductor device.

[0013] In any one of the above semiconductor devices, the source region and the drain region are formed by a channel forming The crystallinity may be higher than that of the region.

[0014] Another embodiment of the present invention is a method for forming a crystalline oxide semiconductor layer, A first insulating layer is formed on the crystalline oxide semiconductor layer, and a gate electrode is formed on the crystalline oxide semiconductor layer via the first insulating layer. The first insulating layer is then etched using the gate electrode as a mask to form a gate insulating layer. and forming a nitrogen plating layer on the portion of the crystalline oxide semiconductor layer that is not covered with the gate insulating film. By performing the ZnO treatment, a crystalline region containing nitrogen is formed in the crystalline oxide semiconductor layer. A method for fabricating a semiconductor device.

[0015] Another embodiment of the present invention is a method for forming an oxide semiconductor layer, forming a first insulating film over the oxide semiconductor layer, and forming a first insulating film over the oxide semiconductor layer. The oxide semiconductor layer is subjected to heat treatment to form a crystalline oxide semiconductor layer. a gate electrode is formed over the crystalline oxide semiconductor layer via a layer, and the gate electrode is used as a mask; The first insulating layer is etched to form a gate insulating layer, and the crystalline oxide semiconductor layer is By performing nitrogen plasma treatment on the part not covered by the gate insulating film, crystalline oxide a crystalline region containing nitrogen in the oxide semiconductor layer, and a crystalline oxide semiconductor layer and a gate electrode forming a second insulating layer covering the source region and the drain region; and forming openings in the regions corresponding to the source and drain regions on the second insulating layer through the openings. Fabrication of a semiconductor device by forming a source electrode and a drain electrode each in contact with the drain region It is a method.

[0016] In this specification and the like, a crystalline oxide semiconductor layer refers to an oxide semiconductor layer that contains crystals and has crystallinity. The crystalline state of the crystalline oxide semiconductor layer is a disordered state in which the crystal axes are oriented in a random manner. However, it may be in a state of having a certain orientation.

[0017] In one embodiment of the invention disclosed in this specification, the crystalline oxide semiconductor layer may be formed of a CA AC-OS(C Axis Aligned Crystalline Oxide S It is possible to form a thin film of silicon dioxide.

[0018] The CAAC-OS film is neither completely single crystalline nor completely amorphous. The oxide semiconductor film has a crystalline-amorphous mixed phase structure in which a crystalline portion and an amorphous portion are contained in the amorphous phase. The crystal part must be small enough to fit inside a cube with one side less than 100 nm. In addition, transmission electron microscope (TEM) In the observation image using a microscope, the amorphous part and the crystalline part in the CAAC-OS film were The boundaries of the crystals are not clear. Therefore, the CAAC-OS film does not show any grain boundary-related defects. This suppresses the decrease in electron mobility.

[0019] The crystal part included in the CAAC-OS film has a c-axis that is the normal vector of the surface on which the CAAC-OS film is formed. The triangle is aligned parallel to the normal vector of the sphere or surface and perpendicular to the ab plane. The metal atoms are arranged in a layered or gold-like shape when viewed perpendicular to the c-axis. The metal atoms and oxygen atoms are arranged in layers. The direction of the b axis may be different. In this specification, when simply referring to vertical, it means 85°. Also, when simply describing it as parallel, it means that the angle is -5° or more and 95° or less. This includes a range of 5° or less.

[0020] In the CAAC-OS film, the distribution of the crystal parts may not be uniform. In the process of forming the C-OS film, when crystals are grown from the surface side of the crystalline oxide semiconductor layer The proportion of crystalline portions may be higher near the surface than near the surface on which the film is formed. By adding impurities to the CAAC-OS film, a crystalline region is formed in the impurity-doped region. may become amorphous.

[0021] The c-axis of the crystalline part in the CAAC-OS film is the normal vector of the surface on which the CAAC-OS film is formed. The CAAC-OS film shape (on the surface on which it is formed) is Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface, the directions may be different from each other. The direction of the c-axis of the crystal is the normal vector of the surface on which the CAAC-OS film is formed or The direction is parallel to the normal vector of the surface. The crystalline part is formed by film formation or after film formation. It is formed by a crystallization treatment such as a heat treatment.

[0022] A part of oxygen contained in the CAAC-OS film may be substituted with nitrogen.

[0023] By using such a crystalline oxide semiconductor layer in a transistor, it is possible to To further suppress the change in the electrical characteristics of the transistor due to the above, and to provide a highly reliable semiconductor device. can be done.

[0024] In this specification, the term "above" means that the positional relationship of a component is "directly above." For example, the expression "gate electrode on a gate insulating layer" is This does not exclude the inclusion of other components between the gate insulating layer and the gate electrode. The same applies to the term.

[0025] In this specification, the terms "electrode" and "wiring" are used to refer to the functional components of these elements. For example, an "electrode" may be used as part of a "wiring." Furthermore, the terms "electrode" and "wire" are used interchangeably to refer to the plural "electrodes." This also includes cases where the "electrode" and "wiring" are formed as a single unit. [Effects of the Invention]

[0026] According to one embodiment of the present invention, a transistor including an oxide semiconductor and capable of high-speed operation and a method for fabricating the same can be provided. A manufacturing method can be provided.

[0027] According to another embodiment of the present invention, a highly reliable semiconductor device and a manufacturing method thereof can be provided. can be done. [Brief explanation of the drawings]

[0028] [Figure 1] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 2] 1A to 1C illustrate an example of a manufacturing process of a semiconductor device. [Figure 3] 1A and 1B are cross-sectional views illustrating one embodiment of a semiconductor device. [Figure 4] 1A to 1C illustrate an example of a manufacturing process of a semiconductor device. [Figure 5] 1A to 1C illustrate an example of a manufacturing process of a semiconductor device. [Figure 6] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 7] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 8] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 9] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 10] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 11] 1 shows the results of measuring the sheet resistance of samples prepared in the examples. [Figure 12] 1 shows the results of measuring the XRD spectrum of the sample prepared in the example. [Figure 13]1 shows the results of measuring the XPS spectrum of the sample prepared in the example. DETAILED DESCRIPTION OF THE INVENTION

[0029] Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. Therefore, the present invention should not be construed as being limited to the following description. In the configuration of the present invention described below, the same parts or parts having similar functions may be used. The same reference numerals are used in common between different drawings, and repeated explanations will be omitted. In addition, when referring to parts with similar functions, the hatch pattern is the same and no special reference numeral is attached. There may not be.

[0030] In each of the drawings described in this specification, the size of each component, the thickness of the film, or the area is not clearly indicated. The figures may be exaggerated for clarity and are not necessarily limited to that scale. .

[0031] In this specification, the ordinal numbers such as first and second are used for convenience. It does not indicate the order of steps or the order of layers. It does not indicate a specific name for the matter.

[0032] (Embodiment 1) In this embodiment, one mode of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. I will explain.

[0033] FIG. 1 shows a cross-sectional view and a plan view of a transistor 510 as an example of a semiconductor device. 1(B) and 1(C) are cross sections taken along the lines AB and C in FIG. 1(A). 1A is a cross-sectional view of the cross section of the substrate 100 shown in FIG. 1A. Some of the components of the transistor 510 (such as the insulating layer 412) are omitted in the illustration. do.

[0034] The transistor 510 shown in FIG. 1 includes a base insulating layer 402 over a substrate 400 having an insulating surface. and a resultant semiconductor layer including a source region 404a, a drain region 404b, and a channel forming region 404c. A crystalline oxide semiconductor layer 404, a gate insulating layer 406, a gate electrode 410, and an opening are formed on the substrate. and a source region 404a in contact with the source region 404a through an opening in the insulating layer 412. The electrode 415a and the drain region 404b are in contact with each other through the opening of the insulating layer 412. The base insulating layer 402 and the insulating layer 412 are necessarily It is not necessary to use the transistor 510 as a component.

[0035] In the crystalline oxide semiconductor layer 404 provided in the transistor 510 shown in FIG. The source region 404a and the drain region 404b are made of a crystalline oxide semiconductor containing nitrogen. This is a body layer and is a region with a lower resistance than the channel formation region 404c.

[0036] The source region 404a and the drain region 404b are formed after the crystalline oxide semiconductor layer 404 is formed. It is formed by intentionally incorporating nitrogen through nitrogen plasma treatment. This region has a higher carrier density than the channel forming region 404c. In the high density region, the source electrode 415a or the drain electrode 41 5b and the crystalline oxide semiconductor layer 404 are in contact with each other, The contact between 404 and the source electrode 415a or the drain electrode 415b is made of ohmic material. This can be used as a contact, and the contact resistance can be reduced. As a result, the on-current of the transistor 510 can be increased.

[0037] In this specification, a low-resistance oxide that functions as a source region and a drain region is referred to as a The semiconductor layer has an n-type conductivity, + It may also be referred to as a layer.

[0038] In the crystalline oxide semiconductor layer 404, a source region 404a, a drain region 404b, and The channel formation region 404c is a region containing crystals (also called a crystalline region). The crystalline state of the crystalline oxide semiconductor layer is such that even if the crystal axis direction is disordered, the crystal structure remains constant. It may be in an oriented state.

[0039] The source region 404a, the drain region 404b, and the channel forming region 404c are By forming the crystalline region, the source region 404a, the channel forming region 404c, and the drain The junction between the silicon region 404b and the channel forming region 404c can be improved. , a source region 404a, a drain region 404b, and a channel forming region 404c, respectively. By forming the oxide semiconductor layer 404 into a crystalline region, the band level in the crystalline oxide semiconductor layer 404 is reduced. Therefore, the transistor characteristics can be improved. This can improve the reliability of the transistor 510.

[0040] An example of a manufacturing process of the transistor 510 will be described below with reference to FIGS. .

[0041] First, a base insulating layer 402 is formed over a substrate 400 having an insulating surface. There is no significant limitation on the substrate that can be used for the substrate 400, but at least the substrate that can be used for the subsequent heat treatment For example, barium borosilicate Glass substrates such as glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, surface treatment A fiber substrate can be used. Single crystal semiconductors such as silicon and silicon carbide can also be used. Solid substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates The substrate 40 may be a semiconductor device. It may be used as 0.

[0042] A flexible substrate may be used as the substrate 400. When a flexible substrate is used, A transistor including an oxide semiconductor film may be directly formed on a substrate. A transistor including a nitride semiconductor film may be fabricated and then peeled off and transferred to a flexible substrate. Note that in order to separate and transfer the semiconductor film from the formation substrate to the flexible substrate, A peeling layer may be provided between the transistor and the insulating film.

[0043] The base insulating layer 402 is made of silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide. Aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum oxynitride a single layer selected from films containing gallium oxide, hafnium oxide, gallium oxide, or a mixture thereof; Alternatively, the base insulating layer 402 can have a stacked structure. a layer or stacked structure in which the oxide insulating film is in contact with an oxide semiconductor layer to be formed later; In this embodiment, the base insulating layer 402 is preferably made of silicon oxide. The film is formed by plasma CVD, sputtering, or the like.

[0044] The base insulating layer 402 has a region containing oxygen exceeding the stoichiometric composition ratio (hereinafter referred to as an oxygen excess region). When the insulating layer 402 has a region (also referred to as a region), excess oxygen contained in the base insulating layer 402 can form a thin film later. The base insulating film is preferably a base insulating film because it can compensate for oxygen vacancies in the oxide semiconductor layer formed on the base insulating film. In the case where the layer 402 has a stacked structure, an oxygen-excess region is formed at least in a layer in contact with the oxide semiconductor layer. To provide the oxygen excess region in the base insulating layer 402, for example, The base insulating layer 402 may be formed in an atmosphere. , oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) is implanted. The oxygen-excess region may be formed by the ion implantation method, the ion doping method, or the like. The method may include a doping method, a plasma immersion ion implantation method, a plasma treatment, etc. do.

[0045] Next, a film having a thickness of 2 nm to 200 nm, preferably 5 nm or more, is formed on the base insulating layer 402. An oxide semiconductor layer having a thickness of 30 nm or less is formed.

[0046] The oxide semiconductor layer formed over the base insulating layer 402 may have an amorphous structure or a crystalline structure. However, when the oxide semiconductor layer has an amorphous structure, In the manufacturing process (at least before the nitrogen plasma treatment process), the oxide semiconductor layer is By performing the treatment, a crystalline oxide semiconductor layer is formed. The temperature of the heat treatment for crystallizing the conductor layer is 250°C or higher and 700°C or lower, preferably 400°C or lower. The temperature is set to 500°C or higher, more preferably 500°C or higher, and even more preferably 550°C or higher. The heat treatment may also serve as another heat treatment in the manufacturing process.

[0047] In this embodiment, the crystalline oxide semiconductor layer 401a is formed over the base insulating layer 402. (See Figure 2(A)).

[0048] The crystalline oxide semiconductor layer 401a is formed by a sputtering method, an MBE (Molecular Beam Epitaxy) method, or the like. lar beam epitaxy) method, CVD method, pulsed laser deposition method, ALD (At A comomic layer deposition method or the like can be used as appropriate.

[0049] When forming the crystalline oxide semiconductor layer 401a, it is preferable to form the crystalline oxide semiconductor layer 401a as thin as possible. It is preferable to reduce the hydrogen concentration contained in the above. To reduce the hydrogen concentration, for example, When forming a film using a sputtering method, the material is supplied into the processing chamber of the sputtering device. The atmospheric gas used is a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed. A rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen is appropriately used. .

[0050] In addition, the residual moisture in the film formation chamber is removed and sputtering gas from which hydrogen and moisture have been removed is introduced. By forming the oxide semiconductor layer in this manner, the hydrogen concentration in the formed oxide semiconductor layer can be reduced. To remove residual moisture in the deposition chamber, an adsorption type vacuum pump, such as a cryopump, is used. It is preferable to use an ion pump or a titanium sublimation pump. The stage may be a turbomolecular pump with a cold trap added. The deposition chamber is evacuated using a gas pump, and contains hydrogen atoms, water (H2O), and other gases. Compounds containing carbon atoms (and more preferably compounds containing carbon atoms) are exhausted from the deposition chamber. The concentration of impurities contained in the formed crystalline oxide semiconductor layer 401a can be reduced.

[0051] In addition, the base insulating layer 402 and the crystalline oxide semiconductor layer 401a are successively formed without being exposed to the air. It is preferable to form the base insulating layer 402 and the crystalline oxide semiconductor layer 401a in the air. If the layers are formed continuously without exposure, impurities such as hydrogen and moisture are adsorbed on the surface of the base insulating layer 402. This can prevent the following from happening.

[0052] In addition, the crystalline oxide semiconductor layer 401a is formed while the substrate 400 is maintained at a high temperature. is also effective in reducing the concentration of impurities that may be contained in the crystalline oxide semiconductor layer 401a. The temperature to which the substrate 400 is heated may be preferably 150° C. or higher and 450° C. or lower. Alternatively, the substrate temperature may be set to 200°C or higher and 350°C or lower. By heating, a crystalline oxide semiconductor layer can be formed.

[0053] The oxide semiconductor used for the crystalline oxide semiconductor layer 401a is at least indium ( It is preferable that the material contains In (In) or zinc (Zn). It is particularly preferable that the material contains In and Zn. In addition, a semiconductor device for reducing variations in electrical characteristics of a transistor including the oxide semiconductor is also disclosed. It is preferable to have gallium (Ga) as a stabilizer in addition to the above. It is preferable to use tin (Sn) as a stabilizer. It is preferable to have hafnium (Hf) as a stabilizer. It is preferable that the material contains aluminum (Al).

[0054] Other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Ru It may contain one or more of tetraethion (Te) and tetraethion (Tb).

[0055] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides Oxides such as In-Ga-Zn oxides, In-Al-Zn oxides, and In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides, Sn-Al-Zn oxides Oxides, In-Hf-Zn oxides, In-La-Zn oxides, In-Ce-Zn oxides oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm-Zn oxides In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides , In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxides and In-Hf-Ga-Zn oxides, which are oxides of the base metals oxides, In-Al-Ga-Zn oxides, In-Sn-Al-Zn oxides, In-Sn In-Hf-Zn based oxides and In-Hf-Al-Zn based oxides can be used.

[0056] Here, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as its main components. The ratio of In, Ga, and Zn is not important. Metal elements other than a and Zn may be included.

[0057] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0 and m is not an integer) It is also possible to use a material represented by the formula: where M is selected from Ga, Fe, Mn, and Co. It refers to one or more metal elements. In addition, as an oxide semiconductor, In2SnO5 (ZnO) n A material expressed as (n>0 and n is an integer) may be used.

[0058] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn oxide with an atomic ratio of a:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) Alternatively, In:Sn:Zn=1: 1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) It is preferable to use an In-Sn-Zn oxide with a molecular ratio or an oxide with a composition close to that.

[0059] However, it is not limited to these, and the required semiconductor characteristics (mobility, threshold, variation, etc.) In addition, in order to obtain the required semiconductor characteristics, Carrier concentration, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond length, density It is preferable to make the following appropriate.

[0060] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. Therefore, even in In-Ga-Zn oxides, the mobility can be increased by reducing the defect density in the bulk. It can be done.

[0061] For example, when the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of the oxide with c=1) is In:Ga:Zn=A:B:C (A+B+C = 1), the oxide composition is close to (aA) 2 +(bB) 2 + (cC) 2 ≦r 2 This means that the following is satisfied. For example, r can be set to 0.05. The same applies to other oxides.

[0062] Note that the crystalline oxide semiconductor layer 401a is formed under conditions in which a large amount of oxygen is contained (for example, For example, a film is formed by sputtering in an atmosphere of 100% oxygen. The oxide semiconductor preferably contains a large amount of oxygen relative to the stoichiometric composition ratio in a crystalline state. It is preferable to use a film containing an area where the content of element is excessive.

[0063] Examples of targets for forming an oxide semiconductor layer by sputtering include those having the following composition: The metal oxide ternary phase was prepared with a molar ratio of In2O3:Ga2O3:ZnO=1:1:2. The target is used to form an In-Ga-Zn film. Without being limited thereto, for example, metals of In2O3:Ga2O3:ZnO=1:1:1 [molar ratio] An oxide target may also be used.

[0064] The filling rate of the metal oxide target is 90% or more and 100% or less, preferably 95% or more. By using a metal oxide target with a high filling rate, the film is formed. In addition, the oxide semiconductor layer can be a dense film.

[0065] In this embodiment, the crystalline oxide semiconductor layer 401a is made of an In—Ga—Zn-based metal oxide substrate. The crystalline oxide semiconductor layer 401 is formed by a sputtering method using a target. The atmosphere during film formation of a can be a rare gas (typically argon) atmosphere, an oxygen atmosphere, or The film is formed in a mixed atmosphere of rare gas and oxygen at a film formation temperature of 200°C to 450°C. By performing the above, a crystalline oxide semiconductor layer 401a, which is an oxide semiconductor layer having a crystalline region, is formed. Form.

[0066] As the oxide semiconductor layer having a crystalline region, for example, a CAAC-OS film can be used. There are three methods for obtaining CAAC-OS films. The oxide semiconductor layer is formed at a temperature of 0°C to 450°C, and the c-axis is oriented approximately perpendicular to the surface. The second method is to deposit a thin oxide semiconductor layer and then heat it at 200°C or higher for 70 The third method is to align the c-axis approximately perpendicular to the surface by heat treatment at 0°C or below. After forming a thin film of the first layer, heat treatment is performed at 200℃ to 700℃, and the second layer is formed. This method involves performing a crystallographic process to orient the c-axis approximately perpendicular to the surface.

[0067] The crystalline oxide semiconductor layer 401a can further reduce defects in the bulk and has a flat surface. By increasing the surface conductivity, it is possible to obtain a mobility higher than that of an amorphous oxide semiconductor. In order to improve the flatness, it is preferable to form an oxide semiconductor on a flat surface. Generally, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, and more preferably It is preferable to form it on a surface of 0.1 nm or less.

[0068] Note that Ra is defined in JIS B 0601:2001 (ISO4287:1997). It is a three-dimensional extension of the arithmetic mean roughness, which is currently used, so that it can be applied to curved surfaces. It can be expressed as the "average of the absolute values ​​of the deviation from the reference surface to the specified surface" and is defined by the following formula: .

[0069]

number

[0070] Here, the specified surface is the surface to be measured for roughness, and has coordinates (x1, y1, f(x1, y 1)),(x1,y2,f(x1,y2)),(x2,y1,f(x2,y1)),(x 2, y2, f(x2, y2)) and the specified surface is the xy plane. The area of ​​the projected rectangle is S0, and the height of the reference plane (average height of the specified plane) is Z0. was measured using an atomic force microscope (AFM). It is possible to determine.

[0071] Therefore, the region of the base insulating layer 402 in contact with the crystalline oxide semiconductor layer 401a The flattening process may be performed on the surface of the substrate. The flattening process is not particularly limited, but may be performed by polishing. (e.g., Chemical Mechanical Polishing CMP), dry etching, and plasma treatment can be used.

[0072] The plasma treatment may be, for example, a reverse plasma treatment in which argon gas is introduced to generate plasma. Tarring can be performed.

[0073] As a planarization process, polishing, dry etching, and plasma treatment may be performed multiple times. In addition, when the steps are combined, there is no particular limitation on the order of the steps. The thickness is not limited to a specific value and may be set appropriately depending on the unevenness of the surface of base insulating layer 402 .

[0074] After the crystalline oxide semiconductor layer 401a is formed, the oxide semiconductor layer 401a contains Heat treatment to remove (dehydrate or dehydrogenate) excess hydrogen (including water and hydroxyl groups) that is present in the The temperature of the heat treatment is typically 200° C. or higher and lower than the strain point of the substrate 400. Preferably, the temperature is 250°C or higher and 450°C or lower.

[0075] This heat treatment can remove hydrogen, which is an n-type impurity, from the oxide semiconductor. For example, the hydrogen concentration in the crystalline oxide semiconductor layer 401a after dehydration or dehydrogenation treatment , 5 × 10 19 / cm 3 Less than or equal to 5 x 10 18 / cm 3 It can be do.

[0076] Note that the heat treatment for dehydration or dehydrogenation is performed after the formation of the crystalline oxide semiconductor layer 401a. However, if the nitrogen plasma treatment step is performed before the nitrogen plasma treatment step, the transistor 510 may be fabricated at any time. However, the heat treatment for dehydration or dehydrogenation may be carried out by heating. If the heat treatment is performed before the conductor layer 401a is processed into an island shape, oxygen contained in the base insulating layer 402 is absorbed by the heat treatment. This is preferable because it is possible to prevent the release of the ions.

[0077] In the heat treatment, nitrogen or rare gas such as helium, neon, or argon is mixed with water, It is preferable that hydrogen and the like are not contained. Alternatively, nitrogen or helical gas introduced into the heat treatment device The purity of rare gases such as ammonium, neon, and argon should be 6N (99.9999%) or higher. 7N (99.99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably 0.1 ppm) pm or less).

[0078] After the crystalline oxide semiconductor layer 401a is heated by the heat treatment, a high-purity oxygen gas is introduced into the same furnace. , high purity nitrous oxide gas, or ultra dry air (CRDS (cavity ring down lathe) When measured using a dew point meter using the laser spectroscopy method, the moisture content was 20 ppm (-5 ppm in terms of dew point). 5°C), preferably 1 ppm or less, preferably 10 ppb or less) It is preferable that the oxygen gas or nitrous oxide gas does not contain water, hydrogen, etc. Alternatively, the purity of the oxygen gas or nitrous oxide gas introduced into the heat treatment device is preferably 6N or more. or 7N or more (i.e., impurity concentration in oxygen gas or nitrous oxide gas is 1 ppm or less) , preferably 0.1 ppm or less). Oxygen gas or nitrous oxide gas The action of the dehydration or dehydrogenation process simultaneously reduces the amount of impurities. By supplying oxygen, which is the main component of oxide semiconductors, The oxide semiconductor layer 401a can be highly purified and made i-type (intrinsic).

[0079] Next, the crystalline oxide semiconductor layer 401a is formed into island-shaped crystalline oxide films by a photolithography process. The crystalline oxide semiconductor layer 401 is then formed by etching. The resist mask for this purpose may be formed by an ink-jet method. When the film is formed by the PET method, a photomask is not used, which reduces the manufacturing cost of the semiconductor device. It is possible.

[0080] Next, a layer of crystalline oxide semiconductor is formed on the island-shaped crystalline oxide semiconductor layer 401 by plasma CVD or sputtering. The insulating layer 403 is formed by the above method (see FIG. 2B). The insulating layer 403 is formed as a turn and functions as a gate insulating layer. Silicon oxide film, gallium oxide film, aluminum oxide film, silicon nitride film, silicon oxynitride film It can be formed using a silicon film, an aluminum oxynitride film, or a silicon nitride oxide film. Cut.

[0081] The insulating layer 403 may be made of hafnium oxide, yttrium oxide, or hafnium silicate. HfSi x O y x>0, y>0), nitrogen-doped hafnium silicate (H fSiO x N y (x>0, y>0)), hafnium aluminate (HfAl x O y (x> 0, y>0)), and the use of high-k materials such as lanthanum oxide reduces gate leakage current can be reduced.

[0082] The insulating layer 403 may be a single layer or a stacked layer. In this embodiment, the insulating layer 403 is preferably a crystalline oxide insulating film. An insulating layer in which a silicon oxide film and an aluminum oxide film are laminated from the side in contact with the conductor layer 401 The aluminum oxide film is resistant to both impurities such as hydrogen and moisture, and oxygen. The blocking effect of preventing the penetration of oxygen from the crystalline oxide semiconductor layer 401 is high. It can be preferably used because it can prevent the release of elements.

[0083] When the insulating layer 403 has an oxygen-excess region, the insulating layer 403 This is preferable because it can compensate for oxygen vacancies in the crystalline oxide semiconductor layer. To provide an oxygen-excess region in the insulating layer 403, for example, the insulating layer 403 may be formed in an oxygen atmosphere. Alternatively, the insulating layer 403 after deposition may contain oxygen (at least oxygen radicals, oxygen atoms, The oxygen-rich region may be formed by implanting oxygen ions (including either oxygen ions).

[0084] Note that the crystalline oxide semiconductor layer 401 is formed before or over the insulating layer 403. By injecting oxygen into the crystalline oxide semiconductor layer 401, an oxygen-excess region may be formed in the crystalline oxide semiconductor layer 401. When oxygen is injected through a film stacked on the crystalline oxide semiconductor layer 401, the oxygen injection Since the depth (implantation region) can be more easily controlled, oxygen can be injected into the crystalline oxide semiconductor layer 401. On the other hand, when the crystalline oxide semiconductor layer 401 is exposed, When oxygen is implanted in this state, the flatness of the surface of the crystalline oxide semiconductor layer 401 can be improved. This can be done.

[0085] The depth of oxygen implantation into the crystalline oxide semiconductor layer 401 depends on implantation conditions such as acceleration voltage and dose. The thickness of the insulating layer 403 through which the electrons pass may be appropriately set and controlled. Therefore, the oxygen content of the crystalline oxide semiconductor layer 401 is increased to a level exceeding the stoichiometric ratio. For example, the crystalline oxide semiconductor layer 4 introduced by oxygen injection treatment is preferably The peak oxygen concentration at 01 is 1×10 18 / cm 3 5x10 or more 21 / cm 3 Below and It is preferable to do so.

[0086] When an oxide insulating film is formed as the insulating layer 403 or when the insulating layer 403 has an oxygen excess region, In this case, it is preferable to perform heat treatment after forming the insulating layer 403. The temperature of the heat treatment is, for example, For example, the temperature is 250°C or higher and 450°C or lower. The heat treatment may be carried out in an atmosphere of nitrogen, oxygen, ultra-dry air, or dilute It may be carried out under a gas atmosphere (argon, helium, etc.), but the above-mentioned nitrogen, oxygen, and ultra-dry air It is preferable that the atmosphere of the gas or rare gas does not contain water, hydrogen, etc. The purity of nitrogen, oxygen, or rare gas introduced into the device is preferably 6N (99.9999%) or higher. or 7N (99.99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably 0 It is preferable to keep it at 0.1 ppm or less.

[0087] This heat treatment simultaneously reduces the amount of carbon dioxide produced by heat treatments aimed at dehydration or dehydrogenation. Oxygen, one of the main components of oxide semiconductors, is introduced into the insulating layer containing oxygen (Fig. In 2(B), the crystalline oxide semiconductor layer 401 can be supplied from the insulating layer 403). This allows the crystalline oxide semiconductor layer 401 to be highly purified and made i-type (intrinsic). In addition, by forming an oxygen excess region in the crystalline oxide semiconductor layer 401, oxygen vacancies can be reduced. Since the charge trapping centers in the crystalline oxide semiconductor layer 401 can be reduced, The timing of the heat treatment is not limited to that of this embodiment mode.

[0088] In the crystalline oxide semiconductor layer, oxygen vacancies exist at the locations where oxygen is released. This causes a donor level that causes fluctuations in the electrical characteristics of the transistor. By supplying oxygen to the crystalline oxide semiconductor layer 404 that has been subjected to hydration or dehydrogenation treatment, This is preferable because it can compensate for oxygen vacancies in the film. By using the conductor layer in a transistor, the threshold voltage of the transistor caused by oxygen vacancies can be reduced. It is possible to reduce the Vth variation and the shift (fluctuation) of the threshold voltage. The low voltage can be shifted to the positive side to make the transistor normally off.

[0089] Note that when oxygen is injected into the crystalline oxide semiconductor layer 401, the oxygen contained in the oxide semiconductor layer The crystal structure of the silicon dioxide may be disturbed and become amorphous, but the oxygen vacancies mentioned above are compensated for by the It is possible to recrystallize it by performing a heat treatment.

[0090] Next, a gate electrode (including wiring formed in the same layer) is formed on the gate insulating layer 406. A conductive film made of the above is formed and processed to form a gate electrode 410. The gate electrode 410 is Molybdenum, titanium, tantalum, tantalum, etc. can be deposited by plasma CVD or sputtering. Metallic materials such as tungsten, aluminum, copper, neodymium, scandium, etc., or materials mainly composed of these The gate electrode 410 can be formed using an alloy material containing phosphorus or the like. Semiconductor films, such as polycrystalline silicon films doped with impurity elements, nickel silicide films, The gate electrode 410 may have a single layer structure. A laminated structure may also be used.

[0091] Next, the insulating layer 403 is etched using the gate electrode 410 as a mask to form a gate insulating layer 406 is formed, and a part of the crystalline oxide semiconductor layer 401 (the gate electrode 410 The area that does not overlap with the area of ​​the substrate (see Figure 2(C)).

[0092] Next, the exposed region of the crystalline oxide semiconductor layer 404 is irradiated with nitrogen plasma 421 . By this nitrogen plasma treatment, the exposed region of the crystalline oxide semiconductor layer 404 The source region 404a and the drain region 404b are partially nitrided to form n-type regions. and a crystalline oxide semiconductor layer 404 having a channel formation region 404c (FIG. 2(D)). Here, the region sandwiched between the source region 404a and the drain region 404b The channel formation region 404c is not exposed to the nitrogen plasma 421 and is therefore i-type or This is essentially an i-type crystalline oxide semiconductor layer.

[0093] The nitrogen plasma treatment can be carried out using, for example, a high-density plasma treatment device. An example of nitrogen plasma processing using a plasma processing apparatus will be described below. After supplying a mixture of nitrogen and rare gases, microwaves are introduced into the plasma processing chamber. In this plasma, a mixture of nitrogen and rare gas is generated. Microwaves excite rare gases to generate rare gas radicals, which Nitrogen radicals are generated by collisions between the atoms and nitrogen molecules. The generated nitrogen radicals and the metal elements or the like contained in the exposed region of the crystalline oxide semiconductor layer are The crystalline oxide semiconductor layer in this region is nitrided by reacting with the silicon dioxide or oxygen.

[0094] The gases applicable to the nitrogen plasma treatment are not limited to the above-mentioned mixed gases, but may include, for example, nitrogen, A mixed gas of hydrogen and a rare gas, or a mixed gas of NH3 and a rare gas, etc. can be used appropriately. Nitrogen radicals and NH radicals are generated in the plasma of these mixed gases. These radicals nitride a part of the crystalline oxide semiconductor layer.

[0095] The heating temperature for the nitrogen plasma treatment is set to a range of 100°C or higher and 550°C or lower. However, the heating temperature of the nitrogen plasma treatment is relatively high (for example, 450°C or higher). In this case, the resistance of the source region 404a and the drain region 404b can be further reduced. Therefore, it is preferable.

[0096] In addition, nitrogen plasma treatment causes little damage to the crystalline oxide semiconductor layer and is highly reactive. This is a treatment in which neutral atoms or neutral molecules are bonded to a metal element contained in a crystalline oxide semiconductor layer. The nitrogen plasma treatment can improve the crystallinity of the crystalline oxide semiconductor layer. Therefore, the source region 404a and the drain region 404b formed by this process are b (at least in the vicinity of the surface of the region) is a crystalline oxynitride semiconductor layer or a crystalline The nitride semiconductor layer is formed, and these regions have a higher crystallinity than the channel forming region 404c. The surface of the gate electrode 410 is also nitrided by the nitrogen plasma treatment. It is possible.

[0097] For example, when an In—Ga—Zn—O film is used as the crystalline oxide semiconductor layer 144, By performing the nitrogen plasma treatment, the surface area of ​​the In-Ga-Zn-O film (for example, the 5 In the In-Ga-Zn-O -N film is formed.

[0098] The source region 404a and the drain region 404b are formed by crystalline deposition using the gate electrode 410 as a mask. The gate electrode 410 is formed by adding nitrogen to the conductive oxide semiconductor layer 401. By forming the source region 404a and the drain region 404b using the The gate electrode 410 does not overlap with the drain region 404a and the drain region 404b. Since the excess parasitic capacitance can be reduced, the transistor 510 to be manufactured can be operated at high speed. It can be made to work.

[0099] Next, an insulating layer 412 is formed to cover the crystalline oxide semiconductor layer 404 and the gate electrode 410. In the insulating layer 412, a region overlapping with the source region 404a and the drain region 404b An opening (also called a contact hole) is provided in each of the contacts. The source electrodes 404a and 404b are connected to the source region 404a and the drain region 404b through holes. The electrode 415a and the drain electrode 415b are formed (FIG. 2(E)). A resistor 510 can be formed.

[0100] Although not shown, when the contact holes are opened, the crystalline oxide semiconductor layer 404 A portion (a portion of the source region 404a and the drain region 404b) is etched to form a recess. In some cases, the crystalline oxide semiconductor layer 404 has a crystalline structure.

[0101] The material of the insulating layer 412 is silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like. Aluminum nitride, aluminum oxide, and aluminum nitride can be used as a single layer or laminated layers. The film can be formed by sputtering, CVD, etc. At this time, oxygen is released by heating. It is preferable to use a material that is difficult to dissolve. This is to prevent the conductivity of 4b from decreasing. The main material is gas, and the appropriate raw material gas is selected from nitrogen oxide gas, nitrogen gas, hydrogen gas, and rare gas. The substrate temperature may be set to 300°C or higher and 550°C or lower. By using the CVD method, it is possible to create a material that is less likely to release oxygen when heated. By using silane gas as the main material, hydrogen remains in the film, and the hydrogen diffuses to form a source. The conductivity of the region 404a and the drain region 404b can be further increased. The hydrogen concentration in 12 may be set to 0.1 atomic % or more and 25 atomic % or less.

[0102] The source electrode 415a and the drain electrode 415b are formed by plasma CVD or sputtering. Molybdenum, titanium, tantalum, tungsten, aluminum, copper, A single layer is made of metal materials such as neodymium and scandium or alloy materials containing these as the main components. Alternatively, it can be formed by laminating layers.

[0103] The transistor 510 described in this embodiment has a crystalline oxide semiconductor layer 404. The source region 404a or the drain electrode 415b is in contact with the source electrode 415a or the drain electrode 415b. The crystalline oxide semiconductor layer 404 and the source region 404b are formed on the substrate 100. The contact with the source electrode 415a or the drain electrode 415b is an ohmic contact. This allows for thermally stable operation compared to a Schottky junction. As a result, the contact resistance of the transistor 51 can be reduced. 0 on-current can be increased.

[0104] It also supplies the carrier of the channel (source side) or stabilizes the carrier of the channel. (drain side) or resistance is formed at the interface with the source electrode (or drain electrode). In order to suppress the formation of the component, the source region 404a and the drain region 404b are provided. It is important to + By providing this layer, good mobility can be achieved even at high drain voltages. The degree can be maintained.

[0105] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0106] (Embodiment 2) In this embodiment, a semiconductor device according to one embodiment of the present invention, which is different from that in Embodiment 1, and a manufacturing method thereof will be described. The method will be described with reference to Figs. 3 to 5. Note that the same parts as those in the first embodiment or similar parts will be used. The functional parts and steps can be performed in the same manner as in the first embodiment, and the repeated explanations are omitted. is omitted.

[0107] FIG. 3A shows a cross-sectional view of a transistor 520 as an example of a semiconductor device. The transistor 520 shown in FIG. 1 is a transistor including a base insulating layer 402 and a semiconductor layer 404 over a substrate 400 having an insulating surface. A crystalline oxide film including a source region 404a, a drain region 404b, and a channel forming region 404c is formed. a gate insulating layer 406; a gate electrode 410; and a source region 404. In a, the source electrode 405a is in contact with the crystalline oxide semiconductor layer 404, and the drain region 4 In the region 04b, a drain electrode 405b in contact with the crystalline oxide semiconductor layer 404 and a source electrode 405c are formed. an insulating layer 414 covering the electrode 405a, the drain electrode 405b, and the crystalline oxide semiconductor layer 404; The base insulating layer 402 and the insulating layer 414 are not necessarily formed as a transistor. It may not be a component of register 520.

[0108] FIG. 3B is a cross-sectional view of a transistor 530 as another example of a semiconductor device. The transistor 530 shown in FIG. 3(B) has a gate electrode 404 formed on a substrate 400 having an insulating surface. 10, a gate insulating layer 406, a source region 404a, a drain region 404b and a channel region The crystalline oxide semiconductor layer 404 including the channel formation region 404c and the a channel protection layer 416 provided in the source region 404a; and a crystalline oxide semiconductor layer The source electrode 405a contacts the layer 404, and the drain region 404b is made of a crystalline oxide semiconductor. The drain electrode 405b contacting the conductor layer 404, the source electrode 405a, and the drain electrode 40 5b and an insulating layer 414 that covers the channel protection layer 416. The panel passivation layer 416 and the insulating layer 414 are not necessarily components of the transistor 530. This is also good.

[0109] An example of a manufacturing process of the transistor 520 will be described below with reference to FIGS. 4A and 4B. .

[0110] First, the base film provided on the substrate 400 is removed by the steps shown in FIGS. 2(A) to 2(D). An insulating layer 402 and a source region 404a and a drain region 404b are provided on the insulating base layer 402. the crystalline oxide semiconductor layer 404 including the channel formation region 404b and the channel formation region 404c; A gate insulating layer 406 is provided on and in contact with the gate insulating layer 406. and a gate electrode 410 provided on the channel forming region 404c.

[0111] Next, a source electrode 405a and a gate electrode 410 are formed on the crystalline oxide semiconductor layer 404 and the gate electrode 410. and a conductive film 405 which will become a drain electrode 405b (including wiring formed in the same layer as this). A film is formed (see Figure 4(A)).

[0112] The conductive film 405 is formed using the same material and method as the source electrode 415a and the drain electrode 415b. The method can be used to form the sintered body.

[0113] Next, the conductive film 405 is processed by a photolithography process to form a source electrode 405a and A resist mask for processing the conductive film 405 is used to form a drain electrode 405b. The resist mask may be formed by an ink-jet method. Since no photomask is used, the manufacturing cost of the semiconductor device can be reduced.

[0114] Note that the crystalline oxide semiconductor layer 404 is removed as much as possible when the conductive film 405 is etched. The materials and etching conditions are adjusted appropriately so that the Therefore, the exposed region of the crystalline oxide semiconductor layer 404 (the gate electrode 410, the source electrode The area (which does not overlap with either the drain electrode 405a or the drain electrode 405b) is partially etched. As a result, a groove (recess) may be formed.

[0115] Next, the source electrode 405a, the drain electrode 405b, and the crystalline oxide semiconductor layer 404 An overlying insulating layer 414 is formed, which allows the formation of transistor 520. (See Figure 4(B)).

[0116] The insulating layer 414 can be formed using a material and a manufacturing method similar to those of the insulating layer 412. .

[0117] An example of a manufacturing process of the transistor 530 will be described with reference to FIGS. 5A to 5D. .

[0118] First, a gate electrode (a wiring formed in the same layer as this) is formed on a substrate 400 having an insulating surface. A conductive film (including the gate electrode) is formed and processed to form the gate electrode 410. A gate insulating layer 406 is formed to cover the gate electrode 410. The gate insulating layer 406 is formed in an oxygen-excess region. It is preferred that the ion exchange region has a region.

[0119] Next, a crystalline oxide semiconductor layer 401a is formed over the gate insulating layer 406 (FIG. 5A). Note that the gate insulating layer 406 and the crystalline oxide semiconductor layer 401a were not exposed to the air. The gate insulating layer 406 and the crystalline oxide semiconductor layer 401 are preferably formed in succession. When the gate insulating layer 406 is formed without exposure to the air, hydrogen, moisture, etc. This can prevent impurities from being adsorbed.

[0120] After the crystalline oxide semiconductor layer 401a is formed, the oxide semiconductor layer 401a contains Heat treatment to remove (dehydrate or dehydrogenate) excess hydrogen (including water and hydroxyl groups) that is present in the It is preferable that the heat treatment for dehydration or dehydrogenation is performed on the crystalline oxide semiconductor. After the formation of layer 401a and before the nitrogen plasma treatment step, the fabrication of transistor 530 can be performed. However, the heat for dehydration or dehydrogenation may be used at any time during the manufacturing process. When the treatment is performed before processing the crystalline oxide semiconductor layer 401a into an island shape, the gate insulating layer 406 This is preferable because it can prevent the oxygen contained therein from being released by heat treatment.

[0121] After the crystalline oxide semiconductor layer 401a is heated by the heat treatment, a high-purity oxygen gas is introduced into the same furnace. High-purity dinitrogen monoxide gas or ultra-dry air may be introduced. The action of nitrogen gas simultaneously removes impurities through dehydration or dehydrogenation treatment. By supplying oxygen, which is the main component material that makes up oxide semiconductors, As a result, the oxide semiconductor film can be highly purified and made to be i-type (intrinsic).

[0122] Next, the crystalline oxide semiconductor layer 401a is formed into island-shaped crystalline oxide films by a photolithography process. Then, an insulating film is formed on the island-shaped crystalline oxide semiconductor layer 401. The insulating layer 416a is formed as a film (see FIG. 5B). This layer is formed as a channel protection layer 416 .

[0123] The insulating layer 416a can be formed using a material and a manufacturing method similar to those of the insulating layer 403. Note that the insulating layer 416a has a single layer structure or a stacked layer structure including an oxide insulating film. The insulating film is preferably in contact with the crystalline oxide semiconductor layer 401 .

[0124] Furthermore, when the insulating layer 416a has an oxygen-excess region, the excess oxygen contained in the insulating layer 416a This is preferable because oxygen vacancies in the crystalline oxide semiconductor layer 401 can be compensated for by the above method. In the case where the insulating layer 416a has a stacked-layer structure, the insulating layer 416a is in contact with at least the crystalline oxide semiconductor layer 401. It is preferable to provide an oxygen excess region in the insulating layer 416a. To prevent this, the insulating layer 416a may be formed in an oxygen atmosphere, for example. Oxygen may be implanted into the insulating layer 416a to form an oxygen-excess region.

[0125] Before forming the insulating layer 416a or from above the insulating layer 416a, the crystalline oxide semiconductor layer 4 By injecting oxygen into the oxide semiconductor layer 401, an oxygen-excess region can be formed in the crystalline oxide semiconductor layer 401. good.

[0126] When an oxide insulating film is formed as the insulating layer 416a or when the insulating layer 416a is formed in an oxygen-excess region, In the case where the insulating layer 416a has a region, it is preferable to perform heat treatment after the insulating layer 416a is formed. Therefore, the oxide semiconductor, which is simultaneously reduced by the heat treatment for dehydration or dehydrogenation, Oxygen, one of the main components that make up the body, is absorbed into the insulating layer (insulating layer in Figure 5(B)) containing oxygen. The insulating layer 416a can be supplied to the crystalline oxide semiconductor layer 401. In this way, the crystalline oxide semiconductor layer 401 can be highly purified and made to be i-type (intrinsic). By forming an oxygen excess region in the crystalline oxide semiconductor layer 401, oxygen vacancies can be immediately compensated for. Therefore, the number of charge trapping centers in the crystalline oxide semiconductor layer 401 can be reduced. The timing of the heat treatment is not limited to that of this embodiment.

[0127] Note that when oxygen is injected into the crystalline oxide semiconductor layer 401, The crystal structure contained in the silicon dioxide may be disturbed and become amorphous, but this is done to compensate for the oxygen defects mentioned above. It is possible to recrystallize the crystal by performing a heat treatment under the above conditions.

[0128] Next, the insulating layer 416a is processed by a photolithography process to form a channel protection layer 416 The resist mask for forming the channel protection layer 416 is formed by inkjet printing. If the resist mask is formed by the ink-jet method, the photomask Since no circuit is used, the manufacturing cost of the semiconductor device can be reduced.

[0129] Next, the exposed portion of the crystalline oxide semiconductor layer 404 was removed using the channel protection layer 416 as a mask. The exposed area is exposed to nitrogen plasma 421. By nitriding a part of the crystalline oxide semiconductor layer 404, which is a region of the crystalline oxide semiconductor layer 404, the n-type source A crystalline semiconductor having a region 404a, a drain region 404b, and a channel forming region 404c. An oxide semiconductor layer 404 is formed (see FIG. 5C). The channel forming region 404c, which is the region sandwiched between the drain region 404b and the drain region 404b, is formed by nitrogen plasma. Since the oxide semiconductor layer is not exposed to the ultraviolet light 421, it is an i-type or substantially i-type crystalline oxide semiconductor layer. do.

[0130] In the bottom gate transistor 530, the source region 404a and the drain region 404b is a graph showing a method for forming a nitrogen-doped layer on the crystalline oxide semiconductor layer 401 using the channel protection layer 416 as a mask. The channel protective layer 416 can be formed by plasma irradiation. However, the source region 404a and the drain region 404b have a function of protecting the back channel portion of the source region 404a. After the drain region 404b is formed, the channel protection layer 416 may be removed.

[0131] Next, a source electrode 405 is formed on the crystalline oxide semiconductor layer 404 and the channel protection layer 416. a and the drain electrode 405b (including wiring formed in the same layer as these). This is then processed to form the source electrode 405a and the drain electrode 405b. The electrode 405a and the drain electrode 405b are connected to the source electrode 415a and the drain electrode 415 It can be formed using the same materials and manufacturing method as b.

[0132] Next, an insulating layer covering the source electrode 405a, the drain electrode 405b and the channel protection layer 416 is 1. Form the edge layer 414. This allows the transistor 530 to be formed (see FIG. 5(D)).

[0133] The insulating layer 414 can be formed using a material and a manufacturing method similar to those of the insulating layer 412. .

[0134] The transistor 520 and the transistor 530 described in this embodiment are made of a crystalline oxide semiconductor. In the layer 404, a source electrode 405a or a drain electrode 405b is provided in a region where the source electrode 405a or the drain electrode 405b is in contact. The source region 404a and the drain region 404b are formed in the crystalline oxide layer 404a and the drain region 404b, respectively. The contact between the compound semiconductor layer 404 and the source electrode 405a or the drain electrode 405b is formed by overcoating. It is possible to make a thermally stable contact compared to a Schottky junction. Furthermore, the contact resistance can be reduced. As a result, the on-state current of the transistor 520 and the transistor 530 can be increased. .

[0135] It also supplies the carrier of the channel (source side) or stabilizes the carrier of the channel. (drain side) or resistance is formed at the interface with the source electrode (or drain electrode). In order to suppress the formation of the component, the source region 404a and the drain region 404b are provided. It is important to + By providing this layer, good mobility can be achieved even at high drain voltages. The degree can be maintained.

[0136] The transistor 520 and the transistor 530 described in this embodiment have a source region 4 The drain region 404a, the drain region 404b, and the channel forming region 404c are crystalline regions. By this, the source region 404a, the channel forming region 404c, and the drain region 404b The junction state of the source region 404a and the drain region 404 can be improved. By making the channel formation region 404b and the channel formation region 404c crystalline regions, a crystalline oxide semiconductor can be obtained. Therefore, the intra-band energy level in the semiconductor layer 404 can be reduced. The reliability of the transistor 520 and the transistor 530 can be improved. It can be done.

[0137] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0138] (Embodiment 3) A semiconductor device having a display function using the transistor as an example shown in the first or second embodiment In addition, a display device (also called a display device) can be manufactured by using a transistor as a driver circuit. The entire display unit or the entire display unit is integrally formed on the same substrate as the pixel unit to form a system-on-panel. can be done.

[0139] In FIG. 6A, a pixel portion 4002 provided on a first substrate 4001 is surrounded by a A sealant 4005 is provided and the substrate is sealed with a second substrate 4006. In A), the area surrounded by the sealant 4005 on the first substrate 4001 and are formed in different regions using a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate. A scanning line driver circuit 4004 and a signal line driver circuit 4003 are also mounted. Various signals and signals are given to the pixel portion 4002 through a circuit 4003 and a scanning line driver circuit 4004. The potential is measured using FPC (Flexible printed circuit) 4018a. Powered by 4018b.

[0140] 6B and 6C, a pixel portion 4002 provided on a first substrate 4001 and a scanning A sealing material 4005 is provided so as to surround the line driver circuit 4004. A second substrate 4006 is provided on the substrate 4002 and the scanning line driver circuit 4004. The pixel portion 4002 and the scanning line driver circuit 4004 are formed by the first substrate 4001 and the sealing material 4004. The display element is sealed by the second substrate 4005 and the second substrate 4006. In C), the area surrounded by the sealant 4005 on the first substrate 4001 and are formed in different regions using a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate. In FIG. 6(B) and (C), a signal line driver circuit 4003 is mounted. Various signals and signals are given to the pixel portion 4002 through a circuit 4003 and a scanning line driver circuit 4004. The voltage and potential are supplied by FPC4018.

[0141] 6B and 6C, the signal line driver circuit 4003 is formed separately, and the first substrate 4 001, but the present invention is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed and mounted. It may be formed separately and mounted.

[0142] The method of connecting the separately formed drive circuit is not particularly limited, and may be ip On Glass) method, wire bonding method, or TAB (Tape A The C This is an example in which a signal line driver circuit 4003 and a scanning line driver circuit 4004 are implemented by the OG method. FIG. 6(B) shows an example in which a signal line driver circuit 4003 is mounted by the COG method, and FIG. 6(C) shows an example in which a signal line driver circuit 4003 is mounted by the COG method. ) is an example in which the signal line driver circuit 4003 is mounted by the TAB method.

[0143] The display device is a panel in which a display element is sealed, and a controller connected to the panel. This includes modules in which ICs, etc., including lasers, are mounted.

[0144] That is, the display device in this specification is an image display device, a display device, or It refers to the light source (including the lighting device). It also refers to the panel in which the display element is sealed. Connectors such as FPC, TAB tape, or TCP are attached to the module. a module with a printed wiring board attached to the end of a TAB tape or TCP, or All modules in which ICs (integrated circuits) are directly mounted on the display element using the COG method are also included in the display device. This shall be included in the location.

[0145] The pixel portion and the scanning line driver circuit provided on the first substrate have a plurality of transistors. The transistors shown as examples in Embodiment 1 or 2 can be applied to this embodiment.

[0146] The display element provided in the display device may be a liquid crystal element (also called a liquid crystal display element), a light-emitting element ( The light-emitting element emits light by applying a current or a voltage. This category includes elements whose brightness can be controlled, specifically inorganic EL (Electroluminescent) Luminescence, organic EL, etc. Also, electronic ink display devices (electronic It can also be used for display media whose contrast changes electrically, such as paper. Cut.

[0147] One mode of a semiconductor device will be described with reference to FIGS. 6A and 6B. FIG. 7 shows the M Equivalent to the cross-sectional view at -N.

[0148] As shown in FIGS. 6 and 7, the semiconductor device has a connection terminal electrode 4015 and a terminal electrode 4016. The connection terminal electrode 4015 and the terminal electrode 4016 are terminals of the FPC 4018. and are electrically connected via an anisotropic conductive film 4019 .

[0149] The connection terminal electrode 4015 is formed from the same conductive film as the first electrode layer 4030. 016 is the same conductor as the source electrode layer and the drain electrode layer of the transistors 4010 and 4011. It is formed of a conductive film.

[0150] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. 6 and 7, the transistors included in the pixel portion 4002 are 4004 and a transistor 4010 included in the scanning line driver circuit 4004. In FIG. 7A, an insulating layer 4020 is provided over the transistors 4010 and 4011. 7B, an insulating layer 4021 is further provided. This is an insulating layer that functions as a base film.

[0151] The transistors 4010 and 4011 may be the transistors shown in Embodiment 1 or 2. In this embodiment, the transistor shown in Embodiment 2 can be applied. An example in which a transistor having a structure similar to that of the transistor 520 is applied will be shown.

[0152] The transistors 4010 and 4011 have channel formation regions in the channel length direction. The low-resistance region (hereinafter simply referred to as the low-resistance region) functions as a source region or a drain region. The transistor has a crystalline oxide semiconductor layer including a crystalline oxide semiconductor layer. The resistor 4010 and the transistor 4011 have on-characteristics (e.g., on-current and field effect It has high mobility, enabling high-speed operation and high-speed response. It can also be miniaturized.

[0153] Therefore, the semiconductor device of this embodiment shown in FIGS. 6 and 7 is a high-performance and highly reliable semiconductor. A body device can be provided.

[0154] The transistor 4010 provided in the pixel portion 4002 is electrically connected to a display element. The display element is not particularly limited as long as it can display, and various display elements can be used. can be used.

[0155] FIG. 7A shows an example of a liquid crystal display device using a liquid crystal element as a display element. The liquid crystal element 4013 includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer The liquid crystal layer 4008 is sandwiched between insulating layers 4008, which function as alignment layers. The second electrode layer 4031 is formed on the second substrate 400. The first electrode layer 4030 and the second electrode layer 4031 are connected via the liquid crystal layer 4008. The structure is such that the electrodes are stacked one on top of the other.

[0156] 4035 is a columnar spacer obtained by selectively etching the insulating layer. It is provided to control the film thickness (cell gap) of the liquid crystal layer 4008. A pacer may be used.

[0157] When liquid crystal elements are used as display elements, thermotropic liquid crystals, ferroelectric liquid crystals, antiferroelectric liquid crystals, These liquid crystals may be low molecular weight compounds or polymers. These liquid crystal materials (liquid crystal compositions) can be in a cholesteric phase, a smectic phase, or a chiral phase depending on the conditions. It shows cubic phase, chiral nematic phase, isotropic phase, etc.

[0158] In addition, a liquid crystal composition that exhibits a blue phase without using an alignment film may be used for the liquid crystal layer 4008. The blue phase is one of the liquid crystal phases, and when the temperature of cholesteric liquid crystal is increased, the cholesteric The blue phase is a phase that appears just before the transition from the black phase to the isotropic phase. The blue phase can be expressed by using a liquid crystal composition in which the above-mentioned compounds are mixed. In order to widen the temperature range, a polymerizable monomer and a polymerization initiator are added to the liquid crystal composition that exhibits the blue phase. The liquid crystal layer can be formed by adding a polymer stabilizer. The liquid crystal composition that exhibits this phase has a short response time and is optically isotropic, so alignment treatment is not required. It has little viewing angle dependency. Also, since there is no need to provide an alignment film, rubbing treatment is not required. Therefore, electrostatic breakdown caused by the rubbing process can be prevented, and the manufacturing process This reduces defects and damage to the liquid crystal display device during the manufacturing process, thereby improving the productivity of the liquid crystal display device. It is possible to improve

[0159] The specific resistance of the liquid crystal material is 1×10 9 Ω·cm or more, preferably 1×10 11 Ω·cm or more, and more preferably 1×10 12 Ω·cm or more. The resistivity values ​​in this document are those measured at 20°C.

[0160] The size of the storage capacitor provided in the liquid crystal display device is determined by the lead of the transistor arranged in the pixel portion. It is set so that the charge can be held for a predetermined period, taking into consideration the current and other factors. The size may be set in consideration of the off-state current of the transistor. By using a transistor having a conductive oxide semiconductor layer, the liquid crystal capacitance in each pixel can be increased. By providing a storage capacitor having a capacity of 1 / 3 or less, preferably 1 / 5 or less, the charging minutes.

[0161] The transistor using a crystalline oxide semiconductor layer disclosed in this specification has a low current density in an off state. Therefore, the retention time of an electric signal such as an image signal can be reduced. Therefore, the frequency of refresh operations can be increased. This reduces the power consumption.

[0162] In addition, the transistor using the crystalline oxide semiconductor layer disclosed in this specification has a high field effect For example, such a transistor can be used in a liquid crystal display. By using it in a display device, it can be used as a switching transistor in the pixel section and a transistor in the driver circuit section. The driver transistor can be formed on the same substrate. By using such a transistor, it is possible to provide a high-quality image. As a result, high reliability can be achieved as a semiconductor device.

[0163] There are two types of LCD displays: TN (Twisted Nematic) mode, IPS (In-P lane-Switching) mode, FFS(Fringe Field Switching) mode, ching) mode, ASM(Axially Symmetric aligned) Micro-cell mode, OCB (Optical Compensated B) refrigeration mode, FLC (Ferroelectric Liquid d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0164] Furthermore, normally black type liquid crystal display devices, for example, those employing vertical alignment (VA) mode The liquid crystal display device may be a transmission type. For example, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode , ASV (Advanced Super View) mode, etc. can be used. It can also be applied to VA type liquid crystal display devices. VA type liquid crystal display devices are: It is a type of method for controlling the alignment of liquid crystal molecules in a liquid crystal display panel. VA type liquid crystal display devices are When no voltage is applied, the liquid crystal molecules are oriented perpendicular to the panel surface. In addition, a pixel is divided into several regions (subpixels), each of which is oriented in a different direction. This is called multi-domain or multi-domain design, which is designed to knock down molecules. The following method can be used.

[0165] In addition, in display devices, black matrices (light-shielding layers), polarizing members, phase difference members, reflecting members, Optical members (optical substrates) such as a protection member are provided as appropriate. For example, a polarizing substrate and a retardation substrate are provided as appropriate. Alternatively, a backlight or a sidelight may be used as the light source. It's fine.

[0166] In addition, the display method in the pixel section uses the progressive method, interlace method, etc. In addition, the color elements controlled by pixels when displaying colors are RGB (R is It is not limited to the three colors (red, green, and blue). For example, RGBW (W stands for white). , or RGB plus one or more colors such as yellow, cyan, magenta, etc. The size of the display area may be different for each dot of the color element. is not limited to color display devices, but also applies to monochrome display devices. It is also possible.

[0167] Furthermore, a light-emitting element that utilizes electroluminescence is used as a display element included in the display device. The light-emitting element using electroluminescence can be applied to a light-emitting material They are distinguished by whether they are organic or inorganic compounds, and generally, the former are organic E The latter is called an inorganic EL element.

[0168] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into the layers containing the light-emitting organic compounds, causing a current to flow. The recombination of the electrons and holes creates an excited state in the light-emitting organic compound. The excited state is then converted to the ground state, at which point light is emitted. Such a light-emitting element is called a current-excited light-emitting element.

[0169] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0170] In order to extract light emitted from the light-emitting element, at least one of the pair of electrodes needs to be light-transmitting. Then, a transistor and a light emitting element are formed on the substrate, and light is extracted from the surface opposite to the substrate. There are various types of light sources, including top emission, bottom emission, and light emission from the substrate side and the opposite side of the substrate. There are light emitting elements with a double-sided emission structure that emits light from both sides, and light emitting elements of any emission structure can be applied. It is possible.

[0171] FIG. 7B shows an example of a light-emitting device using a light-emitting element as a display element. 4002. The transistor 4002 is electrically connected to the transistor 4010 provided in the pixel portion 4002. The light-emitting element 4513 shown in (B) has a structure including a first electrode layer 4030, an electroluminescent layer 4511, and a , the second electrode layer 4031, but is not limited to the structure shown. The configuration of the light emitting element 4513 can be changed appropriately according to the direction of the light extracted from 13. can.

[0172] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material, particularly a photosensitive resin. An opening is formed on the first electrode layer 4030 using a material, and the sidewall of the opening has a continuous curved surface. It is preferable to form the inclined surface so as to have a certain slope.

[0173] The electroluminescent layer 4511 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's done or not.

[0174] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4513. A protective film may be formed on the insulating film 4031 and the partition wall 4510. The protective film may be made of silicon nitride. A silicon nitride film, a silicon oxide film, a DLC film, etc. can be formed on the first substrate 400. The space sealed by the first substrate 4001, the second substrate 4006, and the sealing material 4005 is filled with a filler 45. 14 is provided and sealed. In this way, it is highly airtight and degassed so as not to be exposed to the outside air. Protective films with low wear (laminating films, UV-curing resin films, etc.) and covering materials It is preferable to package (enclose) the

[0175] Filler 4514 can be an inert gas such as nitrogen or argon, or an ultraviolet curing resin or Thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic resin, Imide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate copolymer) can be used.

[0176] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0177] It is also possible to provide electronic paper that drives electronic ink as a display device. Electronic paper is also called an electrophoretic display (electrophoretic display), and is a paper It is possible to make it as easy to read as a digital camera, consume less power than other display devices, and have a thinner and lighter form factor. This has the advantage that

[0178] The electrophoretic display device may have various forms, but it has a structure in which first particles having a positive charge and and a second particle having a negative charge, and a plurality of microcapsules containing the first particle and the second particle having a negative charge are dispersed in a solvent. By applying an electric field to the microcapsules, the particles in the microcapsules The particles are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye and do not move in the absence of an electric field. In addition, the color of the first particles and the color of the second particles are different (including colorless).

[0179] The microcapsules dispersed in a solvent are called electronic ink. Color display is also possible by using color filters or particles containing pigments.

[0180] In addition, a display device using a twist ball display method can also be applied as electronic paper. The twist ball display method uses spherical particles painted in black and white as the display element. The first electrode layer and the second electrode layer are disposed between the first electrode layer and the second electrode layer. This is a display method that controls the orientation of spherical particles by creating a potential difference between the electrode layers. be.

[0181] 6 and 7, the first substrate 4001 and the second substrate 4006 are made of glass. In addition to a glass substrate, a flexible substrate can also be used. For example, a light-transmitting plastic substrate can be used. As for plastic, FRP (Fibreglass) s-Reinforced Plastics) plate, PVF (Polyvinyl Fluoride) A film, a polyester film or an acrylic resin film can be used. If transparency is not required, metal substrates such as aluminum and stainless steel (metal film For example, aluminum foil can be covered with PVF film or polyester film. It is also possible to use a sheet sandwiched between two sheets.

[0182] In this embodiment, an aluminum oxide film is used as the insulating layer 4020.

[0183] The aluminum oxide film provided as the insulating layer 4020 over the crystalline oxide semiconductor layer is , a blocking effect that prevents impurities such as water and oxygen from passing through the membrane (blocking effect) ) is high.

[0184] Therefore, the aluminum oxide film is free from hydrogen, which is a factor of fluctuation during and after the manufacturing process. The incorporation of impurities such as moisture into the crystalline oxide semiconductor layer and the generation of acid from the crystalline oxide semiconductor layer It functions as a protective film that prevents the release of elements.

[0185] The insulating layer 4021 functioning as a planarizing insulating layer is made of a material such as acrylic resin, polyimide, or benzophenone. By using heat-resistant organic materials such as cyclobutene resin, polyamide, and epoxy, In addition to the above organic materials, siloxane resin, PSG (phosphor glass), BP A low-k material such as SG (silicon boron nitride) can be used. The insulating layer 4021 is formed by stacking a plurality of insulating layers made of these materials. You may do so.

[0186] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, a S OG method, spin coating, dip coating, spray coating, droplet ejection method (inkjet method, etc.), Screen printing, offset printing, doctor knife, roll coater, curtain coater A knife coater or the like can be used.

[0187] A display device transmits light from a light source or a display element to display an image. All thin films such as the substrate, insulating layer, and conductive film provided in the part are resistant to light in the visible light wavelength range. It shall be translucent.

[0188] A first electrode layer and a second electrode layer (a pixel electrode layer, a common electrode layer, a pair of electrodes) that apply a voltage to the display element In the case of a light-emitting diode (also called a counter electrode layer), the direction of the light to be extracted, the location of the electrode layer, and The light transmission property or reflectivity can be selected depending on the pattern structure of the electrode layer.

[0189] The first electrode layer 4030 and the second electrode layer 4031 are made of an indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide (ITO), indium tin oxide containing titanium oxide Transparent materials such as zinc oxide, silicon oxide-doped indium tin oxide, and graphene Any conductive material can be used.

[0190] The first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W) and molybdenum. (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (N b), Tantalum (Ta), Chromium (Cr), Cobalt (Co), Nickel (Ni), Titanium Metals such as titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag), It can be formed by using one or more of the metals, alloys thereof, or metal nitrides thereof. Cut.

[0191] The first electrode layer 4030 and the second electrode layer 4031 are made of a conductive polymer (conductive polymer). The conductive polymer can be formed using a conductive composition containing a conductive polymer. For example, a so-called π-electron conjugated conductive polymer can be used. or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or or a copolymer consisting of two or more of aniline, pyrrole and thiophene, or a derivative thereof Conductors and the like are examples.

[0192] A protection circuit for protecting the drive circuit may be provided. The protection circuit is configured using a nonlinear element. It is preferable to do so.

[0193] As described above, by applying the transistors exemplified in the first and second embodiments, various Therefore, a semiconductor device having such functions can be provided.

[0194] (Fourth embodiment) The transistor exemplified in the first or second embodiment is used to read information of an object. A semiconductor device having an image sensor function can be manufactured.

[0195] FIG. 8A shows an example of a semiconductor device having an image sensor function. 8(A) is an equivalent circuit of the photosensor, and FIG. 8(B) is a cross-sectional view showing a part of the photosensor.

[0196] The photodiode 602 has one electrode connected to a photodiode reset signal line 658 and the other One electrode is electrically connected to the gate of transistor 640. One of the source and drain is connected to the photosensor reference signal line 672, and the other of the source and drain is connected to the photosensor reference signal line 673. The other terminal is electrically connected to one of the source and drain terminals of the transistor 656. The transistor 656 has a gate connected to a gate signal line 659 and a source or drain connected to a photodiode. The signal line 671 is electrically connected to the sensor output signal line 671.

[0197] Note that in the circuit diagrams in this specification, a transistor using a crystalline oxide semiconductor layer To make it clear, the symbol for a transistor using a crystalline oxide semiconductor layer is "OS In FIG. 8A, the transistor 640 and the transistor 656 are The transistor exemplified in the first or second embodiment can be applied, and a crystalline oxide semiconductor layer is used. In this embodiment, the transistor 520 shown in Embodiment 2 is An example in which a transistor having a similar structure to that shown in FIG.

[0198] FIG. 8B shows the photodiode 602 and the transistor 640 in the photosensor. 6 is a cross-sectional view showing a substrate 601 (TFT substrate) having an insulating surface, on which a sensor functioning as a sensor is formed. A photodiode 602 and a transistor 640 are provided. A substrate 613 is provided on the board 602 and the transistor 640 using an adhesive layer 608. do.

[0199] On the transistor 640, an insulating layer 631, an insulating layer 632, an interlayer insulating film 633, and an interlayer insulating film The photodiode 602 is provided on the interlayer insulating film 633. An electrode layer 641 formed on the interlayer insulating film 633 and an electrode layer provided on the interlayer insulating film 634 642, a first semiconductor film 606a and a second semiconductor film 606b are formed between the first semiconductor film 606a and the second semiconductor film 606b in this order from the interlayer insulating film 633 side. 6b and a third semiconductor film 606c are stacked.

[0200] The electrode layer 641 is electrically connected to a conductive layer 643 formed on the interlayer insulating film 634. 642 is electrically connected to the conductive layer 645 via the electrode layer 641. The conductive layer 645 is The photodiode 602 is electrically connected to the gate electrode of the transistor 640. It is electrically connected to the transistor 640 .

[0201] Here, the first semiconductor film 606a is a semiconductor film having a p-type conductivity, and the second semiconductor film 606b is a high resistance semiconductor film (i-type semiconductor film), and the third semiconductor film 606c is an n-type A pin-type photodiode in which semiconductor films having different conductivity types are stacked is shown as an example.

[0202] The first semiconductor film 606a is a p-type semiconductor film, and is an amorphous film containing an impurity element that imparts p-type. The first semiconductor film 606a can be formed from a group 13 silicon film. Using semiconductor material gas containing impurity elements (e.g., boron (B)), plasma CVD is used. Silane (SiH4) can be used as the semiconductor material gas. Alternatively, i2H6, SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. may be used. In addition, after forming an amorphous silicon film that does not contain impurity elements, the film is formed by diffusion or ion implantation. Impurity elements may be introduced into the amorphous silicon film by using a method such as ion implantation. It is preferable to diffuse the impurity element by heating or the like after introducing the impurity element. In this case, the amorphous silicon film can be formed by LPCVD, vapor phase growth, Alternatively, sputtering or the like may be used. The thickness of the first semiconductor film 606a is 10 nm or more and 5 nm or less. It is preferable to form it so that the thickness is 0 nm or less.

[0203] The second semiconductor film 606b is an i-type semiconductor film (intrinsic semiconductor film) and is made of amorphous silicon. The second semiconductor film 606b is formed by amorphous silicon using a semiconductor material gas. A thick silicon film is formed by plasma CVD. The semiconductor material gas is silane. (SiH4) can be used. Alternatively, Si2H6, SiH2Cl2, SiHCl3, S The second semiconductor film 606b may be formed by LPCVD. The second semiconductor film 606b may be formed by vapor deposition, sputtering, or the like. It is preferable to form the film so that the thickness is 00 nm or more and 1000 nm or less.

[0204] The third semiconductor film 606c is an n-type semiconductor film and is an amorphous film containing an impurity element that imparts n-type. The third semiconductor film 606c is formed of a thick silicon film. It is formed by the plasma CVD method using a semiconductor material gas containing silicon (e.g., phosphorus (P)). Silane (SiH4) can be used as the semiconductor material gas. SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. may also be used. After forming an amorphous silicon film that does not contain elements, the film is then doped with silicon using diffusion or ion implantation. An impurity element may be introduced into the amorphous silicon film by ion implantation or the like. After the element is introduced, the impurity element may be diffused by heating or the like. The amorphous silicon film can be formed by LPCVD, vapor phase growth, or sputtering. The thickness of the third semiconductor film 606c is 20 nm or more and 200 nm or less. It is preferable to form it so that it faces downward.

[0205] The first semiconductor film 606a, the second semiconductor film 606b, and the third semiconductor film 606c are Instead of an amorphous semiconductor, it may be formed using a polycrystalline semiconductor, or a microcrystalline (semi-amorphous) semiconductor. Rufus (Semi Amorphous Semiconductor: SAS) Semiconductor It may also be formed using a conductor.

[0206] Considering the Gibbs free energy, microcrystalline semiconductors are metastable, intermediate between amorphous and single crystal. In other words, it is a semiconductor with a thermodynamically stable third state. The columnar or needle-like crystals are aligned in the normal direction to the substrate surface. Microcrystalline silicon, a typical example of a microcrystalline semiconductor, has a Raman spectrum The curve shows single-crystal silicon at 520 cm -1 It is shifted to the lower wavenumber side than 520cm indicates crystalline silicon -1 and 480 cm, which indicates amorphous silicon -1 Between There is a peak in the Raman spectrum of microcrystalline silicon. It contains at least 1 atomic % or more of hydrogen or halogen to terminate the Furthermore, rare gas elements such as helium, argon, krypton, and neon are added to form a lattice. By further promoting the strain, stability is increased and a favorable microcrystalline semiconductor film can be obtained.

[0207] This microcrystalline semiconductor film is formed by a high-frequency plasma CVD method with a frequency of several tens to several hundreds of MHz, or Alternatively, it can be formed by a microwave plasma CVD device with a frequency of 1 GHz or more. Representative examples include SiH4, Si2H6, SiH2Cl2, SiHCl3, SiCl4, and S It can be formed by diluting silicon-containing compounds such as iF4 with hydrogen. One or more rare gas elements selected from the group consisting of helium, argon, krypton, and neon A microcrystalline semiconductor film can be formed by diluting silicon hydride with silicon. The flow rate ratio of hydrogen to a compound containing silicon (for example, silicon hydride) is preferably 5 times or more and 200 times or less. Preferably, the ratio is 50 to 150 times, and more preferably 100 times. The gas contains hydrocarbon gases such as CH4 and C2H6, germanium gases such as GeH4 and GeF4. A fluorinated gas, F2, etc. may be mixed in.

[0208] In addition, the mobility of holes generated by the photoelectric effect is smaller than that of electrons, so the pin-type The photodiode exhibits better characteristics when the p-type semiconductor film side is used as the light receiving surface. From the surface of the substrate 601 on which the in-type photodiode is formed to the photodiode 602 This shows an example of converting the light received by the semiconductor film into an electrical signal. Since light from the semiconductor film side having a pattern becomes disturbance light, a conductive film with light blocking properties is used for the electrode layer. It is also possible to use the n-type semiconductor film side as the light-receiving surface.

[0209] The insulating layer 632, the interlayer insulating film 633, and the interlayer insulating film 634 are made of insulating materials. Depending on the material, sputtering, plasma CVD, SOG, spin coating, Spray coating, droplet ejection method (inkjet method, etc.), printing method (screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater It can be formed using a material such as a silicon dioxide particle.

[0210] In this embodiment, an aluminum oxide film is used as the insulating layer 631. It can be formed by sputtering or plasma CVD.

[0211] The aluminum oxide film provided as the insulating layer 631 over the crystalline oxide semiconductor layer is resistant to hydrogen, A blocking effect that prevents impurities such as water and oxygen from passing through the membrane is high.

[0212] Therefore, the aluminum oxide film is free from hydrogen, which is a factor of fluctuation during and after the manufacturing process. The inclusion of impurities such as moisture in the crystalline oxide semiconductor layer and the inclusion of the main component constituting the oxide semiconductor The oxide semiconductor layer functions as a protective film for preventing oxygen, which is a material, from being released from the crystalline oxide semiconductor layer.

[0213] The insulating layer 632 may be made of an inorganic insulating material such as a silicon oxide layer, a silicon oxynitride layer, An oxide insulating layer such as an aluminum oxide layer or an aluminum oxynitride layer, or a silicon nitride layer , a nitride such as a silicon nitride oxide layer, an aluminum nitride layer, or an aluminum nitride oxide layer A single layer or a stack of insulating layers can be used.

[0214] The interlayer insulating films 633 and 634 function as planarizing insulating layers to reduce surface irregularities. The interlayer insulating films 633 and 634 are preferably made of, for example, polyimide or acrylic. Heat-resistant organic insulating materials such as resin, benzocyclobutene resin, polyamide, and epoxy resin In addition to the above organic insulating materials, siloxane resins, PSG, etc. Low-k materials such as phosphate glass (BPSG) and boron phosphorus glass (BPSG) A single layer or a laminate can be used.

[0215] By detecting the light incident on the photodiode 602, information on the detected object is read. It is possible to read the information of the detected object using a light source such as a backlight. It is possible.

[0216] As in the transistors exemplified in the first and second embodiments, the channel A transistor having crystalline oxide semiconductor layers including a low-resistance region sandwiching a formation region is High characteristics (e.g., on-current and field-effect mobility) enable high-speed operation and high-speed response Furthermore, miniaturization can be achieved. Therefore, the use of this transistor will result in high performance and high reliability. Therefore, a highly reliable semiconductor device can be provided.

[0217] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0218] (Embodiment 5) The transistor exemplified in the first or second embodiment is an integrated transistor in which a plurality of transistors are stacked. The present invention can be suitably applied to a semiconductor device having an integrated circuit. As an example, a storage medium (memory element) will be shown.

[0219] In the embodiment, a transistor that is a first transistor manufactured on a single crystal semiconductor substrate 140 and a second transistor formed using a semiconductor film above the transistor 140 via an insulating layer. A semiconductor device including the transistor 162 is manufactured. The transistor 162 may be suitably used as an example of the transistor 2. In this embodiment, the transistor 162 is the transistor 520 shown in Embodiment 2. An example using a transistor having a similar structure to that shown in FIG.

[0220] The semiconductor materials and structures of the stacked transistors 140 and 162 may be the same. In this embodiment, a suitable circuit for a storage medium (memory element) is These are examples using transistors of different materials and structures.

[0221] FIG. 9 shows an example of the configuration of a semiconductor device. FIG. 9(A) shows a cross section of the semiconductor device, and FIG. 9(A) shows a plan view of the semiconductor device. 9(C) corresponds to the cross section taken along lines 1-C2 and D1-D2. An example of a circuit diagram when the device is used as a memory element is shown in Figures 9(A) and 9(B). The semiconductor device shown in FIG. 1 has a transistor 140 using a first semiconductor material in the lower part, A transistor 162 using the second semiconductor material is provided in the upper portion. The first semiconductor material is a semiconductor material other than an oxide semiconductor, and the second semiconductor material is an oxide semiconductor. Examples of semiconductor materials other than oxide semiconductors include silicon, germanium, and silicon dioxide. Congenerium germanium, silicon carbide, or gallium arsenide can be used. It is preferable to use a conductor. Alternatively, an organic semiconductor material may be used. Transistors using oxide semiconductor materials can easily operate at high speeds. The transistor's characteristics allow it to retain charge for a long period of time.

[0222] A method for manufacturing the semiconductor device in FIG. 9 will be described with reference to FIGS.

[0223] The transistor 140 is disposed on a substrate 185 that includes a semiconductor material (e.g., silicon). The channel forming region 116 is formed by doping the impurity ions 116. A region 120, a metal compound region 124 in contact with the impurity region 120, and a channel forming region 1 A gate insulating layer 108 is provided on the gate insulating layer 108. The electrode 110 is a ferroelectric material.

[0224] The substrate 185 containing the semiconductor material may be a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, or a The substrates used include crystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, and SOI substrates. Generally, an "SOI substrate" is a substrate in which a silicon semiconductor film is provided on an insulating surface. However, in this specification, it refers to a substrate having a structure in which a material other than silicon is formed on an insulating surface. In other words, the semiconductor film of the "SOI substrate" The film is not limited to a silicon semiconductor film. In addition, the SOI substrate can be made of an insulating material such as a glass substrate. The term "semiconductor film" includes a structure in which a semiconductor film is provided on a substrate via an insulating layer.

[0225] The SOI substrate is fabricated by implanting oxygen ions into a mirror-polished wafer and then heating it at high temperature. By doing so, an oxide layer is formed at a certain depth from the surface, and the cracks that have occurred in the surface layer are removed. a method for eliminating microvoids formed by hydrogen ion irradiation and a method for forming microvoids by heat treatment A method of cleaving a semiconductor substrate by using a length, or a method of forming a single crystal semiconductor film by crystal growth on an insulating surface. A method for forming the above-mentioned film or the like can be used.

[0226] For example, ions are added from one surface of a single crystal semiconductor substrate to form a single crystal semiconductor substrate. A weakened layer is formed at a certain depth from the surface of the single crystal semiconductor substrate, and the single crystal semiconductor substrate is An insulating layer is formed on either one of the single crystal semiconductor substrate and the element substrate. While the substrates are stacked together, a crack is generated in the weakened layer, and the single crystal semiconductor substrate is separated at the weakened layer. A heat treatment is performed to form a single crystal semiconductor film on the element substrate as a semiconductor film from the single crystal semiconductor substrate. The SOI substrate manufactured by the above method can also be suitably used.

[0227] An element isolation insulating layer 106 is provided on the substrate 185 so as to surround the transistor 140. In order to achieve high integration, the transistor 140 is It is desirable to have a structure that does not have a sidewall insulating layer that becomes a wall. When the characteristics of 140 are important, a sidewall is formed on the side of the gate electrode 110. An insulating layer may be provided to provide impurity regions 120 including regions with different impurity concentrations.

[0228] The transistor 140 using a single crystal semiconductor substrate can operate at high speed. By using this transistor as a readout transistor, it is possible to read out information at high speed. Two insulating layers are formed to cover the transistor 140. As a process before forming the capacitor 162 and the capacitor element 164, the two insulating layers are subjected to CMP. Then, planarized insulating layers 128 and 130 are formed, and at the same time, the upper surface of the gate electrode 110 is Expose.

[0229] The insulating layer 128 and the insulating layer 130 are typically made of a silicon oxide film, a silicon oxynitride film, or an oxide Aluminum film, aluminum oxynitride film, silicon nitride film, aluminum nitride film, nitride An inorganic insulating layer such as a silicon oxide film or an aluminum nitride oxide film can be used. The layer 128 and the insulating layer 130 are formed by using a plasma CVD method, a sputtering method, or the like. It is possible.

[0230] In addition, organic materials such as polyimide, acrylic resin, and benzocyclobutene resin can be used. In addition to the above organic materials, low-dielectric-constant materials (low-k materials) can also be used. When organic materials are used, the insulating layer can be formed by wet methods such as spin coating and printing. 128, an insulating layer 130 may be formed.

[0231] Note that in the insulating layer 130, a silicon oxide film is used as a film in contact with the semiconductor film.

[0232] In this embodiment, the insulating layer 128 is formed by sputtering an oxynitride film having a thickness of 50 nm. A silicon film is formed, and an oxide film having a thickness of 550 nm is formed by sputtering as the insulating layer 130. A silicon film is formed.

[0233] A semiconductor film is formed on the insulating layer 130 that has been sufficiently planarized by CMP processing. In this study, we used an In-Ga-Zn oxide target as a semiconductor film and sputtered it. A more crystalline oxide semiconductor layer is formed.

[0234] Next, the crystalline oxide semiconductor layer is selectively etched to form an island-shaped crystalline oxide semiconductor layer 144 A source electrode or drain electrode 142a, a gate electrode 142b, and a gate electrode 142c are formed on the crystalline oxide semiconductor layer 144. The source or drain electrode 142b is formed.

[0235] A gate insulating layer 146 and a gate electrode 148 are formed on the crystalline oxide semiconductor layer 144. The port electrode 148 is formed by forming a conductive layer and then selectively etching the conductive layer. The gate insulating layer 146 can be formed by insulating the gate electrode 148 using the gate electrode 148 as a mask. The edge layer is formed by etching.

[0236] The gate insulating layer 146 is formed by depositing an oxide silicon dioxide film using a plasma CVD method, a sputtering method, or the like. Silicon film, silicon nitride film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide Aluminum film, aluminum nitride film, aluminum oxynitride film, aluminum nitride oxide film, aluminum oxide film A gallium oxide film or a gallium oxide film can be formed.

[0237] Gate electrode 110, source or drain electrode 142a, source or drain electrode The conductive layer that can be used for the electrode 142b can be formed by a PVD method such as a sputtering method. The conductive layer can be formed by a CVD method such as a plasma CVD method. The materials include elements selected from Al, Cr, Cu, Ta, Ti, Mo, and W, as well as the above-mentioned elements. Alloys containing elements such as Mn, Mg, Zr, Be, Nd, and Sc can be used. Any one of these materials or a combination of two or more of these materials may be used.

[0238] The conductive layer may have a single layer structure or a laminated structure of two or more layers. single-layer structure of silicon film or titanium nitride film, single-layer structure of aluminum film containing silicon, Two-layer structure with titanium film laminated on titanium nitride film, two-layer structure with titanium film laminated on titanium nitride film Examples include a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated. In addition, when the conductive layer has a single layer structure of a titanium film or a titanium nitride film, a tapered shape is The source or drain electrode 142a and the source or drain electrode 142 It has the advantage of being easy to process into b.

[0239] After forming the gate electrode 148, the gate insulating layer is etched using the gate electrode 148 as a mask. Then, the crystalline oxide semiconductor layer 144 exposed by the etching treatment is subjected to nitridation plasma treatment. This results in a crystalline low-resistance region containing nitrogen sandwiching the channel formation region. Therefore, the transistor 162 including the crystalline oxide semiconductor layer 144 can be manufactured.

[0240] A crystalline oxide semiconductor layer 14 including a low resistance region sandwiching a channel formation region in the channel length direction. 4, the transistor 162 has on-characteristics (e.g., on-current and field effect The high photon mobility (PEM) enables high-speed operation and high-speed response.

[0241] The low resistance region can function as a source region or a drain region. By providing the low-resistance region, the electric field applied to the channel forming region formed between the low-resistance regions is reduced. In addition, the crystalline oxide semiconductor layer 144 and the source The source or drain electrode 142a and the source or drain electrode 142b are electrically connected to each other. By electrically connecting the crystalline oxide semiconductor layer 144 and the source electrode or the drain electrode, The contact resistance between the source electrode 142a and the drain electrode 142b is reduced. It is possible.

[0242] An insulating layer 150 is provided over the crystalline oxide semiconductor layer 144. The insulating layer 150 has a stacked structure. The insulating layer 150 may be formed by plasma CVD or sputtering. Silicon oxide film, silicon nitride film, silicon oxynitride film, silicon nitride oxide film, nitride aluminum nitride film, aluminum oxide film, aluminum oxynitride film, aluminum oxide nitride film A hafnium oxide film, a hafnium oxide film, or a gallium oxide film can be used.

[0243] In this embodiment, an aluminum oxide film is used as the insulating layer 150. The aluminum film is a barrier that prevents impurities such as hydrogen and moisture, as well as oxygen, from passing through the film. Therefore, the aluminum oxide film has a high blocking effect during and after the manufacturing process. In this case, impurities such as hydrogen and moisture, which are factors of fluctuation, are mixed into the crystalline oxide semiconductor layer 144. The oxide semiconductor layer 144 is made of oxygen, which is a main component material of the oxide semiconductor. It acts as a protective film to prevent the release of these substances.

[0244] On the insulating layer 150, an electrode is formed in a region overlapping with the source electrode or drain electrode 142a. A layer 153 is formed.

[0245] Next, the insulating layer 152 is formed over the transistor 162 and the insulating layer 150. The layer 2 can be formed by sputtering or CVD. Inorganic insulators such as silicon oxide nitride, silicon nitride, hafnium oxide, and aluminum oxide It can be made using materials including edging materials.

[0246] Next, a source electrode or a drain electrode is formed on the gate insulating layer 146, the insulating layer 150, and the insulating layer 152. An opening is formed that reaches the inner electrode 142b. The opening is formed using a mask or the like. This is done by selective etching.

[0247] Thereafter, a wiring 156 that contacts the source electrode or drain electrode 142b is formed in the opening. In addition, in FIG. 9, the connection point between the source electrode or drain electrode 142b and the wiring 156 is Not shown.

[0248] The wiring 156 is formed by a PVD method such as a sputtering method, or a C method such as a plasma CVD method. After forming a conductive layer using the VD method, the conductive layer is etched to form The material of the conductive layer is selected from Al, Cr, Cu, Ta, Ti, Mo, and W. The elements mentioned above and alloys containing the elements mentioned above can be used. Any one of R, Be, Nd, and Sc, or a combination of these materials may be used. The details are similar to those of the source electrode or drain electrode 142a.

[0249] Through the above steps, the transistor 162 and the capacitor 164 are completed. The crystalline oxide semiconductor layer 144 is highly purified and contains excess oxygen to compensate for oxygen vacancies. Therefore, the transistor 162 has suppressed fluctuations in electrical characteristics. The capacitor 164 is electrically stable. The gate insulating layer 146 is made up of a crystalline oxide semiconductor layer 144, an electrode layer 153, and a gate insulating layer 146. .

[0250] In the capacitor 164 in FIG. 9A, the crystalline oxide semiconductor layer 144 and the gate insulating layer 1 46 are stacked to form a source or drain electrode 142a and an electrode layer 153 Of course, in order to ensure sufficient capacitance, Alternatively, the capacitor 164 may not include the crystalline oxide semiconductor layer 144. Alternatively, a capacitor 164 having an insulating layer may be used. Alternatively, the capacitor 164 may not be provided.

[0251] FIG. 9C shows an example of a circuit diagram in the case where the semiconductor device is used as a memory element. In FIG. 9C, one of the source electrode and the drain electrode of the transistor 162 and the capacitor One of the electrodes of the capacitor 164 is electrically connected to the gate electrode of the transistor 140. In addition, the first wiring (also called the source line) and the transistor 14 The source electrode of bit line 0 is electrically connected to the second wiring (2nd Line: also called bit line). The third electrode (called the drain electrode) of the transistor 140 is electrically connected to the drain electrode of the transistor 140. (also called the 3rd Line: first signal line) and the source electrode of the transistor 162. The other of the drain electrodes is electrically connected to a fourth wiring (4th Line). The second signal line and the gate electrode of the transistor 162 are electrically connected to each other. Then, a fifth wiring (also called a word line) and the capacitor element 164 The other electrode is electrically connected.

[0252] The transistor 162 including an oxide semiconductor has an extremely low off-state current. Therefore, by turning off the transistor 162, the source of the transistor 162 One of the electrodes or drain electrodes of the capacitor 164 and the transistor 140 The potential of the node (hereinafter referred to as node FG) electrically connected to the gate electrode of Furthermore, by having the capacitance element 164, This makes it easier to retain the charge given to the gate FG and to read out the retained information. becomes.

[0253] When storing (writing) information in the semiconductor device, first, the potential of the fourth wiring is set to This sets the potential at which the transistor 162 is turned on, turning the transistor 162 on. As a result, the potential of the third wiring is supplied to the node FG, and a predetermined amount of charge is accumulated in the node FG. Here, the charges that give two different potential levels (hereinafter referred to as low level Either a charge or a high level charge is given. The potential of the fourth wiring is set to a potential that turns off the transistor 162. By turning off 162, node FG is in a floating state, so As described above, a predetermined amount of charge is stored in the node FG. By storing and holding information, the memory cell can store information.

[0254] Since the off-state current of the transistor 162 is extremely small, the charge supplied to the node FG is retained for a long time. Therefore, no refresh operation is required or the data is retained for a certain period of time. It is possible to reduce the frequency of cleaning operations extremely, and power consumption can be reduced significantly. In addition, even if there is no power supply, the memory contents can be retained for a long period of time. It is possible.

[0255] When reading out the stored information (reading), a predetermined potential (constant potential) is applied to the first wiring. In this state, when an appropriate potential (read potential) is applied to the fifth wiring, the potential is held at the node FG. Depending on the amount of charge transferred, transistor 140 assumes different states. If 40 is an n-channel type, when a high level charge is held at node FG, The apparent threshold voltage V of transistor 140 th_H A low-level charge is applied to node FG. The apparent threshold voltage V of transistor 140 when held th_L It became lower Here, the apparent threshold is the voltage at which the transistor 140 is turned on. Therefore, the potential of the fifth wiring is V th _H and V th_L By setting the potential V0 between For example, if a high level charge is applied during writing, The potential of the wire 5 is V0 (> V th_H ), transistor 140 is in the "on state" When a low level charge is applied, the potential of the fifth wire becomes V0( <V th _L ), transistor 140 remains in the "off state." The potential of the wiring is controlled to read out the on / off state of the transistor 140 (second The stored information can be read out by reading out the potential of the wiring.

[0256] When the stored information is rewritten, a predetermined amount of electricity is consumed by the rewriting. By supplying a new potential to node FG, which holds the load, node FG is connected to the new information. Specifically, the potential of the fourth wiring is set to a value corresponding to the potential of the fourth wiring when the transistor 162 is turned on. This turns on the transistor 162. A potential (potential related to new information) is supplied to node FG, and a predetermined amount of charge is accumulated in node FG. After that, the potential of the fourth wiring is set to a potential that turns off the transistor 162. By turning off the transistor 162, the node FG receives the new information. That is, a predetermined amount of charge is stored in the node FG by the first write. While the charge is held, the same operation as the first write (second write) is performed. , it is possible to overwrite the stored information.

[0257] The transistor 162 described in this embodiment is a highly purified, oxygen-free transistor disclosed in this specification. By using a crystalline oxide semiconductor layer containing an excess amount of ZnO, the off-state current of the transistor 162 can be reduced sufficiently. By using such a transistor, it is possible to reduce the Thus, a semiconductor device capable of retaining stored contents for a long period of time can be obtained.

[0258] As described above, the crystalline oxide layer including the low resistance region sandwiching the channel formation region in the channel length direction is A transistor having a compound semiconductor layer has a low off-current and low on-current characteristics (for example, on-current and It has high field-effect mobility, enabling high-speed operation and high-speed response. It can also be miniaturized. Therefore, by using the transistor, a high-performance and highly reliable semiconductor device can be provided. This can be done.

[0259] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0260] (Embodiment 6) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras cameras, digital photo frames, mobile phones (also called mobile phones or mobile phone devices), ), portable game machines, personal digital assistants, audio playback devices, large game machines such as pachinko machines, etc. Examples of electronic devices including the semiconductor device described in the above embodiment will be described. Reveal.

[0261] FIG. 10A shows a notebook personal computer, which includes a main body 3001 and a housing 300 2, a display unit 3003, a keyboard 3004, etc. By applying the semiconductor device shown in FIG. 3 to the display portion 3003, a high performance and highly reliable display can be obtained. The computer may be a portable personal computer.

[0262] FIG. 10B shows a personal digital assistant (PDA), which has a main body 3021 including a display unit 3023 and a An external interface 3025 and operation buttons 3024 are provided. The semiconductor device shown in any of the above embodiments has a stylus 3022 as an accessory. By applying the device to the display unit 3023, a more high performance and highly reliable portable information terminal (P DA).

[0263] FIG. 10C shows an example of an electronic book. For example, the electronic book has a housing 2701 and The housing 2701 and the housing 2703 are made up of two housings. The opening and closing operation can be performed with the shaft portion 2711 as an axis. This configuration allows the device to function like a paper book.

[0264] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display unit (display unit 2705 in FIG. 10C), and An image can be displayed on the display unit (display unit 2707 in FIG. 10C). The semiconductor device shown in any one of the embodiments is applied to the display portion 2705 and the display portion 2707. The display unit 2705 can be a semi-transparent display unit. When using a reflective or reflection type LCD display, it is expected that it will be used in relatively bright conditions. Therefore, a solar cell is installed to generate electricity and charge the battery. It is also possible to use a lithium-ion battery as the battery, as this allows for miniaturization. There are advantages to this.

[0265] FIG. 10C shows an example in which an operation unit and the like are provided in the housing 2701. For example, The housing 2701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The back of the housing may be provided with a keyboard, a pointing device, etc. On the front and sides, there are external connection terminals (earphone terminal, USB terminal, etc.), a recording medium insertion port, etc. Furthermore, the electronic book may be configured to have a function as an electronic dictionary. You may do so.

[0266] The electronic book may also be configured to be capable of transmitting and receiving information wirelessly. It is also possible to purchase and download desired book data from the server. be.

[0267] FIG. 10(D) shows a mobile phone, which is composed of two housings, a housing 2800 and a housing 2801. The housing 2801 contains a display panel 2802, a speaker 2803, a microphone, and 2804, pointing device 2806, camera lens 2807, external connection terminal 2 808, etc. The housing 2800 also includes a solar cell for charging the mobile phone. 2810, an external memory slot 2811, etc. The antenna is mounted on the housing 280 The semiconductor device described in any of the above embodiments is built in the display panel 2. By applying this technology to 802, a high performance and highly reliable mobile phone can be achieved.

[0268] The display panel 2802 is equipped with a touch panel, and the image displayed in FIG. The multiple operation keys 2805 are indicated by dotted lines. It also has a boost circuit to boost the voltage required for each circuit.

[0269] The display direction of the display panel 2802 changes appropriately depending on the usage mode. The camera lens 2807 is located on the same surface as the camera lens 2802, so video calls are possible. The speaker 2803 and microphone 2804 are not limited to voice calls, but can also be used for video calls, recording, etc. Furthermore, the housing 2800 and the housing 2801 can be slid to each other, and the housing 2800 and the housing 2801 can be slid to each other. It can be folded from the unfolded state shown in 0(D) to the overlapped state, making it suitable for carrying. It is possible to make the device smaller.

[0270] The external connection terminal 2808 can be connected to various cables such as AC adapters and USB cables. It is possible to charge the battery and to communicate data with a personal computer, etc. By inserting a recording medium into the memory slot 2811, it is possible to store and transfer a larger amount of data. do.

[0271] In addition to the above functions, even if the device has infrared communication function, TV reception function, etc. good.

[0272] FIG. 10(E) shows a digital video camera, which includes a main body 3051, a display unit (A) 3057, Eyepiece 3053, operation switch 3054, display unit (B) 3055, battery 3056, etc. The semiconductor device described in any of the above embodiments is configured by a display portion (A By applying it to the display part (B) 3055, high performance and high reliability digital It can be a portable video camera.

[0273] FIG. 10(F) shows an example of a television device. The television device 9600 includes: A display unit 9603 is incorporated in a housing 9601. The display unit 9603 displays images. In this case, the housing 9601 is supported by a stand 9605. The semiconductor device described in any of the above embodiments is provided in the display portion 9603. By applying this, a high-performance and highly reliable television device 9600 can be obtained. do.

[0274] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by a remote control operator. A display unit for displaying the output information may be provided.

[0275] The television device 9600 is configured to include a receiver, a modem, and the like. It can receive more general TV broadcasts and can also receive them via wired or wireless modems. By connecting to a communication network, it can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0276] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is. [Example]

[0277] In this example, the measurement results of the sheet resistance of the crystalline oxide semiconductor layer subjected to nitrogen plasma treatment were The evaluation results of the crystallinity and the crystallinity are shown using comparative examples.

[0278] Methods for producing Example Sample 1, Comparative Sample 1, Example Sample 2, and Comparative Sample 2 produced in this example is shown below.

[0279] As a sample for this example, a silicon oxide film was formed on a glass substrate by sputtering to a thickness of 3 mm. The silicon oxide film surface is flattened by reverse sputtering. After the treatment, an In-Ga-Zn-O film was formed to a thickness of 20 nm on the silicon oxide film, and then heat treatment was performed. Comparative Sample 1 was prepared by this heat treatment, and Example Sample 1 was prepared by nitrogen plasma treatment after the heat treatment. In addition, in the comparative sample 1, the planarization process was performed using the CMP method instead of the reverse sputtering method. Comparative sample 2 was then subjected to nitrogen plasma treatment. Example Sample 2 was prepared.

[0280] In Example Sample 1, Example Sample 2, Comparative Sample 1, and Comparative Sample 2, the formation of the silicon oxide film The film conditions were as follows: a silicon oxide (SiO2) target was used as the target, and the glass substrate was The distance between the targets was 60 mm, the pressure was 0.4 Pa, the RF power was 1.5 kW, and argon and Oxygen (argon flow rate 25sccm: oxygen flow rate 25sccm) atmosphere, substrate temperature 100℃ It was decided.

[0281] In addition, in Example Sample 1, Example Sample 2, Comparative Sample 1, and Comparative Sample 2, In-Ga- The deposition conditions for the Zn-O film were as follows: composition ratio: In2O3:Ga2O3:ZnO=1:1:2[ The oxide target was set at a 60 mm distance between the glass substrate and the target. , pressure 0.4 Pa, RF power 0.5 kW, argon and oxygen (argon flow rate 30 sccm The substrate temperature was set to 300°C under an atmosphere of oxygen (oxygen flow rate 15 sccm).

[0282] In addition, Example Sample 1, Example Sample 2, Comparative Sample 1, and Comparative Sample 2 are In—Ga—Zn— After forming the O film, a heat treatment was performed at 450°C for 1 hour in a nitrogen atmosphere to perform dehydration or dehydrogenation treatment. After this, dehydration or dehydrogenation is carried out by introducing high purity oxygen gas into the same furnace. The main components that make up the oxide semiconductor are also reduced by the process of removing impurities through the process. The oxygen, which is the chemical material, was supplied.

[0283] The conditions for the planarization process for Example Sample 1 and Comparative Sample 1 were: argon flow rate 50 sccm; The pressure was 0.6 Pa, the power was 200 W, and the treatment was carried out by reverse sputtering for 10 minutes. In Example Sample 1 and Comparative Sample 1, the formation of a silicon oxide film, reverse sputtering, and In The -Ga-Zn-O film was formed continuously without exposure to the atmosphere.

[0284] The flattening conditions for Example Sample 2 and Comparative Sample 2 were as follows: the slurry temperature was room temperature; The glass substrate was rotated at 60 rpm, the polishing cloth at 56 rpm, and the polishing pressure was 0.001 MPa. The silicon oxide film was polished by 30 nm by this CMP treatment. and flattened the surface.

[0285] In Example Sample 1 and Example Sample 2, the In-Ga-Zn-O film after the heat treatment had a high density. The high-density plasma treatment was carried out by nitriding using argon and nitrogen (argon flow). Amount of 1000sccm: nitrogen flow rate 500sccm) atmosphere, substrate temperature 450℃, reaction pressure 6 Pa, microwave power output 3000 W, microwave frequency 2.45 GHz, 300 Processed in seconds.

[0286] The sheets of Example Sample 1, Comparative Sample 1, Example Sample 2, and Comparative Sample 2 obtained by the above steps were The resistance was measured at five locations on each sample. The results are shown in Figure 11. For the measurement, a resistivity measuring device (product name: Σ-10) manufactured by NPS Corporation was used.

[0287] As shown in FIG. 11, the sheets of Comparative Sample 1 and Comparative Sample 2, which were not subjected to nitriding plasma treatment, The resistance values ​​are both within the measurement limit of the resistivity meter (5.0 x 10 6 Ω / □) or more. On the other hand, the average sheet resistance of Example Sample 1, which was subjected to nitriding plasma treatment, was 1.4 × 10 5 Ω / □, and the average sheet resistance of Example Sample 2 was 2.4×10 5 About Ω / □ It was.

[0288] Therefore, by performing the nitriding plasma treatment, the sheet resistance of the oxide semiconductor layer is reduced. It was confirmed that the conductivity decreased, that is, the conductivity increased.

[0289] In addition, in Example Sample 1, Comparative Sample 1, Example Sample 2, and Comparative Sample 2, In-Ga- The Zn-O film was subjected to X-ray diffraction (XRD) measurement. The results of measuring the XRD spectrum using the out-of-plane method are shown in FIG. FIG. 12(A) shows the results of measuring the XRD spectra of Example Sample 1 and Comparative Sample 1. 12(B) shows the results of measuring the XRD spectra of Example Sample 2 and Comparative Sample 2. In 2, the vertical axis is the X-ray diffraction intensity (arbitrary unit), and the horizontal axis is the rotation angle 2θ (deg.). The XRD spectrum was measured using a Bruker AXS X-ray diffractometer D8 ADVANCE was used.

[0290] From FIG. 12(A), in Example Sample 1, a peak derived from crystals was confirmed near 2θ=33 deg. 12(B), in Example Sample 2, a crystalline region was observed near 2θ=33 deg. The next peak was confirmed.

[0291] XRD measurements revealed that even if the oxide semiconductor layer had crystalline regions, the crystallinity was insufficient. However, from Figure 12, it can be seen that when nitrogen is not present, a clear peak may not be observed. In Example Sample 1 and Example Sample 2, which were subjected to the oxygen plasma treatment, the peaks derived from crystals were This confirms that nitriding plasma treatment is an effective treatment for improving crystallinity. Something has been shown. [Example]

[0292] In this example, the results of analyzing the composition of the surface of the crystalline oxide semiconductor layer that was subjected to nitrogen plasma treatment were , will be shown using a comparative example.

[0293] The methods for producing Example Sample 3, Example Sample 4, and Comparative Samples 3 to 5 in this example are as follows: show.

[0294] As a sample for this example, a silicon oxide film was formed on a glass substrate by sputtering to a thickness of 3 mm. A 2000 nm thick In-Ga-Zn-O film was then formed on the silicon oxide film. .

[0295] In the above, the conditions for forming the silicon oxide film are as follows: ) target, the distance between the glass substrate and the target was 60 mm, the pressure was 0.4 Pa, RF power supply 1.5 kW, argon and oxygen (argon flow rate 25 sccm: oxygen flow rate 25 sccm) The substrate temperature was 100°C under a 100°C (100°F) atmosphere.

[0296] The film formation conditions for the In-Ga-Zn-O film were as follows: In2O3:Ga2O3:Z Using an oxide target with a molar ratio of nO = 1:1:2, the glass substrate and the target were The distance between the electrodes was 60 mm, the pressure was 0.4 Pa, the RF power was 0.5 kW, and the pressure was 0.5 kW. The substrate temperature was set to 250°C in an atmosphere of nitrogen (flow rate: 30 sccm; oxygen (flow rate: 15 sccm)).

[0297] The deposited In-Ga-Zn-O film is nitrided using high-density plasma. The high-density plasma treatment was carried out using argon and Under a nitrogen atmosphere (argon flow rate 1000 sccm: nitrogen flow rate 200 sccm), reaction pressure 4 0 Pa, microwave power output 3000 W, microwave frequency 2.45 GHz, 300 In Example Sample 3, the substrate temperature was set to 350°C, and in Example Sample 4, The substrate temperature was set to 450°C.

[0298] In addition, instead of nitriding the formed In-Ga-Zn-O film, high-density plasma was used. Comparative Samples 3 and 4 were prepared by subjecting the sample to oxidation treatment. In the comparative sample 4, the high-density plasma treatment was performed with argon and oxygen (argon flow rate 900 scc m: nitrogen flow rate 5sccm) atmosphere, reaction pressure 106Pa, microwave power output 3800 The treatment was carried out for 300 seconds at a microwave frequency of 2.45 GHz. The substrate temperature was set to 350°C, and in Comparative Sample 4, the substrate temperature was set to 450°C.

[0299] In addition, a comparison test was conducted on a sample that was not subjected to plasma treatment for the formed In-Ga-Zn-O film. The fee was set at 5.

[0300] The In-Ga alloys of Example Sample 3, Example Sample 4, and Comparative Samples 3 to 5 obtained by the above steps were The composition of the Zn-O film surface was determined by X-ray photoelectron spectroscopy (XPS). The results were quantified and evaluated by ion spectroscopy (Ion Spectroscopy) analysis.

[0301] The results of the XPS analysis are shown in Table 1.

[0302] [Table 1]

[0303] From Table 1, the comparison sample 5 that was not plasma treated and the comparison sample 6 that was oxygen plasma treated were No significant difference was observed in the composition ratio of In-Ga-Zn-O between Sample 3 and Comparative Sample 4. On the other hand, in Example Samples 3 and 4, which were subjected to nitrogen plasma treatment, the composition ratios of Zn and The decrease in Ga and N and the increase in Ga and N were confirmed. This was more noticeable in Example Sample 4, which was subjected to the annealing treatment at a high temperature.

[0304] The spectrum obtained by XPS analysis is shown in Figure 13. In Figure 13, the horizontal axis is The vertical axis represents the N-1s bond energy, and the vertical axis represents the spectral intensity. The peak position is determined by the electronic state of the element, so the peak position depends on the bonding state. The N-1s XPS spectrum shown in Figure 13 allows us to confirm the bonding state of N. do.

[0305] As can be seen from FIG. 13, in Example Sample 3 and Example Sample 4 after the nitriding plasma treatment, the metal elements and nitrogen Peaks due to bonding with elements were confirmed. A stronger peak was observed in Example Sample 4.

[0306] From the above, by applying nitrogen plasma treatment to the In-Ga-Zn-O film, It was shown that the surface of the Ga-Zn-O film was nitrided. It was confirmed that the higher the temperature, the more the nitriding was promoted. [Explanation of symbols]

[0307] 106 Element isolation insulating layer 108 Gate insulating layer 110 gate electrode 116 Channel formation region 120 Impurity region 124 Metal compound area 128 Insulating Layer 130 Insulating layer 140 transistors 142a Drain electrode 142b Drain electrode 144 Crystalline oxide semiconductor layer 146 Gate insulating layer 148 gate electrode 150 insulating layer 152 Insulating layer 153 Electrode layer 156 Wiring 162 transistors 164 Capacitor 185 PCB 400 boards 401 Crystalline oxide semiconductor layer 401a Crystalline oxide semiconductor layer 402 Undercoat insulation layer 403 Insulation Layer 404 Crystalline oxide semiconductor layer 404a Source Area 404b Drain region 404c Channel formation region 405 Conductive film 405a Source electrode 405b Drain electrode 406 Gate insulating layer 410 gate electrode 412 Insulating layer 414 Insulating Layer 415a Source electrode 415b Drain electrode 416 Channel Protection Layer 416a Insulating layer 421 Nitrogen Plasma 510 Transistor 520 transistor 530 Transistor 601 Substrate 602 Photodiode 606a Semiconductor film 606b Semiconductor film 606c Semiconductor film 608 Adhesive layer 613 Substrate 631 Insulating Layer 632 Insulating layer 633 Interlayer insulating film 634 Interlayer insulating film 640 transistors 641 Electrode layer 642 Electrode layer 643 Conductive Layer 645 Conductive Layer 656 Transistor 658 Photodiode reset signal line 659 Gate signal line 671 Photo sensor output signal line 672 Photo sensor reference signal line 2701 Housing 2703 Housing 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation Key 2725 Speaker 2800 chassis 2801 Case 2802 Display panel 2803 Speaker 2804 Microphone 2805 Operation Key 2806 Pointing Device 2807 Camera lenses 2808 External connection terminal 2810 solar cell 2811 External Memory Slot 3001 main unit 3002 Case 3003 Display section 3004 Keyboard 3021 Main Unit 3022 stylus 3023 Display section 3024 Operation button 3025 External Interface 3051 Main Unit 3053 Eyepiece 3054 Operation switch 3055 Display section (B) 3056 Battery 3057 Display section (A) 4001 board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 board 4008 Liquid crystal layer 4010 transistor 4011 transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Insulation layer 4021 Insulation layer 4023 Insulation layer 4030 Electrode layer 4031 Electrode layer 4032 Insulation layer 4510 Bulkhead 4511 Electroluminescent layer 4513 Light-emitting element 4514 Filling material 9600 Television Equipment 9601 Housing 9603 Display section 9605 Stand

Claims

[Claim 1] a crystalline oxide semiconductor layer including a source region, a drain region, and a channel formation region; a gate insulating layer provided on the channel formation region; a gate electrode provided on the channel formation region via the gate insulating layer, The semiconductor device, wherein the source region and the drain region are crystalline regions containing nitrogen.

Images