Method for manufacturing a nitride semiconductor device
The use of an amorphous silicon-containing protective film under controlled pressure and temperature conditions addresses thermal decomposition in nitride semiconductor manufacturing, ensuring a smooth surface and improved device quality.
Patent Information
- Application Number
- JP2024081527
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-05-20
- Publication Date
- 2025-12-03
AI Technical Summary
Existing methods for manufacturing nitride semiconductor devices face issues with thermal decomposition of the nitride semiconductor layer during heat treatment, leading to roughness in the crystal structure.
A method involving the use of an amorphous protective film containing silicon, applied under specific pressure and temperature conditions, including a pressure of 1 MPa to 1 GPa and a temperature of 1200°C to 1500°C, to prevent thermal decomposition and maintain surface smoothness.
The method effectively suppresses thermal decomposition and maintains a smooth surface finish, with an arithmetic mean roughness of the nitride semiconductor layer's front surface below 0.2 nm, enhancing device performance.
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Abstract
Description
[Technical Field]
[0001] The present invention relates to a method for manufacturing a nitride semiconductor device. [Background technology]
[0002] Patent Document 1 describes that "a laminate 60 to be processed including a GaN layer 12 is annealed at a predetermined temperature and pressure for a certain period of time" using a protective film that is "an AlN (aluminum nitride) film." Patent Document 2 describes a method for manufacturing a nitride semiconductor device that "uses SiO2 as a cap layer 20" and "performs heat treatment at 1,200°C or less." Patent Document 3 describes that "a nitride semiconductor layer 20 is heated at a temperature of 1,200°C or more in an ammonia atmosphere at a low pressure of less than 10 kPa" using an "amorphous protective film 42 for annealing."
[0003] Patent Document 2 states that "Even if the cap layer 20 is provided, heat treatment of the laminate 10 at a temperature higher than 1,200°C will cause roughness in the crystal structure of the main surface 15." Furthermore, Patent Document 3 states that "When the annealing treatment step is performed, the amorphous annealing protective film 42 crystallizes." [Prior art document] [Patent documents] [Patent Document 1] Patent No. 6911281 [Patent Document 2] Patent No. 6217719 [Patent Document 3] International Publication No. 2021 / 161509 Summary of the Invention [Problem to be solved by the invention]
[0004] In the method for manufacturing a nitride semiconductor device, it is preferable to suppress thermal decomposition of the nitride semiconductor layer in the heat treatment step. [Means for solving the problem]
[0005] In a first aspect of the present invention, there is provided a method for manufacturing a nitride semiconductor device, comprising the steps of providing an amorphous protective film containing silicon above a nitride semiconductor layer, and heat-treating the nitride semiconductor layer provided with the protective film under pressure conditions of 1 MPa or more and 1 GPa or less and temperature conditions of 1200°C or more and 1500°C or less.
[0006] In the method for manufacturing a nitride semiconductor device described above, the protective film may be in contact with the nitride semiconductor layer.
[0007] In any of the above methods for manufacturing a nitride semiconductor device, the protective film may contain at least one of SiO2, SiN, and SiON.
[0008] In any of the above methods for manufacturing a nitride semiconductor device, the protective film may be a single layer.
[0009] In any of the above methods for manufacturing a nitride semiconductor device, the step of providing the protective film may include the steps of providing a first protective layer in contact with the nitride semiconductor layer, and providing a second protective layer above the first protective layer, the second protective layer containing a material different from that of the first protective layer.
[0010] In any of the above methods for manufacturing a nitride semiconductor device, the first protective layer may contain at least one of SiO 2 , SiN, and SiON.
[0011] In any of the above methods for manufacturing a nitride semiconductor device, the second protective layer may contain at least one of SiO 2 , SiN, SiON, AlN, Al 2 O 3 , and AlGaN.
[0012] In any of the above methods for manufacturing a nitride semiconductor device, the protective film may have a thickness of not less than 10 nm and not more than 500 nm.
[0013] In any of the above methods for manufacturing a nitride semiconductor device, the protective film may have a thickness of 10 nm or more and 50 nm or less.
[0014] In any of the above methods for manufacturing a nitride semiconductor device, the pressure in the heat treatment may be 0.1% or more and 1000% or less of the equilibrium vapor pressure of the nitride semiconductor layer.
[0015] In any of the above methods for manufacturing a nitride semiconductor device, the pressure in the heat treatment may be equal to or greater than the equilibrium vapor pressure of the nitride semiconductor layer.
[0016] In any of the above methods for manufacturing a nitride semiconductor device, the pressure in the heat treatment may be 10 MPa or more and 500 MPa or less.
[0017] In any of the above methods for manufacturing a nitride semiconductor device, the pressure in the heat treatment may be 100 MPa or more and 500 MPa or less.
[0018] Any of the above methods for manufacturing a nitride semiconductor device may include forming a P-type region containing at least one of Mg and Be in at least a portion of the nitride semiconductor layer. Any of the above methods for manufacturing a nitride semiconductor device may include forming an N-type region containing at least one of Si, O, and Ge in at least a portion of the nitride semiconductor layer.
[0019] In any of the above methods for manufacturing a nitride semiconductor device, the temperature in the heat treatment may be 1250°C or higher and 1400°C or lower.
[0020] In any of the above methods for manufacturing a nitride semiconductor device, in the heat treatment step, the temperature of the nitride semiconductor layer may be maintained at 1200° C. or more and 1500° C. or less for 30 minutes or more and 60 minutes or less.
[0021] Any of the above methods for manufacturing a nitride semiconductor device may further include the step of removing the protective film after the heat treatment step.
[0022] Any of the above methods for manufacturing a nitride semiconductor device may further include the step of forming the protective film on a back surface of the nitride semiconductor layer.
[0023] In any of the above methods for manufacturing a nitride semiconductor device, the arithmetic mean roughness (Ra) of the front surface of the nitride semiconductor layer after the heat treatment may be not less than 0.01 nm and not more than 0.2 nm.
[0024] In any of the above methods for manufacturing a nitride semiconductor device, the front surface of the nitride semiconductor layer may be a Ga face.
[0025] In any of the above methods for manufacturing a nitride semiconductor device, the protective film does not need to be crystallized in the heat treatment step.
[0026] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]
[0027] [Figure 1] 1 shows an example of a cross section of an active region of a nitride semiconductor device 100. [Figure 2] 1 is a flowchart showing an example of a method for manufacturing a nitride semiconductor device according to the present embodiment. [Figure 3A] An example of a method for manufacturing the nitride semiconductor device 100 of this example will be described. [Figure 3B] An example of a method for manufacturing the nitride semiconductor device 100 of this example will be described. [Figure 3C] An example of a method for manufacturing the nitride semiconductor device 100 of this example will be described. [Figure 3D] An example of a method for manufacturing the nitride semiconductor device 100 of this example will be described. [Figure 4] A modified method of manufacturing the nitride semiconductor device 100 of this embodiment will be described. [Figure 5] A modified method of manufacturing the nitride semiconductor device 100 of this embodiment will be described. [Figure 6A]1 shows the distribution of Ga concentration inside the protective film 30 and the nitride semiconductor layer 25 in the manufacturing method of the comparative example. [Figure 6B] In the manufacturing method of this example, the distribution of Ga concentration inside the protective film 30 and the nitride semiconductor layer 25 is shown. [Figure 7] 1 shows the arithmetic mean roughness (Ra) of the front surface 21 of the nitride semiconductor layer 25 after the heat treatment step S140. DETAILED DESCRIPTION OF THE INVENTION
[0028] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.
[0029] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "top" and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the top surface and the other surface is referred to as the bottom surface. The directions of "top," "bottom," "front," and "back" are not limited to the direction of gravity or the direction in which the semiconductor device is attached to a substrate or the like when mounted.
[0030] In this specification, layers or regions marked with N or P have electrons or holes as their majority carriers, respectively. Additionally, + and - following N or P indicate higher and lower doping concentrations, respectively, than layers or regions without that prefix.
[0031] FIG. 1 shows an example of a cross section of an active region of a nitride semiconductor device 100. The active region may be a region through which a main current flows when the nitride semiconductor device 100 is in operation. The active region may have a metal-oxide-semiconductor field-effect transistor (MOSFET) structure. The active region may have a planar-gate MOSFET structure or a trench-gate MOSFET structure. The active region may also have a diode structure.
[0032] The nitride semiconductor device 100 of this example includes a nitride semiconductor layer 25, a gate insulating film 42, a back surface side electrode 50, and a front surface side electrode 52. The nitride semiconductor layer 25 includes a semiconductor substrate 10, an epitaxial region 20, and an N-type region 12 and a P-type region 13 provided in the epitaxial region 20. The P-type region 13 includes a body region 14 and a contact region 15.
[0033] The semiconductor substrate 10 is an N+ type semiconductor substrate. The semiconductor substrate 10 may be a GaN substrate or a Si substrate. The semiconductor substrate 10 may be prepared using any method, such as a vapor phase growth method such as hydride vapor phase epitaxy (HVPE) or a liquid phase epitaxy method. The semiconductor substrate 10 may be obtained by cutting out an epitaxially grown GaN layer.
[0034] The epitaxial region 20 is provided above the semiconductor substrate 10. The epitaxial region 20 is provided by epitaxial growth on the semiconductor substrate 10. For example, the epitaxial region 20 is a material that can be epitaxially grown on the semiconductor substrate 10, such as GaN. The epitaxial region 20 may be N-type or I-type. I-type refers to an intrinsic semiconductor that is not doped with dopants. In this example, the epitaxial region 20 is N-type, which has a lower doping concentration than the semiconductor substrate 10. For example, the doping concentration of the epitaxial region 20 is 1E16 cm -3 The thickness of the epitaxial region 20 is not particularly limited, but is, for example, 10 μm.
[0035] The N-type region 12 is an N+ type region provided on the front surface 21 side of the epitaxial region 20. In this example, the N-type region 12 is provided in the front surface side electrode 52 between the gate electrode G and the source electrode S. The N-type region 12 may function as a source region of the nitride semiconductor device 100.
[0036] The doping concentration of N-type region 12 is higher than the doping concentration of epitaxial region 20. The doping concentration of N-type region 12 may be higher than the doping concentration of semiconductor substrate 10. In one example, the doping concentration of N-type region 12 is 1E18 cm -3 More than 1E21cm -3 The following is the result.
[0037] N-type region 12 may be provided by ion implanting an N-type dopant into epitaxial region 20. For example, the N-type dopant is at least one of silicon (Si), oxygen (O), and germanium (Ge).
[0038] P-type region 13 is a P-type region provided in epitaxial region 20. In this example, P-type region 13 includes body region 14 and contact region 15. Body region 14 and contact region 15 are each formed by ion-implanting P-type dopants into the epitaxial region.
[0039] The body region 14 is provided on the epitaxial region 20. The body region 14 is provided by ion implanting a dopant into the epitaxial region 20. In this example, the conductivity type of the body region 14 is P-type. For example, the P-type dopant is at least one of magnesium (Mg) and beryllium (Be). The P-type dopant may also be calcium (Ca) or zinc (Zn).
[0040] In this example, the body region 14 is selectively provided in the epitaxial region 20. Selectively provided means that the body region 14 is provided on a portion of the upper surface of the epitaxial region 20, not on the entire upper surface of the epitaxial region 20. For example, a P-type dopant is ion-implanted into the epitaxial region 20 using a mask with a predetermined pattern.
[0041] The doping concentration of the P-type dopant in the body region 14 is 1E19 cm -3 The doping concentration of the P-type dopant in the body region 14 may be 1E16 cm -3It may be more than 1E17cm -3 It may be more than 1E18cm -3 It may be more than that.
[0042] The contact region 15 is provided above the epitaxial region 20 and in contact with the front surface electrode 52. The contact region 15 is provided by ion implanting a dopant into the epitaxial region 20. The conductivity type of the contact region 15 in this example is P+ type.
[0043] The P-type dopant contained in the contact region 15 may be the same as or different from the P-type dopant contained in the body region 14. The doping concentration of the contact region 15 is greater than the doping concentration of the body region 14. In one example, the doping concentration of the contact region 15 is 1E18 cm -3 More than 1E21cm -3 The following is the result.
[0044] The front surface side electrode 52 is provided above the nitride semiconductor layer 25. The front surface side electrode 52 includes a gate electrode G and a source electrode S. The front surface side electrode 52 is formed of a material containing a metal. At least a portion of the front surface side electrode 52 may be formed of a metal such as aluminum (Al) or an alloy containing aluminum, for example, a metal alloy such as an aluminum-silicon alloy (AlSi) or an aluminum-silicon-copper alloy (AlSiCu).
[0045] The back surface side electrode 50 is provided in contact with the back surface 23. The back surface side electrode 50 includes a drain electrode D. The back surface side electrode 50 is formed of a material including a metal. The back surface side electrode 50 may be formed of the same material as the front surface side electrode 52, or may be formed of a different material.
[0046] The gate insulating film 42 is provided between the channel region above the epitaxial region 20 and the gate electrode G. When a voltage is applied from the gate electrode G through the gate insulating film 42, a main current flows between the source electrode S and the drain electrode D.
[0047] 2 is a flowchart showing an example of a method for manufacturing the nitride semiconductor device 100 of this example. The method for manufacturing the nitride semiconductor device 100 may include step S100 of epitaxially growing the epitaxial region 20 above the semiconductor substrate 10. In step S100, the epitaxial region 20 is formed above the semiconductor substrate 10. The epitaxial region 20 of this example is epitaxially grown above the semiconductor substrate 10 using any method such as metal organic chemical vapor deposition (MOCVD).
[0048] The method for manufacturing the nitride semiconductor device 100 may include step S110 of forming a P-type region 13 in the epitaxial region 20. In step S110, the P-type region 13 is formed in at least a portion of the nitride semiconductor layer 25. The P-type region 13 includes a body region 14 and a contact region 15. The P-type region 13 may contain at least one of magnesium (Mg) or beryllium (Be).
[0049] The method for manufacturing the nitride semiconductor device 100 may include step S120 of forming an N-type region 12 in the epitaxial region 20. In step S120, the N-type region 12 is formed in at least a portion of the nitride semiconductor layer 25. The N-type region 12 may contain at least one of silicon (Si), oxygen (O), and germanium (Ge).
[0050] The method for manufacturing the nitride semiconductor device 100 of this example includes step S130 of forming a protective film 30 above the nitride semiconductor layer 25. In step S130, the protective film 30 is provided above the nitride semiconductor layer 25. The protective film 30 of this example is an amorphous protective film containing silicon. Details of the protective film 30 will be described later.
[0051] The method for manufacturing the nitride semiconductor device 100 of this example includes step S140 of heat-treating the nitride semiconductor layer 25 under predetermined pressure and temperature conditions. In step S140, the nitride semiconductor layer 25 provided with the protective film 30 is heat-treated. In step S140, the nitride semiconductor layer 25 is heat-treated under predetermined pressure and temperature conditions. The predetermined pressure condition is, for example, a pressure condition of 1 MPa or more and 1 GPa or less. The predetermined temperature condition is, for example, a temperature condition of 1200°C or more and 1500°C or less. The temperature condition may be the same as 1200°C or may be a temperature higher than 1200°C.
[0052] The method for manufacturing the nitride semiconductor device 100 may include step S150 of removing the protective film 30. After step S140 of performing the heat treatment, the protective film 30 is removed in step S150. The protective film 30 may be removed by washing with a liquid agent corresponding to the material of the protective film 30. For example, if the protective film 30 is an AlN film, the protective film 30 can be selectively removed by using a potassium hydroxide solution. If the protective film 30 is an amorphous protective film containing silicon, such as an SiO2 film, the protective film 30 can be selectively removed by using a hydrofluoric acid solution.
[0053] The method for manufacturing the nitride semiconductor device 100 may include step S160 of forming a gate insulating film 42, a front surface side electrode 52, and a back surface side electrode 50. In step S160, the gate insulating film 42, the front surface side electrode 52, and the back surface side electrode 50 are formed. The front surface side electrode 52 includes a gate electrode G and a source electrode S. The back surface side electrode 50 includes a drain electrode D.
[0054] The method for manufacturing the nitride semiconductor device 100 of this example is not limited to the example shown in Fig. 2. The method for manufacturing the nitride semiconductor device 100 may include steps other than those shown in Fig. 2. The method for manufacturing the nitride semiconductor device 100 may include a dehydrogenation annealing step for removing hydrogen contained in the nitride semiconductor layer 25, and may include an additional annealing step for densifying the gate insulating film 42. The maximum temperatures in these annealing steps are lower than the maximum temperature in the heat treatment step S140.
[0055] 3A shows an example of a method for manufacturing the nitride semiconductor device 100 of this embodiment. Steps S100 to S110 will be described in detail with reference to FIG.
[0056] In this example, in step S100, GaN, a nitride semiconductor, is epitaxially grown on a semiconductor substrate 10. The epitaxial growth may be performed by MOCVD, in which a source gas containing trimethylgallium (Ga(CH3)3), ammonia (NH3), and monosilane (SiH4) and a pressurized gas containing nitrogen (N2) and hydrogen (H2) are flowed onto the semiconductor substrate 10. In this case, silicon (Si) from the monosilane functions as an N-type dopant in the epitaxial region 20. In this example, the semiconductor substrate 10 is a GaN substrate, but a silicon carbide (SiC) substrate or a zirconium boride (ZrB2) substrate, etc., may also be used. Alternatively, HVPE or molecular beam epitaxy (MBE) may be used instead of MOCVD.
[0057] In step S110, the P-type region 13 is formed. In step S110, the P-type region 13 is formed by selectively ion-implanting a P-type dopant into the nitride semiconductor layer 25. In this example, step S110 includes step S111 for forming the body region 14 and step S112 for forming the contact region 15.
[0058] In step S111, the body region 14 is formed. The body region 14 is selectively formed in at least a portion of the nitride semiconductor layer 25. In step S111, a mask 60 is formed on the front surface 21 of the epitaxial region 20, and then a P-type dopant is ion-implanted using the mask 60. This allows the body region 14 to be selectively formed.
[0059] The P-type dopant implanted in step S111 may be magnesium (Mg) or beryllium (Be). The P-type dopant may be implanted by a multi-stage implantation with different doses and acceleration voltages, thereby adjusting the doping concentration of the body region 14 after the heat treatment in step S140.
[0060] In step S112, the contact region 15 is formed. The contact region 15 is selectively formed in at least a portion of the nitride semiconductor layer 25. In step S112, the mask 60 formed in step S111 is removed, and a new mask 60 may be formed in a region different from the region where the mask 60 was formed in step S111. This allows the contact region 15 to be selectively formed in a region different from the region where the body region 14 is formed.
[0061] The type, dose, and acceleration voltage of the P-type dopant implanted in step S112 may be the same as or different from those in step S111. When both the body region 14 and the contact region 15 are formed by multiple dopant implantations, the number of dopant implantations may be the same or different. This allows the doping concentration of the contact region 15 after the heat treatment in step S140 to be adjusted.
[0062] Fig. 3B shows an example of a method for manufacturing the nitride semiconductor device 100 of this embodiment. Fig. 3B is a continuation of step S110 described in Fig. 3A. Steps S120 to S130 will be described in detail with reference to Fig. 3B.
[0063] In step S120, the N-type region 12 is formed. The N-type region 12 is selectively formed in at least a portion of the nitride semiconductor layer 25. In step S120, the mask 60 formed in step S112 is removed, and a new mask 60 may be formed in a region different from the region where the mask 60 was formed in step S112. This allows the N-type region 12 to be selectively formed in a region different from the region where the P-type region 13 was formed. In this example, the N-type region 12 is formed between the regions where the gate electrode G and the source electrode S will be formed later.
[0064] The N-type dopant implanted in step S120 may be silicon (Si), oxygen (O), or germanium (Ge). The N-type dopant may be implanted in multiple stages with different doses and acceleration voltages, thereby adjusting the doping concentration of N-type region 12 after the heat treatment in step S140.
[0065] In step S130, a protective film 30 is formed. The protective film 30 contacts the nitride semiconductor layer 25. That is, the protective film 30 is formed in direct contact with the front surface 21 of the epitaxial region 20. In this example, the P-type region 13 and the N-type region 12 are formed by ion implantation of P-type and N-type dopants in steps S110 and S120, respectively, which disrupts the crystallinity of the front surface 21 of the epitaxial region 20. This makes the epitaxial region 20 more susceptible to decomposition and release of nitrogen atoms (N) than when each region is formed by epitaxial growth rather than ion implantation. In this example, because the protective film 30 contacts the nitride semiconductor layer 25, decomposition of the epitaxial region 20 and release of N can be reduced in step S140, which is a heat treatment described later.
[0066] The protective film 30 is an amorphous protective film containing silicon. The material of the protective film 30 is an amorphous material that does not crystallize under the temperature conditions of the heat treatment step S140. The protective film 30 not crystallizing may mean that the protective film 30 does not have an observable crystalline phase under the temperature conditions of the heat treatment step S140. The material of the protective film 30 may be a material that has high heat resistance, good adhesion to the epitaxial region 20, and does not allow impurities to diffuse from the protective film 30 to the epitaxial region 20. The material of the protective film 30 may be a material that has etching selectivity with respect to the epitaxial region 20. The protective film 30 in this example includes at least one of SiO2, SiN, and SiON.
[0067] The protective film 30 may be formed by a sputtering method, or by a chemical vapor deposition method such as plasma enhanced chemical vapor deposition (plasma CVD), low pressure chemical vapor deposition (LPCVD), or mist chemical vapor deposition (mist CVD).The protective film 30 may be formed by a method that combines formation by a sputtering method and formation by a chemical vapor deposition method.
[0068] The protective film 30 may be a single layer. The protective film 30 being a single layer may mean that the protective film 30 is formed from a single material or by a single method.
[0069] The thickness of the protective film 30 in this example is 10 nm or more and 500 nm or less. Because the protective film 30 in this example is an amorphous film containing silicon, it does not crystallize even in the heat treatment step S140 described below, and its thickness is less likely to become thin compared to a material that crystallizes. This allows for more precise control of the thickness of the protective film 30 compared to when a material that crystallizes is used for the protective film 30. In one example, the thickness of the protective film 30 is 10 nm or more and 50 nm or less.
[0070] Fig. 3C shows an example of a method for manufacturing the nitride semiconductor device 100 of this embodiment. Fig. 3C is a continuation of step S130 described in Fig. 3B. Step S140 will be described in detail with reference to Fig. 3C.
[0071] In step S140, the nitride semiconductor layer 25 provided with the protective film 30 is heat-treated. In step S140 in this example, the nitride semiconductor layer 25 is placed in a hot isostatic pressing apparatus 110. An initial pressure calculated to obtain a desired pressure at a target heat treatment temperature is then applied to a treatment chamber in the hot isostatic pressing apparatus 110, and the temperature is then raised in a sealed state, thereby increasing the pressure inside the treatment chamber due to thermal expansion of the gas. In this way, the treatment chamber is maintained at a predetermined temperature and pressure, and the nitride semiconductor layer 25 is heat-treated. The heat treatment in this example refers to annealing the nitride semiconductor layer 25 provided with the protective film 30 for a certain period of time under predetermined pressure and temperature conditions.
[0072] In the method for manufacturing the nitride semiconductor device 100 of this example, the nitride semiconductor layer 25 provided with the silicon-containing amorphous protective film 30 is heat-treated under pressure conditions of 1 MPa to 1 GPa and temperature conditions of 1200°C to 1500°C. The temperature condition of 1200°C to 1500°C may mean that the maximum temperature in the heat-treating step S140 is within this temperature range. The temperature in the heat-treating step S140 may be 1250°C to 1400°C.
[0073] The pressure condition of 1 MPa or more and 1 GPa or less may mean that the pressure inside the hot isostatic pressing apparatus 110 at the maximum temperature in the heat treatment step S140 is within this pressure range. The pressure in the heat treatment step S140 may be 10 MPa or more and 500 MPa or less. The pressure in the heat treatment step S140 may be 100 MPa or more and 500 MPa or less.
[0074] The pressure conditions in the heat treatment step S140 may be changed depending on the temperature conditions. For example, the pressure in the heat treatment step S140 is 0.1% or more and 1000% or less of the equilibrium vapor pressure of the nitride semiconductor layer 25. The equilibrium vapor pressure of the nitride semiconductor layer 25 means a pressure that can prevent decomposition and release of N from the nitride semiconductor layer 25 under a predetermined temperature condition.
[0075] In the method for manufacturing the nitride semiconductor device 100 of this example, by using the protective film 30 that is an amorphous film containing silicon, and by pressing the protective film 30 with an atmospheric gas, it is possible to suppress decomposition of the nitride semiconductor layer 25 even under pressure conditions that are equal to or lower than the equilibrium vapor pressure of the nitride semiconductor layer 25. The pressure in the heat treatment step S140 may be 0.3% or more and 400% or less, or may be 3% or more and 200% or less, of the equilibrium vapor pressure of the nitride semiconductor layer 25.
[0076] The pressure in the heat treatment step S140 may be equal to or higher than the equilibrium vapor pressure of the nitride semiconductor layer 25. As an example, since the equilibrium vapor pressure of the nitride semiconductor layer 25 at 1300°C is approximately 300 MPa, the temperature and pressure conditions in the heat treatment step S140 are 1300°C and 300 MPa, respectively. The temperature and pressure conditions in the heat treatment step S140 may be 1300°C and 500 MPa, respectively. By setting the pressure condition to be equal to or higher than the equilibrium vapor pressure of the nitride semiconductor layer 25, decomposition of the nitride semiconductor layer 25 in the heat treatment step S140 can be suppressed.
[0077] In the heat treatment step S140, the temperature of the nitride semiconductor layer 25 may be maintained at 1200° C. or higher and 1500° C. or lower for 30 minutes or longer and 60 minutes or shorter. In the method for manufacturing the nitride semiconductor device 100 of this example, by using the protective film 30 that is an amorphous film containing silicon, decomposition of the nitride semiconductor layer 25 can be suppressed even when the heat treatment is performed for 30 minutes or longer.
[0078] Fig. 3D shows an example of a method for manufacturing the nitride semiconductor device 100 of this embodiment. Fig. 3D is a continuation of step S140 described in Fig. 3C. Steps S150 and S160 will be described in detail with reference to Fig. 3D.
[0079] After the heat treatment step S140, the protective film 30 is removed in step S150. The protective film 30 is made of a material that has etching selectivity with respect to the epitaxial region 20, so that only the protective film 30 can be selectively removed without damaging the epitaxial region 20.
[0080] In step S160, the gate insulating film 42, the front surface side electrode 52, and the back surface side electrode 50 are formed by applying known film formation and patterning methods. The SiO2 film serving as the gate insulating film 42 may be formed by the aforementioned chemical vapor deposition method. The thickness of the gate insulating film 42 is, for example, 100 nm. Note that the gate insulating film 42 may be formed using a silicon oxynitride (SiON) film, an aluminum oxide (Al2O3) film, an aluminum oxynitride (AlON) film, a magnesium oxide (MgO) film, a gallium oxide (GaO x ) film and gadolinium oxide (GdO x ) film and a laminated film containing two or more of these.
[0081] Thereafter, polycrystalline silicon may be formed by LPCVD as the gate electrode G of the front-side electrode 52. During or after the formation of the polycrystalline silicon, the polycrystalline silicon may be doped with one or more elements, such as phosphorus (P) and arsenic (As). This improves the conductivity of the polycrystalline silicon. The gate electrode G may be a metal film of gold (Au), platinum (Pt), nickel (Ni), aluminum (Al), titanium (Ti), or tungsten (W), or an alloy film of these metals. Alternatively, it may be a ceramic film or a silicide film, such as titanium nitride (TiN), tungsten silicide (WSi), or nickel silicide (NiSi). The gate insulating film 42 and the gate electrode G are patterned by photolithography and etching.
[0082] Thereafter, the source electrode S of the front surface side electrode 52 is formed. The source electrode S may be a laminated body having a lower Ti (titanium) layer and an upper Al layer. Note that, in order to reduce the contact resistance between the source electrode S and the contact region 15, the contact region 15 may contain Ni (nickel), Pd (palladium), or Pt (platinum) at the interface with the source electrode S. Thereafter, the drain electrode D of the back surface side electrode 50 is formed. The drain electrode D may be a laminated body having an upper Ti layer and a lower Al layer that are in direct contact with the back surface 23 of the semiconductor substrate 10.
[0083] Fig. 4 shows a modified example of the method for manufacturing the nitride semiconductor device 100 of this example. Fig. 4 is a continuation of step S120 described with reference to Fig. 3B. A modified example of step S130 of providing the protective film 30 will be described with reference to Fig. 4.
[0084] Step S130 of providing the protective film 30 may include step S131 of providing a first protective layer 31 in contact with the nitride semiconductor layer 25, and step S132 of providing a second protective layer 32 containing a material different from that of the first protective layer 31 above the first protective layer 31. The protective film 30 of this example includes the first protective layer 31 and the second protective layer 32. Step S130 of providing the protective film 30 may include a step of providing an additional protective layer above the second protective layer 32. That is, the protective film 30 may include protective layers made of three or more different materials.
[0085] In step S131, a first protective layer 31 is formed in contact with the nitride semiconductor layer 25. The first protective layer 31 is a protective layer of an amorphous film containing silicon. In this example, the first protective layer 31 contains at least one of SiO2, SiN, and SiON. By forming the first protective layer 31 as an amorphous film containing silicon, decomposition of the nitride semiconductor layer 25 in step S140 of performing heat treatment can be suppressed.
[0086] In step S132, a second protective layer 32 containing a different material from the first protective layer 31 is formed above the first protective layer 31. The second protective layer 32 may be an amorphous film containing silicon or another amorphous film. In this example, the second protective layer 32 contains at least one of SiO2, SiN, SiON, AlN, Al2O3, and AlGaN. This improves the stability of the protective layer 30.
[0087] Fig. 5 shows a modified example of the method for manufacturing the nitride semiconductor device 100 of this embodiment. Fig. 5 is a continuation of step S130 described with reference to Fig. 3B.
[0088] The method for manufacturing the nitride semiconductor device 100 of this example includes step S135 of forming a protective film 35 on the back surface 23 of the nitride semiconductor layer 25. This makes it possible to suppress decomposition of the nitride semiconductor layer 25 on the back surface 23 side in step S140 of performing heat treatment.
[0089] Note that step S135 may be omitted. In the method for manufacturing the nitride semiconductor device 100 of this example, the protective film 30 is provided on the front surface 21 side of the nitride semiconductor layer 25. In this example, the front surface 21 of the nitride semiconductor layer 25 is a Ga plane. In the method for manufacturing the nitride semiconductor device 100 of this example, by providing the protective film 30 on the front surface 21 side, which is the Ga plane that is more susceptible to thermal decomposition, it is possible to suppress decomposition of the nitride semiconductor layer 25 in heat treatment step S140.
[0090] 6A shows the distribution of Ga concentration inside the protective film 30 and the nitride semiconductor layer 25 when a comparative example manufacturing method for the nitride semiconductor device 100 is used. Fig. 6A shows the distribution of Ga concentration after the heat treatment step S140 when the protective film 30 is formed of AlN as a comparative example. Fig. 6A is a semi-logarithmic graph in which the horizontal axis represents the depth measured from the top surface of the protective film 30 and the vertical axis represents the Ga concentration. The region from a depth of 0 nm to the front surface 21 indicated by the dotted line is the interior of the protective film 30, and the region to the right of the dotted line is the interior of the nitride semiconductor layer 25.
[0091] In the comparative example, after the protective film 30 was formed of AlN, the nitride semiconductor layer 25 was annealed for 60 minutes at a temperature of 1300°C and a pressure of 500 MPa in the heat treatment step S140. The equilibrium vapor pressure of the nitride semiconductor layer 25 at 1300°C is about 300 MPa. From FIG. 6A, it can be seen that the vapor pressure of the nitride semiconductor layer 25 was 1E22 cm3 both inside the protective film 30 and inside the nitride semiconductor layer 25. -3 This suggests that, even though the pressure condition was equal to or higher than the equilibrium vapor pressure, the nitride semiconductor layer 25 was thermally decomposed and the Ga generated by the decomposition diffused into the protective film 30.
[0092] Fig. 6B shows the distribution of Ga concentration inside the protective film 30 and the nitride semiconductor layer 25 when the manufacturing method of the nitride semiconductor device 100 of this example is used. Fig. 6B shows the distribution of Ga concentration after the heat treatment step S140 when the protective film 30 is made of SiO. The axes and dotted lines are the same as those in Fig. 6A, so their explanation will be omitted.
[0093] 6A, in the example of FIG. 6B, after forming the protective film from SiO2, in the heat treatment step S140, the nitride semiconductor layer 25 was annealed for 60 minutes under the temperature condition of 1300°C and the pressure condition of 500 MPa. Unlike the comparative example of FIG. 6A, in the example of FIG. 6B, the Ga concentration inside the protective film 30 was 1E19 cm -3 below, which means that the Ga concentration differs by about 100 to 1000 times compared to the inside of nitride semiconductor layer 25. This suggests that the method for manufacturing nitride semiconductor device 100 of this example suppresses thermal decomposition of nitride semiconductor layer 25 in heat treatment step S140.
[0094] 6A and 6B, the thickness of the protective film 30 before the heat treatment step S140 is the same, but the film thickness after the heat treatment step S140 is different. This is because the amorphous film used in this example does not crystallize in the heat treatment step S140, whereas the protective film made of AlN or the like used in the comparative example crystallizes in the heat treatment step S140. As such, the protective film 30 used in the method for manufacturing the nitride semiconductor device 100 of this example does not crystallize in the heat treatment step S140, and therefore the thickness of the protective film 30 can be more precisely controlled than when a crystallizable material is used.
[0095] 7 shows the arithmetic mean roughness (Ra) of the front surface 21 of the nitride semiconductor layer 25 after the heat treatment step S140. The data indicated by the dotted line is the arithmetic mean roughness (Ra) of the front surface 21 of the nitride semiconductor layer 25 before the heat treatment step S140. Before the heat treatment step S140, the arithmetic mean roughness (Ra) of the front surface 21 of the nitride semiconductor layer 25 is 0.07 nm. In the manufacturing method of the nitride semiconductor device 100 of this example, decomposition of the nitride semiconductor layer 25 in the heat treatment step S140 can be suppressed compared to when the protective film 30 is not used or when an AlN protective film is used as the protective film 30.
[0096] The data marked "without protective film" in FIG. 7 represents the arithmetic mean roughness (Ra) of the front surface 21 of the nitride semiconductor layer 25 after performing step S140 of heat treatment without using the protective film 30, as a comparative example. In the comparative example, the protective film 30 was not provided on the front surface 21 of the nitride semiconductor layer 25, and the nitride semiconductor layer 25 was annealed for 60 minutes at a temperature of 1300°C and a pressure of 500 MPa. It can be seen that the arithmetic mean roughness (Ra) is increased compared to the state before the heat treatment. The arithmetic mean roughness (Ra) of the front surface 21 of the nitride semiconductor layer 25 after performing step S140 of heat treatment without using the protective film 30 is 0.23 nm.
[0097] The data labeled "AlN protective film" in FIG. 7 represents the arithmetic mean roughness (Ra) of the front surface 21 of the nitride semiconductor layer 25 after performing step S140 of heat treatment using a protective film 30 made of AlN as a comparative example. In the comparative example, an AlN protective film 30 was provided on the front surface 21 of the nitride semiconductor layer 25, and the nitride semiconductor layer 25 was annealed for 60 minutes at a temperature of 1300°C and a pressure of 500 MPa. Referring to FIG. 7, it can be seen that the arithmetic mean roughness (Ra) is increased when the AlN protective film 30 is used, compared to the state before the heat treatment. The arithmetic mean roughness (Ra) of the front surface 21 of the nitride semiconductor layer 25 after performing step S140 of heat treatment using the AlN protective film is 0.35 nm.
[0098] The data labeled "SiO2 protective film" in FIG. 7 is the arithmetic mean roughness (Ra) of the front surface 21 of the nitride semiconductor layer 25 after performing the heat treatment step S140 in the manufacturing method of the nitride semiconductor device 100 of this example. In this example, a SiO2 protective film 30 was provided on the front surface 21 of the nitride semiconductor layer 25, and the nitride semiconductor layer 25 was annealed for 60 minutes at a temperature of 1300°C and a pressure of 500 MPa. Referring to FIG. 7, although the arithmetic mean roughness (Ra) has increased slightly compared to the state before the heat treatment, the increase is smaller than in the comparative examples "without protective film" and "AlN protective film." In this example, the arithmetic mean roughness (Ra) of the front surface 21 of the nitride semiconductor layer 25 is 0.08 nm.
[0099] 7, in the method for manufacturing the nitride semiconductor device 100 of this example, the use of the amorphous protective film 30 containing silicon can suppress decomposition of the nitride semiconductor layer 25 in the heat treatment step S140. In the method for manufacturing the nitride semiconductor device 100 of this example, after the heat treatment step S140, the arithmetic mean roughness (Ra) of the front surface 21 of the nitride semiconductor layer 25 is 0.01 nm or more and 0.2 nm or less.
[0100] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.
[0101] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]
[0102] 10 semiconductor substrate, 12 N-type region, 13 P-type region, 14 body region, 15 contact region, 20 epitaxial region, 21 front surface, 23 back surface, 25 nitride semiconductor layer, 30 protective film, 31 first protective layer, 32 second protective layer, 35 protective film, 42 gate insulating film, 50 back electrode, 52 front electrode, 60 mask, 100 nitride semiconductor device, 110 hot isostatic pressing apparatus
Claims
1. providing an amorphous protective film containing silicon above the nitride semiconductor layer; heat-treating the nitride semiconductor layer provided with the protective film under a pressure condition of 1 MPa or more and 1 GPa or less and a temperature condition of 1200° C. or more and 1500° C. or less; Equipped with A method for manufacturing a nitride semiconductor device.
2. The protective film is in contact with the nitride semiconductor layer. The method for manufacturing a nitride semiconductor device according to claim 1 .
3. The protective film is made of SiO ２ , SiN, or SiON The method for manufacturing a nitride semiconductor device according to claim 1 .
4. The protective film is a single layer. The method for manufacturing a nitride semiconductor device according to claim 1 .
5. The step of providing the protective film comprises: providing a first protective layer in contact with the nitride semiconductor layer; providing a second protective layer above the first protective layer, the second protective layer comprising a different material than the first protective layer; Contains The method for manufacturing a nitride semiconductor device according to claim 1 .
6. The first protective layer is made of SiO ２ , SiN, or SiON The method for manufacturing a nitride semiconductor device according to claim 5 .
7. The second protective layer is made of SiO ２ , SiN, SiON, AlN, Al ２ O ３ or AlGaN The method for manufacturing a nitride semiconductor device according to claim 5 .
8. The thickness of the protective film is 10 nm or more and 500 nm or less. The method for manufacturing a nitride semiconductor device according to claim 1 .
9. The thickness of the protective film is 10 nm or more and 50 nm or less. The method for manufacturing a nitride semiconductor device according to claim 1 .
10. The pressure in the heat treatment step is 0.1% to 1000% of the equilibrium vapor pressure of the nitride semiconductor layer. The method for manufacturing a nitride semiconductor device according to claim 1 .
11. The pressure in the heat treatment step is equal to or greater than the equilibrium vapor pressure of the nitride semiconductor layer. The method for manufacturing a nitride semiconductor device according to claim 1 .
12. The pressure in the heat treatment step is 10 MPa or more and 500 MPa or less. The method for manufacturing a nitride semiconductor device according to claim 1 .
13. The pressure in the heat treatment step is 100 MPa or more and 500 MPa or less. The method for manufacturing a nitride semiconductor device according to claim 1 .
14. forming a P-type region containing at least one of Mg and Be in at least a portion of the nitride semiconductor layer; forming an N-type region containing at least one of Si, O, and Ge in at least a portion of the nitride semiconductor layer; Equipped with The method for manufacturing a nitride semiconductor device according to claim 1 .
15. The temperature in the heat treatment step is 1250° C. or more and 1400° C. or less. The method for manufacturing a nitride semiconductor device according to claim 1 .
16. In the heat treatment, the temperature of the nitride semiconductor layer is maintained at 1200° C. or more and 1500° C. or less for 30 minutes or more and 60 minutes or less. The method for manufacturing a nitride semiconductor device according to claim 1 .
17. After the heat treatment, the protective film is removed. The method for manufacturing a nitride semiconductor device according to claim 1 .
18. forming the protective film on a rear surface of the nitride semiconductor layer. The method for manufacturing a nitride semiconductor device according to claim 1 .
19. After the heat treatment, the arithmetic mean roughness (Ra) of the front surface of the nitride semiconductor layer is 0.01 nm or more and 0.2 nm or less. The method for manufacturing a nitride semiconductor device according to claim 1 .
20. The front surface of the nitride semiconductor layer is a Ga surface. The method for manufacturing a nitride semiconductor device according to claim 1 .
21. The protective film is not crystallized during the heat treatment. The method for manufacturing a nitride semiconductor device according to claim 1 .