3D NAND memory and manufacturing method thereof

Abstract

To provide a method for forming a three-dimensional (3D) memory device.SOLUTION: A method includes disposing an alternating dielectric stack over a substrate, the alternating dielectric stack including first and second dielectric layers alternately stacked on the substrate. The method also includes forming a channel structure penetrating through the alternating dielectric stack into the substrate, the channel structure including a channel layer disposed on sidewalls of the memory film. The method further includes removing a portion of the substrate and the memory film penetrating into the substrate to expose a portion of the channel layer, and disposing an array common source (ACS) on the exposed portion of the channel layer.SELECTED DRAWING: Figure 16

Description

[Technical Field]

[0001] TECHNICAL FIELD The present disclosure relates generally to the field of semiconductor technology, and more particularly to 3D NAND flash memory and methods for fabricating the same. [Background technology]

[0002] As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase storage density, scaling of planar memory cells faces challenges due to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures can address the density and performance limitations of planar memory cells.

[0003] In 3D NAND flash memory, many layers of memory cells can be stacked vertically, which can significantly increase the storage density per unit area. The number of vertically stacked layers can be significantly increased, thereby further increasing storage capacity. However, high aspect ratio structures can be very difficult to fabricate. For example, a channel hole can be formed through the stacked structure by etching, and a memory film and channel layer can be disposed on the sidewalls of the channel hole. To form a source contact to the channel layer, the memory film at the bottom of the channel hole needs to be removed. However, removing the memory film from the bottom of the channel hole without damaging the channel layer on the sidewall is problematic. Pinholes in the channel layer can cause reliability issues and reduce product yield. Therefore, there is a need to provide a method for forming a source contact to the channel layer. Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY Embodiments of three-dimensional (3D) memory devices and methods for forming the same are described in this disclosure. [Means for solving the problem]

[0005] One aspect of the present disclosure provides a method for forming a three-dimensional (3D) memory device, the method including: sequentially forming a first etch stop layer, a second etch stop layer, and an alternating dielectric stack on a substrate; forming a channel hole through the alternating dielectric stack and penetrating into the substrate; disposing a memory film and then a channel layer on sidewalls of the channel hole to form a channel structure; removing the substrate, stopping on the first etch stop layer to expose a portion of the memory film that penetrates into the substrate; removing the first etch stop layer and the exposed portion of the memory film, stopping on a second etch stop layer to expose a portion of the channel layer that penetrates into the substrate; and forming an array common source (ACS) on a back surface of the second etch stop layer remote from the alternating dielectric stack to cover the exposed portion of the channel layer.

[0006] In some embodiments, the first etch stop layer comprises silicon oxide and the second etch stop layer comprises polycrystalline silicon.

[0007] In some embodiments, the substrate includes a handle wafer, an insulator layer (eg, a sacrificial silicon oxide layer), and a semiconductor layer (eg, a sacrificial polycrystalline silicon layer).

[0008] In some embodiments, removing the substrate and stopping on the first etch stop layer comprises removing the substrate by wet etching.

[0009] In some embodiments, removing the first etch stop layer and the exposed portions of the memory film comprises removing the first etch stop layer and the exposed portions of the memory film by wet etching.

[0010] In some embodiments, the alternating dielectric stack includes a stepped region, and the method also includes forming a dummy channel hole in the stepped region, the dummy channel hole penetrating through at least a portion of the alternating dielectric stack and into the substrate.

[0011] In some embodiments, the alternating dielectric stack includes alternating first and second dielectric layers (i.e., sacrificial layers). The method also includes forming a slit opening through the alternating dielectric stack and into the substrate, the slit opening being spaced from the channel structure, removing the sacrificial layer through the slit opening to form a lateral tunnel, forming a conductive layer inside the lateral tunnel, and disposing an insulating material inside the slit opening to form the slit structure.

[0012] In some embodiments, forming the conductive layer inside the lateral tunnel includes disposing a gate dielectric layer on the sidewalls of the lateral tunnel and the slit opening, and disposing a gate adhesion layer on the gate dielectric layer inside the lateral tunnel.

[0013] In some embodiments, the substrate further comprises a peripheral region covered by an insulating layer, and the method also includes forming through-silicon vias (TSVs) in the peripheral region that penetrate through the front insulating layer and into the substrate.

[0014] In some embodiments, forming the TSVs includes forming a TSV interface layer that covers the sidewalls of the TSVs.

[0015] In some embodiments, the method also includes sequentially removing the substrate and the first etch stop layer through a wet etching process to expose portions of the dummy channel holes that extend into the substrate, portions of the slit structures that extend into the substrate, and portions of the TSVs that extend into the substrate.

[0016] In some embodiments, forming the ACS on the back surface of the second etch stop layer includes disposing the ACS to cover exposed portions of the dummy channel holes that extend into the substrate, exposed portions of the slit structures that extend into the substrate, and exposed portions of the TSVs that extend into the substrate.

[0017] In some embodiments, forming the ACS further includes disposing a first polycrystalline silicon layer on a back surface of the second etch stop layer, doping and annealing the first polycrystalline silicon layer, disposing a second polycrystalline silicon layer on a back surface of the first polycrystalline silicon layer remote from the alternating dielectric stack, and doping and annealing the second polycrystalline silicon layer.

[0018] In some embodiments, the method further includes forming an interlevel dielectric layer on a backside of the ACS remote from the alternating dielectric stack.

[0019] In some embodiments, forming the interlevel dielectric layer includes forming a dielectric dielectric layer on a backside of the ACS remote from the alternating dielectric stack; forming a backside deep trench isolation (BDTI) in the dielectric fill layer through the ACS; removing a portion of the dielectric fill layer corresponding to the channel structure to form a first contact opening to expose the ACS; and removing a portion of the dielectric fill layer corresponding to the TSV to form a second contact opening to expose the TSV.

[0020] In some embodiments, the method also includes forming a backside interconnect layer on the interlevel dielectric layer remote from the alternating dielectric stack.

[0021] In some embodiments, forming the backside interconnect layer includes disposing a conductive material inside the first contact opening and the second contact opening, covering a backside of the interlayer dielectric layer remote from the alternating dielectric stack, forming an ACS contact structure inside the first contact opening, forming a TSV contact structure inside the second contact opening, and forming an insulating space between the ACS contact structure and the TSV contact structure.

[0022] Another aspect of the present disclosure provides a three-dimensional (3D) memory device. The 3D memory device includes an array common source (ACS), a film stack having alternating conductive and dielectric layers on a first side of the ACS, and channel structures penetrating through the film stack and into the ACS. Each channel structure includes a core-fill film, a channel layer covering a sidewall of the core-fill film, and a memory film disposed on a portion of the channel layer penetrating through the film stack. The ACS surrounds the portion of the channel layer penetrating from the film stack into the ACS, thereby connecting the ACS to the portion of the channel layer penetrating from the film stack into the ACS.

[0023] In some embodiments, the ACS comprises a p-type or n-type doped polycrystalline silicon layer.

[0024] In some embodiments, the film stack, in which the conductive and dielectric layers are alternated, comprises a stepped region.

[0025] In some embodiments, the 3D memory device also includes a dummy channel hole that penetrates at least a portion of the film stack and into the ACS, the ACS surrounding a portion of the dummy channel hole that penetrates from the film stack into the ACS.

[0026] In some embodiments, the 3D memory device also includes a slit structure (i.e., a gate line slit) that penetrates through the film stack into the ACS. The slit structure is separate from the channel structure, and the ACS surrounds a portion of the slit structure that penetrates from the film stack into the ACS.

[0027] In some embodiments, the slit structure includes a gate dielectric layer disposed on the sidewalls of the slit structure.

[0028] In some embodiments, the film stack also includes a gate dielectric layer covering the sidewalls of the conductive layer, and a gate adhesion layer disposed between the gate dielectric layer and the conductive layer.

[0029] In some embodiments, the 3D memory device also includes a peripheral region covered by an insulating layer. The peripheral region is on the front side of the ACS closer to the film stack. The 3D memory device also includes through-silicon vias (TSVs) that penetrate the insulating layer in the peripheral region. The TSVs are not in contact with the ACS.

[0030] In some embodiments, the TSVs include a TSV interface layer.

[0031] In some embodiments, the 3D memory device also comprises an interlevel dielectric layer on the backside of the ACS, remote from the film stack.

[0032] In some embodiments, the interlevel dielectric layer includes backside deep trench isolation (BDTI) that penetrates the ACS in areas with the TSVs.

[0033] In some embodiments, the 3D memory device also includes a backside interconnect layer on a backside of the interlayer dielectric layer remote from the film stack, the backside interconnect layer including an ACS contact structure connected to the ACS and corresponding to the channel structure, a TSV contact structure connected to the TSV, and an insulating space disposed between the TSV contact structure and the ACS contact structure.

[0034] Yet another aspect of the present disclosure provides a memory storage system. The memory storage system includes a three-dimensional (3D) NAND memory, the 3D NAND memory including an array common source (ACS) and a film stack of alternating conductive and dielectric layers, the film stack including alternating conductive layers and a first dielectric layer on a first side of the ACS. The 3D NAND memory also includes a backside interconnect layer disposed on a second side of the ACS opposite the first side, the backside interconnect layer including an ACS contact structure. The 3D NAND memory further includes a memory string extending through the film stack, the memory string including a channel layer having a first portion covered by the memory film and a second portion in contact with the ACS and electrically connected to the ACS contact structure.

[0035] Other aspects of the present disclosure will be apparent to those skilled in the art in light of the description, claims, and drawings of the present disclosure.

[0036] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable those skilled in the art to make and use the present disclosure. [Brief explanation of the drawings]

[0037] [Figure 1] 1 is a schematic top-down view illustrating an exemplary three-dimensional (3D) memory die, according to some embodiments of the present disclosure. [Figure 2] 1 is a schematic top-down view illustrating areas of a 3D memory die, according to some embodiments of the present disclosure. [Figure 3] 1 is a perspective view illustrating a portion of an exemplary 3D memory array structure, according to some embodiments of the present disclosure. [Figure 4] 1A-1C illustrate methods for forming a 3D memory device according to some embodiments of the present disclosure. [Figure 5] 1A-1C are cross-sectional views illustrating a 3D memory structure at certain process steps according to some embodiments of the present disclosure. [Figure 6A] 1A-1C are cross-sectional views illustrating a 3D memory structure at certain process steps according to some embodiments of the present disclosure. [Figure 6B] 1A-1C are cross-sectional views illustrating a 3D memory structure at certain process steps according to some embodiments of the present disclosure. [Figure 7] 1A-1C are cross-sectional views illustrating a 3D memory structure at certain process steps according to some embodiments of the present disclosure. [Figure 8] 1A-1C are cross-sectional views illustrating a 3D memory structure at certain process steps according to some embodiments of the present disclosure. [Figure 9] 1A-1C are cross-sectional views illustrating a 3D memory structure at certain process steps according to some embodiments of the present disclosure. [Figure 10] 1A-1C are cross-sectional views illustrating a 3D memory structure at certain process steps according to some embodiments of the present disclosure. [Figure 11] 1A-1C are cross-sectional views illustrating a 3D memory structure at certain process steps according to some embodiments of the present disclosure. [Figure 12] 1A-1C are cross-sectional views illustrating a 3D memory structure at certain process steps according to some embodiments of the present disclosure. [Figure 13] 1A-1C are cross-sectional views illustrating a 3D memory structure at certain process steps according to some embodiments of the present disclosure. [Figure 14] 1A-1C are cross-sectional views illustrating a 3D memory structure at certain process steps according to some embodiments of the present disclosure. [Figure 15]1A-1C are cross-sectional views illustrating a 3D memory structure at certain process steps according to some embodiments of the present disclosure. [Figure 16] 1A-1C are cross-sectional views illustrating a 3D memory structure at certain process steps according to some embodiments of the present disclosure. [Figure 17] FIG. 1 illustrates a storage system having one or more memory chips, according to some embodiments of the present disclosure. [Figure 18A] FIG. 1 illustrates a storage system having one or more memory chips, according to some embodiments of the present disclosure. [Figure 18B] FIG. 1 illustrates a storage system having one or more memory chips, according to some embodiments of the present disclosure. [Figure 19] 1 is a schematic diagram illustrating a three-dimensional (3D) memory die according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0038] The features and advantages of the present invention will become more apparent from the detailed description set forth below when read in conjunction with the drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) of the corresponding reference number.

[0039] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0040] While specific configurations and arrangements are described, it will be understood that this is done for illustrative purposes only. A person skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure can be employed in a variety of other applications.

[0041] It should be noted that references in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., indicate that the described embodiment may comprise a particular feature, structure, or characteristic, but that all embodiments may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with one embodiment, it will be within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described.

[0042] Generally, terms can be understood, at least in part, from their usage in context. For example, the phrase "one or more," as used herein, may be used in a singular sense to describe a feature, structure, or characteristic, or in a plural sense to describe a combination of features, structures, or characteristics, depending at least in part on the context. Similarly, again, articles such as "a," "an," or "the" in English text may be understood as conveying singular use or conveying plural use, depending at least in part on the context. Additionally, the phrase "based on" can be understood as not necessarily intended to convey an exclusive series of elements, but instead may permit the presence of additional elements not necessarily explicitly recited, again depending at least in part on the context.

[0043] It should be readily understood that the meanings of "on," "above," and "over" in the original English text of this disclosure should be interpreted in the broadest sense, such that "on" not only means "directly on" something, but also includes the meaning "on" of something with an intermediate feature or layer between them. Furthermore, "above" or "over" in the original English text not only means "above" something or "on" something in the form of being "on" something or "over" something without an intermediate feature or layer between them (i.e., directly on top of something).

[0044] Spatially relative terms such as "beneath," "below," "lower," "above," "upper," and similar terms may be used herein for ease of description in describing the relationship of one element or feature to another, as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or at a process stage in addition to the orientation shown in the figures. The device may be oriented in some other way (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein similarly interpreted accordingly.

[0045] As used herein, the term "substrate" refers to a material onto which subsequent material layers are applied. A substrate has a "top" surface and a "bottom" surface. The top surface of a substrate is typically where semiconductor devices are formed, and therefore, semiconductor devices are formed on the top side of the substrate unless otherwise specified. The bottom surface is opposite the top surface, and therefore, the bottom side of the substrate is opposite the top side of the substrate. The substrate itself can be patterned. Materials applied onto the substrate can be patterned or left unpatterned. Furthermore, substrates can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from an electrically non-conductive material, such as glass, plastic, or a sapphire wafer.

[0046] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer has a top side and a bottom side, with the bottom of the layer being relatively closer to the substrate and the top side being relatively farther from the substrate. A layer can extend across an underlying or overlying structure or can have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer can be a region of a homogeneous or heterogeneous continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be disposed between the top and bottom surfaces of a continuous structure, or between any pair of horizontal surfaces at the top and bottom surfaces. A layer can extend along horizontal, vertical, and / or tapered surfaces. A substrate can be a layer and can include one or more layers therein and / or have one or more layers on, above, and / or below it. A layer can also include multiple layers. For example, the interconnect layers may include one or more conductor layers and contact layers (in which contacts, interconnect lines, and / or vertical interconnect accesses (VIAs) are formed) and one or more dielectric layers.

[0047] In this disclosure, for ease of explanation, "tier" is used to refer to elements that are substantially the same height along the vertical direction. For example, a word line and the gate dielectric layer below it may be referred to as a "tier," a word line and the insulating layer below it may be collectively referred to as a "tier," a word line of substantially the same height may be referred to as a "tier of a word line," or the like, and so on.

[0048] As used herein, the phrase "nominal / nominally" refers to a desired or target value of a characteristic or parameter for a component or process step that is established during the design phase of a product or process, along with a range of values ​​above and / or below the desired value. The range of values ​​may be due to slight variations in the manufacturing process or manufacturing tolerances. As used herein, the term "about" indicates a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" can indicate, for example, a value of a given quantity that varies within 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0049] In this disclosure, the terms "horizontal / horizontally / lateral / outer / laterally" mean nominally parallel to the outer surface of the substrate, and the phrase "vertical / vertically" means nominally perpendicular to the outer surface of the substrate.

[0050] As used herein, the term "3D memory" refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings," such as NAND strings) on a laterally oriented substrate such that the memory strings extend vertically with respect to the substrate.

[0051] FIG. 1 illustrates a schematic top-down view of an exemplary three-dimensional (3D) memory device 100 according to some embodiments of the present disclosure. The 3D memory device 100, such as a 3D NAND flash memory, can be a memory chip (package), a memory die, or any portion of a memory die and can include one or more memory planes 101, each of which can include multiple memory blocks 103. The same simultaneous parallel operations can be performed in each memory plane 101. The memory blocks 103, which can have sizes in megabytes (MB), are the smallest size for performing erase operations. As shown in FIG. 1, the exemplary 3D memory device 100 includes four memory planes 101, each of which includes six memory blocks 103. Each memory block 103 can include multiple memory cells, each of which can be addressed through interconnects such as bit lines and word lines. The bit lines and word lines can be arranged vertically (e.g., in rows and columns, respectively) to form an array of metal lines. The bit line and word line directions are labeled as "BL" and "WL" in Figure 1. In this disclosure, memory block 103 is also referred to as a "memory array" or "array." A memory array is a core region within a memory device that performs storage functions.

[0052] The 3D memory device 100 also includes a peripheral region 105, which is the area surrounding the memory plane 101. The peripheral region 105 contains many digital, analog, and / or mixed-signal circuits to support the functionality of the memory array, such as page buffers, row and column decoders, and sense amplifiers. The peripheral circuits use active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., as will be apparent to those skilled in the art.

[0053] It should be noted that the arrangement of memory planes 101 in the 3D memory device 100 and the arrangement of memory blocks 103 in each memory plane 101 illustrated in FIG. 1 are used as examples only and are not intended to limit the scope of the present disclosure.

[0054] Referring to FIG. 2 , an enlarged top-down view of region 108 in FIG. 1 is illustrated, according to some embodiments of the present disclosure. Region 108 of 3D memory device 100 may include a staircase region 210 and a channel structure region 211. The channel structure region 211 may include an array of memory strings 212, each including a plurality of stacked memory cells. The staircase region 210 may include a staircase structure and an array of contact structures 214 formed on the staircase structure. In some embodiments, a plurality of slit structures 216 extending in the WL direction across the channel structure region 211 and the staircase region 210 may divide the memory block into a plurality of memory fingers 218. At least some of the slit structures 216 may function as common source contacts (e.g., array common source or ACS) for the array of memory strings 212 in the channel structure region 211. A top select gate cut 220 may be disposed, for example, in the middle of each memory finger 218 to divide the top select gate (TSG) of the memory finger 218 into two parts, thereby dividing the memory finger into two memory slices 224, and memory cells in the memory slices 224 that share the same word line form a programmable (read / write) memory page. While erase operations for 3D NAND memory may be performed at the memory block level, read and write operations may be performed at the memory page level. A memory page may have a size in kilobytes (KB). In some embodiments, region 108 also includes dummy memory strings 222 for process variation control during manufacturing and / or for additional mechanical support.

[0055] 3 illustrates a perspective view of a portion of an exemplary three-dimensional (3D) memory array structure 300 according to some embodiments of the present disclosure. The memory array structure 300 comprises a substrate 330, an insulating film 331 overlying the substrate 330, a tier of lower select gates (LSG) 332 overlying the insulating film 331, and multiple tiers of control gates 333, also referred to as “word lines (WL),” stacked on the LSG 332 to form a film stack 335 of alternating conductor and dielectric layers. Dielectric layers adjacent to the tiers of control gates are not shown in FIG. 3 for clarity.

[0056] The control gates of each tier are separated by slit structures 216-1 and 216-2 that penetrate the film stack 335. The memory array structure 300 also includes a tier of top select gates (TSGs) 334 overlying the stack of control gates 333. The stack of TSGs 334, control gates 333, and LSGs 332 is also referred to as a "gate electrode." The memory array structure 300 further includes memory strings 212 and doped source line regions 344 in a portion of the substrate 330 between adjacent LSGs 332. Each memory string 212 includes a channel hole 336 that penetrates the insulating film 331 and the film stack 335 of alternating conductor and dielectric layers. The memory string 212 also includes a memory film 337 on the sidewalls of the channel hole 336, a channel layer 338 overlying the memory film 337, and a core fill film 339 surrounded by the channel layer 338. At the intersections of the control gates 333 (e.g., 333-1, 333-2, 333-3) and the memory strings 212, memory cells 340 (e.g., 340-1, 340-2, 340-3) may be formed. A portion of the channel layer 338 is responsive to each control gate and is also referred to as the channel layer 338 of the memory cell. The memory array structure 300 further includes a plurality of bit lines (BLs) 341 connected together with the memory strings 212 overlying the TSGs 334. The memory array structure 300 also includes a plurality of metal interconnect lines 343 connected together with the gate electrodes through a plurality of contact structures 214. The edges of the film stack 335 are configured in a stepped shape to allow electrical connection to each tier of the gate electrode.

[0057] For illustrative purposes, FIG. 3 illustrates three tiers of control gates 333-1, 333-2, and 333-3, along with one tier of TSG 334 and one tier of LSG 332. In this example, each memory string 212 can include three memory cells 340-1, 340-2, and 340-3, corresponding to control gates 333-1, 333-2, and 333-3, respectively. In some embodiments, the number of control gates and the number of memory cells can be greater than three to increase storage capacity. The memory array structure 300 can also include other structures, such as TSG cuts, common source contacts (i.e., array common sources), and dummy memory strings. These structures are not shown in FIG. 3 for simplicity.

[0058] 4 illustrates a method 400 for forming a three-dimensional (3D) memory device according to some embodiments of the present disclosure. It should be understood that the process steps shown in method 400 are not exhaustive, and that other steps may similarly be performed before, after, or between any of the illustrated steps. In some embodiments, some process steps of method 400 are omitted, or other process steps not described herein for brevity may also be included. In some embodiments, the process steps of method 400 may be performed in a different order and / or varied.

[0059] 5, 6A-6B, and 7 through 16 illustrate example structures of a 3D memory device at specific process steps according to method 400. FIG.

[0060] 4, a first etch stop layer and a second etch stop layer may be disposed on the substrate in step S405. A cross-sectional view of an exemplary 3D memory structure 500 according to process step S405 is shown in FIG.

[0061] As shown in FIG. 5, the 3D memory structure 500 includes a first etch stop layer 550 and a second etch stop layer 552 disposed on the substrate 330 .

[0062] The substrate 330 can provide a platform for forming subsequent structures. In some embodiments, the substrate 330 can be any suitable semiconductor substrate having any suitable semiconductor material, such as a single-crystalline, polycrystalline, or monocrystalline semiconductor. For example, the substrate 330 can include silicon, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), gallium nitride, silicon carbide, a III-V compound, a II-VI compound, or any combination thereof.

[0063] In some embodiments, the substrate 330 can have a composite structure and include a semiconductor layer 547 formed on a handle wafer 545. The substrate 330 also includes an insulator layer 546 disposed between the semiconductor layer 547 and the handle wafer 545. The handle wafer 545 can include glass, plastic, or another semiconductor substrate. The semiconductor layer 547 can include any suitable single-crystalline, polycrystalline, or monocrystalline semiconductor, such as silicon, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), gallium nitride, silicon carbide, III-V compounds, II-VI compounds, or any combination thereof. The insulator layer 546 can include silicon oxide, silicon nitride, silicon oxynitride, TEOS, or any combination thereof. In some embodiments, the insulator layer 546 is silicon oxide, also referred to as a sacrificial silicon oxide layer. In some embodiments, the semiconductor layer 547 is polycrystalline silicon, also referred to as a sacrificial polycrystalline silicon layer. In some embodiments, the substrate 330 can be silicon-on-insulator (SOI), germanium-on-insulator (GOI), or silicon-germanium-on-insulator (SGOI), and the semiconductor layer 547 can be crystalline silicon, crystalline germanium, or crystalline silicon-germanium.

[0064] In some embodiments, the semiconductor layer 547 may be disposed on the insulator layer 546 and the handle wafer 545 by using a deposition method such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), rapid thermal chemical vapor deposition (RTCVD), low-pressure chemical vapor deposition (LPCVD), sputtering, metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), high-density plasma CVD (HDP-CVD), sputtering, evaporation, and / or a combination thereof. In some embodiments, the semiconductor layer 547 may be formed on the insulator layer 546 and the handle wafer 545 through wafer bonding, SIMOX, or the like.

[0065] The front surface 330f of the substrate 330 is also referred to herein as the "major surface" or "top surface" of the substrate. Layers of material may be disposed on the front surface 330f of the substrate 330. A "top" or "upper" layer is the layer furthest or further from the front surface 330f of the substrate. A "bottom" or "lower" layer is the layer closest or closer to the front surface 330f of the substrate.

[0066] In process step S405, a first etch stop layer 550 may be formed on the front surface 330f of the substrate 330, and a second etch stop layer 552 may be formed on the first etch stop layer 550. In some embodiments, the first etch stop layer 550 and the second etch stop layer 552 may be formed on the semiconductor layer 547 of the substrate 330. The first etch stop layer 550 and the second etch stop layer 552 extend in a lateral direction parallel to the front surface 330f of the substrate 330.

[0067] The first etch stop layer 550 and the second etch stop layer 552 can be used as etch stop layers in a subsequent etching process. The first etch stop layer 550 and the second etch stop layer 552 can be disposed by a thin film deposition process, such as CVD, PVD, ALD, sputtering, evaporation, and / or any combination thereof. In some embodiments, the first etch stop layer 550 can include silicon oxide, silicon nitride, silicon oxynitride, TEOS, etc. In some embodiments, the second etch stop layer 552 can include amorphous or polycrystalline silicon. It should be noted that the first etch stop layer 550 and the second etch stop layer 552 can include any suitable material having a predetermined etch selectivity (i.e., etch rate ratio) with respect to the material to be etched.

[0068] 4, in process step S410, an alternating dielectric stack may be disposed on a second etch stop layer overlying a substrate. In process step S415, a stair-step structure may be formed in the alternating dielectric stack. In process step S420, an insulating layer may be disposed over the substrate, covering the stair-step structure and the alternating dielectric stack. A cross-sectional view of an exemplary 3D memory structure 600 according to process steps S405-S420 is shown in FIG. 6A.

[0069] As shown in FIG. 6A, the 3D memory structure 600 includes an alternating dielectric stack 654 having a first dielectric layer 656 and a second dielectric layer 658 alternately stacked on the second etch stop layer 552.

[0070] In some embodiments, the alternating dielectric stack 654 includes multiple dielectric pairs alternately stacked along a vertical direction (i.e., the z-direction) perpendicular to the front surface 330f of the substrate 330, with each dielectric layer pair including a first dielectric layer 656 (also referred to as a "dielectric layer") and a second dielectric layer 658 (also referred to as a "sacrificial layer") that is different from the first dielectric layer 656. The alternating dielectric stack 654 extends in a lateral direction parallel to the front surface 330f of the substrate 330.

[0071] In the alternating dielectric stack 654, the first dielectric layers 656 and the second dielectric layers 658 alternate in a vertical direction perpendicular to the substrate 330. In other words, each second dielectric layer 658 is sandwiched between two first dielectric layers 656, and each first dielectric layer 656 can be sandwiched between two second dielectric layers 658 (excluding the bottom and top layers).

[0072] Forming the alternating dielectric stack 654 can include disposing first dielectric layers 656, each having the same thickness or having different thicknesses. An exemplary thickness of the first dielectric layers 656 can be in the range of 10 nm to 500 nm, preferably about 25 nm. Similarly, the second dielectric layers 658 can each have the same thickness or different thicknesses. An exemplary thickness of the second dielectric layers 658 can be in the range of 10 nm to 500 nm, preferably about 35 nm. It should be understood that the number of dielectric layer pairs in FIG. 6A is for illustrative purposes only, and that any suitable number of layers can be included in the alternating dielectric stack 654.

[0073] In some embodiments, the first dielectric layer 656 comprises any suitable insulating material, such as silicon oxide, silicon oxynitride, silicon nitride, TEOS, or silicon oxide loaded with F-, C-, N-, and / or H-. The first dielectric layer 656 can also comprise a high-k dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, or lanthanum oxide film. In some embodiments, the first dielectric layer 656 can be any combination of the above materials.

[0074] Formation of the first dielectric layer 656 may include any suitable deposition method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), rapid thermal chemical vapor deposition (RTCVD), low-pressure chemical vapor deposition (LPCVD), sputtering, metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), high-density plasma CVD (HDP-CVD), sputtering, evaporation, thermal oxidation, nitridation, other suitable deposition methods, and / or combinations thereof.

[0075] In some embodiments, the second dielectric layer 658 is different from the first dielectric layer 656 and comprises any suitable material that can be selectively removed with respect to the first dielectric layer 656. For example, the second dielectric layer 658 can include silicon oxide, silicon oxynitride, silicon nitride, TEOS, polycrystalline silicon, polycrystalline germanium, polycrystalline germanium silicon, and any combination thereof. In some embodiments, the second dielectric layer 658 also comprises an amorphous semiconductor material, such as amorphous silicon or amorphous germanium. The second dielectric layer 658 can be disposed using a technique similar to that of the first dielectric layer 656, such as CVD, PVD, ALD, sputtering, evaporation, thermal oxidation or nitridation, or any combination thereof.

[0076] In some embodiments, the first dielectric layer 656 may be silicon oxide and the second dielectric layer 658 may be silicon nitride.

[0077] In some embodiments, the alternating dielectric stack 654 can include layers in addition to the first dielectric layer 656 and the second dielectric layer 658, which can be made of different materials and / or different thicknesses.

[0078] As shown in FIG. 6A, the 3D memory structure 600 also includes a staircase structure 657 having a plurality of staircase steps 659 formed in the alternating dielectric stack 654 within the staircase region 210. The staircase steps 659, or "staircase layers," refer to layer stacks having the same lateral dimension in a surface parallel to the substrate surface 330f. Each of the staircase steps 659 terminates at a lateral dimension "a," shown in FIG. 6A, that is shorter than the staircase step below it.

[0079] In some embodiments, each of the staircase steps 659 includes one pair of a first dielectric layer 656 and a second dielectric layer 658. In some embodiments, each of the staircase steps 659 includes two or more pairs of a first dielectric layer 656 and a second dielectric layer 658. As shown in FIG. 6A , each of the staircase steps 659 includes one pair of a first dielectric layer 656 and a second dielectric layer 658, with the second dielectric layer 658 overlying the first dielectric layer 656. Each of the staircase steps 659 exposes a portion of the second dielectric layer 658 at the end of the alternating dielectric stack 654.

[0080] The stair-like structure 657 can be formed by applying a repeated etch-trim process to the alternating dielectric stack 654. The etch-trim process includes an etching process and a trimming process. During the etching process, a portion of the stair-like step 659 whose surface is exposed can be removed. The remaining portion of the stair-like step 659 is either covered by the upper level of the stair-like step or by a patterning mask and is not etched. The etching depth is the thickness of the stair-like step 659. In some embodiments, the thickness of the stair-like step 659 is the thickness of one pair of the first dielectric layer 656 and the second dielectric layer 658. The etching process for the first dielectric layer 656 can have high selectivity over the second dielectric layer 658, and / or vice versa. Therefore, the underlying dielectric layer pair can function as an etch stop layer. By switching the etching process for each layer, the stair-like step 659 can be etched during one etching cycle. As a result, one of the stair-like steps 659 can be formed during each etching-trim cycle.

[0081] In some embodiments, the stair-like steps 659 can be etched using an anisotropic etch, such as a reactive ion etch (RIE) or other dry etching process. In some embodiments, the first dielectric layer 656 is silicon oxide. In this example, the silicon oxide etch can include RIE using a fluorine-based gas, such as carbon-fluorine (CF), hexafluoroethane (CF), CHF, or CF, and / or any other suitable gas. In some embodiments, the silicon oxide layer can be removed by wet chemistry, such as hydrofluoric acid or a mixture of hydrofluoric acid and ethylene glycol. In some embodiments, a timed etch approach can be used. In some embodiments, the second dielectric layer 658 is silicon nitride. In this example, the silicon nitride etch can include RIE using O, N, CF, NF, Cl, HBr, BCl, and / or combinations thereof. The method and etchant for removing the monolayer stack should not be limited by the embodiments of the present disclosure.

[0082] The trimming process includes subjecting the patterning mask to an appropriate etching process (e.g., isotropic dry etching or wet etching) so that the patterning mask can be pulled back laterally. The lateral pullback dimension determines the lateral dimension “a” of each step of the staircase structure 657. After trimming the patterning mask, a portion of the top staircase step 659 is exposed, and another portion of the top staircase step 659 remains covered by the patterning mask. The next cycle of the etch trim process resumes with the etching process. In some embodiments, the patterning mask trimming process can include dry etching, such as RIE using O, Ar, N, or the like. It should be noted that the number of staircase structures and the number of dielectric layer pairs in the 3D memory structure 600 are not limited to the examples herein.

[0083] As shown in FIG. 6A , the 3D memory structure 600 also includes an insulating layer 660 disposed over the substrate and covering the staircase structure 657, the alternating dielectric stack 654, and a portion of the second etch stop layer 552. The insulating layer 660 may include any suitable insulating material, such as silicon oxide, silicon oxynitride, silicon nitride, TEOS, spin-on glass, a low-k dielectric material such as carbon-doped oxide (CDO or SiOC or SiOC:H), or fluorine-doped oxide (SiOF), etc. The insulating layer 660 may be disposed by CVD, PVD, ALD, sputtering, evaporation, etc. In some embodiments, the insulating layer 660 may have a planar top surface over the staircase structure 660 and the alternating dielectric stack 654. The insulating layer 660 may be planarized using CMP and / or RIE etchback.

[0084] In some embodiments, a barrier layer (not shown in FIG. 6A ) can be disposed on the stair-like structure and alternating dielectric stack before disposing the insulating layer 660. The barrier layer can cover the stair-like structure 657 and the alternating dielectric stack 654 on both the outer surfaces and the vertical sidewalls. The barrier layer on the outer surfaces and the vertical sidewalls can have the same thickness or different thicknesses. The barrier layer can function as an etch stop for forming contact structures on the stair-like steps.

[0085] Upon completion of process step S420, a stair-like structure 657 is formed in the stair-like region 210, which may be used to form electrical contacts to word lines in subsequent processes. In the peripheral region 105, an insulating layer 660 covers the first / second etch stop layers 550 / 552 and the substrate 330, and electrical contacts to peripheral circuitry may be formed in subsequent processes. In some embodiments, peripheral devices may be formed in the peripheral region 105 on the front side 330f of the substrate 330. The peripheral devices may include any suitable semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), diodes, resistors, capacitors, etc. The peripheral devices may be used in the design of digital, analog, and / or mixed-signal circuits that support the storage functions of the memory core, such as row and column decoders, drivers, page buffers, sense amplifiers, timing, and control.

[0086] 6B illustrates an example peripheral circuit 600B in the peripheral region 105 according to some embodiments of the present disclosure. The peripheral circuit 600B may be part of the 3D memory structure 600 shown in FIG. 6A. The peripheral circuit 600B may be formed before the alternating dielectric stack 654 is disposed. The peripheral circuit 600B may also be formed after the staircase structure 657 is formed. It should be noted that the order of forming the peripheral circuit 600B in the peripheral region 105 and the staircase structure 657 in the staircase region 210 is not limited to the example described above.

[0087] The peripheral circuit 600B can include one or more peripheral devices 50 on the front side of the substrate 330 (e.g., semiconductor layer 547). The peripheral devices 50 can be formed “on” the substrate 330, where all or a portion of the peripheral devices 50 are formed in the substrate 330 (e.g., below the front side 330f of the substrate 330) and / or directly on the substrate 330. The peripheral devices 50 can include any suitable semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), diodes, resistors, capacitors, inductors, etc. Of the semiconductor devices, p-type and / or n-type MOSFETs (i.e., CMOS) are widely implemented in logic circuit designs and are used as examples of the peripheral devices 50 in this disclosure.

[0088] The peripheral device 50 may be either a p-channel or n-channel MOSFET and may include, but is not limited to, an active device region surrounded by shallow trench isolation (STI) 52, a well 54 formed in the active device region with n-type or p-type doping, and a gate stack 56 including a gate dielectric, a gate conductor, and / or a gate hard mask. The peripheral device 50 may also include source / drain extensions and / or halo regions (not shown in FIG. 6B ), gate spacers 58, and source / drains 60 disposed on each side of the gate stack. The peripheral device 50 may further include silicide contact regions (not shown) on top of the source / drains. Other known devices may also be formed on the substrate 330. The structure and fabrication methods of the peripheral device 50 are known to those skilled in the art and are incorporated herein in their entirety.

[0089] Peripheral device 50 can be formed on a substrate 330 having a planar active device region (as shown in FIG. 6B ), with the MOSFET's channel and current flow direction parallel to the front surface 330f of substrate 330. In some embodiments, peripheral device 50 can be a 3D active device region, e.g., a so-called "FINFET" (not shown) shaped like a "FIN," formed on substrate 330, with the MOSFET's gate stack wrapped around the FIN and the MOSFET's channel along three sides of the FIN (the top and two sidewalls under the gate). FINFET device structures and methods are known to those skilled in the art and will not be further described in this disclosure.

[0090] In some embodiments, the peripheral circuit 600B includes a peripheral interconnect layer 62 above the peripheral devices 50, which can provide electrical connections between different peripheral devices 50 and external devices (e.g., power supplies, another chip, I / O devices, etc.). In some embodiments, the peripheral interconnect layer 62 can be formed in an insulating layer 660. In some embodiments, the peripheral interconnect layer 62 can be formed in an insulating layer different from the insulating layer 660 of FIG. 6A.

[0091] The peripheral interconnect layer 62 may include one or more interconnect structures, such as one or more vertical contact structures 64 and one or more lateral conductive lines 66. The contact structures 64 and conductive lines 66 may broadly include any suitable type of interconnect, such as middle-of-the-line (MOL) interconnects and back-end-of-the-line (BEOL) interconnects. The contact structures 64 and conductive lines 66 of the peripheral circuit 600B may be made of tungsten (W), cobalt (Co), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (WSi), or other metals. x , CoSi x , NiSi x , AlSi xThe conductive material may comprise any suitable conductive material, such as a metal alloy, a metal nitride, a silicon nitride, a silicon nitride film ...

[0092] 6B, two conductive levels 70-1 and 70-2 (also referred to as "metal levels") are illustrated as an example, with each metal level 70 (e.g., 70-1 or 70-2) including contact structures 64 and conductive lines 66. Conductive lines 66 on the same metal level are disposed at the same distance from the substrate 330. The number of metal levels 70 for the peripheral circuit 600B is not limited and may be any number optimized for the performance of the 3D memory.

[0093] The peripheral interconnect layer 62 may be formed by stacking metal levels 70 from the bottom to the top of the peripheral circuit 600B. In the example of the peripheral circuit 600B of Figure 6B, a bottom metal level 70-1 may be formed first, and then an upper metal level 70-2 may be formed on top of the bottom metal level 70-1.

[0094] In some embodiments, the peripheral circuit 600B also includes one or more substrate contacts 72, which provide electrical connection to the substrate 330. The substrate contacts 72 may include one or more conductive levels 70 having multiple tiers of vertical contact structures 64 and lateral conductive lines 66. In Figure 6B, a substrate contact 72 having one tier of contact structures and conductive lines is shown as an example, with the vertical contact structure of the substrate contact 72 penetrating the insulating layer 660 and making electrical contact with the substrate 330.

[0095] However, the peripheral devices 50 are not limited to MOSFETs. Other device structures, such as diodes, resistors, capacitors, inductors, and BJTs, can be formed simultaneously during MOSFET fabrication through different mask designs and layouts. To form devices other than MOSFETs, process steps can be added or modified in the MOSFET process flow, such as processes to achieve different dopant profiles, film thicknesses, or material stacks. In some embodiments, peripheral devices 50 other than MOSFETs can also be fabricated through additional design and / or lithography mask levels to achieve specific circuit requirements. The peripheral devices 50 can be used to form any digital, analog, and / or mixed-signal circuitry for the operation of the peripheral circuit 600B. The peripheral circuit 600B can perform, for example, row / column decoding, timing and control, reading, writing, and erasing data from a memory array, and the like.

[0096] 4, in process step S425, a plurality of channel holes and a plurality of dummy channel holes may be formed in the channel structure region and the stepped region, respectively. A memory film and a channel layer may be disposed on the sidewalls of each channel hole. A cross-sectional view of an exemplary 3D memory structure 700 according to process step S425 is shown in FIG.

[0097] 7, the 3D memory structure 700 includes a plurality of channel holes 336 in the channel structure region 211. The plurality of channel holes 336 vertically penetrate the insulating layer 660 and the alternating dielectric stack 654. In some embodiments, the plurality of channel holes 336 further penetrates through the second etch stop layer 552 and the first etch stop layer 550 and penetrates into the substrate 330, for example, into the semiconductor layer 547.

[0098] Techniques used to form the channel hole 336 may include processes such as photolithography and etching. The etching process for forming the channel hole 336 may also include dry etching, wet etching, or a combination thereof. In some embodiments, the alternating dielectric stack 654 may be etched using anisotropic etching such as reactive ion etching (RIE). In some embodiments, fluorine-based or chlorine-based gases such as fluorocarbon (CF), hexafluoroethane (CF), CHF, CF, Cl, BCl, or any combination thereof may be used. The method and etchant for etching the first dielectric layer 656 and the second dielectric layer 658 should not be limited by the embodiments of the present disclosure. In some embodiments, the semiconductor layer 547 can function as an etch stop during the etching process of the channel hole 336 to prevent the channel hole 336 from penetrating further into the insulator layer 546 and the handle wafer 545.

[0099] After forming the channel hole 336, a memory film 337 may be disposed on the sidewall of the channel hole 336. In some embodiments, the memory film 337 may be a composite layer including a tunnel layer 3373, a storage layer 3372 (also referred to as a "charge trap / storage layer"), and a blocking layer 3371. In some embodiments, the tunnel layer 3373, the storage layer 3372, and the blocking layer 3371 are arranged in the above order along a direction from the center of the channel hole 336 toward the outside of the channel hole 336. The tunnel layer 3373 may include silicon oxide, silicon nitride, or any combination thereof. The blocking layer 3371 may include silicon oxide, silicon nitride, a high-k dielectric, or any combination thereof. The storage layer 3372 may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the memory film 337 includes an ONO dielectric (e.g., a tunnel layer 3373 including silicon oxide, a storage layer 3372 including silicon nitride, and a blocking layer 3371 including silicon oxide). The memory film 337 may be formed by using a thin film deposition process such as ALD, CVD, PVD, sputtering, or any other suitable process. In some embodiments, the thickness of the memory film 337 may be in the range of about 10 nm to about 50 nm.

[0100] A channel layer 338 and a core fill film 339 may then be disposed in the channel hole 336, with the channel layer 338 covering the sidewalls of the memory film 337 inside the channel hole 336. The channel layer 338 may be any suitable semiconductor material, such as silicon. In some embodiments, the channel layer 338 may be amorphous, polysilicon, or monocrystalline silicon. The channel layer 338 may be formed by any suitable thin film deposition process, including, but not limited to, CVD, PVD, ALD, sputtering, evaporation, or a combination thereof. In some embodiments, the thickness of the channel layer 338 may be in the range of about 10 nm to about 30 nm.

[0101] In some embodiments, the core fill film 339 may be disposed to fill the channel hole 336 to form the channel structure 761. In some embodiments, the center of the core fill film 339 may include one or more seams 860. The core fill film 339 may be any suitable insulator, such as silicon oxide, silicon nitride, silicon oxynitride, spin-on glass, boron- or phosphorus-doped silicon oxide, carbon-doped oxide (CDO or SiOC or SiOC:H), fluorine-doped oxide (SiOF), or any combination thereof. The core fill film 339 may be deposited, for example, by using ALD, PVD, CVD, spin coating, sputtering, or any other suitable film deposition technique. The core fill film 339 may also be formed by using a repeated deposition and etch-back process. The etch-back process may include, but is not limited to, wet etching, dry etching, or a combination thereof. In some embodiments, one or more seams may be formed in the core fill film 339 to reduce mechanical stress.

[0102] In some embodiments, the 3D memory structure 700 also includes a channel top plug 762 at the top of the channel structure 761. The channel top plug 762 can form electrical contact with the channel layer 338 inside the channel hole 336. The channel top plug 762 can be amorphous or polycrystalline silicon and can include a metal, a metal alloy, and / or a metal silicide, such as tungsten, titanium, tantalum, tungsten nitride, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, or a combination thereof. The channel top plug 762 can be formed by a recess etching process followed by thin film deposition. The recess etching process can include wet etching, dry etching, or a combination thereof. The thin film deposition can include CVD, PVD, ALD, sputtering, or any other suitable process.

[0103] In some embodiments, the 3D memory device 700 may also include an epitaxial plug (not shown) at the bottom of the channel structure 761. The epitaxial plug may comprise any suitable semiconductor material, such as silicon, silicon germanium, germanium, gallium arsenide, gallium nitride, III-V compounds, or any combination thereof. The epitaxial plug may be epitaxially grown from the substrate 330 (e.g., the semiconductor layer 547). In some embodiments, the epitaxial plug may also comprise a polycrystalline semiconductor material, such as polycrystalline silicon. In some embodiments, a portion of the memory film 337 at the bottom of the channel hole 336 may be removed to allow the channel layer 338 to be in direct contact with the epitaxial plug.

[0104] It should be noted that the number and arrangement of the channel structures 761 in the channel structure region 211 may be designed according to actual storage requirements and is not limited to the example shown in Fig. 7. As previously described with respect to Fig. 2, the channel structure region 211 provides the storage function of a three-dimensional memory.

[0105] 7, the 3D memory structure 700 also includes a plurality of dummy channel holes (DCHs) 764 in the stepped region 210. The DCHs 764 penetrate through the insulating layer 660, a portion of the stepped structure 657 (i.e., a portion of the alternating dielectric stack 654), the second etch stop layer 552, and the first etch stop layer 550, and into the substrate 330 (e.g., the semiconductor layer 547). Formation of the DCHs 764 includes lithography and etching, and the etching process can include dry etching, wet etching, and / or a combination thereof. In some embodiments, the etching process for the DCHs 764 includes anisotropic etching, such as RIE.

[0106] After forming the DCH 764, a DCH filler 765 can be disposed inside the DCH 764, thereby forming a dummy channel structure 763. The DCH filler 765 can include any suitable insulator, such as silicon oxide, silicon nitride, silicon oxynitride, TEOS, a high-k dielectric material (Al2O3, HfO2, Ta2O3, ZrO2, La2O3, etc.), or any combination thereof. The DCH filler 765 can be disposed by any suitable thin film deposition technique, such as CVD, ALD, PVD, sputtering, evaporation, etc. In some embodiments, one or more seams can be formed in the DCH filler 765 to reduce mechanical stress. The dummy channel structure 763 formed in the stepped region 210 can be configured to provide mechanical support for the 3D memory structure in subsequent processes.

[0107] In some embodiments, the channel structure 761 and the dummy channel structure 763 may be planarized to have a coplanar surface. The planarization process includes RIE etchback, CMP, or a combination thereof.

[0108] The 3D memory structure 700 also includes a first capping layer 766 disposed on the insulating layer 660 to cover the channel structure 761 in the channel structure region 211 and the dummy channel structure 763 in the stepped region 210. The first capping layer 766 may include silicon oxide, silicon nitride, silicon oxynitride, TEOS, or a combination thereof. The first capping layer 766 may be deposited by CVD, PVD, ALD, sputtering, etc.

[0109] Referring to FIG. 4, in process step S430, gate line slit (GLS) openings can be formed in the alternating dielectric stack. In process step S435, a second dielectric layer in the alternating dielectric stack can be replaced with a conductive layer, thereby forming a film stack of alternating conductive and dielectric layers. In process step S440, a GLS filler material can be disposed inside the GLS openings to form the GLS. A cross-sectional view of an exemplary 3D memory structure 800 according to process steps S430-S440 is shown in FIG. 8.

[0110] As shown in FIG. 8 , the 3D memory structure 800 includes gate line slit (GLS) openings 869 formed in the alternating dielectric stacks 654. The GLS openings 869 penetrate through the insulating layer 660 and the alternating dielectric stacks 654. In some embodiments, the GLS openings 869 also penetrate through the second etch stop layer 552 and the first etch stop layer 550 and further into the substrate 330 (e.g., into the semiconductor layer 547). The GLS openings 869 may be formed by lithography and etching processes. The etching process may include any suitable dry etching, wet etching, and / or a combination thereof. In a subsequent process, the GLS openings 869 may be used to form the slit structures 216 as illustrated in FIG. 2 .

[0111] In process step S435, the second dielectric layer 658 (in FIG. 7 ) in the alternating dielectric stack 654 and the staircase structure 657 can be removed through the GLS opening 869 to form a lateral tunnel. The lateral tunnel can extend laterally between adjacent first dielectric layers 656. Note that the term “lateral / lateral / outer” as used herein refers to a plane parallel to the top surface 330f of the substrate 330. The second dielectric layer 658 in the alternating dielectric stack 654, also referred to as a sacrificial layer, can be selectively removed from between the first dielectric layers 656. In other words, the etching process for the second dielectric layer 658 can minimize the impact on the first dielectric layer 656. The second dielectric layer 658 can be removed by isotropic dry etching and / or wet etching. The plasma and / or chemicals used in the dry / wet etching can move vertically and laterally from the GLS opening 869. In some embodiments, the second dielectric layer 658 may be silicon nitride and the first dielectric layer 656 may be silicon oxide. In this example, the second dielectric layer 658 may be removed by RIE using one or more etchants such as CF, CHF, C, F, C, F, and CHF. In some embodiments, the second dielectric layer 658 may be removed using a wet etch such as phosphoric acid.

[0112] A conductive layer 870 may then be disposed inside the lateral tunnel through the GLS opening 869. The conductive layer 870 may be disposed between adjacent first dielectric layers 656, and the conductive layer 870 and the first dielectric layer 656 may form a film stack 335 of alternating conductive and dielectric layers (as in FIG. 3 ).

[0113] In some embodiments, the conductive layer 870 can be formed by filling the lateral tunnel with a suitable conductive material. The conductive material of the conductive layer 870 can include a metal or metal alloy, such as tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), cobalt (Co), nickel (Ni), titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), AlTi, or any combination thereof. In some embodiments, the conductive material of the conductive layer 870 can also include a polycrystalline semiconductor, such as polycrystalline silicon, polycrystalline germanium, polycrystalline germanium silicon, and any other suitable material and / or combination thereof. In some embodiments, the polycrystalline material can be incorporated with any suitable type of dopant, such as boron, phosphorus, arsenic, or any combination thereof. In some embodiments, the conductive layer 870 can also be an amorphous semiconductor, such as amorphous silicon. In some embodiments, the conductive material may be disposed using a suitable deposition method, such as chemical vapor deposition (CVD) (e.g., LPCVD, PECVD, MOCVD, RTCVD, etc.), physical vapor deposition (PVD), sputtering, evaporation, atomic layer deposition (ALD), or any combination thereof. In some embodiments, the conductive layer 870 comprises tungsten (W) deposited by CVD.

[0114] As described above, by replacing the second dielectric layer 658 with the conductive layer 870, the alternating dielectric stack 654 is transformed into a film stack 335 of alternating conductive and dielectric layers. Thus, the channel structures 761 formed in the alternating dielectric stack 654 become memory strings 212, and the intersections of the memory strings 212 and the film stack 335 form vertically stacked memory cells 340. Although the film stack 335 here is formed by a substitution method (i.e., replacing the second dielectric layer 658 with the conductive layer 870), it should be understood that the film stack 335 may also be formed by other approaches, such as by directly disposing the conductive layer 870 and the first dielectric layer 656 on the substrate 330.

[0115] In some embodiments, a gate dielectric layer 872 can be disposed in the lateral tunnel before disposing the conductive layer 870. The gate dielectric layer 872 can include any suitable insulator, such as silicon oxide, silicon nitride, silicon oxynitride, and / or any suitable combination thereof. The gate dielectric layer 872 can also include a high-k dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, and / or any combination thereof. The gate dielectric layer 872 can be disposed by one or more suitable deposition processes, such as CVD, PVD, and / or ALD.

[0116] In some embodiments, prior to disposing the conductive layer 870, a gate adhesion layer 874 may be disposed on the gate dielectric layer 872. The gate adhesion layer 874 may be used to promote adhesion between the gate dielectric layer 872 and the conductive layer 870. The gate adhesion layer 874 may include, for example, tantalum nitride (TaN) and / or titanium nitride (TiN).

[0117] In some embodiments, an etching and cleaning process can be used to remove excess conductive material on the sidewalls of the GLS opening 869. As such, each conductive layer 870 of the film stack 335 can be electrically isolated from one another. In some embodiments, the conductive layers 870 can be recessed back from the sidewalls of the GLS opening 869. In some embodiments, excess conductive material on the first capping layer 766 can also be removed, for example, by CMP.

[0118] Next, a GLS filler 871 can be disposed inside the GLS opening 869, thereby forming a slit structure 216 (also referred to as a GLS), as shown in FIGS. 2-3 and 8. The GLS 216 penetrates vertically through the insulating layer 660, the film stack 335 of alternating conductive and dielectric layers, and into the substrate 330. The GLS filler 871 can include any suitable insulator, such as silicon oxide, silicon nitride, silicon oxynitride, boron- or phosphorus-doped silicon oxide, carbon-doped oxide (CDO or SiOC or SiOC:H), fluorine-doped oxide (SiOF), or any combination thereof. The GLS filler 871 can be deposited, for example, by using ALD, CVD (e.g., PECVD, RTCVD, LPCVD, etc.), PVD, sputtering, evaporation, or any other suitable film deposition technique. In some embodiments, the GLS fill material 871 outside the GLS opening 869 can be removed by etching (e.g., RIE) and / or CMP. As such, the GLS 216 can be coplanar with the first capping layer 766. As mentioned above, the GLS 216 can divide the memory block into multiple functional units (e.g., memory fingers). The GLS 216 can also provide mechanical support within the channel structure region 211.

[0119] In some embodiments, a second capping layer 868 can be disposed on the first capping layer 766 to cover the GLS 216. The second capping layer 868 can include silicon oxide, silicon nitride, silicon oxynitride, TEOS, or a combination thereof. The second capping layer 868 can be deposited by CVD, PVD, ALD, sputtering, etc.

[0120] 4, in process step S445, through silicon vias (TSVs) can be formed in the peripheral region. A cross-sectional view of an exemplary 3D memory structure 900 according to process step S445 is shown in FIG.

[0121] 9 , the 3D memory structure 900 includes TSVs 976 that vertically penetrate the second capping layer 868, the first capping layer 766, and the insulating layer 660. In some embodiments, the TSVs 976 also penetrate the second etch stop layer 552 and the first etch stop layer 550 and further into the substrate 330 (e.g., into the semiconductor layer 547). In some embodiments, one or more of the TSVs 976 can be electrically connected to contact structures 64, conductive lines 66, or substrate contacts 72 in the peripheral circuit 600B (shown in FIG. 6B ) to provide electrical connection to the peripheral device 50. The number and layout of the TSVs 976 may be adjusted accordingly and are not limited to the example shown in FIG. 9 .

[0122] To form the TSV 976, a TSV opening may be formed by lithography and etching. The etching process for the TSV 976 may include dry etching, wet etching, and / or a combination thereof. When the insulating layer 660 is silicon oxide, anisotropic RIE with a chemical etchant, such as CF4, CHF3, C2F6, C3F6, and / or any combination thereof, may be used to etch the silicon oxide. The etching processes and chemistries listed here are merely examples and should not be limited. Next, a conductive material may be disposed inside the TSV opening. The TSV 976 may include any suitable conductive material, such as a metal or metal compound, such as tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), and / or any combination thereof. The metal or metal compound may be disposed by using a suitable deposition method such as CVD, PVD, ALD, sputtering, evaporation, or the like.

[0123] In some embodiments, the TSVs 976 can have a shape similar to a cylinder, a cube, or any other shape. In some embodiments, prior to disposing the conductive material, a TSV interface layer 978 can be disposed on the sidewalls of the TSV openings by a suitable thin film deposition technique, such as CVD, PVD, ALD, sputtering, etc. The TSV interface layer 978 can include TiN, TaN, etc.

[0124] In some embodiments, the formation of TSV 976 may include a planarization process, such as CMP, to remove excess conductive material above second capping layer 868. As shown in FIG. 9 , TSV 976 may be flush with second capping layer 868.

[0125] It should be understood that the channel holes 336 (or memory strings 212), the dummy channel holes 764 (or dummy channel structures 763), the GLS 216, and the TSVs 976 can have the same or different depths inside the substrate 330.

[0126] 4, it can be seen that in process step S450, the substrate can be removed, stopping on the first etch stop layer so that a portion of the memory film that penetrates into the substrate can be exposed. A cross-sectional view of an exemplary 3D memory structure 1000 according to process step S450 is shown in FIG.

[0127] 9 and 10 , the 3D memory structure 1000 is a 180° rotation of the 3D memory structure 900, and the substrate 330 may be removed from the back side of the substrate 330 (i.e., the side opposite the front side 330f and farther from the film stack 335). In some embodiments, the handle wafer 545 of the substrate 330 may be first removed by a process such as wafer grounding, CMP, and / or dry / wet etching, stopping on the insulator layer 546. In other words, the process of removing the handle wafer 545 may be selective to the insulator layer 546. For example, the etch rate of the handle wafer 545 may be much faster than the etch rate of the insulator layer 546. Next, the insulator layer 546 may be removed by, for example, a dry etching or wet etching process, stopping on the semiconductor layer 547. In other words, the process of removing the insulator layer 546 may be selective to the semiconductor layer 547. For example, the etch rate of insulator layer 546 can be much faster than the etch rate of semiconductor layer 547. Semiconductor layer 547 can then be removed by a dry or wet etching process, stopping on first etch stop layer 550. In other words, the process of removing semiconductor layer 547 can be selective to first etch stop layer 550. For example, the etch rate of semiconductor layer 547 can be much faster than the etch rate of first etch stop layer 550.

[0128] In some embodiments, the process of removing the substrate 330 and / or removing the semiconductor layer 547 may also be selective to the memory film 337 (e.g., the blocking layer 3371) of the memory string 212. Thus, after removing the substrate 330, portions of the memory film 337 (e.g., the blocking layer 3371) that penetrate into the substrate 330 may be exposed. The memory string 212 with the exposed portions of the memory film 337 protrudes out of the first etch stop layer 550 from the back side of the film stack 335 (i.e., the side of the film stack 335 closer to the substrate 330 or the first etch stop layer 550). Similarly, portions of the TSVs 976, the dummy channel structures 763, and the GLSs 216 that penetrate into the substrate 330 may be exposed from the back side of the film stack 335 after removing the substrate 330.

[0129] By adding an etch stop layer and using a selective etching process, the process uniformity for removing the substrate can be significantly improved.

[0130] 4, in process step S455, the exposed portions of the first etch stop layer and memory film can be removed to expose a portion of the channel layer. A cross-sectional view of an exemplary 3D memory structure 1100 according to process step S455 is shown in FIG.

[0131] 10 and 11 , the first etch stop layer 550 can be removed from the 3D memory structure 1000 to form the 3D memory structure 1100. The first etch stop layer 550 can be removed, for example, by a dry etching or a wet etching process, and the etching process can stop at the second etch stop layer 552. In other words, the process of removing the first etch stop layer 550 can be selective to the second etch stop layer 552. For example, the etch rate of the first etch stop layer 550 can be significantly faster than the etch rate of the second etch stop layer 552.

[0132] In some embodiments, the etching process of the first etch stop layer 550 can also remove exposed portions of the memory film 337 (i.e., portions that penetrate into the substrate 330) and can also be selective to the channel layer 338 of the memory string 212. In other words, the exposed portions of the memory film 337 can be removed and stop on the underlying channel layer 338. For example, the etch rate of the memory film 337 can be significantly faster than the etch rate of the channel layer 338. As such, a portion of the channel layer 338 of the memory string 212 can be exposed from the backside of the film stack 335.

[0133] In some embodiments, the memory film 337 may be pulled back (or recessed) further into the film stack 335 to expose a greater portion of the channel layer 338 from the backside of the film stack 335 .

[0134] In some embodiments, the etching process of the first etch stop layer 550 and the memory film 337 may also be selective to the dummy channel structures 763, the GLS216, and the TSVs 976. Thus, a portion of the dummy channel structures 763, a portion of the GLS216, and a portion of the TSVs 976 may be exposed from the back surface of the film stack 335. The exposed portions of the dummy channel structures 763, the exposed portions of the GLS216, and the exposed portions of the TSVs 976 protrude out from the back surface of the film stack 335 and out from the second etch stop layer 552.

[0135] By implementing the second etch stop layer 552, the exposed portions of the memory film 337 can be controllably removed from the backside of the film stack without affecting the underlying film stack 335. The uniformity of the exposed portions of the channel layer 338 can also be improved. By controllably recessing the memory film 337 below the second etch stop layer 552 (i.e., into the film stack 335), the exposed portions of the channel layer 338 can be controlled.

[0136] 4, in process step S460, an array common source (ACS) can be formed on the backside of the second etch stop layer. A cross-sectional view of an exemplary 3D memory structure 1200 according to process step S460 is shown in FIG.

[0137] 12, the 3D memory structure 1200 includes an ACS 1280 disposed on the back surface of the second etch stop layer 552, the back surface of the second etch stop layer 552 being the side farther away from the film stack 335. In some embodiments, the ACS 1280 includes one or more polycrystalline silicon layers.

[0138] As illustrated in FIG. 12 , ACS 1280 includes a first polycrystalline silicon layer 1281 and a second polycrystalline silicon layer 1282. A thin film deposition process, such as CVD, PVD, ALD, sputtering, evaporation, or any combination thereof, can be used to deposit first polycrystalline silicon layer 1281 on the back surface of second etch stop layer 552, covering exposed portions of memory strings 212, GLS 216, dummy channel structures 763, and TSVs 976. Next, first polycrystalline silicon layer 1281 can be doped with p-type or n-type dopants using, for example, an ion implantation process, followed by an annealing process (e.g., laser annealing, rapid thermal annealing, etc.) to activate the dopants and reduce defects caused by the ion implantation process. Similarly, second polycrystalline silicon layer 1282 can be disposed on first polycrystalline silicon layer 1281 from the back surface using a similar technique (e.g., ion implantation and annealing). The second polycrystalline silicon layer 1282 can have a different dopant and / or dopant concentration than the first polycrystalline silicon layer 1281. In some embodiments, the ACS 1280 can include one or more polycrystalline silicon layers that are in-situ doped during deposition (e.g., CVD, PVD, ALD, etc.).

[0139] In the 3D memory structure 1200, the ACS 1280 can contact the exposed portion of the channel layer 338, thereby providing electrical connection to the channel layer 338 of the memory string 212. As previously described, the exposed portion of the channel layer 338 can be increased by recessing the memory film 337. The contact area between the ACS 1280 and the channel layer 338 can also be increased. Therefore, the contact resistance between the ACS 1280 and the channel layer 338 of the memory string 212 can be reduced, and the performance of the 3D memory can be improved. Note that the ACS can contact the channel layer 338 of multiple memory strings 212. In some embodiments, the ACS can provide electrical connection to all memory strings 212 in the same memory block. In some embodiments, the ACS 1280 can also cover exposed portions of the dummy channel structures 763, the GLS 216, and the TSVs 976.

[0140] In some embodiments, the second etch stop layer 552 can also be used as a spacer between the film stack 335 and ACS1280. By adjusting the thickness of the second etch stop layer 552, the distance between ACS1280 and the conductive layer 870 (i.e., the word line 333 as in FIG. 3) can be effectively controlled.

[0141] 4, a dielectric fill layer may be disposed on the backside of the ACS in process step S465. A cross-sectional view of an exemplary 3D memory structure 1300 in accordance with process step S465 is shown in FIG.

[0142] 13, a dielectric fill layer 1384 may be disposed on the back surface (i.e., the side farther away from the film stack 335) of the ACS 1280. The dielectric fill layer 1384 may be disposed by any suitable thin film deposition technique, for example, CVD (e.g., high-density plasma chemical vapor deposition), PVD, ALD, sputtering, evaporation, or a combination thereof. The first dielectric fill layer 1384 may include silicon oxide, silicon nitride, silicon oxynitride, TEOS, or the like. In some embodiments, a CMP process may be used to planarize the back surface (the side farther away from the film stack 335) of the dielectric fill layer 1384.

[0143] 4, in process step S470, first and second contact openings are formed in the dielectric fill layer, thereby exposing the ACS and the TSVs, respectively. A cross-sectional view of an exemplary 3D memory structure 1400 according to process step S470 is shown in FIG.

[0144] As shown in FIG. 14 , the 3D memory structure 1400 includes a first contact opening 1490 formed in the dielectric fill layer 1384, thereby exposing at least a portion of the ACS 1280. The first contact opening 1490 penetrates through the dielectric fill layer 1384 and the ACS 1280. In some embodiments, the first contact opening 1490 penetrates through the second etch stop layer 552 and into the insulating layer 660. The first contact opening 1490 exposes the TSV 976 from the backside of the film stack 335 and removes a portion of the ACS 1280 surrounding the TSV 976, electrically isolating the TSV 976 from the ACS 1280. The first contact opening 1490 can be formed by lithography and an etching process, including dry etching or wet etching.

[0145] In some embodiments, insulating spacers 1491 may be formed on the sidewalls of the first contact opening 1490. The insulating spacers 1491 may include any suitable insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, TEOS, etc. The insulating spacers 1491 may be formed by thin film deposition (e.g., CVD, PCV, ALD, sputtering, etc.) and anisotropic etching (e.g., RIE).

[0146] The 3D memory structure 1400 also includes a second contact opening 1492 formed in the dielectric fill layer 1384. The second contact opening 1492 penetrates the dielectric fill layer 1384 to expose the ACS 1280. The second contact opening 1492 may be formed by lithography and an etching process, including dry etching or wet etching. Unlike the first contact opening 1490, the etching process for the second contact opening 1492 does not remove the ACS 1280. In some embodiments, the first contact opening 1490 and the second contact opening 1492 may be formed sequentially through different lithography and etching processes. In some embodiments, the first contact opening 1490 is formed before the second contact opening 1492, or vice versa. Note that FIG. 14 illustrates only one first contact opening 1490 and one second contact opening 1492. However, the number and arrangement of first contact openings 1490 and second contact openings 1492 are not so limited and can be any suitable number or arrangement as desired.

[0147] After forming the first contact opening 1490 and the second contact opening 1492 in the dielectric fill layer 1384, an interlayer dielectric (ILD) layer 1486 may be formed. The ILD layer 1486 (also referred to as an "intermetal dielectric (IMD) layer") may include one or more insulating materials (e.g., silicon oxide, silicon nitride, silicon oxynitride, TEOS, polyimide, spin-on glass, etc.) and may provide insulation for metal interconnects formed in subsequent processes.

[0148] In some embodiments, ILD layer 1486 also includes backside deep trench isolation (BDTI) 1488. BDTI 1488 can include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, TEOS, etc. In some embodiments, BDTI 1488 can also include a different dielectric material than dielectric fill layer 1384 and insulating spacers 1491, such as a high-k dielectric.

[0149] In some embodiments, the BDTI 1488 can be deposited on the sidewalls of the first contact opening 1490 before depositing the insulating spacer 1491. In this example, the BDTI 1488 can be formed by thin film deposition followed by anisotropic etching. In some embodiments, the BDTI 1488 can be formed anywhere in the dielectric fill layer 1384. The BDTI 1488 can penetrate through the dielectric fill layer 1384 and the ACS 1280 and can further penetrate into the insulating layer 660. In this example, the BDTI 1488 can be formed by an etching process (e.g., dry / wet etching) followed by a thin film deposition process (e.g., CVD, PVD, ALD, etc.). The BDTI 1488 can have a coplanar surface with the ILD layer 1486 on the backside (the side away from the film stack 335) through a planarization process (e.g., CMP).

[0150] 4, in process step S475, a backside interconnect layer having ACS contact structures and TSV contact structures can be formed on the backside of the ILD layer. A cross-sectional view of an exemplary 3D memory structure 1500 according to process step S475 is shown in FIG.

[0151] 15, the 3D memory structure 1500 includes a backside interconnect layer 1594 having an ACS contact structure 1595 and a TSV contact structure 1596. The backside interconnect layer 1594 may be formed on the backside of the ILD layer 1486, the side farther away from the film stack 335. The backside interconnect layer 1594 may be made of any suitable conductive material, such as tungsten (W), cobalt (Co), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (WSi x , CoSi x , NiSi x , AlSi x The conductive material may include a metal or metal alloy, such as a metal nitride, a silicon nitride, a silicon dioxide, a silicon dioxide film ...

[0152] The ACS contact structure 1595 can provide an electrical connection from the backside (the side farther away from the film stack 335) of the ACS 1280 to the channel layer 338 of the memory string 212. Connections of the ACS 1280 brought out from the backside can save area, thereby increasing the storage capacity of the 3D memory.

[0153] TSV contact structures 1596 can provide electrical connection from the backside (the side farther away from film stack 335) of ILD layer 1486 to TSV 976. As previously described, TSV 976 can provide electrical connection to peripheral devices 50 in peripheral circuit 600B via contact structures 64 and / or conductive lines 66 (see FIG. 6B ). Thus, electrical connection to the peripheral devices can be routed from the backside of ILD layer 1486. ​​Similarly, connections to peripheral devices brought out from the backside can save area, thereby increasing the storage capacity of the 3D memory.

[0154] In some embodiments, the insulating gap 1597 may be formed through a dry / wet etching process to separate the ACS contact structures 1595 and the TSV contact structures 1596. In some embodiments, a dielectric material is disposed inside the insulating gap 1597, which can further avoid crosstalk between the ACS contact structures 1595 and the TSV contact structures 1596 when transmitting and receiving signals, and the dielectric material may be silicon oxide, silicon nitride, silicon oxynitride, TEOS, polyimide, spin-on glass, etc., and may be disposed by any suitable process, such as CVD, PVD, ALD, sputtering, evaporation, spin-on, etc.

[0155] In some embodiments, the backside interconnect layer 1594 (including the TSV contact structures 1596 and the ACS contact structures 1595) can be made flush with the ILD layer 1486 through a planarization process (e.g., CMP). In this example, the backside interconnect layer 1594 can be buried or recessed inside the ILD layer 1486.

[0156] The present disclosure also provides a 3D memory device manufactured using the method 400 described above.

[0157] 16 illustrates a 3D memory device 1600 according to some embodiments of the present disclosure. The 3D memory device 1600 includes a film stack 335 of alternating conductive and dielectric layers, an ILD layer 1486, and an ACS 1280 disposed between the film stack 335 and the ILD layer 1486.

[0158] The film stack 335 includes a vertically alternating conductive layer 870 and a first dielectric layer 656. The first dielectric layer 656 includes any suitable insulating material, such as silicon oxide, silicon oxynitride, silicon nitride, TEOS, or silicon oxide loaded with F-, C-, N-, and / or H-. The first dielectric layers 656 may have the same or different thicknesses, which may be in the range of 10 nm to 500 nm. In some embodiments, the first dielectric layer 656 may be silicon oxide with a thickness of approximately 25 nm. The conductive layer 870 includes any suitable metal or metal alloy, such as tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), cobalt (Co), nickel (Ni), titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), AlTi, or any combination thereof. The conductive layers 870 may have the same or different thicknesses, which may be in the range between 10 nm and 500 nm. In some embodiments, the conductive layer 870 comprises W with a thickness of about 35 nm.

[0159] The film stack 335 may also include a gate dielectric layer 872 surrounding the conductive layer 870. The gate dielectric layer 872 may include any suitable insulator, such as silicon oxide, silicon nitride, silicon oxynitride, and / or any suitable combination thereof. The gate dielectric layer 872 may also include a high-k dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, and / or any combination thereof. In some embodiments, the film stack 335 may also include a gate adhesion layer 874 sandwiched between the gate dielectric layer 872 and the conductive layer 870. The gate adhesion layer 874 may be used to promote adhesion between the gate dielectric layer 872 and the conductive layer 870. The gate adhesion layer 874 may include, for example, tantalum nitride (TaN) and / or titanium nitride (TiN).

[0160] The 3D memory device 1600 also includes a staircase structure 657 formed in the film stack 335 in the staircase region 210. The staircase structure 657 includes a plurality of staircase steps 659. The staircase steps 659, or "staircase layers," refer to layer stacks that are parallel to and have the same lateral dimensions as the conductive layer 870 and the first dielectric layer 656. Each of the staircase steps 659 terminates at a shorter length than the staircase step below it.

[0161] The 3D memory device 1600 also includes an insulating layer 660 disposed on the staircase structure 657 and the film stack 335. The insulating layer 660 may also be disposed on the ACS 1280 in the peripheral region 105. The insulating layer 660 includes a low-k dielectric material such as silicon oxide, silicon oxynitride, silicon nitride, TEOS, spin-on glass, carbon-doped oxide (CDO or SiOC or SiOC:H), or fluorine-doped oxide (SiOF), etc. In some embodiments, the insulating layer 660 can have a planar surface over the staircase structure 657 in the staircase region 210, the film stack 335 in the channel structure region 211, and the ACS 1280 in the peripheral region 105.

[0162] The 3D memory device 1600 also includes a plurality of memory strings 212 within the channel structure region 211, where the memory strings 212 vertically penetrate the film stack 335. In some embodiments, the memory strings penetrate into the ACS 1280 and the ILD layer 1486. ​​In some embodiments, the memory strings 212 may have a cylindrical shape. The memory strings 212 may include a core fill film 339 at their centers, which may be surrounded by a channel layer 338. The core fill film 339 may include any suitable insulator, such as silicon oxide, silicon nitride, silicon oxynitride, spin-on glass, boron- or phosphorus-doped silicon oxide, carbon-doped oxide (CDO or SiOC or SiOC:H), fluorine-doped oxide (SiOF), or any combination thereof. The channel layer 338 may include any suitable semiconductor, such as polycrystalline silicon having a thickness in a range from about 10 nm to about 30 nm. The memory string 212 may also include a memory film 337 covering the sidewalls of the channel layer 338, i.e., surrounding the channel layer 338. The memory film 337 may be a composite layer including a tunnel layer, a storage layer (also referred to as a "charge trap / storage layer"), and a blocking layer. In some embodiments, the tunnel layer, storage layer, and blocking layer are arranged in the above order along a direction from the center of the memory string 212 to the outside of the memory string 212. The tunnel layer may include silicon oxide, silicon nitride, or any combination thereof. The blocking layer may include silicon oxide, silicon nitride, a high-k dielectric, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the memory film 337 includes an ONO dielectric (e.g., a tunnel layer including silicon oxide, a storage layer including silicon nitride, and a blocking layer including silicon oxide). In some embodiments, the thickness of the memory film 337 can be in the range of about 10 nm to about 50 nm.3D memory device 1600 includes a plurality of vertically stacked memory cells 340. Memory cells 340 are formed at the intersections between conductive layers 870 and memory strings 212. Conductive layers 870 can form word lines 333 of FIG. 3 to address memory cells 340.

[0163] In some embodiments, the memory string 212 also includes an epitaxial plug (not shown in FIG. 16 ) at the bottom of the memory string 212 (closer to the ACS 1280). The epitaxial plug can include any suitable semiconductor material, such as silicon, silicon germanium, germanium, gallium arsenide, gallium nitride, III-V compounds, or any combination thereof. In some embodiments, the epitaxial plug can also include a polycrystalline semiconductor material, for example, polycrystalline silicon. The epitaxial plug can be connected to the channel layer 338 of the memory string 212.

[0164] In some embodiments, the memory string 212 may also include a channel top plug 762 configured to provide electrical contact to the channel layer 338. Bit lines (not shown) of the 3D memory device 1600 can address the memory cells 340 through the channel top plug 762. The channel top plug 762 may be amorphous or polycrystalline silicon and may include a metal, a metal alloy, and / or a metal silicide, such as tungsten, titanium, tantalum, tungsten nitride, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, or a combination thereof.

[0165] The 3D memory device 1600 also includes a GLS 216 that penetrates vertically through the film stack 335. In some embodiments, the GLS 216 further penetrates into the ACS 1280 and the ILD layer 1486. ​​The GLS 216 can include a GLS filler 871, which can include any suitable insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, TEOS, etc.

[0166] In some embodiments, the 3D memory device 1600 also includes a dummy channel structure 763 in the stepped region 210. The dummy channel structure 763 penetrates vertically through the insulating layer 660 and the stepped structure 657. In some embodiments, the dummy channel structure 763 penetrates into the ACS 1280 and the ILD layer 1486. ​​The dummy channel structure 763 may be configured to provide mechanical support for the 3D memory device 1600 during various manufacturing processes. The dummy channel structure 763 may include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, TEOS, a high-k dielectric material (such as Al2O3, HfO2, Ta2O3, ZrO2, La2O3, or the like), or any combination thereof.

[0167] 3D memory device 1600 further includes TVS 976 that penetrate insulating layer 660. In some embodiments, TSVs 976 penetrate through ACS 1280 and into ILD layer 1486. ​​TSVs 976 can comprise any suitable conductive material, for example, a metal or metal alloy, such as tungsten, titanium, tantalum, tungsten nitride, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, or combinations thereof. In some embodiments, TSVs 976 can be configured to provide electrical connection to peripheral devices in the peripheral region.

[0168] The ACS1280 includes one or more polycrystalline silicon layers (e.g., a first polycrystalline silicon layer 1281 and a second polycrystalline silicon layer 1282). The one or more polycrystalline silicon layers may be doped with n-type or p-type dopants. The ACS1280 is in contact with the channel layer 338 of the memory string 212. The ACS1280 surrounds a portion of the memory string 212 that penetrates into the ILD layer 1486, and the memory film 337 is removed from this portion of the memory string 212, so that the ACS1280 contacts the channel layer 388. In other words, the memory film 337 covers a first portion of the channel layer 388, and the ACS1280 covers a second portion of the channel layer 388. The contact area between the channel layer 388 and the ACS1280 can be increased by further pulling back the memory film 337 away from the ACS1280 (or toward the film stack 335). As such, the contact resistance between the ACS 1280 and the channel layer 388 may be reduced, improving the performance of the 3D memory device 1600.

[0169] Similarly, ACS 1280 can also surround a portion of GLS 216 that penetrates into ILD layer 1486. ​​ACS 1280 can also surround a portion of dummy channel structure 763 that penetrates into ILD layer 1486. ​​In some embodiments, ACS 1280 is separated from TSV 976 by electrical isolation provided by insulating spacers 1491 and / or BDTI 1488. ACS 1280 can provide mechanical support for film stack 335.

[0170] The 3D memory device 1600 further includes a backside interconnect layer 1594 formed on the backside of the ACS 1280, the side farther away from the film stack 335. The backside interconnect layer 1594 includes an ACS contact structure 1595 and a TSV contact structure 1596, and an insulating space 1597 may be formed between the ACS contact structure 1595 and the TSV contact structure 1596. The backside interconnect layer 1594 may be made of any suitable conductive material, such as tungsten (W), cobalt (Co), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), nickel, or a silicide (WSi x , CoSi x , NiSi x , AlSi x The ACS contact structure 1595 may provide electrical connection to the channel layer 388 of the memory string 212 through the ACS 1280. The TSV contact structure 1596 may provide electrical connection to a peripheral device through the TSV 976.

[0171] The ILD layer 1486 may include one or more insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, TEOS, polyimide, spin-on glass, etc., to provide insulation to the backside interconnect layer 1594. The ILD layer 1486 may include insulating spacers 1491 and BDTI 1488. The BDTI 1488 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, TEOS, etc. In some embodiments, the BDTI 1488 may also include a different dielectric material than the insulating spacers 1491, such as a high-k dielectric.

[0172] In some embodiments, the 3D memory device 1600 also includes a second etch stop layer 552 disposed between the film stack 335 and the ACS 1280. In some embodiments, the second etch stop layer 552 may also be disposed between the insulating layer 660 and the ACS 1280. The distance between the film stack 335 and the ACS 1280 may be determined by the thickness of the second etch stop layer 552.

[0173] In some embodiments, the 3D memory device 1600 also includes a first capping layer 766 and a second capping layer 868 disposed on the front side of the insulating layer 660 over the memory strings 212, the GLS 216, and the dummy channel structures 763. The front side of the insulating layer is the side away from the ACS 1280 and the ILD layer 1486. ​​In some embodiments, the memory strings 212 and the dummy channel structures 763 are coplanar with the insulating layer 660. In some embodiments, the GLS 216 is coplanar with the first capping layer 766. In some embodiments, the TSVs 976 are coplanar with the second capping layer 868.

[0174] As described above, the channel layers 338 of the memory strings 212 may be connected through ACS contact structures 1595 on the backside of the film stack 335, which may be referred to as source terminals. The channel layers 338 of the memory strings 212 may be connected through channel top plugs 762 on the front side of the film stack 335, which may be referred to as drain terminals. The drain terminals of the memory strings 212 may be connected to bit lines, while the source terminals of the memory strings 212 in the same memory block (or sub-block) may be connected together through ACS 1486. ​​The ACS contact structures 1595 through the backside of the film stack 335 can save area and increase storage capacity for the 3D memory device 1600.

[0175] Conventionally, to form an electrical connection from the bottom (at the source terminal) of the memory string 212 to the channel layer 338, the memory film 337 at the bottom of the channel hole 336 must be removed. By removing the memory film 337 and providing electrical contact to the channel layer 338 from the backside via the ACS contact structure 1595, etching the memory film 337 from the bottom of the high-aspect-ratio channel hole 336 can be avoided. In addition, filling a portion of the GLS 216 with a conductive material to provide electrical connection to the ACS 1280 can also be avoided. As such, leakage from the conductive layer 870 to the GLS 216 filled with the conductive material can be eliminated. Furthermore, by using the first etch stop layer 550 and the second etch stop layer 552, the substrate 330 and the memory film 337 can be controllably removed from the backside. Process uniformity and yield can be significantly improved.

[0176] FIG. 17 illustrates a block diagram of an exemplary system S1 having a storage system 10 according to some embodiments of the present disclosure. The system S1 may be a mobile phone, a desktop computer, a laptop computer, a tablet, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. The storage system 10 (also referred to as a NAND storage system) may include a memory controller 20 and one or more semiconductor memory chips 25-1, 25-2, 25-3, ..., 25-n. Each semiconductor memory chip 25 (hereinafter simply "memory chip") may be a NAND chip (i.e., "flash," "NAND flash," or "NAND"). Storage system 10 can communicate with host computer 15 through memory controller 20, which can be connected to one or more memory chips 25-1, 25-2, 25-3, ..., 25-n via one or more memory channels 30-1, 30-2, 30-3, ..., 30-n. In some embodiments, each memory chip 25 can be managed by memory controller 20 via a memory channel 30.

[0177] In some embodiments, host computer 15 may comprise a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). Host computer 15 sends data to be stored in the NAND storage system or storage system 10, or retrieves data by reading storage system 10.

[0178] The memory controller 20 can process I / O requests received from the host computer 15, ensure data integrity and efficient storage, and manage the memory chips 25. To perform these tasks, the controller executes firmware 21, which may be executed by one or more processors 22 (e.g., microcontroller units, CPUs) within the controller 20. For example, the controller 20 executes firmware 21 to map logical addresses (i.e., addresses used by the host associated with host data) to physical addresses (i.e., the actual locations where the data is stored) within the memory chips 25. The controller 20 also executes firmware 21 to manage defective memory blocks within the memory chips 25; the firmware 21 can remap logical addresses to different physical addresses, i.e., move data to different physical addresses. The controller 20 can also include one or more memories 23 (e.g., DRAM, SRAM, EPROM, etc.), which can be used to store various metadata used by the firmware 21. In some embodiments, the memory controller 20 can also perform error recovery through an error correcting code (ECC) engine 29. ECC is used to detect and correct raw bit errors that occur within each memory chip 25 .

[0179] The memory channel 30 can provide data and control communication between the memory controller 20 and each memory chip 25 via a data bus. The memory controller 20 can select one of the memory chips 25 according to a chip enable signal.

[0180] In some embodiments, each memory chip 25 of FIG. 17 can include one or more memory dies 100, and each memory die can be a 3D NAND memory 100 as shown in FIGS. 1-3. In some embodiments, each of the one or more memory dies 100 can include a 3D memory device 1600 shown in FIG. 16, which can be fabricated using the method 400 of FIG.

[0181] The memory controller 20 and one or more memory chips 25 can be integrated into various types of storage devices and included in the same package, such as a universal flash storage (UFS) package or an eMMC package. That is, the storage system 10 can be implemented and packaged in different types of end electronic products. In one example, as shown in FIG. 18A , the memory controller 20 and a single memory chip 25 can be integrated into a memory card 26. The memory card 26 can include a PC card (PCMCIA, PC Memory Card International Association), a CF card, a SmartMedia (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 26 can further include a memory card connector 24 that couples the memory card 26 to a host (e.g., the host computer 15 of FIG. 17 ). In another example, as shown in FIG. 18B , the memory controller 20 and multiple memory chips 25 can be integrated into a solid-state drive (SSD) 27. The SSD 27 may further include an SSD connector 28 that couples the SSD 27 to a host (eg, the host computer 15 of FIG. 17).

[0182] FIG. 19 illustrates a schematic diagram of a memory die 100 according to some embodiments of the present disclosure. The memory die 100 includes one or more memory blocks 103 (e.g., 103-1, 103-2, 103-3). Each memory block 103 includes multiple memory strings 212. Each memory string 212 includes multiple memory cells 340. The memory cells 340 that share the same word line form a memory page 432. The memory strings 212 may also include at least one field-effect transistor (e.g., MOSFET) at each end, which is controlled by a lower select gate (LSG) 332 and a top select gate (TSG) 334, respectively. The drain terminal of the top select transistor 334-T may be connected to a bit line 341, and the source terminal of the lower select transistor 332-T may be connected to an array common source (ACS) 430. The ACS 430 may be shared by the memory strings 212 within an entire memory block and is also referred to as a common source line.

[0183] In some embodiments, ACS 430 can include ACS 1280 shown in Figure 16 and can be manufactured using method 400 shown in Figure 4. In this example, memory die 100 can include 3D memory device 1600 shown in Figure 16.

[0184] Memory die 100 may also include peripheral circuits, including numerous digital, analog, and / or mixed-signal circuits that support the functionality of memory block 103, such as page buffer / sense amplifiers 50, row decoder / word line drivers 40, column decoder / bit line drivers 52, control circuitry 70, voltage generators 65, and input / output buffers 55. These circuits may include active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., as will be apparent to those skilled in the art.

[0185] The memory blocks 103 may be coupled to the row decoder / word line driver 40 via word lines ("WL") 333, bottom select gates ("LSG") 332, and top select gates ("TSG") 334. The memory blocks 103 may be coupled to the page buffer / sense amplifier 50 via bit lines ("BL") 341. The row decoder / word line driver 40 may select one of the memory blocks 103 on the memory die 100 in response to an X-path control signal provided by the control circuit 70. The row decoder / word line driver 40 may transfer a voltage provided by the voltage generator 65 to the word lines in response to the X-path control signal. During read and program operations, the row decoder / word line driver 40 may select a read voltage V in accordance with the X-path control signal received from the control circuit 70. read and the program voltage V pgm to the selected word line, and the pass voltage V pass can be transferred to unselected word lines.

[0186] The column decoder / bit line driver 52 generates an inhibit voltage V inhibitThe column decoder / bit line driver 52 may transfer a signal to an unselected bit line and connect a selected bit line to ground. In other words, the column decoder / bit line driver 52 may be configured to select or deselect one or more memory strings 212 according to a Y-path control signal from the control circuit 70. The page buffer / sense amplifier 50 may be configured to read and program (write) data to and from the memory block 103 according to the control signal Y-path control from the control circuit 70. For example, the page buffer / sense amplifier 50 may store a page of data to be programmed in one memory page 432. In another example, the page buffer / sense amplifier 50 may perform a verify operation to confirm that the data has been properly programmed into each memory cell 340. In yet another example, during a read operation, the page buffer / sense amplifier 50 may sense the current flowing through the bit line 341, which reflects the logic state (i.e., data) of the memory cell 340, and amplify the small signal by a measurable factor.

[0187] Input / output buffer 55 can transfer I / O data to and from page buffer / sense amplifier 50, as well as addresses ADDR or commands CMD to control circuitry 70. In some embodiments, input / output buffer 55 can serve as an interface between memory controller 20 (FIG. 1) and memory die 100 on memory chip 25.

[0188] The control circuit 70 can control the page buffer / sense amplifier 50 and the row decoder / word line driver 40 in response to a command CMD transferred by the input / output buffer 55. During a program operation, the control circuit 70 can control the row decoder / word line driver 40 and the page buffer / sense amplifier 50 to program a selected memory cell. During a read operation, the control circuit 70 can control the row decoder / word line driver 40 and the page buffer / sense amplifier 50 to read a selected memory cell. The X-path control signal and the Y-path control signal include a row address X-ADDR and a column address Y-ADDR that can be used to identify a selected memory cell in the memory block 103. The row address X-ADDR can include a page index PD, a block index BD, and a plane index PL to identify the memory page 432, the memory block 103, and the memory plane 101 (in the case of FIG. 1), respectively. The column address Y-ADDR can identify a byte or word within the data of the memory page 432.

[0189] The voltage generator 65 can generate voltages to be supplied to the word lines and bit lines under the control of the control circuit 70. The voltages generated by the voltage generator 65 are read voltages V read , program voltage V pgm , pass voltage V pass , inhibit voltage V inhibit Includes:

[0190] In summary, the present disclosure provides a method for forming a three-dimensional (3D) memory device, the method including: disposing an alternating dielectric stack on a substrate, the alternating dielectric stack including first and second dielectric layers alternately stacked on the substrate; forming a channel structure penetrating through the alternating dielectric stack into the substrate, the channel structure including a channel layer disposed on a sidewall of the memory film; removing a portion of the substrate and the memory film penetrating into the substrate to expose a portion of the channel layer; and disposing an array common source (ACS) on the exposed portion of the channel layer.

[0191] The present disclosure also provides a three-dimensional (3D) memory device. The 3D memory device includes an array common source (ACS), a film stack of alternating conductive and dielectric layers, the film stack including alternating conductive layers and a first dielectric layer on a first side of the ACS, a backside interconnect layer disposed on a second side of the ACS opposite the first side, the backside interconnect layer including an ACS contact structure, and a memory string extending through the film stack. The memory string includes a channel layer having a first portion covered by a memory film and a second portion in contact with the ACS and electrically connected to the ACS contact structure.

[0192] The present disclosure also provides a memory storage system. The memory storage system includes a three-dimensional (3D) NAND memory, the 3D NAND memory including an array common source (ACS) and a film stack of alternating conductive and dielectric layers, the film stack including alternating conductive layers and first dielectric layers on a first side of the ACS. The 3D NAND memory also includes a backside interconnect layer disposed on a second side of the ACS opposite the first side, the backside interconnect layer including an ACS contact structure. The 3D NAND memory further includes a memory string extending through the film stack, the memory string including a channel layer having a first portion covered by the memory film and a second portion in contact with the ACS and electrically connected to the ACS contact structure.

[0193] The foregoing description of specific embodiments will fully clarify the general nature of the present disclosure so that those skilled in the art can readily modify and / or adapt such specific embodiments for various uses without departing from the general concepts of the disclosure and without undue experimentation. Such adaptations and modifications are therefore intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the disclosure and guidance presented herein. It will be understood that the phraseology or terminology used herein is for the purpose of description and not of limitation, and as such should be interpreted by one of ordinary skill in the art in light of the disclosure and guidance.

[0194] The embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating implementations of specified functions and their relationships. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of description. Alternative boundaries may be defined so long as the specified functions and their relationships are appropriately performed.

[0195] The Summary and Abstract sections may define one or more, but not all, exemplary embodiments of the present disclosure as contemplated by the inventors, and are therefore not intended to limit the disclosure and appended claims in any way.

[0196] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. [Explanation of symbols]

[0197] S1 System 10 Storage Systems 15 Host Computer 20 Memory Controller 21 Firmware 22 processors 23 Memory 24 Memory card connector 25 memory chips 25-1, 25-2, 25-3, ..., 25-n semiconductor memory chips 26 Memory Card 27 SSD 28 SSD connectors 30 memory channels 30-1, 30-2, 30-3, ..., 30-n memory channels 40 Row decoder / word line driver 50 Peripheral Devices 50 Page Buffer / Sense Amplifier 52 Shallow Trench Isolation (STI) 52 Column decoder / bit line driver 54 wells 55 Input / Output Buffers 56 Gate Stack 58 Gate spacer 60 Source / Drain 62 Peripheral Interconnect Layer 64 vertical contact structure 65 Voltage Generator 66 Horizontal conductive lines 70, 70-1 or 70-2 metal level 70 Control circuit 72 board contacts 100 Three-dimensional (3D) memory devices 101 Memory Plane 103 memory blocks 105 Surrounding Area 108 areas 210 Stepped area 211 Channel structure region 212 Memory String 214 Contact Structure 216 Slit structure 216-1 and 216-2 Slit Structure 218 Memory Finger 220 Top selective gate cut 222 Dummy Memory String 224 memory slices 300 Memory Array Structure 330 Substrate 330f front 331 Insulating Film 333-1, 333-2, 333-3 control gates 332 Lower Select Gate (LSG) 332-T Lower select transistor 333 Control Gate 334 Top Select Gate (TSG) 334-T Top Select Transistor 335 Film Stack 336 Channel Hall 337 Memory Film 338 Channel Layer 339 Core-filled film 340 memory cells 340-1, 340-2, and 340-3 memory cells 341 bit line (BL) 343 Metal Interconnection Wires 344 doped source line region 400 ways 432 memory pages 500 3D memory structure 545 Handle wafer 546 Insulator Layer 547 Semiconductor Layer 550 First Etch Stop Layer 552 Second Etch Stop Layer 600 3D memory structure 600B peripheral circuit 654 Alternating Dielectric Stack 656 First Dielectric Layer 657 Stepped structure 658 Second Dielectric Layer 659 Staircase Steps 660 Insulation Layer 700 3D memory structure 761 Channel Structure 762 Channel Top Plug 763 Dummy Channel Structure 764 Dummy Channel Hole (DCH) 765 DCH Filler 766 First Capping Layer 800 3D memory structure 860 seam 868 Second Capping Layer 869 Gate line slit (GLS) opening 870 Conductive layer 871 GLS Filler 872 Gate dielectric layer 874 Gate adhesion layer 900 3D memory structure 976 TSV 1000 3D memory structure 1100 3D memory structure 1200 3D memory structure 1280 ACS 1300 3D memory structure 1384 Dielectric Filler Layer 1400 3D memory structure 1486 Interlayer Dielectric (ILD) Layer 1488 Backside Deep Trench Isolation (BDTI) 1490 first contact opening 1491 Insulating spacer 1492 Second Contact Opening 1500 3D memory structure 1594 Backside Interconnect Layer 1595 ACS contact structure 1596 TSV contact structure 1597 Insulation Spacing 1600 3D memory devices 3371 Blocking Layer 3372 storage tier 3373 Tunnel Layer

Claims

1. 1. A method for forming a three-dimensional (3D) memory device, comprising: disposing an alternating dielectric stack over a substrate, the alternating dielectric stack including first and second dielectric layers alternately stacked on the substrate; forming a channel structure penetrating through the alternating dielectric stack into the substrate, the channel structure including a channel layer disposed on a sidewall of a memory film; removing the substrate and a portion of the memory film that penetrates into the substrate to expose a portion of the channel layer; disposing an array common source (ACS) on the exposed portion of the channel layer; A method comprising:

2. disposing a first etch stop layer over the substrate; disposing a second etch stop layer over the first etch stop layer; disposing the alternating dielectric stack on the second etch stop layer; The method of claim 1 further comprising:

3. The step of removing the substrate and the portion of the memory film that penetrates into the substrate comprises: removing the substrate, stopping on the first etch stop layer to expose the portion of the memory film that extends into the substrate; removing the first etch stop layer and the exposed portion of the memory film, stopping on the second etch stop layer to expose the portion of the channel layer; The method of claim 2 , comprising:

4. The method of claim 1 , further comprising forming an ACS contact structure contacting a backside of the ACS, the backside of the ACS being a side farther away from the first dielectric layer.

5. The method of claim 1 , further comprising disposing an insulating layer on the substrate covering the alternating dielectric stack.

6. 6. The method of claim 5, further comprising forming a through silicon via (TSV) in the peripheral region, the TSV penetrating through the insulating layer and into the substrate.

7. 7. The method of claim 6, further comprising forming a TSV contact structure contacting the TSV from a back surface of the insulating layer, the back surface of the insulating layer being a side farther away from the first dielectric layer.

8. 8. The method of claim 7, wherein forming the TSV contact structure comprises electrically connecting the TSV contact structure to a peripheral device in the peripheral region through the TSV.

9. The method of claim 1 , further comprising forming a stair-step structure within the alternating dielectric stack.

10. forming a dummy channel structure penetrating through the staircase structure and into the substrate; removing the substrate to expose a portion of the dummy channel structure extending into the substrate; disposing the ACS on the exposed portion of the dummy channel structure; 10. The method of claim 9, further comprising:

11. forming gate line slit (GLS) openings through the alternating dielectric stack and into the substrate; replacing the second dielectric layer with a conductive layer to form a film stack of alternating conductive and dielectric layers, the film stack including the conductive layers and the first dielectric layer alternately stacked on the substrate; disposing a GLS filler material inside the GLS opening to form a GLS; The method of claim 1 further comprising:

12. removing the substrate to expose a portion of the GLS that penetrates into the substrate; disposing the ACS over the exposed portion of the GLS; The method of claim 11 further comprising:

13. 1. A three-dimensional (3D) memory device, comprising: an array common source (ACS); a film stack of alternating conductive and dielectric layers, the film stack including alternating conductive layers and a first dielectric layer on a first side of the ACS; a backside interconnect layer disposed on a second side of the ACS opposite the first side, the backside interconnect layer including an ACS contact structure; and a memory string passing through the film stack, the memory string comprising: A channel layer, a first portion covered by a memory film; a second portion in contact with the ACS and electrically connected to the ACS contact structure; A channel layer including a memory string containing A three-dimensional (3D) memory device comprising:

14. 14. The 3D memory device of claim 13, further comprising an insulating layer disposed on the first side of the film stack and the ACS.

15. 15. The 3D memory device of claim 14, further comprising a through silicon via (TSV) extending through the insulating layer, the backside interconnect layer including a TSV contact structure electrically connected to the TSV.

16. 16. The 3D memory device of claim 15, wherein the TSV contact structures are electrically connected to peripheral devices through the TSVs.

17. 16. The 3D memory device of claim 15, wherein the backside interconnect layer further comprises an insulating space between the TSV contact structure and the ACS contact structure.

18. 16. The 3D memory device of claim 15, further comprising an inter-level dielectric (ILD) layer disposed on the second side of the ACS.

19. The ILD layer comprises: an insulating spacer that electrically isolates the TSV contact structure from the ACS; a backside deep trench isolation (BDTI) including a dielectric material different from the insulating spacer; 20. The 3D memory device of claim 18, further comprising:

20. 15. The 3D memory device of claim 14, further comprising a first capping layer disposed on the insulating layer, the memory strings being flush with the insulating layer and covered by the first capping layer.

21. 14. The 3D memory device of claim 13, further comprising a staircase structure formed in said film stack of alternating conductive and dielectric layers.

22. 22. The 3D memory device of claim 21, further comprising a dummy channel structure penetrating the staircase structure and filled with an insulating material, a portion of the dummy channel structure being covered by the ACS.

23. 14. The 3D memory device of claim 13, further comprising a gate line slit (GLS) that penetrates the film stack of alternating conductive and dielectric layers and is filled with an insulating material, a portion of the GLS being covered by the ACS.

24. 14. The 3D memory device of claim 13, further comprising an etch stop layer sandwiched between the film stack and the ACS.

25. 14. The 3D memory device of claim 13, wherein the ACS comprises a p-type or n-type doped polycrystalline silicon layer.

26. 1. A memory storage system, comprising: A three-dimensional (3D) NAND memory, the three-dimensional (3D) NAND memory comprising: an array common source (ACS); a film stack of alternating conductive and dielectric layers, the film stack including alternating conductive layers and a first dielectric layer on a first side of the ACS; a backside interconnect layer disposed on a second side of the ACS opposite the first side, the backside interconnect layer including an ACS contact structure; and a memory string passing through the film stack, the memory string comprising: A channel layer, a first portion covered by a memory film; a second portion in contact with the ACS and electrically connected to the ACS contact structure; a channel layer; a memory string; A memory storage system comprising:

27. 27. The memory storage system of claim 26, wherein the ACS comprises a p-type or n-type doped polycrystalline silicon layer.

28. 27. The memory storage system of claim 26, further comprising an etch stop layer sandwiched between said film stack and said ACS.

29. 27. The memory storage system of claim 26, further comprising a gate line slit (GLS) passing through the film stack of alternating conductive and dielectric layers and filled with an insulating material, a portion of the GLS being covered by the ACS.

30. 27. The memory storage system of claim 26, further comprising an insulating layer disposed on the first side of the film stack and the ACS.

31. 31. The memory storage system of claim 30, further comprising a through silicon via (TSV) extending through the insulating layer, the backside interconnect layer including a TSV contact structure electrically connected to the TSV.

32. 32. The memory storage system of claim 31, wherein the TSV contact structure is electrically connected to a peripheral device through the TSV.

33. 32. The memory storage system of claim 31, wherein the backside interconnect layer further comprises an insulating space between the TSV contact structure and the ACS contact structure.

34. 32. The memory storage system of claim 31, further comprising an inter-level dielectric (ILD) layer disposed on the second side of the ACS.

35. The ILD layer comprises: an insulating spacer that electrically isolates the TSV contact structure from the ACS; a backside deep trench isolation (BDTI) including a dielectric material different from the insulating spacer; 35. The memory storage system of claim 34, further comprising:

36. 31. The memory storage system of claim 30, further comprising a first capping layer disposed on the insulating layer, the memory strings being flush with the insulating layer and covered by the first capping layer.

37. 27. The memory storage system of claim 26, further comprising a staircase structure formed within said film stack of alternating conductive and dielectric layers.

38. 38. The memory storage system of claim 37, further comprising a dummy channel structure penetrating the staircase structure and filled with an insulating material, a portion of the dummy channel structure being covered by the ACS.

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