Printed wiring board

Abstract

To provide a printed wiring board having high quality.SOLUTION: A printed wiring board has an outermost resin insulation layer, an outermost conductor layer formed on the outermost resin insulation layer, and a solder resist layer formed on the outermost resin insulation layer and the outermost conductor layer. The outermost conductor layer has a first surface facing the solder resist layer, whose the first surface is not roughened, and the solder resist layer has a second surface facing the outermost conductor layer, in which arithmetic average roughness of the second surface is 0.6 μm or more and 1.1 μm or less.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a printed wiring board. [Background technology]

[0002] Patent Document 1 discloses a printed wiring board having a dry film and a resin obtained by curing the dry film. The dry film in Patent Document 1 is formed of a first film, a second film, and a resin layer sandwiched between the first film and the second film. The arithmetic mean surface roughness Ra of the surface of the second film that contacts the resin layer is 0.1 to 1.2 μm. The surface of the second film that contacts the resin layer is the surface that is laminated to the substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-86000 A Summary of the Invention

[0004] [Problem of Patent Document 1] When the dry film of Patent Document 1 is used to form a solder resist layer, it is thought that a part of the solder resist layer will peel off from the solder resist layer due to thermal shock. [Means for solving the problem]

[0005] The printed wiring board of the present invention comprises an outermost resin insulating layer, an outermost conductor layer formed on the outermost resin insulating layer, and a solder resist layer formed on the outermost resin insulating layer and the outermost conductor layer, wherein the outermost conductor layer has a first surface facing the solder resist layer, and the first surface is not roughened; The solder resist layer has a second surface facing the outermost conductor layer, and the arithmetic mean roughness of the second surface is 0.6 μm or more and 1.1 μm or less.

[0006] In a printed wiring board according to an embodiment of the present invention, the first surface of the outermost conductor layer facing the solder resist layer is not roughened. The arithmetic mean roughness of the second surface of the solder resist layer facing the outermost conductor layer is 0.6 μm or more and 1.1 μm or less. The second surface of the solder resist layer in contact with the smooth first surface of the outermost conductor layer is rough. Therefore, when the solder resist layer is vacuum-laminated onto the outermost conductor layer, air bubbles are easily removed. According to the embodiment, the adhesion between the outermost conductor layer and the solder resist layer is high. By setting the arithmetic mean roughness to 1.1 μm or less, a decrease in adhesion due to an excessively large arithmetic mean roughness is suppressed. The solder resist layer of the printed wiring board according to the embodiment is less likely to peel off, as is the case with the solder resist layer of Patent Document 1. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a cross-sectional view schematically showing a printed wiring board according to an embodiment. [Figure 2] 1A to 1C are cross-sectional views schematically illustrating a method for manufacturing a printed wiring board according to an embodiment. [Figure 3] 1A to 1C are cross-sectional views schematically illustrating a method for manufacturing a printed wiring board according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] <Printed wiring board according to an embodiment> Fig. 3 shows a cross section of intermediate substrate 2. Fig. 1 is a cross section of semiconductor device 200 of the embodiment. Semiconductor device 200 is formed by printed wiring board 10 of the embodiment and electronic component 90 mounted on printed wiring board 10.

[0009] As shown in FIG. 1, printed wiring board 10 has core substrate 30 and buildup layers 80A, 80B formed on the front and back surfaces of core substrate 30. Buildup layers 80A, 80B are formed of resin insulating layers 150U, 150L, ​​conductor layers 158U, 158L, and via conductors 160U, 160D that penetrate resin insulating layers 150U, 150L and connect adjacent conductor layers. Resin insulating layer 150U is the outermost resin insulating layer. Conductor layer 158U is the outermost conductor layer. Conductor layer 158U is formed on resin insulating layer 150U.

[0010] The printed wiring board 10 has solder resist layers 70U and 70D on the buildup layers 80A and 80B. The solder resist layer 70U has a plurality of openings 71U. A conductor layer 158U exposed by the opening 71U functions as a pad 158p for mounting an electronic component 90. The conductor layer 158U is formed of copper. The conductor layer 158U has a first surface 158a facing the solder resist layer 70U. The first surface 158a is not roughened. The root-mean-square roughness of the first surface 158a is 0.23 μm or less. The openings 71U lead to the pads 158p. The electronic component 90 is mounted on the printed wiring board 10 via the plurality of pads 158p. The solder resist layer 70U is formed on the resin insulating layer 150U and the plurality of pads 158p. The solder resist layer 70U has a second surface 70a facing the conductor layer 158U. The arithmetic mean roughness of the second surface 70a is not less than 0.6 μm and not more than 1.1 μm. Solder bumps 76U for mounting electronic components 90 are formed on each pad 158p.

[0011] <Method for manufacturing a printed wiring board according to an embodiment> 2 and 3 show a method for manufacturing the printed wiring board 10 of the embodiment.

[0012] The intermediate substrate 1 shown in FIG. 2 is manufactured. The intermediate substrate 1 has a core substrate 30, an upper buildup layer 80A, and a lower buildup layer 80B. The core substrate 30 and the buildup layers 80A and 80B are manufactured by a well-known method. The upper buildup layer 80A has a resin insulating layer 150U and a conductor layer 158U on the resin insulating layer 150U. A first surface 158a of the conductor layer 158U is not roughened.

[0013] As shown in FIG. 3, a solder resist layer 70U is formed on the resin insulating layer 150U and the conductor layer 158U. The solder resist layer 70U is bonded to the resin insulating layer 150U and the conductor layer 158U. The solder resist layer 70U is placed on the resin insulating layer 150U and the conductor layer 158U, pressed together, and vacuum-laminated. In this embodiment, the arithmetic mean roughness of the second surface 70a of the solder resist layer 70U facing the conductor layer 158U is 0.6 μm or more and 1.1 μm or less. The second surface 70a of the solder resist layer 70U, which is in contact with the smooth first surface 158a of the conductor layer 158U, is rough. Therefore, air bubbles are easily removed when the solder resist layer 70U is vacuum-laminated onto the conductor layer 158U. According to this embodiment, the conductor layer 158U and the solder resist layer 70U have high adhesion. By setting the arithmetic mean roughness of the second surface 70a to 1.1 μm or less, a decrease in adhesion due to an excessively large arithmetic mean roughness is suppressed. The solder resist layer 70U of the printed wiring board 10 of the embodiment is less likely to peel off, unlike the solder resist layer of Patent Document 1.

[0014] The solder resist layer 70U has openings 71U that expose the conductor layer 158U. The conductor layer 158U exposed by the openings 71U functions as pads 158p for mounting the electronic component 90. Solder bumps 76U are formed on the pads 158p.

[0015] 1, an electronic component 90 is mounted on the solder bumps 76U, and the semiconductor device 200 of the embodiment is obtained. [Explanation of symbols]

[0016] 1: Intermediate board 2: Intermediate board 10: Printed wiring board 30: Core board 70a: 2nd surface 70D: Solder resist layer 70U: Solder resist layer 71U: Opening 76U: Solder bump 90: Electronic Components 150U: Resin insulation layer 158a: 1st surface 158L: Conductive layer 158U: Conductor layer 158p: Pad 160D: Via conductor 160U: Via conductor 200: Semiconductor device

Claims

1. an outermost resin insulating layer; an outermost conductor layer formed on the outermost resin insulating layer; a printed wiring board having the outermost resin insulating layer and a solder resist layer formed on the outermost conductor layer, the outermost conductor layer has a first surface facing the solder resist layer, the first surface being unroughened; The solder resist layer has a second surface facing the outermost conductor layer, and the arithmetic mean roughness of the second surface is 0.6 μm or more and 1.1 μm or less.

2. 2. The printed wiring board of claim 1, wherein the root mean square roughness of the first surface is 0.23 [mu]m or less.

3. 2. The printed wiring board according to claim 1, wherein the outermost conductor layer is made of copper.

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