Electronic control device

Abstract

To provide an electronic control device which can early transmit important data without disturbing communication processing performed by a transmission core when the important data to be urgently transmitted is generated in a microcomputer on the transmission side.SOLUTION: When communication is performed between a control microcomputer 2 and a monitoring microcomputer 3, the monitoring microcomputer 3 being on the transmission side comprises an SPI 11 and a DMAC 10 which performs DMA transfer from a transmission buffer 9 to the SPI 11. A transmission core 7 which performs transmission processing in the monitoring microcomputer 3 writes transmission date to the transmission buffer 9 and causes the DMAC 10 to start DMA transfer. When important data to be urgently transmitted to the control microcomputer 2 is generated as a result of monitoring during a period in which the DMAC 10 is performing the DMA transfer, a monitoring core 8 temporarily interrupts the DMA transfer and transfers the important data to the SPI 11 and then resumes the DMA transfer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an electronic control device that includes a plurality of microcomputers with a multi-core configuration. [Background technology]

[0002] In electronic control devices equipped with multiple microcomputers with a multi-core configuration, for example, one microcomputer is designated as a main microcomputer and the other as a sub-microcomputer, and the sub-microcomputer monitors the operation of the main microcomputer (see Patent Documents 1 and 2). In this case, when the processing load on the sub-microcomputer is relatively heavy and control synchronization is required, it is necessary to separate the cores into those that communicate with the main microcomputer and those that monitor it. Hereinafter, the cores corresponding to each function will be referred to as the transmitting core and the monitoring core, respectively. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-20544 [Patent Document 2] Japanese Patent Publication No. 2022-96920 Summary of the Invention [Problem to be solved by the invention]

[0004] In the above configuration, the transmission core of the sub-microcomputer communicates with the main microcomputer periodically. This is called periodic communication. However, when the monitoring core detects an abnormality in the object it is monitoring, it needs to send data notifying the occurrence of the abnormality to the main microcomputer as quickly as possible.

[0005] Furthermore, due to the constraints of microcomputer resources, the option of increasing the number of communication lines is not an option, and the interval between periodic communications by the transmitting core must also be maintained. In order for the monitoring core to send notification data of an abnormality, inter-core synchronization with the transmitting core is achieved using a method such as a spinlock, and the transmitting core is then made to send the notification data. In this case, if the transmitting core is performing periodic communication when inter-core synchronization begins, the notification data must be sent in the next periodic communication cycle, resulting in a significant delay in the notification of the abnormality.

[0006] The present invention has been made in consideration of the above circumstances, and its purpose is to provide an electronic control device that can transmit important data that needs to be transmitted urgently in the transmitting microcomputer quickly without interfering with the communication processing performed by the transmitting core. [Means for solving the problem]

[0007] According to the electronic control device of claim 1, when communication is performed between any two of a plurality of microcomputers, the microcomputer (3) acting as the transmitting side includes a communication interface unit (11), a transmission buffer (9), and a DMA controller (10) that performs DMA transfer from the transmission buffer to the communication interface unit. A transmission core (7) that performs transmission processing in the transmitting microcomputer writes transmission data to the transmission buffer and causes the DMA controller to start DMA transfer. If, as a result of monitoring, the DMA controller detects important data that must be urgently transmitted to another microcomputer while it is performing DMA transfer, a monitoring core (8) temporarily suspends the DMA transfer, transfers the important data to the communication interface unit, and then resumes the DMA transfer.

[0008] With this configuration, important data transferred from the monitoring core to the communication interface unit is sent to the other microcomputer promptly, and DMA transfer is then resumed. Therefore, important data that needs to be sent urgently to the other microcomputer can be sent promptly while maintaining the cycle at which the sending core executes DMA transfers for inter-microcomputer communication.

[0009] According to the electronic control device of claim 2, the monitoring core transfers important data with a data pattern that allows the receiving microcomputer to identify the important data, thereby enabling the receiving microcomputer to easily identify the received important data.

[0010] According to the electronic control device of claim 3, when important data that does not need to be urgently transmitted to another microcomputer occurs, the transmission core writes the important data with an identification data pattern to the end of the data area of ​​the transmission buffer and then starts DMA transfer, thereby transferring the relatively less urgent important data to the communication interface unit at the end of the DMA transfer and transmitting it to another microcomputer.

[0011] According to the electronic control device of claim 4, when the microcomputer (2) on the receiving side of the communication recognizes that important data has been transmitted during a DMA transfer using the identification data pattern, it invalidates the important data that was written to the end of the data area and transmitted. In other words, if relatively urgent important data is transmitted during a DMA transfer, there is no problem in invalidating relatively less urgent important data, thereby improving the efficiency of the reception process. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a diagram showing the configuration of an electronic control device according to an embodiment. [Figure 2] A flowchart showing the transmission process mainly performed by the monitoring core of the monitoring microcontroller. [Figure 3] Flowchart showing reception processing mainly by the communication core of the control microcomputer [Figure 4] A diagram showing the data format of the send buffer when regular periodic communication is performed [Figure 5] A diagram showing the data format of the receive buffer when the monitoring core sends important data during regular communication. [Figure 6] Sequence diagram showing the transmission process by each component of the monitoring microcontroller DETAILED DESCRIPTION OF THE INVENTION

[0013] An embodiment will be described below. As shown in Fig. 1, an electronic control device 1 of this embodiment includes a control microcomputer 2 and a monitoring microcomputer 3. The control microcomputer 2 controls the drive motor of, for example, an electric vehicle by controlling an inverter and a generator. The monitoring microcomputer 3 monitors the operation of the control microcomputer 2 and also monitors the state of the battery pack, which serves as the inverter drive power source and has secondary batteries as unit cells, via a battery monitoring unit 4 that includes a temperature sensor, a voltage sensor, etc. (not shown).

[0014] The control microcontroller 2 includes a communication core 5 and a monitoring core 6, and the monitoring microcontroller 3 similarly includes a communication core 7 and a monitoring core 8, each configured as a multi-core. Also, in the diagram, the communication core is designated "Core 0" and the monitoring core is designated "Core 1." The monitoring microcontroller 3 includes a transmit buffer 9, a DMA controller (DMAC) 10, and an SPI (Serial Peripheral Interface) 11. The control microcontroller 2 includes a receive buffer 12, a DMA controller 13, and an SPI 14. The communication cores 5 and 7 communicate between the microcontrollers 2 and 3, with the monitoring microcontroller 3 acting as the master and the control microcontroller 2 acting as the slave in this inter-microcontroller communication. The SPIs 11 and 14 correspond to communication interfaces.

[0015] The DMAC 10 includes a control unit CTR 15 and a transfer counter 16. When a DMA transfer starts, the transfer counter 16 is set to "0x63," which corresponds to "99," and is decremented each time one byte is transferred, becoming "0x00" when the DMA transfer ends. The monitoring core 8 can access the CTR 15 to stop or resume a DMA transfer, and can also access the transfer counter 16 to read its count value.

[0016] The communication process performed between the control microcomputer 2 and the monitoring microcomputer 3 will be outlined below. After writing the periodic communication data to the transmission buffer 9, the communication core 7 starts the DMAC 10. The periodic communication data is 100 bytes of data shown in FIG. 4, which is transmitted by the communication core 7 at regular intervals. The DMAC 10 transfers the data written in the transmit buffer 9 to the register of the SPI 11 via DMA.

[0017] SPI11 sequentially sends the DMA transferred data to SPI14. On the control microcomputer 2 side, the data received by the SPI 14 is DMA transferred to the receive buffer 12 by the DAMC 13. When the DMA transfer is completed, the communications core 5 reads the transferred data into the receive buffer 12. The monitoring core 6 of the control microcomputer 2 monitors the operation of the communication core 5 in the same manner as the monitoring microcomputer 3, but the operation of the monitoring core 6 is not relevant to the gist of this embodiment, so a description thereof will be omitted.

[0018] Next, the operation of this embodiment will be described. As shown in FIG. 4, the size of the transmission buffer 9 is, for example, 100 bytes, and the communication core 7 writes 100 bytes of periodic communication data to the transmission buffer 9 before starting the DAMC 10. The last four bytes of the 100 bytes are defined as an important data area. The first and fourth bytes of the four bytes contain data 0xAA and 0x55 for identifying important data, and the two bytes sandwiched between these identification data constitute the main body of the important data. The important data written to this important data area is data indicating the status of the battery, inverter, motor, etc., and is acquired by the monitoring core 8 and transferred to the communication core 7. However, the communication core 7 may also directly access the battery monitoring unit 4 to acquire important data.

[0019] Fig. 4 shows the data format of the send buffer 9 when 100 bytes of periodic communication data are sent as usual. This embodiment is characterized by the processing that is performed when the monitoring core 8 acquires important data related to the occurrence of an abnormality and that must be sent urgently while the periodic communication data is being DMA transferred from the send buffer 9 to the SPI 11, as shown in Fig. 5.

[0020] 2, when the battery monitoring unit 4 detects, for example, an overheating of the battery pack, an overcurrent flowing through the battery pack, or an overvoltage of a unit cell, it generates an important data update interrupt to the monitoring core 8 (S1).Then, the monitoring core 8 accesses the transfer counter 16 of the DMAC 10 to determine whether or not there are any DMA transfers remaining (S2).If the value of the transfer counter 16 is "0" and there are no DMA transfers remaining (No), the monitoring core 8 writes the important data together with the identification data directly into a register in the SPI 11 and transmits them (S6).

[0021] On the other hand, if there are DMA transfers remaining (S2; Yes), the monitoring core 8 accesses the CTR 15 and temporarily stops the DMA transfer (S3). Then, as in step S6, the important data is written directly to the SPI 11 and transmitted (S4). Thereafter, the monitoring core 8 resumes the DMA transfer (S5). Figure 6 is a sequence diagram showing the operation of the monitoring microcomputer 3 corresponding to the above transmission process.

[0022] As shown in Figure 3, when the communication core 5 of the control microcomputer 2 on the receiving side receives data via the SPI 14, it determines whether or not periodic communication is in progress (S11). If periodic communication is not in progress (No), it receives the data transmitted at that time as truly important data (S16). On the other hand, if periodic communication is in progress (Yes), it determines whether data for identifying important data is present anywhere other than the last 4 bytes of the 100 bytes (S12). If it is present only in that predetermined position (No), it treats all data as regular periodic communication data (S15), as shown in Figure 4.

[0023] In step S12, if the identification data is present in a location other than the predetermined location (Yes), the important data in the location other than the predetermined location is determined to be true (S13). The positions of the other periodic communication data are then corrected (S14) taking into account the location of the important data area in the location other than the predetermined location. That is, in response to the determination of (Yes) in step S12, for example, as shown in FIG. 5, suppose that after 60 bytes of periodic communication data are transmitted, a 4-byte important data area is transmitted. When DMA transfer is subsequently resumed, the remaining 40 bytes are transferred, but the last 4 bytes will exceed the 100-byte size.

[0024] In this case, the important data transmitted during the periodic communication is related to the occurrence of an abnormality and therefore has a relatively high urgency, while the important data located at the end of the 40 bytes is data indicating the steady state of the battery and therefore has a relatively low urgency. Therefore, by invalidating the last 4 bytes of data that exceed 100 bytes, the size of the data to be received and processed is kept within 100 bytes. This corresponds to the correction in step S14.

[0025] As described above, according to this embodiment, when communication is performed between the control microcomputer 2 and the monitoring microcomputer 3 in the electronic control device 1, the monitoring microcomputer 3, which is on the transmitting side, includes the SPI 11 and the DMAC 10, which performs DMA transfer from the transmit buffer 9 to the SPI 11. The transmit core 7, which performs transmission processing in the monitoring microcomputer 3, writes transmission data to the transmit buffer 9 and causes the DMAC 10 to start the DMA transfer. If, as a result of monitoring, important data that needs to be urgently transmitted to the control microcomputer 2 occurs while the DMAC 10 is performing DMA transfer, the monitoring core 8 temporarily suspends the DMA transfer, transfers the important data to the SPI 11, and then resumes the DMA transfer.

[0026] With this configuration, important data transferred from the monitoring core 8 to the SPI 11 is sent to the control microcomputer 2 promptly, and DMA transfer is then resumed. Therefore, important data that must be sent urgently to the control microcomputer 2 can be sent promptly while maintaining the cycle at which the transmission core 7 executes DMA transfer for inter-microcomputer communication.

[0027] Furthermore, the monitoring core 7 transfers important data with a data pattern attached to it that enables the control microcomputer 2 to identify the important data. This allows the control microcomputer 2 to easily identify the received important data. Furthermore, when important data that does not need to be sent urgently to the control microcomputer 2 occurs, the transmission core 7 writes the important data with a data pattern to the end of the data area of ​​the transmission buffer 9 and then starts DMA transfer. This allows the important data with a relatively low urgency to be transferred to the SPI 11 at the end of the DMA transfer and sent to the control microcomputer 2.

[0028] Furthermore, if the control microcomputer 2 recognizes from the data pattern that important data has been transmitted during a DMA transfer, it invalidates the important data that was written to the end of the data area. In other words, if relatively urgent important data is transmitted during a DMA transfer, there is no problem in invalidating relatively less urgent important data, thereby improving the efficiency of the reception process.

[0029] (Other embodiments) The data size of the send / receive buffer is not limited to 100 bytes, and the size of the important data area is not limited to 4 bytes. The identification data may be placed only at the beginning of the important data area. The identification data may be other than 0x55 or 0xAA. The number of cores in the microcomputer may be "3" or more. The number of microcomputers may also be "3" or more. The objects to be monitored are not limited to batteries, inverters, motors, etc. The electronic control device is not limited to that installed in an electric vehicle.

[0030] Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and equivalent modifications. In addition, various combinations and forms, including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure. [Explanation of symbols]

[0031] In the drawing, 1 indicates an electronic control device, 2 indicates a control microcomputer, 3 indicates a monitoring microcomputer, 7 indicates a communication core, 8 indicates a monitoring core, 9 indicates a transmission buffer, 10 indicates a DMA controller, and 11 indicates an SPI.

Claims

1. It has multiple microcomputers (hereinafter referred to as "microcomputers"), each of which is configured with a multi-core, When communication is performed between any two microcomputers, the microcomputer (3) that is the transmitting side has a communication interface unit (11), a transmission buffer (9), and a DMA controller (10) that performs DMA (Direct Memory Access) transfer from the transmission buffer to the communication interface unit, A transmission core (7) that performs transmission processing in the transmitting microcomputer writes the transmission data to the transmission buffer and causes the DMA controller to start the DMA transfer; One of the other cores is a monitoring core (8) that has a function of monitoring the operation of peripheral devices including other microcomputers, When important data that needs to be urgently sent to another microcomputer is generated as a result of the monitoring while the DMA controller is performing the DMA transfer, the monitoring core temporarily suspends the DMA transfer, transfers the important data to a communication interface unit, and then resumes the DMA transfer.

2. 2. The electronic control device according to claim 1, wherein the monitoring core transfers the important data with a data pattern attached thereto for enabling a receiving microcomputer to identify the important data.

3. 3. The electronic control device according to claim 2, wherein when important data that does not need to be urgently transmitted to the other microcomputer occurs, the transmission core writes the important data with the data pattern to the end of the data area of ​​the transmission buffer before starting the DMA transfer.

4. 4. The electronic control device according to claim 3, wherein when important data that does not need to be urgently transmitted to another microcomputer occurs, the transmission core writes the important data with a data pattern to the end of the data area of ​​the transmission buffer and then starts DMA transfer.

5. The microcomputer (2) on the receiving side in the communication is a control microcomputer that controls a peripheral device, 5. The electronic control device according to claim 1, wherein the transmitting microcomputer is a monitoring microcomputer in which the monitoring core monitors the operation of the control microcomputer.

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