Capacitor module
The capacitor module design on both sides of the substrate with via connections addresses integration limitations, achieving higher integration and reduced deformation through uniform thermal expansion compensation.
Patent Information
- Application Number
- JP2024084228
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-05-23
- Publication Date
- 2025-12-05
AI Technical Summary
Existing capacitor modules are limited in their ability to achieve high integration of capacitors, leading to potential deformation due to uneven thermal expansion and tension.
A capacitor module design where capacitors are mounted on both sides of an insulating substrate with vias penetrating to connect them, allowing for higher integration and uniform thermal expansion compensation.
Enhances capacitor integration while minimizing substrate deformation by ensuring uniform thermal expansion and tension distribution, improving reliability and performance.
Smart Images
Figure 2025177413000001_ABST
Abstract
Description
[Technical Field]
[0001] The present disclosure relates to a capacitor module. [Background technology]
[0002] Patent Documents 1 to 3 disclose capacitor modules in which a plurality of capacitors are integrated. In all of these documents, all of the capacitors are mounted on one surface. [Prior art documents] [Patent documents]
[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-110214 [Patent Document 2] Japanese Patent Publication No. 2020-4826 [Patent Document 3] Patent Publication No. 2021-57589 Summary of the Invention [Problem to be solved by the invention]
[0004] The above configuration has limitations on how highly integrated the capacitors can be.
[0005] An object of the present disclosure is to provide a technique that enables higher integration of capacitors. [Means for solving the problem]
[0006] The capacitor module of the present disclosure comprises: an insulating substrate having a first surface and a second surface opposite to the first surface; a plurality of first ceramic capacitors mounted on the first surface; a plurality of second ceramic capacitors mounted on the second surface; a via that penetrates the insulating substrate and electrically connects the first ceramic capacitor and the second ceramic capacitor, In the thickness direction of the insulating substrate, at least one of the first ceramic capacitors and at least one of the second ceramic capacitors are arranged at positions where they at least partially overlap each other. [Effects of the Invention]
[0007] According to the present disclosure, capacitors can be more highly integrated. [Brief explanation of the drawings]
[0008] [Figure 1] FIG. 1 is a plan view of a capacitor module according to a first embodiment. [Figure 2] FIG. 2 is a bottom view of the capacitor module of the first embodiment. [Figure 3] FIG. 3 is a cross-sectional view taken along line AA in FIG. [Figure 4] FIG. 4 is an explanatory diagram illustrating overlapping patterns in the first embodiment. [Figure 5] FIG. 5 is an explanatory diagram showing overlapping patterns in the second embodiment. [Figure 6] FIG. 6 is an explanatory diagram showing overlapping patterns in the third embodiment. [Figure 7] FIG. 7 is an explanatory diagram showing overlapping patterns in the fourth embodiment. [Figure 8] FIG. 8 is an explanatory diagram showing overlapping patterns in the fifth embodiment. [Figure 9] FIG. 9 is an explanatory diagram showing overlapping patterns in the sixth embodiment. [Figure 10] FIG. 10 is an explanatory diagram showing the overlapping area, overlapping rate, and results of Examples 1 to 6. [Figure 11] FIG. 11 is a plan view of the capacitor module of the second embodiment. [Figure 12] FIG. 12 is a cross-sectional view taken along line BB in FIG. DETAILED DESCRIPTION OF THE INVENTION
[0009] [Description of the embodiments of the present disclosure] In the following, embodiments of the present disclosure are listed and illustrated.
[0010] [1] An insulating substrate having a first surface and a second surface opposite to the first surface; a plurality of first ceramic capacitors mounted on the first surface; a plurality of second ceramic capacitors mounted on the second surface; a via that penetrates the insulating substrate and electrically connects the first ceramic capacitor and the second ceramic capacitor, In the thickness direction of the insulating substrate, at least one of the first ceramic capacitors and at least one of the second ceramic capacitors are disposed at positions where they at least partially overlap each other. Capacitor module.
[0011] In the capacitor module, at least one first ceramic capacitor and at least one second ceramic capacitor are arranged in a position where they at least partially overlap each other in the thickness direction of the insulating substrate. This allows for higher integration of the capacitors compared to a configuration in which the capacitors are arranged on only one side. Furthermore, similar compression and tension tend to occur on both sides of the insulating substrate when the ambient temperature is high or low, which helps to prevent deformation such as bending of the insulating substrate.
[0012] [2] When viewed from the thickness direction of the insulating substrate, the relationship between the area S1 of the region where the plurality of first ceramic capacitors are arranged and the area S2 of the region where the plurality of first ceramic capacitors and the plurality of second ceramic capacitors overlap satisfies the condition of the following formula (1): The capacitor module described in [1]. (S2 / S1)×100≧50[%]...Equation (1)
[0013] According to this configuration, the ratio of the area where the first ceramic capacitor and the second ceramic capacitor overlap in the thickness direction (overlap ratio) is 50% or more, which allows for higher integration of the capacitors.
[0014] [3] The relationship between the area S1 and the area S2 satisfies the condition of the following formula (2). The capacitor module according to [2]. (S2 / S1)×100≧82[%]...Equation (2)
[0015] With this configuration, the overlap rate is 82% or more, which allows for higher integration of the capacitors and suppresses deformation of the insulating substrate.
[0016] [4] When viewed from the thickness direction, each of the second ceramic capacitors is disposed at a position where it at least partially overlaps the first ceramic capacitor. The capacitor module according to any one of [1] to [3].
[0017] This configuration allows for higher integration of the capacitors compared to a configuration in which only some of the second ceramic capacitors are arranged in positions that overlap the first ceramic capacitors.
[0018] [5] The plurality of first ceramic capacitors and the plurality of second ceramic capacitors are all of the same shape. The capacitor module according to [4].
[0019] With this configuration, compression and tension occurring on both sides of the insulating substrate when the ambient temperature is high or low is more likely to be uniform, and as a result, deformation of the insulating substrate is more likely to be suppressed.
[0020] [6] The plurality of first ceramic capacitors and the plurality of second ceramic capacitors are molded with resin. The capacitor module according to any one of [1] to [5].
[0021] This configuration improves the insulation between the plurality of first ceramic capacitors and the plurality of second ceramic capacitors and the outside, and also makes the plurality of first ceramic capacitors and the plurality of second ceramic capacitors less likely to peel off from the insulating substrate.
[0022] [7] In the range of -40°C to 300°C, the difference between the linear expansion coefficient of the first ceramic capacitor and the second ceramic capacitor and the linear expansion coefficient of the insulating substrate is 10% or less. The capacitor module according to any one of [1] to [6].
[0023] According to this configuration, the amount of deformation of the first ceramic capacitor and the second ceramic capacitor relative to the insulating substrate is small in the temperature range of −40° C. to 300° C. Therefore, deformation of the insulating substrate is more easily suppressed.
[0024] [8] The first ceramic capacitor and the second ceramic capacitor contain a tungsten bronze material as a dielectric material; Used as a smoothing capacitor for inverters installed in vehicles The capacitor module according to any one of [1] to [7].
[0025] According to this configuration, the capacitor module can be used as a smoothing capacitor for an inverter to which a high voltage is applied.
[0026] [Details of the embodiments of the present disclosure] 1. First embodiment The capacitor module 1 of the first embodiment is used, for example, as a smoothing capacitor for an inverter mounted on a vehicle. As shown in Figures 1 to 3, the capacitor module 1 of the first embodiment includes an insulating substrate 10, a conductive layer 20, a plurality of first ceramic capacitors 31, and a plurality of second ceramic capacitors 32.
[0027] The insulating substrate 10 has a first surface 11 and a second surface 12 opposite to the first surface 11 .
[0028] The conductive layer 20 has a first one-side conductive layer 21, a first other-side conductive layer 22, a first intermediate conductive layer 23, a second one-side conductive layer 24, a second other-side conductive layer 25, and a second intermediate conductive layer 26.
[0029] The first one-side conductive layer 21, the first other-side conductive layer 22, and the first intermediate conductive layer 23 are disposed on the first surface 11. The second one-side conductive layer 24, the second other-side conductive layer 25, and the second intermediate conductive layer 26 are disposed on the second surface 12.
[0030] The first ceramic capacitors 31 are multilayer ceramic capacitors. The first ceramic capacitors 31 are rectangular parallelepiped-shaped. Each first ceramic capacitor 31 is mounted on the first surface 11. Each first ceramic capacitor 31 is soldered to the conductive layer 20 with solder 33. The multiple first ceramic capacitors 31 are connected in series between the first one-side conductive layer 21 and the first other-side conductive layer 22 via the first intermediate conductive layer 23. The multiple first ceramic capacitors 31 are connected in parallel between the first one-side conductive layer 21 and the first other-side conductive layer 22.
[0031] The second ceramic capacitors 32 are multilayer ceramic capacitors. The second ceramic capacitors 32 have a rectangular parallelepiped shape. Each second ceramic capacitor 32 is mounted on the second surface 12. Each second ceramic capacitor 32 is soldered to the conductive layer 20 with solder 33. The multiple second ceramic capacitors 32 are connected in series between the second one-side conductive layer 24 and the second other-side conductive layer 25 via the second intermediate conductive layer 26. The multiple second ceramic capacitors 32 are connected in parallel between the second one-side conductive layer 24 and the second other-side conductive layer 25.
[0032] The first ceramic capacitor 31 and the second ceramic capacitor 32 all have the same shape. The first ceramic capacitor 31 and the second ceramic capacitor 32 contain tungsten bronze as a dielectric material. With this configuration, the capacitor module 1 can be used as a smoothing capacitor for an inverter to which a high voltage is applied.
[0033] Moreover, in the temperature range of -40°C to 300°C, the difference between the linear expansion coefficient of the first ceramic capacitor 31 and the second ceramic capacitor 32 and the linear expansion coefficient of the insulating substrate 10 is 10% or less. With this configuration, in the temperature range of -40°C to 300°C, the amount of deformation of the first ceramic capacitor 31 and the second ceramic capacitor 32 relative to the insulating substrate 10 is small. Therefore, deformation of the insulating substrate 10 is more easily suppressed.
[0034] The capacitor module 1 includes vias 41 and 42 that penetrate the insulating substrate 10. The via 41 electrically connects the first one-side conductive layer 21 and the second one-side conductive layer 24. The via 42 electrically connects the first other-side conductive layer 22 and the second other-side conductive layer 25. The first intermediate conductive layer 23 is not electrically connected to the second intermediate conductive layer 26.
[0035] 1 to 3, when viewed from the thickness direction, each second ceramic capacitor 32 is disposed at a position where it entirely overlaps the first ceramic capacitor 31. When viewed from the thickness direction, each first ceramic capacitor 31 is disposed at a position where it entirely overlaps the second ceramic capacitor 32.
[0036] However, the first ceramic capacitor 31 and the second ceramic capacitor 32 do not have to overlap entirely in the thickness direction. A high overlap ratio is preferable from the viewpoints of high integration of the ceramic capacitors and suppression of deformation of the insulating substrate 10. The overlap ratio is expressed by S2 / S1. When viewed from the thickness direction of the insulating substrate 10, S1 is the larger of the area of the region AR1 where the multiple first ceramic capacitors 31 are arranged and the area of the region AR2 where the multiple second ceramic capacitors 32 are arranged. S2 is the area of the overlap region between the region AR1 and the region AR2 (hereinafter also referred to as the overlap area). It is preferable that the overlap ratio satisfy the condition of the following formula (1). Duplicate rate (S2 / S1)×100≧50[%]...Equation (1)
[0037] Fig. 10 shows the experimental results for the six patterns shown in Fig. 4 to Fig. 9. The experiment was conducted by repeatedly changing the temperature from -40°C to 150°C 1000 times for the six patterns shown in Fig. 4 to Fig. 9 to determine whether the first ceramic capacitor 31 and the second ceramic capacitor 32 peeled off from the conductive layer 20.
[0038] In Fig. 1 and Fig. 4 to Fig. 9, the area AR1 is indicated by a dashed-dotted frame. In Fig. 2 and Fig. 4 to Fig. 9, the area AR2 is indicated by a dashed-double-dotted frame. The overlapping area between the area AR1 and the area AR2 is indicated by a dotted pattern. The first ceramic capacitor 31 and the second ceramic capacitor 32 used in the experiment have a short side of 7 mm and a long side of 10 mm when viewed in the thickness direction. In addition, the areas of the areas AR1 and AR2 shown in Fig. 4 to Fig. 7 are both 24 mm × 39 mm = 936 mm 2 is.
[0039] 10 shows the overlapping area, overlapping rate, and results of Examples 1 to 6 corresponding to the configurations shown in Figures 4 to 9. In Example 1, the overlapping area was 23 mm x 39 mm = 897 mm 2 The overlap rate is 897 mm 2 / 936mm 2In Example 2, the overlapping area was 20 mm × 39 mm = 780 mm 2 The overlap rate is 780 mm 2 / 936mm 2 In Example 3, the overlapping area was 20 mm × 38 mm = 760 mm 2 The overlap rate is 760 mm 2 / 936mm 2 In Example 4, the overlapping area was 24 mm × 36 mm = 864 mm 2 The overlap rate is 864 mm 2 / 936mm 2 In Example 5, the overlapping area was 18 mm × 34 mm = 612 mm 2 The overlap rate is 612 mm 2 / 936mm 2 In Example 6, the overlapping area was 16 mm × 39 mm = 624 mm 2 The overlap rate is 624 mm 2 / 936mm 2 The figure was approximately 66.7%.
[0040] In Examples 1 to 4, where the overlap rate was 82% or more, no peeling occurred. In contrast, in Examples 5 and 6, where the overlap rate was 67% or less, peeling occurred. From the above, from the viewpoint of high integration of ceramic capacitors and suppression of deformation of insulating substrate 10, it is more preferable to satisfy the condition of the following formula (2). Duplicate rate (S2 / S1)×100≧82[%]...Equation (2)
[0041] As described above, in the capacitor module 1, at least a portion of each first ceramic capacitor 31 is arranged in a position that overlaps with the second ceramic capacitor 32 in the thickness direction of the insulating substrate 10. This allows for higher integration of the capacitors compared to a configuration in which the capacitors are arranged on only one side of the insulating substrate 10. Furthermore, when the ambient temperature is high or low, similar compression and tension tend to occur on both sides of the insulating substrate 10, which tends to prevent deformation such as bending of the insulating substrate 10.
[0042] Furthermore, the first ceramic capacitor 31 and the second ceramic capacitor 32 all have the same shape. With this configuration, compression and tension occurring on both sides of the insulating substrate 10 when the ambient temperature is high or low tends to become more uniform, and as a result, deformation of the insulating substrate 10 tends to be more easily suppressed.
[0043] 2. Second embodiment In the second embodiment, a configuration in which a capacitor module is resin-molded will be described. Note that the same components as those in the first embodiment are given the same reference numerals, and detailed description thereof will be omitted.
[0044] As shown in FIGS. 11 and 12, a capacitor module 201 of the second embodiment includes a resin 70, a first lead portion 71, and a second lead portion 72 in addition to the configuration of the capacitor module 1 of the first embodiment.
[0045] The insulating substrate 10, the conductive layer 20, the plurality of first ceramic capacitors 31, and the plurality of second ceramic capacitors 32 are covered with resin 70. The first lead portion 71 is electrically connected to the first one-side conductive layer 21 and protrudes outside the resin 70. The second lead portion 72 is electrically connected to the first other-side conductive layer 22 and protrudes outside the resin 70.
[0046] This configuration improves the insulation between the plurality of first ceramic capacitors 31 and the plurality of second ceramic capacitors 32 and the outside. Also, the plurality of first ceramic capacitors 31 and the plurality of second ceramic capacitors 32 are less likely to peel off from the insulating substrate 10.
[0047] <Other embodiments> The present invention is not limited to the embodiments described above and illustrated in the drawings, and the following embodiments are also included within the technical scope of the present invention. Furthermore, the various features of the above-mentioned embodiments and the embodiments to be described later may be combined in any combination as long as they are not contradictory.
[0048] (1) It is not necessary for all of the second ceramic capacitors to overlap with the first ceramic capacitors. At least some of the second ceramic capacitors may overlap with at least some of the first ceramic capacitors.
[0049] (2) The plurality of first ceramic capacitors may be connected in series or in parallel, and the plurality of second ceramic capacitors may be connected in series or in parallel.
[0050] It should be noted that the embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present invention is not limited to the embodiments disclosed herein, but is intended to include all modifications within the scope indicated by the claims or the scope equivalent to the claims. [Explanation of symbols]
[0051] 1...Capacitor module 10...Insulating substrate 11...Side 1 12…Second side 20...Conductive layer 21...First one-side conductive layer 22...First other-side conductive layer 23...First intermediate conductive layer 24...Second one-side conductive layer 25...Second other-side conductive layer 26...Second intermediate conductive layer 31...First ceramic capacitor 32...Second ceramic capacitor 41...Beer 42...Beer 71...First lead section 72...Second lead section 201...Capacitor module AR1: Region in which a plurality of first ceramic capacitors are arranged when viewed from the thickness direction of the insulating substrate AR2: Region in which multiple second ceramic capacitors are arranged when viewed from the thickness direction of the insulating substrate
Claims
1. an insulating substrate having a first surface and a second surface opposite the first surface; a plurality of first ceramic capacitors mounted on the first surface; a plurality of second ceramic capacitors mounted on the second surface; a via that penetrates the insulating substrate and electrically connects the first ceramic capacitor and the second ceramic capacitor, In the thickness direction of the insulating substrate, at least one of the first ceramic capacitors and at least one of the second ceramic capacitors are disposed at positions where they at least partially overlap each other. Capacitor module.
2. When viewed from the thickness direction of the insulating substrate, the relationship between the area S1 of the region where the plurality of first ceramic capacitors are arranged and the area S2 of the region where the plurality of first ceramic capacitors and the plurality of second ceramic capacitors overlap satisfies the condition of the following formula (1): The capacitor module according to claim 1 . (S2 / S1)×100≧50[%] ...Formula (1)
3. The relationship between the area S1 and the area S2 satisfies the condition of the following formula (2): The capacitor module according to claim 2 . (S2 / S1)×100≧82[%] ...Formula (2)
4. Each of the second ceramic capacitors is disposed at a position where it at least partially overlaps with the first ceramic capacitor when viewed in the thickness direction. The capacitor module according to any one of claims 1 to 3.
5. The plurality of first ceramic capacitors and the plurality of second ceramic capacitors all have the same shape. The capacitor module according to claim 4 .
6. The plurality of first ceramic capacitors and the plurality of second ceramic capacitors are molded with resin. The capacitor module according to any one of claims 1 to 3.
7. In the temperature range of −40° C. to 300° C., the difference between the linear expansion coefficient of the first ceramic capacitor and the second ceramic capacitor and the linear expansion coefficient of the insulating substrate is 10% or less. The capacitor module according to any one of claims 1 to 3.
8. the first ceramic capacitor and the second ceramic capacitor contain a tungsten bronze material as a dielectric material; Used as a smoothing capacitor for inverters installed in vehicles The capacitor module according to any one of claims 1 to 3.
Citation Information
Patent Citations
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JP2019110214A
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