Semiconductor integrated circuit

Abstract

To omit a complicated compensation circuit and the like.SOLUTION: A semiconductor integrated circuit is provided with an inner power line VHI which outputs an inner power voltage generated based on an external power 10, and an inner block 14 connected to the inner power line VHI. The semiconductor integrated circuit further includes: an inner ground line SUB being the ground of the inner power line VHI, an external ground terminal 12b connected with the ground of the external power 10; a rectifier element M4 arranged between the inner ground line SUB and the external ground terminal 12b and for supplying a current to the external ground terminal 12b; and a reference circuit 16 for generating a reference voltage. The ground of the reference circuit 16 is connected to the external ground terminal 12b via a first individual transistor M7.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor integrated circuit having an internal power supply line that outputs an internal power supply voltage generated based on an external power supply, and an internal circuit connected to the internal power supply line. [Background technology]

[0002] Semiconductor integrated circuits such as LSIs are usually supplied with power from an external source. Therefore, the external power line is connected to a power terminal provided on the semiconductor integrated circuit. In this case, if the external power supply is AC or to prevent the external power line from being connected in reverse, a rectifier circuit may be provided internally. The rectifier circuit is often composed of a bridge of rectifier elements such as diodes and transistors. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-220351 Summary of the Invention [Problem to be solved by the invention]

[0004] Here, when a rectifier circuit is provided, a current flows from the ground of the internal power supply line to the ground of the external power supply line via the rectifier element.

[0005] In this case, the voltage drop across the rectifier element causes the ground level of the internal power supply line of the semiconductor integrated circuit to be higher than the ground potential of the external power supply line. Therefore, in a circuit that operates based on the ground level of the external power supply line, the offset caused by the voltage drop across the rectifier element must be taken into consideration, making the compensation circuitry complex. [Means for solving the problem]

[0006] The semiconductor integrated circuit according to the present disclosure includes: A semiconductor integrated circuit having an internal power supply line that outputs an internal power supply voltage generated based on an external power supply, and an internal block connected to the internal power supply line, an internal ground line that is the ground for the internal power supply line; an external ground terminal to which the ground of the external power supply is connected; a rectifying element disposed between the internal ground line and the external ground terminal, for causing a current to flow toward the external ground terminal; a reference circuit that generates a reference voltage; Including, The ground of the reference circuit is connected to the external ground terminal via a first discrete transistor. [Effects of the Invention]

[0007] According to the semiconductor integrated circuit according to the present disclosure, by providing a dedicated rectifier with a relatively simple configuration, it is possible to omit a complex compensation circuit and the like. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a circuit diagram showing the configuration of a semiconductor integrated circuit according to an embodiment. [Figure 2] FIG. 10 is a circuit diagram showing a configuration of a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that the following embodiments do not limit the present disclosure, and configurations formed by selectively combining multiple examples are also included in the present disclosure.

[0010] "Overall structure" 1 is a circuit diagram showing the configuration of a semiconductor integrated circuit according to an embodiment. A DC voltage from an external power supply 10 is supplied to input terminals 12a and 12b. In the illustrated example, it is assumed that an external upper voltage VIN is supplied to input terminal 12a, and an external lower voltage GND is input to input terminal 12b. In this case, input terminal 12a corresponds to the external power supply terminal, and input terminal 12b corresponds to the external ground terminal.

[0011] It is also possible to reversely connect the external power supply 10, supplying the external lower voltage GND to the input terminal 12a and the external upper voltage VIN to the input terminal 12b. An AC voltage can also be supplied.

[0012] Four transistors M1, M2, M3, and M4 are connected to form a transistor bridge as a rectifier circuit. The source of transistor M1 is connected to the drain of transistor M2. The source of transistor M3 is connected to the drain of transistor M4. The drain of transistor M1 is connected to the drain of transistor M3. Furthermore, the source of transistor M2 is connected to the source of transistor M4.

[0013] In this example, the transistors M1, M2, M3, and M4 are n-channel MOSFETs, but it is also possible to use p-channel transistors, bipolar transistors, or the like.

[0014] An input terminal 12a is connected to the connection point between the source of the transistor M1 and the drain of the transistor M2, and an input terminal 12b is connected to the connection point between the source of the transistor M3 and the drain of the transistor M4.

[0015] The drains of transistors M1 and M3 are connected to an internal upper line VHI. The sources of transistors M2 and M4 are connected to an internal lower line SUB. The upper line VHI is an internal power supply line, and the lower line SUB is an internal ground line; the voltage between them is the internal power supply voltage. The input terminal 12a is connected to the gate of transistor M4 via transistor M5 and resistor R2. The gate of transistor M4 is connected to the lower line SUB via transistor Q2. Transistor Q2 is a pnp transistor with an emitter connected to the gate of transistor M4, a collector connected to the lower line SUB, and a base supplied with a clamp voltage VST. The input terminal 12b is connected to the gate of transistor M2 via transistor M6 and resistor R1. The gate of transistor M2 is connected to the lower line SUB via transistor Q1. Transistor Q1 is a pnp transistor with an emitter connected to the gate of transistor M2, a collector connected to the lower line SUB, and a base supplied with a clamp voltage VST. The transistors M5 and M6 are n-channel transistors.

[0016] One end of resistor R3 is connected to the upper line VHI, and the other end of resistor R3 is connected to the cathode of Zener diode D0, the anode of which is connected to the lower line SUB. The junction of resistor R3 and Zener diode D0 is connected to the gate of n-channel transistor M7. The drain of transistor M7 is connected to the upper line VHI, and the source is connected to the lower line SUB via resistor R4. A clamp voltage VST is taken from the junction of the source of transistor M7 and resistor R4.

[0017] In this circuit, voltage is applied to Zener diode D0 from the upper line VHI via resistor R3. If the voltage at the cathode of Zener diode D0 is equal to or greater than the breakdown voltage of Zener diode D0, the voltage at the cathode of Zener diode D0 becomes the breakdown voltage Vbr. This causes the gate voltage of transistor M7 to become Vbr, and its source voltage becomes a voltage VST = Vbr - Vgs lower than the gate voltage. In this way, the clamp voltage VST can be set according to the breakdown voltage of Zener diode D0.

[0018] The gates of transistors M5 and M6 are connected together, to which a clamp voltage VST is applied. The clamp voltage VST is also applied to the bases of transistors Q1 and Q2. Therefore, the source voltages of transistors M5 and M6 are clamped to VST-Vgs, and the bases of transistors Q1 and Q2 are clamped to VST+Vbe. This clamps the gate voltages of transistors M2 and M4 to a predetermined voltage, protecting transistors M2 and M4. Resistors R1 and R2 also mitigate sudden changes in current.

[0019] The gates and sources of the transistors M1 and M3 are shorted together, causing them to function as diodes. This sets a voltage on the upper line VHI that corresponds to the external upper voltage VIN input to either the input terminal 12a or the input terminal 12b. Note that a forward voltage drop occurs in the diode of the transistor M1 or M3, so that VHI = VIN - Vf. Note that Vf is the voltage drop of the parasitic diode of the transistor M1 or M3.

[0020] When an external upper voltage VIN is input to the input terminal 12a and an external lower voltage GND is input to the input terminal 12b, the transistor M4 turns on and the transistor M2 turns off, whereby the external upper voltage VIN is supplied to the upper line VHI and the external lower voltage GND is supplied to the lower line SUB.

[0021] Furthermore, when an external upper voltage VIN is input to the input terminal 12b and an external lower voltage GND is input to the input terminal 12a, the transistor M2 is turned on and the transistor M4 is turned off, whereby the external upper voltage VIN is supplied to the upper line VHI and the external lower voltage GND is supplied to the lower line SUB.

[0022] Transistors Q1 and Q2 are normally off because a clamp voltage VST is supplied to their bases. When an external upper voltage VIN is supplied to either input terminal 12a or input terminal 12b, the gate voltage of transistor M2 or transistor M4 may rise significantly. In this example, the voltage is clamped by transistors M5 and M6 as described above, and the rise is suppressed by resistor R1 or R2. Furthermore, transistor Q1 or Q2 is turned on, protecting transistors M2 and M4.

[0023] The upper line VHI and the lower line SUB are connected to an internal block 14. The internal block 14 is a circuit that operates by receiving power from the upper line VHI and the lower line SUB, and various circuits are employed depending on the purpose of the semiconductor integrated circuit.

[0024] The semiconductor integrated circuit also includes a reference circuit 16 that generates a reference voltage. The reference circuit 16 is normally connected to the upper line VHI and the lower line SUB to generate the reference voltage.

[0025] In this embodiment, the ground side of the reference circuit 16 is not directly connected to the lower line SUB, but is connected to the input terminal 12b via an n-channel first discrete transistor M7. The gate of the first discrete transistor M7 is connected to the gate of the transistor M4, and the first discrete transistor M7 turns on and off in the same way as the transistor M4, bypassing the transistor M4 and connecting the ground of the reference circuit 16 to the input terminal 12b.

[0026] The semiconductor integrated circuit is also provided with an ADC (analog-to-digital converter) 18 that converts analog signals into digital data. In this example, an analog signal input from a terminal ADC_IN is converted into digital data. The resulting digital data may be processed by a digital data processing unit within the semiconductor integrated circuit.

[0027] The ADC 18 compares the reference voltage supplied from the reference circuit 16 with the input analog signal and outputs the comparison result. For example, the reference voltage is resistively divided to obtain a plurality of divided voltages, and each divided voltage is compared with the input analog signal to obtain output digital data based on which divided voltage the input analog signal is higher than and which input analog signal it is lower than.

[0028] In this example, the ADC 18 receives a divided voltage from a plurality of resistors connected between an upper voltage topref, which is the power supply voltage, and a lower voltage botref, which is ground. The lower voltage botref is then connected to the input terminal 12b via a second n-channel discrete transistor M8. The second discrete transistor M8 switches on and off in the same manner as transistor M4, bypassing transistor M4 and connecting the ground of the ADC 18 to the input terminal 12b.

[0029] As described above, in this embodiment, the reference circuit 16 and the ADC 18 are connected to the input terminal 12b by the individual transistors M7 and M8, respectively. Therefore, the current I1 from the internal block 14 flows to the input terminal 12b via the transistor M4, the current I2 from the reference circuit 16 flows to the input terminal 12b via the transistor M7, and the current I3 from the ADC 18 flows to the input terminal 12b via the transistor M4. Therefore, the only currents flowing through the individual transistors M7 and M8 are the currents flowing through the reference circuit 16 and the ADC 18, respectively. In other words, the currents flowing through the reference circuit 16 and the ADC 18 can be prevented from flowing through the transistor M4 together with the current flowing through the internal block 14, and from being affected by a voltage drop at the transistor M4.

[0030] Generally, the current used for the reference is much smaller than the current consumed by the entire semiconductor integrated circuit, for example, 1 / 500 to 1 / 10,000, so rectifiers such as dedicated discrete transistors M7 and M8 can be implemented in a small area.

[0031] The ground of the reference circuit 16 is connected to the internal lower line SUB by diodes D1 and D2 that form a bidirectional circuit, and the ground of the ADC 18 is connected to the internal lower line SUB by diodes D3 and D4 that form a bidirectional circuit.

[0032] When the external power supply 10 is reverse-connected to the input terminals 12a and 12b, transistor M4 turns off and transistor M2 turns on. When transistor M4 turns off, individual transistors M7 and M8 also turn off. Therefore, the grounds of the reference circuit 16 and ADC 18 are not connected anywhere, but because there are diodes D1 and D2 and diodes D3 and D4 that allow current to flow in both directions, they are connected to the internal lower line SUB via these diodes. This eliminates problems such as unnecessary voltage application to internal elements when the external power supply 10 is reverse-connected.

[0033] "Variations" 2 is a circuit diagram showing the configuration of a modified example, in which an n-channel transistor M9 is used instead of the diodes D1 and D2, and an n-channel transistor M10 is used instead of the diodes D3 and D4.

[0034] The ground of the reference circuit 16 is connected to the input terminal 12a by a transistor M9, and the ground of the ADC 18 is connected to the input terminal 12a by a transistor M10. The gates of the transistors M9 and M10 are connected to the gate of the transistor M2.

[0035] Therefore, when the external power supply 10 is reversely connected to the input terminals 12a and 12b, the transistor M2 is turned on and the transistors M9 and M10 are turned on, so that both the reference circuits 16 and 8 can operate as they are.

[0036] "Effects of the embodiment" The circuits shown in Figures 1 and 2 incorporate a bridge-type rectifier to accommodate reverse connection of the external power supply. In this case, the voltage drop across the rectifying element (such as M4 in Figure 1) causes the ground level within the LSI (such as SUB in Figure 1) to be higher than the potential of the externally connected ground (such as GND in Figure 1). Therefore, when considering using a voltage relative to the external ground level, the offset caused by the voltage drop across the rectifying element must be taken into account, making the compensation circuitry complex.

[0037] Offset correction can also be performed by taking out the internal ground potential as an external terminal and referencing this potential as the ground level, but this also requires a separate compensation circuit.

[0038] In this embodiment, a dedicated rectifier (such as M7 and M8 in Figure 4) is provided for the reference block, etc. The voltage drop of this dedicated rectifier is simply the product of its equivalent resistance and the current flowing through it, and is not affected by other current consumption. As mentioned above, the current used for the reference is much smaller (1 / 500 to 1 / 10,000) than the current consumed by the entire LSI, so the dedicated rectifier can be implemented in a small area.

[0039] As described above, according to the semiconductor integrated circuit of this embodiment, by providing a dedicated rectifier with a relatively simple configuration, it is possible to omit a complex compensation circuit and the like. [Explanation of symbols]

[0040] 10 external power supply, 12a input terminal, 12b input terminal, 14 internal block, 16 reference circuit.

Claims

1. A semiconductor integrated circuit having an internal power supply line that outputs an internal power supply voltage generated based on an external power supply, and an internal block connected to the internal power supply line, an internal ground line that is the ground for the internal power supply line; an external ground terminal to which the ground of the external power supply is connected; a rectifying element disposed between the internal ground line and the external ground terminal, for causing a current to flow toward the external ground terminal; a reference circuit that generates a reference voltage; Including, the ground of the reference circuit is connected to the external ground terminal via a first discrete transistor; Semiconductor integrated circuit.

2. 2. The semiconductor integrated circuit according to claim 1, moreover, an ADC that performs AD conversion based on the reference voltage; the ground of the ADC is connected to the external ground terminal via a second discrete transistor; Semiconductor integrated circuit.

3. 2. The semiconductor integrated circuit according to claim 1, a connection point between the ground line and the first individual transistor and a ground of the internal power supply line are connected by a bidirectional circuit; a power supply voltage is applied to the external ground terminal, and when the first discrete transistor is turned off, the ground of the internal power supply line is connected to the external power supply terminal; Semiconductor integrated circuit.

4. 2. The semiconductor integrated circuit according to claim 1, the external power supply terminal and the internal power supply line are connected via a rectifier circuit, The rectifying element is included in the rectifying circuit. Semiconductor integrated circuit.

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