Electronic module and electronic apparatus

Abstract

To increase communication speed in an electronic module.SOLUTION: In an electronic module, a wiring board includes a plurality of wiring layers and a first to a fourth via groups. A first via connected to a first terminal of a first terminal group of a first semiconductor element and a second via connected to a second terminal of the first terminal group are arranged in a first direction. A third via connected to a third terminal of a second terminal group and a fourth via connected to a fourth terminal of the second terminal group and adjacent to the third via are arranged in a second direction intersecting the first direction. A virtual straight line connecting the first via and the second via passes between the third via and the fourth via. First wiring connecting the first via and a fifth via connected to a fifth terminal of a third terminal group of a second semiconductor element and second wiring connecting the second via and a sixth via connected to a sixth terminal of the third terminal group pass between the third via and the fourth via.SELECTED DRAWING: Figure 5A

Description

[Technical Field]

[0001] The present disclosure relates to electronic modules and electronic devices. [Background technology]

[0002] Patent Document 1 discloses a memory system including a memory controller having a plurality of transmitting terminals, a memory element having a plurality of terminals, and a printed wiring board on which the memory controller and the memory element are mounted. The transmitting terminals of the memory controller and the receiving terminals of the memory element are electrically connected by bus wiring provided on the printed wiring board. The memory controller controls the memory element by transmitting control signals, such as command signals and address signals, to the memory element via the bus wiring. The memory controller and the memory element also have data terminals for transmitting and receiving data signals. The data terminals of the memory controller are electrically connected to the data terminals of the memory element by data signal lines on the printed wiring board. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-16867 Summary of the Invention [Problem to be solved by the invention]

[0004] To process large volumes of data at high speed, electronic modules are required to have faster communication speeds. For example, a memory interface, which is an example of an electronic module, operates in synchronization with a clock signal. As the frequency of the clock signal increases due to speed increases, the period of the clock signal becomes shorter. Furthermore, control signals operate in synchronization with the clock signal. Therefore, to achieve faster communication speeds, it is necessary to reduce the variance in the time it takes for a control signal to be received by a memory element. Therefore, an object of the present disclosure is to provide an electronic module and an electronic device that can achieve higher communication speeds. [Means for solving the problem]

[0005] According to one aspect of the present disclosure, there is provided an electronic module including a wiring board and a first semiconductor element and a second semiconductor element mounted on one main surface of the wiring board, wherein the first semiconductor element includes a first terminal group and a second terminal group, the second semiconductor element includes a third terminal group and a fourth terminal group, the wiring board includes a plurality of wiring layers, a first via group having a plurality of through vias connected to a plurality of terminals of the first terminal group, a second via group having a plurality of through vias connected to a plurality of terminals of the second terminal group, a third via group having a plurality of through vias connected to a plurality of terminals of the third terminal group, and a fourth via group having a plurality of through vias connected to a plurality of terminals of the fourth terminal group, an electronic module is provided, each connected to the fourth terminal group of a semiconductor element; the first via group has a first via connected to a first terminal of the first terminal group and a second via connected to a second terminal of the first terminal group; the second via group has a third via connected to a third terminal of the second terminal group and a fourth via connected to a fourth terminal of the second terminal group and adjacent to the third via; the third via group has a fifth via connected to a fifth terminal of the third terminal group and a sixth via connected to a sixth terminal of the third terminal group; the first vias and the second vias are arranged in a first direction, and the third vias and the fourth vias are arranged in a second direction intersecting the first direction; an imaginary line connecting the first via and the second via passes between the third via and the fourth via; and a first wiring connecting the first via and the fifth via and a second wiring connecting the second via and the sixth via pass between the third via and the fourth via. [Effects of the Invention]

[0006] According to the present disclosure, it is possible to achieve higher communication speeds in electronic modules. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a perspective view illustrating an example of an electronic device according to an embodiment. [Figure 2] 1 is an explanatory diagram schematically illustrating an example of the overall configuration of an electronic module according to an embodiment; [Figure 3] 1 is a cross-sectional view illustrating a structure of a wiring layer and a via in an electronic module according to an embodiment. [Figure 4] FIG. 2 is a plan view showing an arrangement structure of terminals in a memory element according to an embodiment. [Figure 5A] 1 is a wiring diagram schematically illustrating the positional relationship and connection structure between control terminals and vias in a wiring layer of a printed wiring board according to an embodiment. [Figure 5B] FIG. 2 is a wiring diagram schematically illustrating a connection structure between command / address signal lines and vias in a wiring layer of a printed wiring board according to an embodiment. [Figure 5C] FIG. 2 is a wiring diagram schematically illustrating a connection structure between command / address signal lines and vias in a wiring layer of a printed wiring board according to an embodiment. [Figure 6A] 1 is a wiring diagram schematically illustrating the positional relationship and connection structure between control terminals and vias in a wiring layer of a printed wiring board according to an embodiment. [Figure 6B] FIG. 2 is a wiring diagram schematically illustrating a connection structure between command / address signal lines and vias in a wiring layer of a printed wiring board according to an embodiment. [Figure 6C] FIG. 2 is a wiring diagram schematically illustrating a connection structure between command / address signal lines and vias in a wiring layer of a printed wiring board according to an embodiment. [Figure 7] FIG. 2 is a plan view schematically illustrating command / address signal lines according to the first embodiment. [Figure 8A]3 is a wiring diagram schematically showing the positional relationship and connection structure between control terminals and vias in a wiring layer of the printed wiring board according to the first embodiment. FIG. [Figure 8B] 3 is a wiring diagram schematically illustrating a connection structure between command / address signal lines and vias in a wiring layer of a printed wiring board according to Example 1. FIG. [Figure 8C] 3 is a wiring diagram schematically illustrating a connection structure between command / address signal lines and vias in a wiring layer of a printed wiring board according to Example 1. FIG. [Figure 9] FIG. 10 is a diagram showing a simulation waveform in the first embodiment. [Figure 10] FIG. 10 is a plan view schematically illustrating command / address signal lines according to a second embodiment. [Figure 11A] FIG. 10 is a wiring diagram schematically illustrating a connection structure between command / address signal lines and vias in a wiring layer of a printed wiring board according to a second embodiment. [Figure 11B] FIG. 10 is a wiring diagram schematically illustrating a connection structure between command / address signal lines and vias in a wiring layer of a printed wiring board according to a second embodiment. [Figure 11C] FIG. 10 is a wiring diagram schematically illustrating a connection structure between command / address signal lines and vias in a wiring layer of a printed wiring board according to a second embodiment. [Figure 12A] 10 is a wiring diagram schematically showing a connection structure between command / address signal lines and vias in a wiring layer of a printed wiring board according to a reference example. FIG. [Figure 12B] 10 is a wiring diagram schematically showing a connection structure between command / address signal lines and vias in a wiring layer of a printed wiring board according to a reference example. FIG. [Figure 12C] 10 is a wiring diagram schematically showing a connection structure between command / address signal lines and vias in a wiring layer of a printed wiring board according to a reference example. FIG. [Figure 13] FIG. 10 is a diagram showing a simulation waveform of a reference example. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments for carrying out the present disclosure will be described in detail with reference to the drawings. Note that the present disclosure is not limited to the following embodiments and can be modified as appropriate without departing from the spirit thereof. Furthermore, in the drawings described below, components having the same function are given the same reference numerals, and their description may be omitted or simplified. Components having the same or similar functions but different configurations are described with the same name but different reference numerals, and these can also be distinguished by appropriately assigning ordinal numbers such as first and second.

[0009] [One embodiment] An electronic module and an electronic device using the electronic module according to an embodiment of the present disclosure will be described with reference to FIGS. 1 to 6C.

[0010] FIG. 1 is a perspective view showing an example of an electronic device 100 according to this embodiment. The electronic device 100 is not particularly limited, but may be, for example, an imaging device, a display device, an office machine, a printing machine, an industrial machine, or a medical machine. The electronic device 100 may include an image device 101 that handles information such as images. The electronic device 100 may also include a circuit device that handles image data corresponding to the images. The image device 101 may be, for example, an image acquisition device or an image forming device. The image acquisition device may be, for example, a sensor-based imaging device, a user-input drawing device, or an artificial intelligence-based image generation device. The image forming device may be, for example, a display device or a printing device. The circuit device may be at least one of a storage device, a communication device, a control device, an input / output device, and a computing device (processing device). For example, the circuit device may output image data based on an image signal obtained by the image acquisition device. The image forming device forms an image based on the image data output by the circuit device. In a camera, the circuit device outputs image data based on an image signal obtained by an imaging device such as a CMOS image sensor, and a display device such as a liquid crystal display or an organic electroluminescence (EL) display displays (forms) an image based on the image data output by the circuit device. In a copier, a circuit device outputs image data based on an image signal obtained by an imaging device such as a scanner, and an electrophotographic or inkjet printing device prints (forms) an image based on the image data output by the circuit device. Not only copiers, but single-function scanners and single-function printers can also be equipped with circuit devices and imaging devices.

[0011] In the example shown in Fig. 1, the electronic device 100 is an X-ray flat panel detector that can be used as a medical device. As shown in Fig. 1, the electronic device 100 includes an imaging device 101, an electronic module 200, and a housing 102. The circuit device included in the electronic device 100 includes the electronic module 200. The electronic module 200 is provided on the back surface of the imaging device 101 and is arranged inside the housing 102 together with the imaging device 101. The imaging device 101 in the X-ray flat panel detector is an imaging device that outputs image data corresponding to electromagnetic waves such as X-rays that are incident on the imaging device 101. The imaging device 101 includes a scintillator, a photodiode, a thin-film transistor array, an analog-to-digital converter, a low-noise amplifier, etc., which are not shown.

[0012] The electronic module 200 is a printed circuit board. The electronic module 200 is connected to the imaging device 101 so as to be able to control the imaging device 101. The imaging device 101 is a separate electronic module from the electronic module 200. The electronic module 200 also receives image data output by the imaging device 101. The electronic module 200 stores the input image data. The electronic module 200 performs image processing on the input image data. The electronic module 200 also transmits the image data to other electronic modules via an interface such as a LAN (Local Area Network) or a USB (Universal Serial Bus). In this way, the electronic module 200 is a circuit device that can function as a control device, a storage device, a processing device, an input / output device, and a communication device. The electronic module 200, acting as a first electronic module, is connected to a second electronic module.

[0013] FIG. 2 is an explanatory diagram schematically illustrating an example of the overall configuration of an electronic module 200 according to this embodiment. As shown in FIG. 2, the electronic module 200 includes a memory element 611, which is an example of a first semiconductor element, a memory element 612, which is an example of a second semiconductor element, and a memory controller 610, which is an example of a third semiconductor element. The memory controller 610 inputs and outputs data to and from the memory elements 611 and 612. The electronic module 200 also includes a connector 301, a connector 302, a connector 303, a converter chip 201, a resistor 613, and a printed wiring board 500. The memory element 611, the memory element 612, the memory controller 610, the connector 301, the connector 302, the connector 303, the converter chip 201, and the resistor 613 are mounted on one main surface of the printed wiring board 500. The printed wiring board 500 is, for example, a rigid board. The printed wiring board 500 has a wiring 401 , a wiring 402 , a wiring 403 , a wiring 404 , a command / address signal line 710 , a data signal line 791 , and a data signal line 792 .

[0014] The memory element 611 and the memory element 612 are the same type of memory element. The memory element 611 and the memory element 612 are, for example, DDR (Double Data Rate) 4 memories. Note that the memory element 611 and the memory element 612 are not limited to DDR4 memories, and may be memories of other standards or other types.

[0015] The imaging device 101 is connected to the connector 302 and the connector 303 via wiring members such as cables and flexible substrates (not shown). Image data is input from the imaging device 101 to the connector 302 and the connector 303 via the respective cables. The connectors 302 and the connector 303 are also electrically connected to the memory controller 610 via wiring 401 and wiring 402 of the printed wiring board 500. The image data input to the connector 302 and the connector 303 is output to the memory controller 610 via wiring 401 and wiring 402, respectively.

[0016] The memory controller 610 stores image data in the memory elements 611 and 612. The memory controller 610 also reads out the image data stored in the memory elements 611 and 612. The memory controller 610 is also electrically connected to the conversion chip 201 via the wiring 403 of the printed wiring board 500. The memory controller 610 outputs the processed image data to the conversion chip 201 via the wiring 403.

[0017] The converter chip 201 is electrically connected to the connector 301 via wiring 404 of the printed wiring board 500. A cable 304 (wiring member) is connected to the connector 301. The converter chip 201 converts image data transmitted from the memory controller 610 into a format defined by a communication standard. The converter chip 201 then outputs the converted image data to the cable 304 via the wiring 404 and the connector 301. The cable 304 is a wiring member that interconnects electronic modules and is connected to, for example, a computer for displaying images. The computer for displaying images is also an electronic module. The image data is input to the computer via the cable 304, where it is processed by the computer, such as for display on a display and for storage in a storage device.

[0018] The memory controller 610, the memory element 611, and the memory element 612 are each configured as a single semiconductor package. The memory element 611 and the memory element 612 are each electrically connected to the memory controller 610 via a data signal line 791 and a data signal line 792 on the printed wiring board 500. The data signal line 791 and the data signal line 792 are each bus wiring made up of a plurality of wires. This forms a transmission path for image data (data signals) between the memory element 611 and the memory controller 610, and between the memory element 612 and the memory controller 610.

[0019] Furthermore, the memory controller 610, the memory element 611, and the memory element 612 are electrically connected by a command / address signal line 710 on the printed wiring board 500. The command / address signal line 710 is a bus wiring made up of a plurality of signal lines. This forms a transmission path for command signals and address signals between the memory controller 610, the memory element 611, and the memory element 612.

[0020] The memory controller 610 transmits command signals and address signals to the memory elements 611 and 612 via command / address signal lines 710 in a parallel transmission manner. The parallel command signals and address signals transmitted from the memory controller 610 are received by the two memory elements 611 and 612 via the command / address signal lines 710. The memory controller 610 controls the memory elements 611 and 612 by transmitting control signals, command signals, and address signals to the memory elements 611 and 612 via the command / address signal lines 710. Each of the memory elements 611 and 612 performs processes such as storing and erasing image data in accordance with the command signals and address signals from the memory controller 610.

[0021] As described above, a memory system is configured by the memory controller 610, the memory device 611, the memory device 612, and the printed wiring board 500. The memory system is configured as a printed circuit board.

[0022] FIG. 3 is a cross-sectional view showing an electronic module 200 according to this embodiment. The printed wiring board 500 has an insulating base material and a conductive conductor that forms the wiring. The base material is, for example, glass epoxy resin. The conductor is, for example, copper. A memory controller 610, a memory element 611, and a memory element 612 are mounted on the printed wiring board 500. Note that components other than the memory controller 610, the memory element 611, and the memory element 612 may also be mounted on the printed wiring board 500.

[0023] The printed wiring board 500 is a laminated substrate having a plurality of wiring layers. The printed wiring board 500 shown in FIG. 3 has, for example, ten wiring layers 501 to 510. The wiring layers 501 to 510 are laminated in a direction perpendicular to the main surface of the printed wiring board 500 (the Z direction in the figure). Note that a base material (i.e., an insulating layer) (not shown) is provided between the wiring layers 501 to 510. The wiring layers 501 to 510 are arranged in the Z direction in the following order: wiring layer 501, wiring layer 502, wiring layer 503 (first wiring layer), wiring layer 504, wiring layer 505, wiring layer 506, wiring layer 507, wiring layer 508, wiring layer 508 (second wiring layer), and wiring layer 510. The wiring layer 501 and the wiring layer 510 form the main surface of the printed wiring board 500. That is, the wiring layer 501 and the wiring layer 510 are surface layers that are mounting surfaces on which the memory controller 610, the memory element 611, the memory element 612, etc. can be mounted. The wiring layers 502 to 509 located between the wiring layer 501 and the wiring layer 510 are inner layers. Note that a protective film such as a solder resist (not shown) may be disposed on the surfaces of the wiring layer 501 and the wiring layer 510.

[0024] Conductive patterns 570, which are conductive films that form the wiring, are formed on each of the wiring layers 501 to 510. Through vias (hereinafter referred to as "vias") 560, 561, and 562 that form the wiring are arranged so as to straddle the wiring layers 501 to 510. The vias 560, 561, and 562 are conductors formed in through holes in the wiring layers.

[0025] Note that Figure 3 does not accurately depict the data signal lines 711, 712, and command / address signal lines 710 shown in Figure 2, but rather depicts a schematic cross section of the printed wiring board 500 to explain the wiring layers 501 to 510.

[0026] The memory controller 610, memory elements 611, and memory elements 612 are mounted on a wiring layer 501, which is one of the main surfaces. Components such as capacitors and resistors (not shown) are mounted on the wiring layer 501 and the wiring layer 510. A conductor pattern that mainly serves as ground is formed on the wiring layer 502, which is adjacent to the wiring layer 501 via an insulating layer. The same is true for the wiring layer 505, which is adjacent to the wiring layer 506 via an insulating layer. The wiring layers 503 and 504 are formed with conductor patterns that mainly serve as part of wiring such as data signal lines 711, 712, and command / address signal lines 710.

[0027] The memory controller 610, the memory element 611, and the memory element 612 are joined to the printed wiring board 500 by solder 103. The memory controller 610, the memory element 611, and the memory element 612 each have a plurality of signal terminals, a plurality of power supply terminals, and a plurality of ground terminals. Of the plurality of signal terminals, some (e.g., 16) of the signal terminals are data terminals. The terminals of the memory controller 610, the memory element 611, and the memory element 612 each have a ball grid array structure in which the terminals are arranged in a matrix.

[0028] Fig. 4 is a plan view showing the arrangement of terminals in memory element 611 and memory element 612. Fig. 4 shows memory element 611 and memory element 612 as viewed from the side opposite to the side on which the terminals are arranged. In Fig. 4, each terminal is indicated by a dashed line.

[0029] The memory device 611 and the memory device 612 are DDR4-SDRAMs. As shown in Fig. 4, each of the memory device 611 and the memory device 612 has terminals in the first to third columns and the seventh to ninth columns of an area partitioned into 16 rows and 9 columns. No terminals are provided in the fourth to sixth columns. The total number of terminals is 96.

[0030] In FIG. 4, among the multiple terminals, the terminals indicated by diagonal lines are command / address terminals CKE, CS, ODT, A0 to A16, BA0, BA1, BG0, ACT, PAR, and TEN. The command / address terminals are control terminals of the memory elements, and are arranged in rows 10 to 16 and columns 2 to 9. The terminals indicated by a mesh are data terminals DQU0 to DQU7, data mask terminals DMU_n, data strobe terminals DQSU_c and DQSU_t, data terminals DQL0 to DQL7, data mask terminals DML_n, and data strobe terminals DQSL_c and DQSL_t. The data terminals, data mask terminals, and data strobe terminals are arranged in rows 1 to 9 and columns 2 to 8. The clock terminals CK_t and CK_c are arranged in rows 10 to 7 and columns 8. Other terminals include an ALERT terminal, a RESET terminal, a power supply terminal, and a ground terminal, all of which are not shown.

[0031] In general, the memory elements 611 and 612 are arranged so that their respective data terminals face the memory controller 610. The data terminals of the memory elements 611 and 612 and the data terminal of the memory controller 610 are electrically connected to each other via data signal lines 711 and 712.

[0032] In each of the memory elements 611 and 612, the command / address terminals are arranged on the side farther from the memory controller 610. The command / address signal line 710 has a fly-by wiring structure composed of multiple wires functioning as multiple signal lines. The command / address terminals of each of the memory elements 611 and 612 are electrically connected to the command / address terminal of the memory controller 610 via the command / address signal line 710. One end of the command / address signal line 710 is connected to a resistor 613. The resistor 613 is a termination element and is a chip resistor that is pulled up and connected to a termination voltage. As shown in FIG. 2, the command / address signal line 710 can be connected to the memory elements 611 and 612 by a wire that is bent in a substantially L-shape.

[0033] Referring to Figure 4, the configuration of a memory interface when connecting wiring to the command / address terminals of memory device 611 and memory device 612 is described below. When using a memory device with a 16-bit data width for 8 Gb addressing of DDR4 memory, one clock enable signal (CKE) line, one chip select signal (CS) line, and one on-die termination signal (ODT) line are used. Also, one bank group signal (BG) line, two bank address signal (BA) lines, and 17 address signal (A) lines are used. Furthermore, one active command signal (ACT) line, one parity signal (PAR) line, and one test enable signal (TEN) line are used. Therefore, a total of 26 signal lines are used.

[0034] The memory interface operates in synchronization with a clock signal. As the frequency of the clock signal increases, the period of the clock signal decreases. To increase the communication speed of the memory interface, it is effective to reduce the variation in the time it takes for the command / address signals output from the memory controller 610 to reach the memory devices 611 and 612. For example, the period of the command / address signal in a DDR3-800 memory interface is 2500 picoseconds. If the allowable variation in arrival time is 10% of the period, then the allowable value is 250 picoseconds. If the interconnect delay time for a 1mm interconnect is 7 picoseconds, then a variation in arrival time between the command / address signal lines of approximately 35.7mm is allowable. On the other hand, when using a faster DDR4-2400 memory interface, the period of the address signal is 375 picoseconds. If the allowable variation in arrival time is 10% of the period, then the allowable value is 37.5 picoseconds. In this case, the allowable variation in length between command / address signal lines is approximately 5.4 mm. As speeds continue to increase, it will be necessary to further suppress the variation in length between the multiple wires that make up the command / address signal lines.

[0035] One example of a method for aligning the lengths of command / address signal lines is meander wiring. Meander wiring is a wiring structure that adjusts the length of the wiring by making the wiring meander. When using meander wiring to align the lengths of the wiring, the length of the command / address signal bus line must be adjusted to match the longest signal line. This increases the overall length of the wiring. Therefore, as communication speeds in memory interfaces increase, the impact of frequency loss of electrical signals due to wiring becomes significant. Frequency loss reduces the amplitude voltage and increases the rise and fall times of signal waveforms, reducing voltage noise margins and timing margins. Therefore, longer wiring length hinders the speed of memory interfaces. To achieve higher communication speeds in memory interfaces, it is necessary to reduce frequency loss of electrical signals due to wiring, or in other words, shorten the wiring.

[0036] Thus, in order to increase the communication speed in the memory interface, it is necessary to suppress the variation in the length of the 26 wires connecting the control terminal of memory element 611 and the control terminal of memory element 612, and to reduce the need for wiring adjustment using meander wiring, etc.

[0037] The wiring structure of the command / address signal lines 710 in the electronic module according to this embodiment will be described in detail below. Fig. 5A is a wiring diagram that schematically shows the positional relationship and connection structure between the control terminals and vias in the wiring layer 501 of the printed wiring board 500. An area 611r surrounded by a dashed line indicates an area in the wiring layer 501 where the memory element 611 is mounted. Within the area 611r, areas R1 and R2 are areas where the command / address control terminals are arranged. The memory element 611 includes two terminal groups.

[0038] The first terminal group in region R1 includes a plurality of terminals arranged in columns 2 and 3 of rows 10 to 16. The second terminal group in region R2 includes a plurality of terminals arranged in columns 7 and 8 of rows 11 to 16 and columns 14 to 8. In an electronic module incorporating a plurality of memory devices, control terminals having the same function are connected by wiring. Therefore, command / address wiring is routed in the left-right direction (X direction in the figure) of region 611r in which memory devices are arranged in FIG. 5A. The 14 command / address wirings connected to the first terminal group cross region R2, in which the second terminal group is arranged, through vias in a layer (inner layer) inside wiring layer 501. Similarly, the 12 command / address wirings connected to the second terminal group cross region R1, in which the first terminal group is arranged, in an inner layer.

[0039] 5A, a via is connected to each terminal of the first terminal group and the second terminal group. In an area 611r where a memory element 611 is mounted, printed wiring board 500 includes a first via group having a plurality of vias connected to the plurality of terminals of the first terminal group, respectively, and a second via group having a plurality of vias connected to the plurality of terminals of the second terminal group, respectively.

[0040] Specifically, via 562a (first via) of the first via group is connected to control terminal 611a (first terminal) of the first terminal group. Via 562b (second via) of the first via group is connected to control terminal 611b (second terminal) of the first terminal group. Control terminals 611a and 611b are arranged in row M (12). Via 562c (third via) of the second via group is connected to control terminal 611c (third terminal) of the second terminal group. Control terminal 611c is arranged in row L (11). Via 562d (fourth via) of the second via group is connected to control terminal 611d (fourth terminal).

[0041] The control terminal 611d is arranged in row N (13). The via 562d is adjacent to the via 562c in the Y direction. The vias 562a and 562b are arranged in the X direction (first direction). The vias 562c and 562d are arranged in the Y direction (second direction) that intersects the X direction. An imaginary line connecting the vias 562a and 562b passes between the vias 562c and 562d. The control terminal 611a (first terminal) and the control terminal 611b (second terminal) are arranged in the X direction (fourth direction). The control terminal 611i (ninth terminal) and the control terminal 611b (second terminal) are arranged in the Y direction (third direction).

[0042] 5A, the control terminal (A14 signal terminal) 611n is arranged in row L(11) and is connected to the via 562n by wiring. The via 562n is arranged in row V1a, which is spaced apart from row L(11). Similar structures are provided in multiple locations as shown in FIG. 5A. By arranging the vias in this manner, in the first terminal group, the number of control terminals is seven rows from row K(10) to row T(16), while the vias are arranged in five rows from row V1a to row V1e. In the first terminal group, the number of via rows is less than the number of control terminal rows. The control terminals arranged in seven rows and two columns are matrix-converted into a via arrangement of five rows and three columns.

[0043] Similarly, in the second terminal group, the control terminals are arranged in six rows from row L(11) to row T(16), while the vias are arranged in four rows from row V2a to row V2d. In the third terminal group, the number of via rows is also fewer than the number of control terminal rows. The control terminals arranged in 6 rows and 2 columns are matrix converted to a via arrangement of 4 rows and 3 columns.

[0044] As shown in FIG. 5A, rows V1a, V1b, V1c, V1d, and V1e in which vias connected to the first terminal group are arranged alternate with rows V2a, V2b, V2c, and V2d in which vias connected to the second terminal group are arranged.

[0045] 5B is a wiring diagram schematically showing the positional relationship between vias and wires in the wiring layer 503 of the printed wiring board 500. Wiring S1 (first wiring) extending from the via 562a is a command / address wiring connected to a via (fifth via) on the memory element 612 side, which will be described later. Wiring S2 (second wiring) extending from the via 562b is a command / address wiring connected to a via (second via) on the memory element 612 side, which will be described later. A first signal (control signal) from the memory controller 610 is supplied to the memory elements 611 and 612 via wiring S1. Similarly, a second signal (control signal) from the memory controller 610 is supplied to the memory elements 611 and 612 via wiring S2.

[0046] 5B, four command / address lines are arranged between via 562m and via 562b. Line S3 connected to via 562c is generally linear because its wiring path is not obstructed by vias 562m and 562b. Linear wiring allows memory elements to be connected with short wiring. Taking line S3 as an example, it is wired in the X direction between rows V1a and V1b. The same applies to line S4 extending from via 562d.

[0047] Furthermore, since the vias are arranged regularly, the wiring can also be arranged regularly. Therefore, for example, wirings of similar shapes, such as wirings S3, S4, S13, and S14, can be used. Using wirings of similar shapes can reduce the variation in length between the wirings of the memory elements. Note that, in FIG. 5B, the wiring S1 (first wiring) and the wiring S2 (second wiring) extending from the via 562b have partially different shapes. However, the difference in length between the wirings S1 and S2 is preferably within 10% or less of the length of the reference wiring (e.g., wiring S1 or wiring S2), and more preferably within 5% or less. If the difference is within this range, the variation in length between the two wirings can be considered small.

[0048] FIG. 5C is a wiring diagram schematically showing the positional relationship of multiple vias in wiring layer 508 of printed wiring board 500. In row V1b, via 562i (9th via) is arranged between via 562a and via 562b. Via 562i is connected to control terminal 611b (second terminal) of the first terminal group shown in FIG. 5A. Wiring S5 (5th wiring) extending from via 562i is connected to a via (10th via) on the side of memory element 612, which will be described later. The above-mentioned wiring S1 and wiring S2 are wirings formed in wiring layer 503 of multiple wiring layers. In contrast, wiring S5 is formed in a wiring layer different from wiring S1 and wiring S2.

[0049] As shown in FIG. 5C, multiple vias are arranged between row V1a and row V1b. Two command / address wirings are arranged between via 562b and via 562m. The wiring S21 connected to via 562o is not obstructed by vias 562b and 562m, so it is a generally straight wiring. This allows memory elements to be connected with short wiring.

[0050] Furthermore, since the vias are arranged regularly, the wiring can also be arranged regularly. For example, wirings of similar shapes, such as wirings S21, S22, S23, and S24, can be used. This reduces the variation in wiring length between the multiple wirings connecting the memory element 611 and the memory element 612.

[0051] 6A is a wiring diagram that schematically illustrates the positional relationship between control terminals, vias, and wiring in wiring layer 501 of printed wiring board 500. Region 612r surrounded by a dashed line indicates the region in wiring layer 501 where memory element 612 is mounted. Like memory element 611, memory element 612 includes two terminal groups. Within region 612r, regions R3 and R4 are regions where command / address control terminals are arranged.

[0052] The third terminal group in region R3 includes a plurality of terminals arranged in the second and third columns of the tenth to sixteenth rows. The fourth terminal group in region R4 includes a plurality of terminals arranged in the seventh and eighth columns of the eleventh to sixteenth rows and the eighth column of the fourteenth row. As in the case of FIG. 5A, the command / address wiring is routed in the left-right direction (the X direction in the figure) of region 612r in which memory elements are arranged in FIG. 6A. The fourteen command / address wirings connected to the third terminal group cross region R4 in which the fourth terminal group is arranged, via vias, in a layer more inward than wiring layer 501. Similarly, the twelve command / address wirings connected to the fourth terminal group cross region R3 in which the third terminal group is arranged, via vias, in a layer more inward than wiring layer 501.

[0053] In Fig. 6A, a via is connected to each control terminal of the third terminal group and the fourth terminal group. In an area 612r where a memory element 612 is mounted, printed wiring board 500 includes a third via group having a plurality of vias connected to a plurality of terminals of the third terminal group, respectively, and a fourth via group having a plurality of vias connected to a plurality of terminals of the fourth terminal group, respectively. The first terminal group of memory element 611 shown in Fig. 5A is connected to the third terminal group of memory element 612 via the first via group and the third via group. Similarly, the second terminal group of memory element 611 is connected to the fourth terminal group of memory element 612 via the second via group and the fourth via group, respectively.

[0054] Specifically, via 562e (fifth via) of the third via group is connected to control terminal 612e (fifth terminal) of the third terminal group. Via 562f (sixth via) of the third via group is connected to control terminal 612f (sixth terminal) of the third terminal group. Via 562g (seventh via) of the fourth via group is connected to control terminal 612g (seventh terminal) of the fourth terminal group. Via 562h (eighth via) is connected to control terminal 612h (eighth terminal). Vias 562e and 562f are adjacent to each other in the Y direction. Vias 562e and 562f are arranged in the X direction. Vias 562g and 562h are arranged in the Y direction that intersects with the X direction. An imaginary line connecting vias 562e and 562f passes between vias 562g and 562h. In this embodiment, since memory element 611 and memory element 612 are arranged side by side on the main surface of printed wiring board 500, the imaginary line connecting via 562e and via 562f and the imaginary line connecting via 562a and via 562b described above are located on the same imaginary line.

[0055] 6A, the control terminal 612u is arranged in row L(11) and is connected to the via 562u by a wiring. The via 562u is arranged in row V1a, which is spaced apart from row L(11) in the Y direction. Similar structures are provided in multiple locations. By arranging the vias in this manner, in the third terminal group, the number of control terminals is seven rows from row K(10) to row T(16), while the number of vias is five rows from row V1a to row V1e. In the third terminal group, the number of via rows is less than the number of control terminal rows.

[0056] Similarly, in the fourth terminal group, the control terminals are arranged in six rows from row L(11) to row T(16), while the vias are arranged in four rows from row V2a to row V2d. In the fourth terminal group as well, the number of via rows is fewer than the number of control terminal rows.

[0057] As shown in FIG. 6A, rows V1a, V1b, V1c, V1d, and V1e in which vias connected to the third terminal group are arranged alternate with rows V2a, V2b, V2c, and V2d in which vias connected to the fourth terminal group are arranged.

[0058] FIG. 6B is a wiring diagram schematically showing the positional relationship between vias and wiring in wiring layer 503 of printed wiring board 500. In FIG. 6B, multiple vias are arranged between row V2a and row V2b. Therefore, four command / address wirings can be arranged between row V2a and row V2b. Wiring S1 (first wiring) is a command / address wiring that connects via 562e and via 562a (first via) shown in FIG. 5A. Wiring S2 (second wiring) is a command / address wiring that connects via 562f and via 562b (second via) shown in FIG. 5A. Wiring S3 (third wiring) is a command / address wiring that connects via 562g and via 562c (third via) shown in FIG. 5A. Wiring S4 (fourth wiring) is a command / address wiring that connects via 562h and via 562d (fourth via) shown in FIG. 5A. The wires S1 and S2 pass between the wires S3 and S4. The wire S1 is not obstructed by the vias 562g and 562h, so it is a generally straight wire. This is also true for the wire S2 connected to the via 562f. The length of the wire S1 is the length from the via 562a (first via) to the via 562e (fifth via), and the length of the wire S2 is the length from the via 562b (second via) to the via 562f (sixth via). Similarly, the length of the other wires is the length between the two vias they connect.

[0059] Furthermore, since the vias are arranged regularly, the wiring can also be arranged regularly. This allows the use of wiring with similar shapes, such as wiring S3 and S4. By using wiring with similar shapes, it is possible to reduce the variation in wiring length between memory elements.

[0060] 6C is a wiring diagram schematically showing the positional relationship of multiple vias in wiring layer 508 of printed wiring board 500. In row V1b, via 562j (tenth via) is arranged between via 562e and via 562f. Via 562j is connected to control terminal 611j (tenth terminal) of the third terminal group shown in FIG. 6A. Via 562j is connected to via 562i (ninth via) shown in FIG. 5C by wiring S5 (fifth wiring). Wiring S5 passes between via 562g and via 562h in the Y direction. The wiring path of wiring S5 is not obstructed by vias 562g and via 562h.

[0061] Furthermore, since the vias are arranged regularly, the wiring can be arranged regularly. Also, wirings of similar shapes can be used. By using wirings of similar shapes, it is possible to reduce variations in the lengths of the wirings connecting the memory element 611 and the memory element 612.

[0062] As described above, the via placement according to this embodiment can suppress variations in the lengths of the wires among multiple wires and reduce the need for wire adjustments using meander wiring or the like. Furthermore, suppressing variations in the lengths of the wires can reduce variations in the arrival times of control signals received by memory elements. As a result, the communication speed in the memory interface can be increased.

[0063] In this embodiment, a memory element (storage element) has been described as an example of a semiconductor element, but the semiconductor element in the electronic module 200 according to this embodiment is not limited to a memory element. The semiconductor element in the electronic module 200 may be a sensor element, a display element, a control element, a power supply element, a communication element, an arithmetic element, a control element, or the like. The wiring board in the electronic module 200 may be a printed circuit board including a printed wiring board having a wiring structure similar to that of the printed wiring board 500.

[0064] [Example] Next, a more specific configuration of the printed wiring board 500 according to this embodiment will be described using Example 1, Example 2, and a reference example with reference to FIGS. Example 1 Fig. 7 is a plan view schematically illustrating command / address signal lines according to Example 1. As shown in Fig. 7, the memory controller 610 is arranged on the printed wiring board 500 at a distance from the memory elements 611 and 612 in the Y direction, which is perpendicular to the X and Z directions.

[0065] The command / address signal lines 710 have a fly-by wiring structure. The connection structure of one command / address line among the 25 command / address signal lines 710 will be described below. The command / address terminal 610a of the memory controller 610 and the via 561 are connected by a data signal line 711 formed on the wiring layer 501, which is the surface layer of the printed wiring board 500. In this description, the data signal line 711 is an inner layer wiring, but the data signal line 711 may also be a surface layer wiring. The via 561 and the via 560 are connected to a data signal line 712 provided on an inner layer. The via 560 and a via 562a arranged close to the memory element 611 are connected by the data signal line 712, which is an inner layer wiring.

[0066] In the first embodiment, the data signal line 712 is formed in the wiring layer 503. The via 562k and the control terminal 611k, which is a command / address terminal of the memory element 611, are connected by a surface wiring 713. The via 562k and the via 562s arranged close to the memory element 612 are connected by an inner layer wiring 714 formed in the wiring layer 508, which is an inner layer. The via 562s and the command / address terminal 612s of the memory element 612 are connected by a surface wiring 715 formed in the wiring layer 501, which is a surface layer. The via 562s and the via 562u are connected by a wiring 716 formed in the wiring layer 503, which is an inner layer. The via 562u and the resistor 613 are connected by a wiring 717 formed in the surface layer. In this way, the wiring connecting the first memory element and the second memory element has a structure in which the wiring layer is switched for each intervening via. Similarly, wiring layers for wiring other than the command / address signal line 710 are switched for each via. Wiring layers connecting memories are preferably inner layers close to the surface. In this embodiment, the inner wiring layers 502 and 509 are ground plane layers. The command / address wiring connecting memories is arranged in wiring layers 503 and 508, which are located inside the ground plane layer.

[0067] Next, the structure of the command / address wiring connecting the memory element 611 and the memory element 612 will be described with reference to FIGS. 8A to 8C. FIG. 8A is a diagram of the wiring structure of the wiring layer 501 as viewed from the Z direction. FIG. 8B is a diagram of the wiring structure of the wiring layer 503. FIG. 8C is a diagram of the wiring structure of the wiring layer 508. The via arrangement in FIGS. 8A to 8C is similar to the via arrangement shown in FIGS. 5A to 6C. The command / address wiring connecting the memory element 611 and the memory element 612 can be wired in a straight line. Straight wiring allows the memory elements to be connected with short wiring. Furthermore, since the vias are arranged regularly, the wiring can also be arranged regularly. For example, the wirings S3, S4, S13, and S14 in FIG. 8B have similar shapes. Similarly, the wirings S21, S22, S23, and S24 in FIG. 8C have similar shapes. Using wirings with similar shapes can reduce variations in the length of the wiring between the memory elements.

[0068] In Example 1, the center-to-center distance L between the memory elements 611 and 612 is 13.6 mm. The lengths of the inner layer wiring between the memory elements 611 and 612 for the CKE signal wiring, CS signal wiring, ODT signal wiring, A14 signal wiring, A15 signal wiring, and A16 signal wiring are as shown in Table 1. The length excluding the 13.6 mm memory center-to-center distance is 0.3 mm to 0.7 mm. It can be seen that memories are connected with short wiring. The length variation is 0.4 mm, which indicates that the wiring length variation is suppressed. Because the command / address wiring is short, the signal driving capability of the memory controller can be reduced. The variation in wiring length between multiple wirings is preferably 10% or less of the reference wiring length, and more preferably 5% or less. [Table 1]

[0069] Figure 9 shows the waveform simulation results of the command / address signal of Example 1. In Figures 9(a) to 9(c), the data transfer rate was changed to 2400 Mbps, 4800 Mbps, and 6400 Mbps, and the waveform degradation was compared. Here, the delay time variation (jitter) was observed under voltage conditions where the rising and falling edges of the waveform cross. In Figures 9(a) to 9(c), no significant increase in the delay time variation was observed. In other words, it was confirmed that the command / address wiring of Example 1 is suitable for increasing the communication speed in a memory interface.

[0070] As described above, the via arrangement shown in Example 1 can suppress variations in length between wirings and reduce the need for wiring adjustments using meander wiring, etc., thereby increasing the communication speed in the memory interface.

[0071] Example 2 FIG. 10 is a plan view schematically illustrating command / address signal lines according to the second embodiment. Here, a part of the memory controller 610 and parts of the memory elements 611 and 612 are shown when the electronic module 200 is viewed in a plan view, i.e., in the Z direction. Also, FIGS. 11A to 11C are wiring diagrams schematically illustrating the connection structure between the command / address signal lines and vias in the wiring layer of the printed wiring board according to the second embodiment. As shown in FIG. 10, the memory controller 610 is disposed on the printed wiring board 500 at intervals in the Y direction relative to the four memory elements (memory elements 611-1, 612-1, 611-2, and 612-2).

[0072] Since the vias are arranged regularly, the wiring can also be arranged regularly. For example, wirings of similar shapes can be used, such as the four wirings S11a, S12a, S13a, and S14a shown in Figure 11B. Wires of similar shapes in the X direction can be used, such as wirings S11b, S12b, S13b, and S14b. Similarly, wirings of similar shapes in the Y direction can be used, such as wirings S21a to S24a in Figure 11C, and wirings of similar shapes in the X direction can be used, such as wirings S21b to S24b.

[0073] As described above, according to the via arrangement shown in Example 2, similar wiring can be used in the X and Y directions. Even when the number of memory elements is increased, the variation in length between wirings can be suppressed and the need for wiring adjustment using meander wiring or the like can be reduced, thereby increasing the communication speed in the memory interface.

[0074] (Reference example) 12A to 12C are wiring diagrams showing the connection structure between command / address signal lines and vias in the wiring layer of a printed wiring board according to a reference example. Parts of regions 611x and 612x where two memory devices are mounted are shown. To shorten the stub wiring, vias are arranged to shorten the wiring between the control terminals and vias. For example, via 562bx is arranged close to control terminal (ODT signal terminal) 611bx and connected by wiring. In this arrangement, vias are arranged at the same interval as the control terminal interval in the Y direction, so that the vias are arranged consecutively between the control terminals. In region R1, seven vias are arranged consecutively in the Y direction. If one wire is arranged between the vias, only eight or nine wires can cross region R1, which is insufficient for the 26 command / address wires. Therefore, the number of wiring layers must be increased or the wires must be routed outside regions 611x and 612x where the memories are arranged in the Y direction. Since the wiring length increases due to the detour, the length of the wiring that does not take the detour must be adjusted by using meander wiring or the like so that it is approximately the same length as the length increased by the detour.

[0075] In the reference example, the center-to-center distance L between the regions 611x and 612x in which the memory elements are arranged is 13.6 mm, the same distance as in Example 1. The lengths of the inner layer wiring in the regions 611x and 612x for the CKE signal wiring, CS signal wiring, ODT signal wiring, and A14, A15, and A16 signal wiring are as shown in Table 2. The length excluding the 13.6 mm memory center-to-center distance is 1.3 mm to 5.3 mm. The wiring is longer by the amount of the wiring detour. The variation in length is 4.0 mm, which is greater than in Example 1. [Table 2]

[0076] The signal driving capability of the memory controller must be increased to accommodate the longer command / address wiring. Figure 13 shows the waveform simulation results for the command / address signal of the reference example. Figures 13(a) to 13(c) show the waveform simulation results when the data transfer rate is changed to 2400Mbps, 4800Mbps, and 6400Mbps, respectively, and compare the waveform degradation. Here, the delay time variation (jitter) was observed under voltage conditions where the rising and falling edges of the waveform intersect. Figures 13(a) to 13(c) show an increase in the delay time variation, unlike the above-mentioned example.

[0077] As described above, according to the first and second embodiments of the present disclosure, unlike the reference example, the variation in wiring length is suppressed and the wiring can be shortened, thereby increasing the communication speed in the memory interface.

[0078] [Modified embodiment] The present disclosure is not limited to the above-described embodiments, and many modifications are possible within the technical concept of the present disclosure. For example, an example in which part of the configuration of one embodiment is added to another embodiment, or an example in which part of the configuration of another embodiment is replaced with another embodiment, is also an embodiment of the present disclosure. Furthermore, the effects described in the embodiments are merely a list of the most preferable effects resulting from the present disclosure, and the effects of the present disclosure are not limited to those described in the embodiments.

[0079] For example, in the above-described embodiment, the memory element 611 and the memory element 612 are located at the same position in the Y direction on one main surface of the printed wiring board 500 and are arranged along the X direction. Therefore, the multiple wirings extend in parallel in the X direction from the terminal group of the memory element 611 to the terminal group of the memory element 612. However, the relative positions of the memory element 611 and the memory element 612 are not limited to this. That is, the memory element 611 and the memory element 612 may be arranged offset in the Y direction. In this case, the wirings extend in parallel in a diagonal direction from the terminal group of the memory element 611 to the terminal group of the memory element 612, but variation in the length of the wirings among the multiple wirings can be suppressed, as in the above-described embodiment.

[0080] In the above-described embodiment, the memory element 611 and the memory element 612 have a common structure, and the positional relationship between the terminal group and the via group in the memory element 611 is the same as the positional relationship between the terminal group and the via group in the memory element 612. Therefore, region R2 (second terminal group) is located between region R1 (first terminal group) and region R3 (third terminal group), and region R3 (third terminal group) is located between region R2 (second terminal group) and region R4 (fourth terminal group). However, the structures of the memory element 611 and the memory element 612 may be different. For example, the memory element 611 and the memory element 612 may have mirror-symmetric structures. For example, region R2 (second terminal group) may be located between region R1 (first terminal group) and region R3 (third terminal group), and region R4 (fourth terminal group) may be located between region R2 (second terminal group) and region R3 (third terminal group).

[0081] In the above-described embodiment, the electronic device is described as including an imaging device, but the electronic device to which the electronic module of the present disclosure can be applied is not limited to those including an imaging device, and may be, for example, an information device or communication device that does not include an imaging device, a display device, or a printing device.

[0082] The present disclosure includes the following configurations. (Configuration 1) A wiring board; an electronic module comprising: a first semiconductor element and a second semiconductor element mounted on one main surface of the wiring board; the first semiconductor element includes a first terminal group and a second terminal group; the second semiconductor element includes a third terminal group and a fourth terminal group; the wiring board includes a plurality of wiring layers, a first via group having a plurality of through vias respectively connected to a plurality of terminals of the first terminal group, a second via group having a plurality of through vias respectively connected to a plurality of terminals of the second terminal group, a third via group having a plurality of through vias respectively connected to a plurality of terminals of the third terminal group, and a fourth via group having a plurality of through vias respectively connected to a plurality of terminals of the fourth terminal group; the first terminal group of the first semiconductor element is connected to the third terminal group of the second semiconductor element via the first via group and the third via group, and the second terminal group of the first semiconductor element is connected to the fourth terminal group of the second semiconductor element via the second via group and the fourth via group, the first via group includes a first via connected to a first terminal of the first terminal group and a second via connected to a second terminal of the first terminal group; the second via group includes a third via connected to a third terminal of the second terminal group, and a fourth via connected to a fourth terminal of the second terminal group and adjacent to the third via; the third via group includes a fifth via connected to a fifth terminal of the third terminal group and a sixth via connected to a sixth terminal of the third terminal group; the first vias and the second vias are arranged in a first direction, the third vias and the fourth vias are arranged in a second direction intersecting the first direction, a virtual line connecting the first vias and the second vias passes between the third vias and the fourth vias, and a first wiring connecting the first vias and the fifth vias and a second wiring connecting the second vias and the sixth vias pass between the third vias and the fourth vias; 1. An electronic module comprising: (Configuration 2) the fourth via group includes a seventh via connected to a seventh terminal of the fourth terminal group, and an eighth via connected to an eighth terminal of the fourth terminal group and adjacent to the seventh via, the seventh via and the eighth via are arranged in the second direction, the first wiring and the second wiring pass between a third wiring that connects the third via and the seventh via and a fourth wiring that connects the fourth via and the eighth via; 2. The electronic module according to claim 1, (Configuration 3) the fifth via and the sixth via are disposed between the third wiring and the fourth wiring; 3. The electronic module according to configuration 2. (Configuration 4) the fifth via and the sixth via are arranged in the first direction, and a virtual line connecting the fifth via and the sixth via passes between the seventh via and the eighth via; 3. The electronic module according to configuration 2. (Configuration 5) the imaginary line connecting the first via and the second via and the imaginary line connecting the fifth via and the sixth via are located on the same imaginary line; 5. The electronic module according to any one of configurations 1 to 4. (Configuration 6) the first via group includes a ninth via connected to a ninth terminal of the first terminal group; the imaginary line connecting the first via and the second via passes through the ninth via, the second terminals and the ninth terminals are arranged in a third direction intersecting the first direction; 2. The electronic module according to claim 1, (Configuration 7) the ninth via is disposed between the first via and the second via; 7. The electronic module according to configuration 6. (Configuration 8) the first terminals and the second terminals are arranged in a fourth direction intersecting the third direction; 7. The electronic module according to configuration 6. (Configuration 9) the fourth via group includes a seventh via connected to a seventh terminal of the fourth terminal group, and an eighth via connected to an eighth terminal of the fourth terminal group and adjacent to the seventh via, the third via group includes a tenth via connected to a tenth terminal of the third terminal group; a fifth wiring connecting the ninth via and the tenth via passes between the seventh via and the eighth via; 7. The electronic module according to configuration 6. (Configuration 10) the third via group includes a tenth via connected to a tenth terminal of the third terminal group; the tenth via is disposed between the fifth via and the sixth via; 9. The electronic module of configuration 8. (Configuration 11) the first wiring and the second wiring are provided in a first wiring layer of the plurality of wiring layers, The fifth wiring is provided in a second wiring layer of the plurality of wiring layers. 10. The electronic module of claim 9. (Configuration 12) a difference between the length of the first wiring and the length of the second wiring is 10% or less of the length of the first wiring or the second wiring; 2. The electronic module according to claim 1, (Configuration 13) the first wiring and the second wiring have a fly-by wiring structure; 2. The electronic module according to claim 1, (Configuration 14) a first signal is supplied to the first semiconductor element and the second semiconductor element via the first wiring, and a second signal is supplied to the first semiconductor element and the second semiconductor element via the second wiring; 2. The electronic module according to claim 1, (Configuration 15) the first semiconductor device and the second semiconductor device are memories, a memory controller mounted on the wiring board and performing input and output of data with the first semiconductor element and the second semiconductor element; 2. The electronic module of claim 1, further comprising: (Configuration 16) the first terminal, the second terminal, the fifth terminal, and the sixth terminal are control terminals; 2. The electronic module according to claim 1, (Configuration 17) the first terminal group, the second terminal group, the third terminal group, and the fourth terminal group have a ball grid array structure; 2. The electronic module according to claim 1, (Configuration 18) Further comprising a plurality of connectors mounted on the wiring board. 2. The electronic module according to claim 1, (Configuration 19) a first electronic module that is the electronic module according to any one of configurations 1 to 18; a second electronic module; a wiring member that connects the first electronic module and the second electronic module to each other; An electronic device comprising: (Configuration 20) an image capture device; a circuit device that outputs image data based on an image signal obtained by the image acquisition device, The circuit arrangement includes an electronic module according to any one of configurations 1 to 18. An electronic device characterized by: (Configuration 21) an image forming device that forms an image based on the image data; 21. The electronic device according to configuration 20. (Configuration 22) a circuit device for outputting image data; an image forming device that forms an image based on the image data, The circuit arrangement includes an electronic module according to any one of configurations 1 to 18. An electronic device characterized by: (Configuration 23) the image forming device is a display device, 23. The electronic device according to configuration 22. (Configuration 24) the image forming apparatus is a printing apparatus; 23. The electronic device according to configuration 22.

[0083] The disclosure of this specification includes not only what is explicitly described in this specification, but also all matters that can be understood from this specification and the drawings attached hereto. The disclosure of this specification also includes the complement of the individual concepts described in this specification. In other words, if this specification states, for example, that "A is B," it can be said that this specification discloses that "A is not B," even if it omits the statement that "A is not B." This is because when "A is B," it is assumed that the case where "A is not B" is taken into consideration. [Explanation of symbols]

[0084] 100...Electronic equipment 200 Electronic Module 500···Printed wiring board 501, 502, 503, 504, 505, 506, 507, 508, 509, 510...Wiring layer 562a, 562b, 562c, 562d, 562e, 562f, 562g, 562h, 562i, 562j... via 610 Memory Controller 611, 612...Memory elements

Claims

1. A wiring board; an electronic module comprising: a first semiconductor element and a second semiconductor element mounted on one main surface of the wiring board; the first semiconductor element includes a first group of terminals and a second group of terminals; the second semiconductor element includes a third terminal group and a fourth terminal group; the wiring board includes a plurality of wiring layers, a first via group having a plurality of through vias respectively connected to a plurality of terminals of the first terminal group, a second via group having a plurality of through vias respectively connected to a plurality of terminals of the second terminal group, a third via group having a plurality of through vias respectively connected to a plurality of terminals of the third terminal group, and a fourth via group having a plurality of through vias respectively connected to a plurality of terminals of the fourth terminal group; the first terminal group of the first semiconductor element is connected to the third terminal group of the second semiconductor element via the first via group and the third via group, and the second terminal group of the first semiconductor element is connected to the fourth terminal group of the second semiconductor element via the second via group and the fourth via group, the first via group includes a first via connected to a first terminal of the first terminal group and a second via connected to a second terminal of the first terminal group; the second via group includes a third via connected to a third terminal of the second terminal group, and a fourth via connected to a fourth terminal of the second terminal group and adjacent to the third via; the third via group includes a fifth via connected to a fifth terminal of the third terminal group and a sixth via connected to a sixth terminal of the third terminal group; the first vias and the second vias are arranged in a first direction, the third vias and the fourth vias are arranged in a second direction intersecting the first direction, an imaginary line connecting the first vias and the second vias passes between the third vias and the fourth vias, and a first wiring connecting the first vias and the fifth vias and a second wiring connecting the second vias and the sixth vias pass between the third vias and the fourth vias; 1. An electronic module comprising:

2. the fourth via group includes a seventh via connected to a seventh terminal of the fourth terminal group, and an eighth via connected to an eighth terminal of the fourth terminal group and adjacent to the seventh via, the seventh via and the eighth via are arranged in the second direction, the first wiring and the second wiring pass between a third wiring that connects the third via and the seventh via and a fourth wiring that connects the fourth via and the eighth via; 2. The electronic module of claim 1.

3. the fifth via and the sixth via are disposed between the third wiring and the fourth wiring; 3. The electronic module of claim 2.

4. the fifth via and the sixth via are arranged in the first direction, and a virtual line connecting the fifth via and the sixth via passes between the seventh via and the eighth via; 3. The electronic module of claim 2.

5. the imaginary line connecting the first via and the second via and the imaginary line connecting the fifth via and the sixth via are located on the same imaginary line; 5. An electronic module according to any one of claims 1 to 4.

6. the first via group includes a ninth via connected to a ninth terminal of the first terminal group; the imaginary line connecting the first via and the second via passes through the ninth via, the second terminals and the ninth terminals are arranged in a third direction intersecting the first direction; 2. The electronic module of claim 1.

7. the ninth via is disposed between the first via and the second via; 7. The electronic module according to claim 6.

8. the first terminals and the second terminals are arranged in a fourth direction intersecting the third direction; 7. The electronic module according to claim 6.

9. the fourth via group includes a seventh via connected to a seventh terminal of the fourth terminal group, and an eighth via connected to an eighth terminal of the fourth terminal group and adjacent to the seventh via, the third via group includes a tenth via connected to a tenth terminal of the third terminal group; a fifth wiring connecting the ninth via and the tenth via passes between the seventh via and the eighth via; 7. The electronic module according to claim 6.

10. the third via group includes a tenth via connected to a tenth terminal of the third terminal group; the tenth via is disposed between the fifth via and the sixth via; 9. The electronic module of claim 8.

11. the first wiring and the second wiring are provided in a first wiring layer of the plurality of wiring layers, the fifth wiring is provided in a second wiring layer of the plurality of wiring layers; 10. The electronic module of claim 9.

12. a difference between the length of the first wiring and the length of the second wiring is 10% or less of the length of the first wiring or the length of the second wiring; 2. The electronic module of claim 1.

13. the first wiring and the second wiring have a fly-by wiring structure; 2. The electronic module of claim 1.

14. a first signal is supplied to the first semiconductor element and the second semiconductor element via the first wiring, and a second signal is supplied to the first semiconductor element and the second semiconductor element via the second wiring; 2. The electronic module of claim 1.

15. the first semiconductor device and the second semiconductor device are memories, a memory controller mounted on the wiring board and performing input and output of data with the first semiconductor element and the second semiconductor element; 10. The electronic module of claim 1, further comprising:

16. the first terminal, the second terminal, the fifth terminal, and the sixth terminal are control terminals; 2. The electronic module of claim 1.

17. the first terminal group, the second terminal group, the third terminal group, and the fourth terminal group have a ball grid array structure; 2. The electronic module of claim 1.

18. Further comprising a plurality of connectors mounted on the wiring board.

2. The electronic module of claim 1.

19. a first electronic module, the first electronic module being the electronic module of claim 1; a second electronic module; a wiring member that connects the first electronic module and the second electronic module to each other; An electronic device comprising:

20. an image capture device; a circuit device that outputs image data based on an image signal obtained by the image acquisition device, The circuit arrangement comprises an electronic module according to claim 1. An electronic device characterized by:

21. an image forming device that forms an image based on the image data; 21. The electronic device according to claim 20.

22. a circuit device for outputting image data; an image forming device that forms an image based on the image data, The circuit arrangement comprises an electronic module according to claim 1. An electronic device characterized by:

23. the image forming device is a display device, 23. The electronic device according to claim 22.

24. the image forming apparatus is a printing apparatus; 23. The electronic device according to claim 22.

Images