Test device
By integrating a drive circuit, antenna, cutoff switch, and gate driver with optical signal isolation, the apparatus addresses the issue of increased stray inductance from sensors, ensuring accurate and rapid interruption of breakdown currents in power semiconductor testing.
Patent Information
- Application Number
- JP2024087027
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-05-29
- Publication Date
- 2025-12-11
AI Technical Summary
Existing test apparatuses for power semiconductors face increased stray series inductance (Ls) due to the inclusion of current and voltage sensors, which complicates accurate measurement of switching performance by lengthening the wiring path and detouring the current flow, leading to potential damage from breakdown currents.
The apparatus employs a drive circuit, an antenna for breakdown detection, a cutoff switch, and a gate driver to detect and interrupt breakdown currents without the need for current or voltage sensors in the main circuit, using optical signals for isolation to reduce Ls and improve measurement accuracy.
This configuration reduces stray series inductance, enabling precise electrical characteristic testing by quickly cutting off breakdown currents, thereby minimizing damage to test components and reducing the frequency of repairs.
Smart Images

Figure 2025180002000001_ABST
Abstract
Description
[Technical Field]
[0001] The present disclosure relates to a test device for power semiconductors. [Background technology]
[0002] Power semiconductors undergo electrical characteristic tests to check their quality and performance before shipping. Defective power semiconductors may be destroyed during the electrical characteristic tests. When a power semiconductor is destroyed, a large breakdown current flows, damaging the components used in the test (e.g., circuits, jigs, electrodes, etc.), so a circuit breaker is used to protect these components.
[0003] Japanese Patent Laid-Open Publication No. 2016-11953 (see Patent Document 1) discloses a test circuit for a semiconductor device. This test circuit includes a semiconductor device under test (hereinafter also referred to as DUT), a current sensor or voltage sensor for detecting a breakdown current, a cutoff element for cutting off the breakdown current, and a coil that forms a loop path when the DUT is turned on.
[0004] In dynamic characteristics tests, which are part of electrical characteristics tests, the current is turned on and off at high speed during the switching operation of power semiconductors, so it is desirable for the stray series inductance component (hereinafter also referred to as Ls) of the main circuit of the test equipment to be small. The main circuit is the path through which the current flows when the DUT performs switching operations. If the test equipment has a large Ls, the time change in current dI / dt is rate-determined by the Ls of the test circuit, making it difficult to accurately measure the switching performance of the DUT. To reduce Ls, it is necessary to shorten the wiring path of the main circuit and configure the main circuit with as many parallel plates as possible to reduce the loop area of the path through which the current flows. [Prior art documents] [Patent documents]
[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-11953 Summary of the Invention [Problem to be solved by the invention]
[0006] However, in Patent Document 1, a current sensor is used, for example, to detect the breakdown current of the DUT. The current sensor has a cylindrical shape, and the wiring through which the current flows must be arranged so that it passes through the center of the cylinder. In this configuration, the current sensor must be arranged midway along the wiring path of the main circuit, which increases the length of the wiring path by the axial length of the cylindrical shape of the current sensor. Furthermore, in order to pass through the center of the cylinder, the wiring must detour by the radial thickness of the cylindrical shape of the current sensor. As described above, the length of the wiring path and the detour of the current path cause the problem of an increase in Ls of the main circuit due to the current sensor.
[0007] Similarly, when detecting DUT breakdown using a voltage sensor, the voltage sensor must be connected to the main circuit, which increases the wiring length for the connection, resulting in a problem of a larger Ls. Also, since a voltage sensor cannot directly detect the breakdown current that is the target for interruption, it is preferable to use a current sensor for breakdown detection.
[0008] The test apparatus of the present disclosure reduces Ls, which increases due to the current sensor or voltage sensor, and improves the measurement accuracy of the electrical characteristics test. [Means for solving the problem]
[0009] The test apparatus of the present disclosure includes a drive circuit that drives the object to be measured, an antenna provided for the object to be measured, a breakdown detection circuit that detects breakdown of the object to be measured by the drive circuit via the antenna, a cut-off switch that is provided in a current path connected to the object to be measured and cuts off the breakdown current, and a first gate driver that drives the cut-off switch based on the detection result of the breakdown detection circuit. [Effects of the Invention]
[0010] The test apparatus of the present disclosure reduces Ls, which increases due to the current sensor or voltage sensor, and improves the measurement accuracy of the electrical characteristics test. [Brief explanation of the drawings]
[0011] [Figure 1] FIG. 1 is a diagram illustrating a configuration of a test apparatus 1 according to a first embodiment. [Figure 2] 10A and 10B are diagrams illustrating waveforms received by the antenna AT when the DUT under test according to the first embodiment performs a normal switching operation and when the DUT under test is broken. [Figure 3] FIG. 1 is a diagram illustrating an overview of a destruction detection circuit 52 according to the first embodiment. [Figure 4] FIG. 10 is a diagram illustrating a configuration of a test apparatus 2 according to a second embodiment. [Figure 5] FIG. 10 is a diagram illustrating the configuration of a test device 3 for an avalanche resistance test according to a comparative example. [Figure 6] FIG. 10 is a diagram illustrating a configuration of a test apparatus 4 according to a third embodiment. [Figure 7] FIG. 10 is a diagram illustrating a configuration of a test apparatus 5 according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION
[0012] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings will be denoted by the same reference numerals, and their description will not be repeated in principle.
[0013] Embodiment 1 Fig. 1 is a diagram illustrating the configuration of a test apparatus 1 according to the embodiment 1. Referring to Fig. 1, the test apparatus 1 according to the embodiment 1 includes a test circuit 10, a shutoff switch 20 made of a semiconductor switch, gate circuits 30 and 40 for driving the shutoff switch 20, a detection circuit 50, a DUT under test, an antenna AT for detecting breakdown of the DUT under test, a gate driver GD for driving the DUT under test, and isolated power supplies V1 to V4.
[0014] An isolated power supply V1 supplies a drive voltage to the gate driver GD. An isolated power supply V2 supplies a drive voltage to the gate circuit 30. An isolated power supply V3 supplies a drive voltage to the gate circuit 40. A power supply V4 supplies a drive voltage to the detection circuit 50.
[0015] The detection circuit 50 includes a collapse detection circuit 52 connected to the antenna AT, and an optical transmitter 54 for converting a detection signal from the collapse detection circuit 52 into an optical signal.
[0016] The gate circuit 30 includes a gate driver 32 and an optical receiver 34 that receives an optical signal from an optical transmitter 54 via an optical fiber. The gate circuit 40 includes a gate driver 42 and an optical receiver 44 that receives an optical signal from the optical transmitter 54 via an optical fiber.
[0017] The cutoff switch 20 includes a plurality of semiconductor switches 21 to 26. The semiconductor switches 21 to 23 are driven by receiving gate signals from a gate driver 32. The semiconductor switches 24 to 26 are driven by receiving gate signals from a gate driver 42.
[0018] The test device 1 includes a power supply, circuits, and measuring instruments required for performing electrical characteristic tests. In this example, the DUT to be measured is described as an IGBT element, but the DUT to be measured may also be a MOSFET, an RC-IGBT, an IGBT with a regenerative diode, etc.
[0019] The semiconductor switches 21 to 26 included in the cutoff switch 20 may be connected in series if the withstand voltage is insufficient, or may be connected in parallel if the current capacity is insufficient.
[0020] In this example, two in series and three in parallel are shown as an example, but the actual number of series and parallel connections may vary depending on the specifications of the semiconductor switches included in the cutoff switch 20 and the specifications of the test device 1.
[0021] Although the power supply V4 supplied to the detection circuit 50 will be described as a ground power supply, it does not necessarily have to be a ground power supply. However, a ground power supply is generally used because it is cheaper and smaller in size than an isolated power supply.
[0022] In this example, the gate of the DUT under test is driven by a gate driver GD for driving the DUT under test, and a switching operation is performed to perform an electrical characteristic test.
[0023] If the DUT under test is destroyed during an electrical characteristics test, a magnetic field or electromagnetic wave different from that generated when the DUT is not destroyed will be generated.
[0024] An antenna AT connected to the destruction detection circuit 52 detects a specific magnetic field or electromagnetic wave that is generated when the DUT under test is destroyed.
[0025] If the breakdown detection circuit 52 determines that the DUT under test has been broken, it outputs a detection signal. The optical transmitter 54 converts the detection signal into an optical signal and outputs it to the optical receivers 34 and 44 via an optical fiber.
[0026] The gate drivers 32, 42 receive the detection signals via the optical receivers 34, 44, and send cutoff signals to the semiconductor switches 21 to 26 of the cutoff switch 20 to drive the semiconductor switches 21 to 26 of the cutoff switch 20, thereby cutting off the destructive current of the DUT under test.
[0027] The configuration relating to optical signals is merely an example, and as long as the signal can be isolated, it does not necessarily have to be an optical signal. Because the potential of the semiconductor switch for the cutoff switch fluctuates before and after the cutoff operation of the cutoff switch 20, the potential of the gate drivers 32, 42 of the gate circuits 30, 40 must also match that of the semiconductor switch of the cutoff switch 20, and an isolated power supply is required for the gate drivers 32, 42 of the gate circuits 30, 40.
[0028] 2A and 2B are diagrams illustrating waveforms received by the antenna AT when the DUT under test according to the first embodiment performs a normal switching operation and when the DUT under test is damaged. As an example, waveforms when the DUT under test is switched off are compared between normal and damaged states with reference to FIGS. 2A and 2B. When the DUT under test is not performing a switching operation, the signal maintains a constant value.
[0029] 2A, when the DUT under test performs a normal switching operation, the DUT under test starts switching at time t1, and the signal begins to fluctuate as the current decreases.Then, at time t3, the switching operation ends, and the current stops flowing through the DUT under test, so the signal returns to a constant value.
[0030] Referring to Figure 2(B), we will explain what happens when the DUT under test is destroyed. Switching operation begins at time t1, just as it would if the switching operation were normal. If the DUT under test were to be destroyed at time t2, the current flowing through the DUT under test will suddenly increase. As a result, the signal will fluctuate significantly in the opposite direction to the direction from time t1 to time t2.
[0031] By detecting this difference in signal waveforms, it is possible to determine whether the DUT under test has been damaged. Specifically, a timer is set to enable damage detection from time t1 to time t3, and the signal is masked during unnecessary periods, and a threshold is set for the signal fluctuation range, or a threshold is set for the differential signal of the signal, thereby detecting damage to the DUT under test.
[0032] 3 is a diagram illustrating an overview of destruction detection circuit 52 according to the first embodiment. Referring to FIG. 3, destruction detection circuit 52 according to the first embodiment includes a filter circuit 68, a comparator 64, a reference signal generation circuit 66, a timer circuit 62, and a mask circuit 60.
[0033] The input signal of the destruction detection circuit 52 is an analog input signal from the antenna AT, and the output signal is a digital signal such as TTL.
[0034] The output destination of breakdown detection circuit 52 according to the first embodiment is an isolation signal generating unit such as optical transmitter 54.
[0035] The input signal from the antenna AT passes through a filter circuit 68. The filter circuit 68 is designed to reduce the effects of noise and to focus on the signal that occurs when the DUT under test is damaged. The optimal filter circuit configuration can be adjusted as needed depending on the noise around the antenna AT and the waveform when the DUT under test is damaged. For example, the filter circuit 68 is designed to increase the overall S / N ratio by combining filters that limit frequency bands, such as high-pass filters and band-pass filters, amplifiers for signal amplification, differentiation circuits, and integration circuits. Because passing the signal through amplifiers or band-limiting filters can cause adverse effects such as signal delay time and offset deviation, it is desirable to use a circuit that is as simple as possible and passes through as few circuit elements as possible.
[0036] The signal that passes through the filter circuit 68 is compared in the comparator 64 with a reference signal generated by the reference signal generation circuit 66. When the signal level exceeds or falls below the reference level, the comparator output is inverted, and it is determined that the DUT under test has been destroyed. The reference signal generation circuit 66 generates a signal with a threshold level for determining that the DUT under test has been destroyed. Because the threshold level for determining destruction varies depending on the test conditions and the characteristics of the individual DUT under test, the signal level may be adjusted appropriately depending on the test conditions and the type of DUT under test. Furthermore, since a simpler reference signal waveform is more reproducible and easier to adjust, it is desirable to configure the filter circuit 68 so that the reference signal is a constant voltage, particularly by utilizing a differentiation circuit, i.e., so that the reference voltage that the comparator 64 compares to is the constant voltage threshold voltage itself.
[0037] The mask circuit 60 and timer circuit 62 are circuits for validating the determination of destruction only during the destruction determination period from time t1 to time t3 shown in Fig. 2. The timer circuit 62 generates a signal that is valid only during the period from time t1 to time t3 so that the cutoff switch does not malfunction due to disturbances such as noise. The mask circuit 60 masks the output signal from the comparator 64 and outputs it so that it is valid only during the period from time t1 to time t3.
[0038] The configuration and operation of the breakdown detection circuit 52 described above is merely an example, and it is of course possible to adopt a different circuit configuration as long as the purpose of detecting breakdown in the DUT under test can be achieved.
[0039] The antenna AT may be installed in a location where the difference in waveform between the normal and damaged states of the DUT under test can be detected with sufficient signal strength. Generally, most parts of the main circuit are made up of parallel plates, so there is little leakage of magnetic fields or generation of electromagnetic waves. For this reason, it is desirable to install it near the DUT under test, where a relatively large loop in the main circuit is likely to form. However, if the difference in waveform between the normal and damaged states of the DUT under test can be detected with sufficient signal strength, it is not necessarily necessary to install the antenna AT near the DUT under test.
[0040] By configuring the device under test (DUT) to detect breakdown using the method described above, there is no need to place a current sensor for breakdown detection in the main circuit of the test circuit, and it is possible to perform electrical characteristics testing using a main circuit with reduced Ls, enabling the electrical characteristics of the device under test (DUT) to be measured with high accuracy.
[0041] Embodiment 2 Fig. 4 is a diagram illustrating the configuration of a test apparatus 2 according to embodiment 2. Referring to Fig. 2, the test apparatus 2 according to embodiment 2 differs from the test apparatus 1 according to embodiment 1 in that it has gate circuits 70 and 80 instead of gate circuits 30 and 40 and detection circuit 50, and in that it has two antennas AT.
[0042] Specifically, the gate circuit 80 includes a gate driver 32 and a breakdown detection circuit 74. The breakdown detection circuit 74 is connected to the antenna AT1. The gate circuit 80 is provided with an isolated power supply V2. The breakdown detection circuit 74 detects that the DUT under test has been broken via the antenna AT1, and outputs a detection signal to the gate driver 32. The gate driver 32 receives the detection signal and shuts off the semiconductor switches 21 to 23 of the cutoff switch 20.
[0043] The gate circuit 70 also includes a gate driver 42 and a breakdown detection circuit 72. The breakdown detection circuit 72 is connected to the antenna AT2. The gate circuit 70 is provided with an isolated power supply V3. The breakdown detection circuit 72 detects that the DUT under test has been broken via the antenna AT2, and outputs a detection signal to the gate driver 42. The gate driver 42 receives the detection signal and shuts off the semiconductor switches 24 to 26 of the cutoff switch 20.
[0044] Since destruction detection circuits 72 and 74 have the same configuration as destruction detection circuit 52 described in the first embodiment, detailed description thereof will not be repeated.
[0045] The test apparatus 2 according to the second embodiment differs from the test apparatus 1 according to the first embodiment in that the signals output from the breakdown detection circuits 72, 74 are input directly to the gate drivers without being converted into isolated signals such as optical signals. Accordingly, the isolated power supplies V2, V3 for the gate drivers of the gate circuits 70, 80 are configured to also supply power to the breakdown detection circuits 72, 74.
[0046] The configuration is such that the same number of antennas are provided as the number of series-connected semiconductor switches in the cutoff switch 20. In this example, as an example, the semiconductor switches in the cutoff switch 20 are connected in two series and three parallel, but since the number of series and parallel connections varies depending on the specifications of the semiconductor switches in the actual cutoff switch 20 and the specifications of the device, the configuration of the set of gate driver, breakdown detection circuit, and antenna may be changed depending on the specifications.
[0047] The test apparatus 2 according to the second embodiment, like the test apparatus 1 according to the first embodiment, does not include a current sensor or voltage sensor in the main circuit, making it possible to perform electrical characteristic tests using a main circuit with reduced Ls. In the test apparatus 1 according to the first embodiment, after the antenna AT and breakdown detection circuit 52 determine whether the DUT under test has been broken, the electrical signal from the breakdown detection circuit 52 is converted to an isolated signal, such as an optical signal, via the optical transmitter 54 for isolation, and then the optical signal is reconverted to an electrical signal and input to the gate driver. Because this conversion to an optical signal and then to an electrical signal causes delays, the operation from the breakdown of the DUT under test to the interruption of the breakdown current may be delayed. Note that optical signals are merely an example, and signals other than optical signals may also be used. Furthermore, conversion delays and the like may also occur with isolated signals other than optical signals, which may delay the interruption.
[0048] The test apparatus 2 according to the second embodiment does not require conversion from an optical signal to an insulating signal and then to an electrical signal, and therefore has a shorter delay time, making it possible to quickly drive the gate drivers 32, 42. This enables the cutoff switch 20 of the test apparatus 2 to quickly cut off the breakdown current. When the cutoff switch 20 quickly cuts off the breakdown current, damage to the jig or electrodes caused by the breakdown current is reduced, making it possible to reduce the frequency of replacement and repair of the jig or electrodes.
[0049] Embodiment 3 In the third embodiment, an example of the configuration of a test device for an avalanche resistance test will be described.
[0050] Fig. 5 is a diagram illustrating the configuration of a test apparatus 3 for an avalanche resistance test according to a comparative example. Referring to Fig. 5, the test apparatus 3 according to the comparative example includes a power supply Vcc, a main capacitor MC connected to the power supply Vcc, semiconductor switches 150 and 152 which are cutoff switches, semiconductor switches 154 and 156 which are regenerative switches, an inductive load LL connected in parallel with the regenerative switches, a regenerative diode DD connected in series with the regenerative switches, a current sensor IS, a DUT under test, a gate driver GD for driving the DUT under test, a detection circuit 85 to which the current sensor IS is connected, gate circuits 100 to 130 provided corresponding to the semiconductor switches 150, 152, 154, and 156, respectively, and a control unit CT.
[0051] The power supply Vcc is connected in series with semiconductor switches 150, 152, 154, and 156, a regenerative diode DD, a current sensor IS, and a DUT under test.
[0052] The detection circuit 85 includes a breakdown detection circuit 83 and optical transmitters 82 and 84 .
[0053] The gate circuit 100 includes an optical receiver 102 and a gate driver 104. The gate circuit 100 is provided with an isolated power supply V8. The gate circuit 110 includes an optical receiver 112 and a gate driver 114. The gate circuit 110 is provided with an isolated power supply V7. The gate circuit 120 includes an optical receiver 122 and a gate driver 124. The gate circuit 120 is provided with an isolated power supply V6. The gate circuit 130 includes an optical receiver 132 and a gate driver 134. The gate circuit 130 is provided with an isolated power supply V5.
[0054] The control unit CT controls the gate circuits 100 to 130 via the power supply Vcc, the gate driver GD, and the detection circuit 85. The control unit CT can turn on / off the semiconductor switches 150, 152, 154, and 156 by controlling the gate circuits 100 to 130. Although not shown in FIG. 5, the control unit CT may also be configured to control the voltages of the power supplies V1 to V8.
[0055] The signals from the destruction detection circuit 83 to each of the gate circuits 100 to 130 are generally converted into optical signals for isolation and transmitted via optical fibers, but it is not necessary to use optical signals as long as the signals can be isolated.
[0056] The configuration of the test device 3 according to the comparative example is merely an example, and any configuration may be used as long as it satisfies the operations and functions described below. Although an IGBT is used as the DUT to be measured in the description, the DUT to be measured may also be a MOSFET, an RC-IGBT, an IGBT with a regenerative diode, etc.
[0057] The semiconductor switches 150 and 152 for the cutoff switches and the semiconductor switches 154 and 156 for the regeneration switches may be connected in series if their withstand voltage is insufficient. In this example, two switches are connected in series as an example, but the number of switches in series varies depending on the specifications of the actual device. In addition, if the current capacity is insufficient, this can be addressed by increasing the number of semiconductor switches connected in parallel.
[0058] The operation of a general avalanche resistance test will be described.
[0059] The control unit CT applies voltage Vcc with the cutoff switch on and the regeneration switch off, turning on the DUT under test and passing current through the DUT under test via the inductive load. The amount of current flowing through the inductive load LL gradually increases, and when it reaches a specified value, the DUT under test is turned off.
[0060] Because the inductive load LL tries to continue to pass current, a high voltage is applied to the DUT under test due to the back electromotive force of the inductive load LL. The high voltage causes the DUT under test to enter avalanche mode, causing current to flow. The energy stored in the inductive load LL due to the above operation is consumed by the DUT under test, and it is confirmed that the DUT under test can withstand this.
[0061] If the DUT under test is defective, it will not be able to withstand the load and will be destroyed.
[0062] When the DUT under test is destroyed, the current sensor IS detects a breakdown current signal that is different from when the DUT is not destroyed. The breakdown detection circuit 83 detects the breakdown current signal from the current sensor IS and outputs a detection signal. The optical transmitters 82 and 84 convert the detection signal into an optical signal and output it to the optical receivers 102, 112, 122, and 132 via optical fibers.
[0063] The optical transmitter 82 converts the detection signal into an optical signal and outputs an OFF signal to the optical receivers 102 and 112 via the optical fiber. The optical transmitter 84 converts the detection signal into an optical signal and outputs an ON signal to the optical receivers 122 and 132 via the optical fiber.
[0064] The gate drivers 104, 114 receive the OFF signal via the optical receivers 102, 112, send a cutoff signal to the semiconductor switches 150, 152 of the cutoff switches, and drive the semiconductor switches 150, 152 of the cutoff switches to cut off the destructive current of the DUT under test.
[0065] The gate drivers 124, 134 receive the ON signal via the optical receivers 122, 132, and send a drive signal to the semiconductor switches 154, 156 of the regenerative switch to drive the semiconductor switches 154, 156 of the regenerative switch and supply the regenerative current.
[0066] In avalanche resistance testing, a regenerative switch is provided in addition to a cutoff switch to interrupt the breakdown current. Because the inductive load LL continues to attempt to pass current even after the DUT under test is destroyed, a regenerative path is required to prevent the current from flowing to the DUT under test, the jig, and the electrodes. The regenerative circuit consists of a regenerative diode DD and a regenerative switch. The regenerative switch is a switch that quickly turns on when it detects damage to the DUT under test. The breakdown detection circuit 83 detects damage to the DUT under test and inputs the signal via an optical signal to the gate drivers 124 and 134 of the gate circuits 120 and 130. The gate drivers 124 and 134 then drive and turn on the regenerative switches, which are semiconductor switches 154 and 156. The regenerative circuit has a similar configuration to a cutoff switch, but because the cutoff switch and the regenerative switch have different potentials, they are provided in separate systems for each semiconductor switch.
[0067] Fig. 6 is a diagram illustrating the configuration of a test apparatus 4 according to a third embodiment. Referring to Fig. 6, the test apparatus 4 according to the third embodiment differs from the configuration of the test apparatus 3 described in Fig. 5 in that detection circuit 85 is replaced with detection circuit 90 and an antenna AT is provided instead of the current sensor IS. As the other configurations are similar to the configuration of the test apparatus 3 described in Fig. 5, the details thereof will not be repeated.
[0068] Specifically, detection circuit 90 includes a destruction detection circuit 95 and optical transmitters 82 and 84. Destruction detection circuit 95 is connected to antenna AT. Since destruction detection circuit 95 has a configuration similar to that of destruction detection circuit 52 described in the first embodiment, detailed description thereof will not be repeated.
[0069] An antenna AT connected to the destruction detection circuit 95 detects a specific magnetic field or electromagnetic wave that is generated when the DUT under test is destroyed.
[0070] If the breakdown detection circuit 95 determines that the DUT under test has been broken, it outputs a detection signal. The optical transmitters 82 and 84 convert the detection signal into an optical signal and output it to the optical receivers 102, 112, 122, and 132 via optical fibers.
[0071] The optical transmitter 82 converts the detection signal into an optical signal and outputs an OFF signal to the optical receivers 102 and 112 via the optical fiber. The optical transmitter 84 converts the detection signal into an optical signal and outputs an ON signal to the optical receivers 122 and 132 via the optical fiber.
[0072] The gate drivers 104, 114 receive the OFF signal via the optical receivers 102, 112, send a cutoff signal to the semiconductor switches 150, 152 of the cutoff switches, and drive the semiconductor switches 150, 152 of the cutoff switches to cut off the destructive current of the DUT under test.
[0073] The gate drivers 124, 134 receive the ON signal via the optical receivers 122, 132, and send a drive signal to the semiconductor switches 154, 156 of the regenerative switch to drive the semiconductor switches 154, 156 of the regenerative switch and supply the regenerative current.
[0074] By configuring the device under test (DUT) to detect breakdown using the method described above, it is no longer necessary to place a current sensor for breakdown detection in the main circuit of the test circuit in the avalanche resistance test, and it is possible to perform electrical characteristics testing with a main circuit with reduced Ls, allowing for highly accurate measurement of the electrical characteristics of the DUT under test.In addition, the wiring for the current sensor can be shortened and the wiring loop for passing the wiring to the current sensor can be reduced, allowing for a smaller Ls for the main circuit.
[0075] Embodiment 4 Fig. 7 is a diagram illustrating the configuration of test apparatus 5 according to embodiment 4. Referring to Fig. 7, test apparatus 5 according to embodiment 4 differs from test apparatus 4 according to embodiment 3 in that it has gate circuits 200, 210, 220, and 230 instead of gate circuits 100, 110, 120, and 130 and detection circuit 90, that it has four antennas AT, and that control unit CT is replaced with control unit CTA.
[0076] Specifically, the gate circuit 200 includes a gate driver 104 and a breakdown detection circuit 202. The breakdown detection circuit 202 is connected to an antenna AT1. The gate circuit 200 is provided with an isolated power supply V8. The breakdown detection circuit 202 detects that the DUT under test has been broken via the antenna AT1, and outputs a detection signal to the gate driver 104. The gate driver 104 receives the detection signal and turns off the semiconductor switch 150 of the cutoff switch.
[0077] The gate circuit 210 includes a gate driver 114 and a breakdown detection circuit 212. The breakdown detection circuit 212 is connected to the antenna AT2. The gate circuit 210 is provided with an isolated power supply V7. The breakdown detection circuit 212 detects that the DUT under test has been broken via the antenna AT2, and outputs a detection signal to the gate driver 114. The gate driver 114 receives the detection signal and shuts off the semiconductor switch 152 of the cutoff switch.
[0078] The gate circuit 220 includes a gate driver 124 and a breakdown detection circuit 222. The breakdown detection circuit 222 is connected to the antenna AT3. The gate circuit 220 is provided with an isolated power supply V6. The breakdown detection circuit 222 detects that the DUT under test has been broken via the antenna AT3, and outputs a detection signal to the gate driver 124. Upon receiving the detection signal, the gate driver 124 turns on the semiconductor switch 154 of the regenerative switch.
[0079] The gate circuit 230 includes a gate driver 134 and a breakdown detection circuit 232. The breakdown detection circuit 232 is connected to the antenna AT4. The gate circuit 230 is provided with an isolated power supply V5. The breakdown detection circuit 232 detects that the DUT under test has been broken via the antenna AT4, and outputs a detection signal to the gate driver 134. Upon receiving the detection signal, the gate driver 134 turns on the semiconductor switch 156 of the cutoff switch.
[0080] The control unit CTA controls the gate circuits 200 to 230. As explained in Fig. 5, the control unit CTA applies a voltage Vcc with the cutoff switch on and the regeneration switch off, turning on the DUT under test and causing a current to flow through the DUT under test via the inductive load. The amount of current flowing through the inductive load LL gradually increases, and when it reaches a specified value, the DUT under test is turned off.
[0081] Since destruction detection circuits 202, 212, 222, and 232 have the same configuration as destruction detection circuit 52 described in the first embodiment, detailed description thereof will not be repeated.
[0082] The test apparatus 5 according to the fourth embodiment has a shorter delay time because it does not require conversion from an optical signal to an isolated signal and then back to an electrical signal, making it possible to drive the gate drivers 104, 114, 124, and 134 quickly. Therefore, the breaker switches of the test apparatus 5 can quickly cut off the breakdown current. When the breaker switches can quickly cut off the breakdown current, damage to jigs and electrodes caused by the breakdown current is reduced, making it possible to reduce the frequency of replacement and repair of jigs and electrodes. Furthermore, similar effects can be obtained for regenerative switches as for breaker switches.
[0083] The configuration is such that the same number of antennas are provided as the number of series-connected semiconductor switches in the cutoff switch and regenerative switch. In this example, two cutoff switches are connected in series as an example, but the number of series-connected switches varies depending on the specifications of the actual cutoff switches and the specifications of the device, so the configuration of the set of gate driver, breakdown detection circuit, and antenna may be changed according to the specifications. Furthermore, similar changes can be made to the regenerative switch as well as the cutoff switch.
[0084] Antennas AT1 to AT4 may be installed in a location where the difference in waveform between the normal and damaged states of the DUT under test can be detected with sufficient signal strength. Generally, most parts of the main circuit are made up of parallel plates, so there is little leakage of magnetic fields or generation of electromagnetic waves. For this reason, it is desirable to install them near the DUT under test, where a relatively large main circuit loop is likely to form. However, as long as the difference in waveform between the normal and damaged states of the DUT under test can be detected with sufficient signal strength, it is not necessary to install antennas AT1 to AT4 near the DUT under test.
[0085] When the antennas are arranged in separate locations, the waveforms generated when destruction is detected are different, so the detection sensitivity and threshold of each destruction detection circuit 142, 152, 162, 172 may be adjusted to correspond to each of the antennas AT1 to AT4. When the antennas AT1 to AT4 are arranged in the same location, the same potential difference occurs between the antennas as between the semiconductor switches for the cutoff switches and regeneration switches, so a spatial distance may be maintained to prevent discharge from occurring when the antennas are too close.
[0086] The embodiments disclosed herein are intended to be combined as appropriate within the scope of compatibility. The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]
[0087] 1,2,3,4,5 Test equipment, 10 Test circuit, 30,40,70,80,100,110,120,130,200,210,220,230 Gate circuit, 20 Isolation switch, 21,23,24,26,150,152,154,156 Semiconductor switch, 32,42,104,114,124,134,GD Gate driver, 34,44,102,112,122,132 Optical receiver, 50,85,90 Detection circuit, 52,72,74,83,95,202,212,222,232 Breakdown detection circuit, 54,82,84 Optical transmitter, 60 Mask circuit, 62 Timer circuit, 64 Comparator, 66 Reference signal generation circuit, 68 Filter circuit.
Claims
1. a drive circuit for driving the object to be measured; an antenna provided for the measurement target; a destruction detection circuit that detects destruction of the measurement target caused by the drive circuit via the antenna; a cutoff switch provided in a current path connected to the object to be measured and configured to cut off a destructive current; a first gate driver that drives the cutoff switch based on a detection result of the breakdown detection circuit.
2. an optical transmitter that converts a detection result of the destruction detection circuit into an optical signal; an optical fiber for transmitting the optical signal; 2. The test apparatus according to claim 1, further comprising an optical receiver that converts the optical signal into a detection signal and outputs the detection signal to the first gate driver.
3. a plurality of cutoff switches connected in series to the current path are provided; a plurality of first gate drivers are provided corresponding to the plurality of cutoff switches, respectively; The test apparatus according to claim 1 , further comprising a plurality of breakdown detection circuits and a plurality of antennas respectively corresponding to the plurality of first gate drivers.
4. an inductive load provided in a current path to be measured; a regenerative switch that regenerates a regenerative current flowing through the inductive load; The test apparatus according to claim 1 , further comprising: a second gate driver that drives the regenerative switch based on a detection result of the breakdown detection circuit.
5. a plurality of regenerative switches connected in series to the current path are provided; a plurality of second gate drivers are provided corresponding to the plurality of regenerative switches, respectively; The test apparatus according to claim 4 , further comprising a plurality of breakdown detection circuits and a plurality of antennas respectively corresponding to the plurality of second gate drivers.
Citation Information
Patent Citations
Power semiconductor test apparatus
JP2016011953A