Da conversion device

Abstract

To provide a digital / analog conversion device capable of suppressing divergence of an output signal and enabling precise waveform reproduction with a finite dynamic range in an entire band up to a Nyquist frequency.SOLUTION: A DA conversion device 10 that generates an analog output signal d(n) by performing DA conversion on a digital target signal x(n) includes a plurality of sub-DA conversion units 30a to 30d that perform DA conversion on the target signal so that relative phases with respect to the target signal are different from each other in a common first sampling period, a first additional DA conversion unit 40 that performs DA conversion on the target signal in a second sampling period different from the first sampling period, and an output unit 50 that generates an output signal on the basis of an output y0(n) to y3(n) of the sub DA conversion units and an output s0(n) of the first additional DA conversion unit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a digital-to-analog converter. [Background technology]

[0002] Patent Document 1 describes a digital / analog converter. [Prior art document] [Patent documents] Patent Document 1: JP 2018-182744 A Summary of the Invention

[0003] In a first aspect of the present invention, there is provided a DA conversion device that generates an analog output signal by DA converting a digital target signal, the DA conversion device comprising: a plurality of sub DA conversion units that DA convert the target signal at a common first sampling period so that the relative phases with respect to the target signal are different from each other; a first additional DA conversion unit that DA converts the target signal at a second sampling period that is different from the first sampling period; and an output unit that generates an output signal based on the outputs of each of the plurality of sub DA conversion units and the output of the first additional DA conversion unit.

[0004] In the above-described DA conversion device, the first sampling period and the second sampling period may be integer multiples of the period of the reference clock, and the integer multiples may be relatively prime multiples.

[0005] In any of the above DA conversion devices, the output section may generate an output signal by adding together the outputs of the plurality of sub DA conversion sections and the output of the first additional DA conversion section.

[0006] Any of the above DA conversion devices may further include an input processing section that outputs object signals with different phases to each of the plurality of sub DA conversion sections, and outputs the object signal to the first additional DA conversion section.

[0007] In the above DA conversion device, the input processing section may output the setting value to the sub DA conversion section at the sampling timing of the first additional DA conversion section.

[0008] In the above DA conversion device, the input processing section may output a setting value of 0 to the sub DA conversion section at the sampling timing of the first additional DA conversion section.

[0009] In any of the above DA conversion devices, the first additional DA conversion section may output a signal according to the value of the target signal at the sampling timing of the first additional DA conversion section.

[0010] In any of the above DA conversion devices, the output section may generate, as the output signal, an output at a sampling timing of the first additional DA conversion section.

[0011] In any of the above DA conversion devices, the input processing unit may have a first path that extracts the amount of change in the value of the target signal, adds the extracted amount of change in the value to the input at the previous sampling timing in each of the sub DA conversion units, and outputs the result to the sub DA conversion units; a second path that extracts the amount of change in the value of the target signal, adds the extracted amount of change in the value to the input at the previous sampling timing in the first additional DA conversion unit, and outputs the result to the first additional DA conversion unit; and a selection unit that selects one of the first path and the second path based on the sampling timing of the first additional DA conversion unit.

[0012] In the above-described DA conversion device, the first path may output 0 when the second path is selected by the selection section.

[0013] In any of the above DA conversion devices, the selection section may select the first path from the first path and the second path at a timing different from the sampling timing of the first additional DA conversion section, and may select the second path at the sampling timing of the first additional DA conversion section.

[0014] In the above DA conversion device, the selection section may select the second path from the first path and the second path at intermittent timings among the sampling timings of the first additional DA conversion section.

[0015] In any of the above DA conversion devices, the first path may include a first delay unit that delays the target signal output from the first path by a first delay time, and a first adder unit that adds the output of the first delay unit to the target signal input to the first path, and the second path may include a second delay unit that delays the target signal output from the second path by a second delay time different from the first delay time, and a second adder unit that adds the output of the second delay unit to the target signal input to the second path.

[0016] In any of the above DA conversion devices, the output section may generate an output signal by delaying and adding the outputs of the sub DA conversion sections by a third delay time, and then adding the output of the first additional DA conversion section to the added value by delaying it by a fourth delay time that is greater than the third delay time.

[0017] In the above-described DA conversion device, the fourth delay time may be equal to the sum of the third delay times in the output section.

[0018] Any of the above DA conversion devices may further include a second additional DA conversion unit that performs DA conversion on the target signal at a third sampling period that is different from both the first sampling period and the second sampling period, and the output unit may generate an output signal based on the outputs of each of the multiple sub DA conversion units, the output of the first additional DA conversion unit, and the output of the second additional DA conversion unit.

[0019] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions. [Brief explanation of the drawings]

[0020] [Figure 1] 1 shows a first configuration example of a DA conversion device 10 according to the present embodiment. [Figure 2] 2 shows a more detailed configuration of the distribution section 100 of the DA conversion device 10 in this embodiment. [Figure 3] 2 shows an example of a timing chart of signals in the DA conversion device 10 of this embodiment. [Figure 4] 2 shows a second configuration example of the DA conversion device 10 according to the present embodiment. [Figure 5] 10 shows a more detailed configuration of the distribution section 100 of the DA conversion device 10 of the second configuration example according to the present embodiment. [Figure 6] 1 shows the configuration of a test apparatus 600 together with a device under test 700. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0021] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0022] FIG. 1 shows a first configuration example of a DA conversion device 10 according to this embodiment. The DA conversion device 10 generates and outputs an analog output signal by performing DA conversion (digital-to-analog conversion) on a digital target signal x(n) input to an input terminal. The DA conversion device 10 generates an output signal d(n) by combining multiple analog levels generated by DA conversion of the target signal x(n) so that the relative phases of the target signal x(n) are different. The DA conversion device 10 may further include a waveform data memory that stores the target signal x(n) in advance, or an AD converter that outputs the target signal x(n). The DA conversion device 10 may also receive the target signal x(n) from an external device.

[0023] The DA conversion device 10 may receive a reference clock and perform DA conversion in response to the reference clock. A target signal x(n) indicating a value (for example, one bit) for each cycle of the reference clock may be input to the DA conversion device 10. The DA conversion device 10 includes an input processing unit 20, a plurality of sub DA conversion units 30, a first additional DA conversion unit 40, and an output unit 50. Here, n indicates a signal corresponding to the n-th value or phase of the bit string of the target signal, and so on.

[0024] The input processing unit 20 processes the input target signal x(n) to obtain a target signal y(n), and outputs the result to the sub DA conversion unit 30 and the first additional DA conversion unit 40. The input processing unit 20 may input the target signals y(n) with different phases to each of the sub DA conversion units 30, and may input the target signal s(n) to the first additional DA conversion unit 40. The input processing unit 20 may output a setting value (for example, 0) to the sub DA conversion unit 30 at the sampling timing of the first additional DA conversion unit 40. The input processing unit 20 includes a distribution unit 100, a first input delay unit 110a, a second input delay unit 110b, and a third input delay unit 110c. Hereinafter, the first input delay unit 110a, the second input delay unit 110b, and the third input delay unit 110c will also be simply referred to as the input delay unit 110 or multiple input delay units 110.

[0025] The distribution section 100 may receive a target signal x(n) and input filtered target signals y(n) and s(n) to the sub DA conversion section 30 and the first additional DA conversion section 40, respectively. The distribution section 100 switches the output destination of the target signal between the sub DA conversion section 30 and the first additional DA conversion section 40.

[0026] The multiple input delay units 110 are connected to the distribution unit 100. Each input delay unit 110 may delay the target signal y(n) output from the distribution unit 100 by a predetermined delay time. Each of the multiple input delay units 110 may delay the target signal y(n) by the same delay amount. The predetermined delay time of each input delay unit 110 is, for example, one period of the reference clock. The multiple input delay units 110 may be connected between the input terminals of adjacent sub-DA conversion units 30 and may be connected in series with each other. In the embodiment of FIG. 1, the first input delay unit 110a is connected between the node between the distribution unit 100 and the first-stage sub-DA conversion unit 30a and the input terminal of the second-stage sub-DA conversion unit 30b. The second input delay unit 110b is connected between the output terminal of the first input delay unit 110a and the input terminal of the third-stage sub-DA conversion unit 30c. The third input delay section 110c is connected between the output terminal of the second input delay section 110b and the input terminal of the fourth-stage sub DA conversion section 30d. When N sub DA conversion sections 30 (N=4 in the present embodiment shown in FIG. 4) are arranged, N-1 input delay sections 110 may be arranged.

[0027] The multiple sub DA conversion units 30 are connected to the distribution unit 100. The second to fourth stage sub DA conversion units 30b, 30c, and 30d are connected to the distribution unit 100 via one or more input delay units 110. The multiple sub DA conversion units 30 perform DA conversion on the target signal y(n) at a common first sampling period so that the relative phases with respect to the target signal y(n) are different from each other. The sub DA conversion units 30 may output currents of analog levels corresponding to the digital values ​​of the target signal y(n) at different phases. The multiple sub DA conversion units 30 may receive the target signals y(n) delayed by the respective input delay units 110 and having different relative phases from each other, and sample the input target signals y(n) at the same timing to output signals (e.g., currents) y0(n) to y3(n) of analog levels corresponding to the values ​​of the target signal y(n) at different phases.

[0028] 1, the first-stage sub DA conversion unit 30a receives the target signal y(n) without delay, the second-stage sub DA conversion unit 30b receives the target signal y(n) delayed by a predetermined delay time a, the third-stage sub DA conversion unit 30c receives the target signal y(n) delayed by a delay time 2a, and the fourth-stage sub DA conversion unit 30d receives the target signal y(n) delayed by a delay time 3a. As a result, the multiple sub DA conversion units 30 receive the target signal y(n) delayed by different delay times, and can perform DA conversion so that the relative phases of the sub DA conversion units 30 with respect to the target signal y(n) are different from each other.

[0029] The first additional DA conversion section 40 is connected to the distribution section 100. The first additional DA conversion section 40 performs DA conversion on the target signal s(n) at a second sampling period different from the first sampling period. The first additional DA conversion section 40 may output a signal corresponding to the value of the target signal s(n) at the sampling timing of the first additional DA conversion section 40.

[0030] The first sampling period and the second sampling period are integer multiples of the reference clock period, and the integer multiples may be relatively prime multiples. For example, the first sampling period is N times the reference clock period (for example, N=4), and the second sampling period is M times the reference clock period (for example, M=5), where N and M are relatively prime integers. Alternatively, M=N±1 may be acceptable. In this way, if N and M are relatively prime integers or have a relationship of M=N±1, it is possible to reduce the sampling timings that overlap between the first sampling period and the second sampling period.

[0031] The output section 50 is connected to the plurality of sub DA conversion sections 30 and the first additional DA conversion section 40. The output section 50 generates an output signal d(n) based on the outputs y0(n) to y3(n) of the sub DA conversion sections 30 and the output s0(n) of the first additional DA conversion section 40. The output section 50 may generate the output signal d(n) by combining the outputs y0(n) to y3(n) of the sub DA conversion sections 30 and the output s0(n) of the first additional DA conversion section 40. The output section 50 may generate the output signal d(n) by adding the outputs y0(n) to y3(n) of the sub DA conversion sections 30 and the output s0(n) of the first additional DA conversion section 40. For example, the output section 50 may generate the output signal d(n) by adding the outputs y0(n) to y3(n) of the sub DA conversion section 30 with a delay of a third delay time, and then adding the output s0(n) of the first additional DA conversion section 40 to the added value with a delay of a fourth delay time that is greater than the third delay time. The output section 50 may generate the output s0(n) at the sampling timing of the first additional DA conversion section 40 as the output signal d(n).

[0032] The output section 50 has a first output delay section 120, a first output adder section 130, a second output delay section 140, a second output adder section 150, a third output delay section 160, a fourth output delay section 170, and a third output adder section 180.

[0033] The first output delay unit 120 is connected to the output terminal of the first-stage sub DA conversion unit 30a. The first output delay unit 120 may delay the output y0(n) of the first-stage sub DA conversion unit 30a by a third delay time. The first output adder 130 is connected to the first output delay unit 120 and the output terminal of the second-stage sub DA conversion unit 30b. The first output adder 130 may add the output y0(n) of the first-stage sub DA conversion unit 30a delayed by the first output delay unit 120 and the output y1(n) of the second-stage sub DA conversion unit 30b. The second output delay unit 140 is connected to the first output adder 130. The second output delay unit 140 delays the output of the first output adder 130 by a third delay time. The second output adder 150 is connected to the second output delay unit 140 and the output terminal of the third-stage sub DA conversion unit 30. The second output adder 150 may add the output of the first output adder 130 delayed by the second output delay unit 140 to the output y2(n) of the third-stage sub DA conversion unit 30c. The third output delay unit 160 is connected to the second output adder 150. The third output delay unit 160 may delay the output of the second output adder 150 by a third delay time. Note that the third delay time may be the same as the predetermined delay time in each input delay unit 110.

[0034] The fourth output delay unit 170 is connected to the output terminal of the first additional DA conversion unit 40. The fourth output delay unit 170 delays the output s0(n) of the first additional DA conversion unit 40 by a fourth delay time. The third output adder 180 is connected to the third output delay unit 160, the output terminal of the fourth-stage sub DA conversion unit 30d, and the fourth output delay unit 170. The third output adder 180 may add the output of the second output adder 150 delayed by the third output delay unit 160 to the output y3(n) of the fourth-stage sub DA conversion unit 30d and the output s0(n) of the first additional DA conversion unit 40 delayed by the fourth output delay unit 170. The fourth delay time may be the same as the sum of the third delay times in the output unit 50. In this embodiment, the fourth delay time is equal to the total delay time in the first output delay section 120, the second output delay section 140, and the third output delay section 160 (=the third delay time×3).

[0035] In the following description, the "output of a unit" such as the "output of the sub DA conversion unit 30" may refer to a signal or current output by the unit, and the "input of a unit" may refer to a signal or current input to the unit. The same applies hereinafter.

[0036] 2 shows a more detailed example of the configuration of the distribution section 100 of the DA conversion device 10 according to this embodiment. The distribution section 100 includes a first path 200, a second path 210, and a selection section 220.

[0037] The first path 200 is connected between the input terminal of the DA conversion device 10 and the sub DA conversion unit 30. The first path 200 may extract a change amount Δx(n) in the value of the target signal x(n), add the extracted change amount Δx(n) to an input y(n-1) at the previous sampling timing in the sub DA conversion unit 30, and output the added value y(n) to the sub DA conversion unit 30. The first path 200 may include a fourth input delay unit 230, a subtraction unit 240, a fifth input delay unit 250, and a first input addition unit 260.

[0038] The fourth input delay section 230 may be connected to the input terminal of the DA conversion device 10 and may delay the input target signal x(n) by a predetermined delay time. The delay time of the fourth input delay section 230 may be the same as one cycle of the reference clock.

[0039] The subtraction section 240 is connected to the input terminal of the DA conversion device 10 and the fourth input delay section 230. The subtraction section 240 may extract the difference obtained by subtracting the target signal x(n-1) delayed by the fourth input delay section 230 from the input target signal x(n), as the amount of change Δx(n) in the value of the target signal.

[0040] The fifth input delay unit 250 is connected to one input terminal of the first input adder 260 and an input terminal of the sub DA conversion unit 30 (i.e., the output terminal of the first path 200). The fifth input delay unit 250 may delay the target signal y(n) output from the first path 200 by a first delay time and input the delayed signal to the first input adder 260. Here, the first delay time is, for example, the same time as one cycle of the first sampling period of the sub DA conversion unit 30 (i.e., N times one cycle of the reference clock). In this case, the fifth input delay unit 250 can input to the first input adder 260 the value output to the sub DA conversion unit 30 at the previous sampling timing of the sub DA conversion unit 30.

[0041] The first input adder unit 260 is connected to the subtractor unit 240 and the output terminal of the first path 200. The first input adder unit 260 may add the output y(nN) of the fifth input delay unit 250 to the target signal x(n) input to the first path 200. In this embodiment, the first input adder unit 260 may add the output y(nN) of the fifth input delay unit 250 to the target signal Δx(n) output from the subtractor unit 240. The first path 200 may output the output y(n) of the first input adder unit 260 to the sub DA conversion unit 30. Here, the fifth input delay unit 250 is an example of a first delay unit in the present application, and the first input adder unit 260 is an example of a first adder unit in the present application.

[0042] The second path 210 may be connected between the input terminal of the DA conversion device 10 and the first additional DA conversion section 40. The second path 210 may extract a change amount Δx(n) in the value of the target signal x(n), add the extracted change amount Δx(n) to an input s(nM) at the previous sampling timing in the first additional DA conversion section 40, and output the added value s(n) to the first additional DA conversion section 40. The second path 210 may share the fourth input delay section 230, the subtraction section 240, and the first input adder section 260 with the first path 200, and may further include a sixth input delay section 270 and a second input adder section 280. The second path 210 may process the signal y(n) processed in the first path 200 using the sixth input delay section 270 and the second input adder section 280, and output the processed signal.

[0043] The sixth input delay unit 270 is connected to the output terminal of the second path 210 (in this embodiment, the output terminal of the second input adder 280). The sixth input delay unit 270 may delay the target signal s(n) output from the second path 210 by a second delay time different from the first delay time, and output the delayed signal to the second input adder 280. Here, the second delay time is, for example, the same as one cycle of the second sampling period of the first additional DA conversion unit 40 (i.e., M times one cycle of the reference clock). In this case, at the current sampling timing of the first additional DA conversion unit 40, the sixth input delay unit 270 can input to the second input adder 280 the value s(nM) input to the first additional DA conversion unit 40 at the previous sampling timing of the first additional DA conversion unit 40 (i.e., the value previously sampled by the first additional DA conversion unit 40).

[0044] The second input adder 280 is connected to the first input adder 260 via the selector 220. The second input adder 280 may add the output s(nM) of the sixth input delay unit 270 to the target signal x(n) input to the second path 210. In this embodiment, the second input adder 280 may add the target signal y(n) output from the first input adder 260 to the output s(nM) of the sixth input delay unit 270, and output the added value s(n) to the first additional DA conversion unit 40. Here, the sixth input delay unit 270 is an example of the second delay unit of the present application, and the second input adder 280 is an example of the second adder of the present application.

[0045] The selection unit 220 is connected to the first input adder unit 260, the second input adder unit 280, and the output terminal of the first path 200. The selection unit 220 is, for example, a switch or a multiplexer. The selection unit 220 may select one of the first path 200 and the second path 210 based on the sampling timing of the first additional DA conversion unit 40. For example, the selection unit 220 may select the first path 200 from the first path 200 and the second path 210 at a timing different from the sampling timing of the first additional DA conversion unit 40, and may select the second path 210 at the sampling timing of the first additional DA conversion unit 40. The selection unit 220 may select one of the first path 200 and the second path 210 and output the processed target signal from the selected path to one of the sub DA conversion unit 30 and the first additional DA conversion unit 40. In response to the selection section 220 selecting the first path 200, the distribution section 100 may be connected from the input terminal of the DA conversion device 10 to the sub DA conversion section 30, thereby outputting the target signal y(n) to the sub DA conversion section 30. In response to the selection section 220 selecting the second path 210, the distribution section 100 may be connected from the input terminal of the DA conversion device 10 to the first additional DA conversion section 40, thereby outputting the target signal s(n) to the first additional DA conversion section 40.

[0046] When the second path 210 is selected by the selection unit 220, the first path 200 may output a setting value (for example, 0) to the sub DA conversion unit 30. This allows the input processing unit 20 to output the setting value to the sub DA conversion unit 30 via the first path 200 at the sampling timing of the first additional DA conversion unit 40, and to output the target signal s(n) to the first additional DA conversion unit 40 via the second path 210. Furthermore, the input processing unit 20 may output the target signal y(n) to the sub DA conversion unit 30 via the first path 200, and to output the setting value to the first additional DA conversion unit 40 via the second path 210, at timings other than the sampling timing of the first additional DA conversion unit 40.

[0047] FIG. 3 shows an example of a timing chart of signals in the DA conversion device 10 of this embodiment. In FIG. 3, an example is shown where N=4 and M=5. t0 to t10 respectively indicate the timing of changes in the reference clock, and t0 to t1, t1 to t2, . . . t8 to t9, and t9 to t10 respectively indicate the period of the reference clock. x(n) indicates a bit string of the target signal input to the input terminal of the DA conversion device 10. y0(n) indicates the output of the sub DA conversion unit 30a in the first column. y1(n) indicates the output of the sub DA conversion unit 30b in the second column. y2(n) indicates the output of the sub DA conversion unit 30c in the third column. y3(n) indicates the output of the sub DA conversion unit 30d in the fourth column. s0(n) indicates the output of the first additional DA conversion unit 40. In FIG. 3, the outputs of the sub DA conversion unit 30 and the first additional DA conversion unit 40 are indicated by bit values ​​corresponding to the outputs.

[0048] For the target signal at t0, the first additional DA conversion unit 40 samples the input target signal with a value of 1 because t0 is the sampling timing, and outputs a current corresponding to the value 1. The sub DA conversion unit 30a in the first column is to sample the target signal at t0, but because t0 is the sampling timing of the first additional DA conversion unit 40, it outputs a current corresponding to the set value 0. This allows the output unit 50 to generate an output signal corresponding to the sum of the outputs of the sub DA conversion units 30 and the first additional DA conversion unit 40, with respect to the target signal with a value of 1 from t0 to t1.

[0049] For the target signal at t1, the first additional DA conversion unit 40 continues to output a current corresponding to the value 1 because t1 is not the sampling timing. The sub DA conversion unit 30a in the first column continues to output a current corresponding to the set value 0 because the target signal at t1 is not the target to be sampled. The sub DA conversion unit 30b in the second column samples the input signal with value 0 and outputs a current corresponding to the value 0 because the target signal at t1 is the target to be sampled. This allows the output unit 50 to generate an output signal corresponding to the sum of the outputs of the sub DA conversion unit 30 and the first additional DA conversion unit 40 with respect to the target signal with value 1 from t1 to t2.

[0050] For the target signal at t2, the first additional DA conversion unit 40 continues to output a current corresponding to the value 1 because t2 is not the sampling timing. The sub DA conversion unit 30a in the first column and the sub DA conversion unit 30b in the second column continue to output the same current because the target signal at t2 is not the target for sampling. The sub DA conversion unit 30c in the third column samples the input signal with a value of −1 and outputs a current corresponding to the value −1 because the target signal at t2 is the target for sampling. This allows the output unit 50 to generate an output signal corresponding to the sum of the outputs of the sub DA conversion unit 30 and the first additional DA conversion unit 40, which is a value of 0, for a target signal with a value of 0 from t2 to t3.

[0051] For the target signal at t3, the first additional DA conversion unit 40 continues to output a current corresponding to the value 1 because t3 is not a sampling timing. The sub DA conversion unit 30a in the first column, the sub DA conversion unit 30b in the second column, and the sub DA conversion unit 30c in the third column continue to output the same output because the target signal at t3 is not the target for sampling. The sub DA conversion unit 30d in the fourth column samples the target signal at t3 with value 1 and outputs a current corresponding to value 1. This allows the output unit 50 to generate an output signal corresponding to the sum of the outputs of the sub DA conversion unit 30 and the first additional DA conversion unit 40, with respect to the target signal with value 1 from t3 to t4.

[0052] For the target signal at t4, the first additional DA conversion unit 40 continues to output a current corresponding to the value 1 because t4 is not the sampling timing. The sub DA conversion unit 30a in the first column samples the input signal with a value of 0 because the target signal at t4 is the target to be sampled, and outputs a current corresponding to the value 0. The sub DA conversion unit 30b in the second column, the sub DA conversion unit 30c in the third column, and the sub DA conversion unit 30d in the fourth column continue to output the same signal because the target signal at t4 is not the target to be sampled. This allows the output unit 50 to generate an output signal corresponding to the sum of the outputs of the sub DA conversion unit 30 and the first additional DA conversion unit 40, with respect to the target signal with a value of 1 from t4 to t5.

[0053] For the target signal at t5, the first additional DA conversion unit 40 samples the input signal with a value of 0 because t5 is the sampling timing, and outputs a current corresponding to the value 0. The sub DA conversion unit 30b in the second column is to sample the target signal at t5, but because t5 is the sampling timing of the first additional DA conversion unit 40, it outputs a current corresponding to the set value 0. The sub DA conversion unit 30a in the first column, the sub DA conversion unit 30c in the third column, and the sub DA conversion unit 30d in the fourth column continue to output the same signal because the target signal at t5 is not to be sampled. This allows the output unit 50 to generate an output signal corresponding to the sum of the outputs of the sub DA conversion unit 30 and the first additional DA conversion unit 40, which is a value of 0, for the target signal with a value of 0 from t5 to t6.

[0054] The DA conversion device 10 of this embodiment can generate output signals from t6 onwards in the same manner as in the periods t1 to t6. The calculation procedure in the distribution section 100 of the DA conversion device 10 of this embodiment will be described below.

[0055]

number

[0056] In the calculation procedure of the DA conversion device 10 shown in Equation 1, x(n) represents the value of the n-th phase (tn in FIG. 3) of the target signal, and yi (n) indicates the output of the sub DA conversion unit 30 in the (i+1)th column to which the target signal of the nth phase is input, and s0(n) indicates the output of the first additional DA conversion unit 40 to which the target signal of the nth phase is input. N indicates the multiple of the sampling period of the sub DA conversion unit 30 relative to the period of the reference clock, and M indicates the multiple of the sampling period of the first additional DA conversion unit 40 relative to the period of the reference clock.

[0057] The DA conversion device 10 of this embodiment can suppress divergence of the output signal of the DA conversion device 10 by using the output of the first additional DA conversion unit 40, which has a different sampling rate, instead of part of the output of the sub DA conversion unit 30. Furthermore, by combining the sub DA conversion unit 30 and the first additional DA conversion unit 40, each of which has a sampling rate lower than the sampling rate of the entire DA conversion device 10, and implementing the output unit 50 using a simple addition method, it is possible to accurately reproduce waveforms within a finite dynamic range over the entire frequency band up to the Nyquist frequency.

[0058] 4 shows a second configuration example of the DA conversion device 10 according to this embodiment. The DA conversion device 10 of the second configuration example has a configuration similar to that of the DA conversion device 10 of the first configuration example shown in FIG. 1 and may perform similar operations, except that it further includes a second additional DA conversion section 400. The following will mainly describe the configuration that differs from the first configuration example of FIG. 1.

[0059] The second additional DA conversion unit 400 is connected to the distribution unit 100. The second additional DA conversion unit 400 may perform DA conversion on the target signal q(n) output by the distribution unit 100 at a third sampling period different from both the first sampling period and the second sampling period. The third sampling period may be an integer multiple L of the period of the reference clock, and the multiple L may be a coprime multiple or consecutive value of the multiples N and M of the first and second sampling periods. For example, when N=4 and M=5, the third sampling period may be 6 or 7 times the period of the reference clock.

[0060] The output section 50 receives the output y i The output section 50 may generate an output signal based on the outputs y(n) of the sub DA conversion sections 30, the output s0(n) of the first additional DA conversion section 40, and the output q0(n) of the second additional DA conversion section 400. i The output section 50 may generate an output signal by combining the output s0(n) of the first additional DA conversion section 40, the output s0(n) of the first additional DA conversion section 40, and the output q0(n) of the second additional DA conversion section 400. The output section 50 may further include a fourth output adder 410.

[0061] The fourth output adder 410 is connected to the first additional DA conversion section 40, the second additional DA conversion section 400, and the fourth output delay section 170. The fourth output adder 410 may add the output s0(n) of the first additional DA conversion section 40 to the output q0(n) of the second additional DA conversion section 400. The fourth output delay section 170 may delay the output of the fourth output adder 410 by a fourth delay time and output the delayed output to the third output adder 180. The third output adder 180 may add the output of the second output adder 150 delayed by the third output delay section 160 to the output y3(n) of the fourth-stage sub DA conversion section 30d and the output of the fourth output adder 410 delayed by the fourth output delay section 170. As a result, the third output adder 180 may output the added signal as the output signal d(n).

[0062] 5 shows the configuration of the distribution section 100 of the DA conversion device 10 of a second configuration example according to this embodiment. The distribution section 100 of the second configuration example has a configuration similar to that of the distribution section 100 shown in FIG. 2 and may perform similar operations, except that it further includes a third path 500. The following mainly describes the configuration different from the configuration example of FIG. 2.

[0063] The third path 500 may be connected between the input terminal of the DA conversion device 10 and the second additional DA conversion section 400. The third path 500 may extract a change amount Δx(n) in the value of the target signal x(n), add the extracted change amount Δx(n) to the input q(nL) at the previous sampling timing in the second additional DA conversion section 400, and input the result to the second additional DA conversion section 400. The third path 500 may share the fourth input delay section 230, the subtraction section 240, and the first input adder section 260 with the first path 200 and the second path 210, and may further include a seventh input delay section 510 and a third input adder section 520. The third path 500 may process the signal processed in the first path 200 using the seventh input delay section 510 and the third input adder section 520, and output the processed signal q(n) to the second additional DA conversion section 400.

[0064] The seventh input delay unit 510 is connected to the output terminal of the third path 500 (in this embodiment, the output terminal of the third input adder 520) and one of its input terminals. The seventh input delay unit 510 may delay the target signal output from the third path 500 by a delay time different from both the first delay time and the second delay time, and input the delayed signal q(nL) to the third input adder 520. Here, the delay time of the seventh input delay unit 510 is, for example, the same as one third sampling period of the second additional DA conversion unit 400 (i.e., L times one period of the reference clock). In this case, at the current sampling timing of the second additional DA conversion unit 400, the seventh input delay unit 510 can input to the third input adder 520 the value output to the second additional DA conversion unit 400 at the previous sampling timing of the second additional DA conversion unit 400 (i.e., the value previously sampled by the first additional DA conversion unit 40).

[0065] The third input adder 520 is connected to the first input adder 260 via the selector 220. The third input adder 520 may add the output q(nL) of the seventh input delay unit 510 to the target signal input to the third path 500. In this embodiment, the third input adder 520 may add the target signal y(n) output from the first input adder 260 to the output q(nL) of the seventh input delay unit 510, and output the signal q(n) to the second additional DA conversion unit 400.

[0066] The selection section 220 is connected to the first input adder section 260, the second input adder section 280, the third input adder section 520, and the output terminal of the first path 200. The selection section 220 may select one of the first path 200, the second path 210, and the third path 500 based on the sampling timing of the first additional DA conversion section 40 and the sampling timing of the second additional DA conversion section 400. For example, the selection section 220 may select the first path 200 from the first path 200, the second path 210, and the third path 500 at a timing different from the sampling timing of the first additional DA conversion section 40 and the sampling timing of the second additional DA conversion section 400, select the second path 210 at the sampling timing of the first additional DA conversion section 40, and select the third path 500 at the sampling timing of the second additional DA conversion section 400. In response to the selection of the third path 500 by the selection section 220, the distribution section 100 may be connected from the input terminal of the DA conversion device 10 to the second additional DA conversion section 400, thereby outputting the target signal q(n) to the second additional DA conversion section 400. The paths not selected by the selection section 220 may output a set value (for example, 0).

[0067] The second configuration example of the DA conversion device 10 of this embodiment may further include an additional DA conversion section whose sampling period is different from that of the sub DA conversion section 30, the first additional DA conversion section 40, and the second additional conversion section.

[0068] In the first or second configuration example of the present embodiment, the DA conversion device 10 samples the target signal s(n) in the first additional DA conversion section 40 at each sampling timing of the first additional DA conversion section 40 to generate an output signal in the output section 50, but this is not limited to this, and the target signal s(n) may be sampled in the first additional DA conversion section 40 at some of the sampling timings of the first additional DA conversion section 40.

[0069] For example, the selection section 220 may select the second path 210 from the first path 200 and the second path 210 at intermittent timings among the sampling timings of the first additional DA conversion section 40. The selection section 220 may select the second path 210 at one of multiple sampling timings of the first additional DA conversion section 40, and may select the first path 200 at timings among the sampling timings of the first additional DA conversion section 40 at which the second path 210 is not selected. For example, the selection section 220 may alternately select the first path 200 and the second path 210 at the sampling timings of the first additional DA conversion section 40.

[0070] For example, the selection section 220 may select the second path 210 so that the output to the sub DA conversion section 30 and the first additional DA conversion section 40 (i.e., the output of the first input adder section 260 and the second input adder section 280) becomes smaller at the sampling timing of the first additional DA conversion section 40. The selection section 220 may determine the timing at which to select the second path 210 among the sampling timings of the first additional DA conversion section 40 for each bit pattern of the input target signal x(n). The selection section 220 may determine in advance, by decision tree analysis or the like, for each bit pattern of the target signal x(n), a combination that minimizes the value output to the sub DA conversion section 30 and the first additional DA conversion section 40 from all combinations of the first path 200 and the second path 210 selected for each sampling timing of the first additional DA conversion section 40. As an example, the selection section 220 may determine in advance a combination of paths to be selected so as to minimize the output to the sub DA conversion section 30 and the first additional DA conversion section 40 for the bit pattern of the target signal x(n) input at multiple (for example, five) sampling timings (for example, t0, t5, t10, t15, and t20 in FIG. 3 ) of the first additional DA conversion section 40. As an example, the selection section 220 may determine in advance a combination in which the first path 200 is selected at t0, the first path 200 is selected at t5, the second path 210 is selected at t10, the second path 210 is selected at t15, and the first path 200 is selected at t20. This allows the ranges of the sub DA conversion section 30 and the first additional DA conversion section 40 to be narrower, thereby reducing the cost of the DA conversion device 10.

[0071] Furthermore, similar to the second path 210, the selection section 220 in the DA conversion device 10 of the second configuration example may select the third path 500 from the first path 200, the second path 210, and the third path 500 at intermittent timings among the sampling timings of the second additional DA conversion section 400. The selection section 220 may select the first path 200 at timings among the sampling timings of the second additional DA conversion section 400 at which the third path 500 is not selected. The selection section 220 may select the third path 500 at intermittent timings among the sampling timings of the second additional DA conversion section 400 so that the outputs to the sub DA conversion section 30, the first additional DA conversion section 40, and the second additional DA conversion section 400 are smaller (minimum). Similar to the second path 210, the selection section 220 may determine the timing at which the third path 500 is selected from among the sampling timings of the second additional DA conversion section 400 for each bit pattern of the input target signal x(n).

[0072] In addition, the selection section 220 may similarly determine a combination of the timing at which the second path 210 is selected among the sampling timings of the first additional DA conversion section 40 and the timing at which the third path 500 is selected among the sampling timings of the second additional DA conversion section 400 so that the output to the sub DA conversion section 30, the first additional DA conversion section 40, and the second additional DA conversion section 400 is smaller (minimum).

[0073] 6 is a diagram showing the configuration of a test apparatus 600 together with a device under test 700. The test apparatus 600 tests the device under test 700, such as an analog circuit, a digital circuit, a memory, or a system on chip (SOC).

[0074] The test apparatus 600 includes a signal generating section 610, a DA conversion apparatus 10, a voltage supplying section 620, a test signal outputting section 630, and a judging section 640. The DA conversion apparatus 10 generates a voltage to be applied to the device under test 700. The DA conversion apparatus 10 has the same configuration as the DA conversion apparatus 10 according to the present embodiment described with reference to FIGS. 1 to 5, and therefore a description thereof will be omitted.

[0075] The signal generating section 610 outputs a voltage to be supplied to the device under test 700 as a digital value to the DA conversion apparatus 10. The DA conversion apparatus 10 outputs an analog output signal corresponding to the digital target signal. The voltage supplying section 620 supplies a test voltage corresponding to the output signal generated by the DA conversion apparatus 10 to the device under test 700. The voltage supplying section 620 is, for example, a power amplifier.

[0076] The test signal output section 630 outputs a test signal to the device under test 700. The DA conversion apparatus 10 may be used as part of the test signal output section 630. The test signal output section 630 may also output an expected value that the device under test 700 outputs in response to the test signal to the judging section 640. The judging section 640 receives a response signal in response to the test signal from the device under test 700. The judging section 640 then judges whether the device under test 700 is good or bad based on the received response signal.

[0077] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0078] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0079] 10. DA conversion device 20 Input processing section 30 Sub DA conversion section 40 First additional DA conversion unit 50 Output section 100 Distribution section 110 Input Delay Section 110a First input delay unit 110b Second input delay unit 110c Third Input Delay Unit 120 First output delay unit 130 First output adder 140 Second output delay unit 150 Second output adder 160 Third output delay unit 170 4th output delay unit 180 Third output adder 200 Route 1 210 Route 2 220 Selection Section 230 4th input delay unit 240 Subtraction Section 250 5th Input Delay Unit 260 First input addition unit 270 6th Input Delay Unit 280 Second input addition unit 400 Second additional DA conversion unit 410 Fourth output adder 500 Route 3 510 7th Input Delay Unit 520 Third input addition unit 600 Test Equipment 610 Signal Generator 620 Voltage supply unit 630 Test signal output section 640 Judgment section 700 Devices Under Test

Claims

1. A DA conversion device that generates an analog output signal by DA converting a digital target signal, a plurality of sub DA conversion units that perform DA conversion on the target signal at a common first sampling period so that the relative phases of the target signal and the sub DA conversion units are different from each other; a first additional DA conversion unit that performs DA conversion on the target signal at a second sampling period different from the first sampling period; an output unit that generates the output signal based on the outputs of the plurality of sub DA conversion units and the output of the first additional DA conversion unit. DA conversion device.

2. The first sampling period and the second sampling period are integer multiples of the period of the reference clock, and the integer multiples are relatively prime multiples.

2. The DA conversion device according to claim 1.

3. The output unit generates the output signal by adding together the outputs of the plurality of sub DA conversion units and the output of the first additional DA conversion unit.

2. The DA conversion device according to claim 1.

4. an input processing unit that outputs the target signal with a different phase to each of the plurality of sub DA conversion units and outputs the target signal to the first additional DA conversion unit; 2. The DA conversion device according to claim 1.

5. The input processing unit outputs a setting value to the sub DA conversion unit at a sampling timing of the first additional DA conversion unit.

5. The DA conversion device according to claim 4.

6. The input processing unit outputs the set value of 0 to the sub DA conversion unit at the sampling timing of the first additional DA conversion unit.

6. The DA conversion device according to claim 5.

7. The first additional DA conversion unit outputs a signal corresponding to a value of the target signal at a sampling timing of the first additional DA conversion unit.

5. The DA conversion device according to claim 4.

8. The output unit generates an output at a sampling timing of the first additional DA conversion unit as the output signal.

5. The DA conversion device according to claim 4.

9. The input processing unit a first path that extracts a change amount of the target signal, adds the extracted change amount of the target signal to an input at a previous sampling timing in each of the sub D / A conversion units, and outputs the result to the sub D / A conversion units; a second path that extracts a change amount of the value of the target signal, adds the extracted change amount of the value to an input at a previous sampling timing in the first additional DA conversion unit, and outputs the result to the first additional DA conversion unit; a selection unit that selects one of the first path and the second path based on a sampling timing of the first additional DA conversion unit; 5. The DA conversion device according to claim 4.

10. The first path outputs 0 when the second path is selected by the selection unit.

10. The DA conversion device according to claim 9.

11. The selector selects the first path from the first path and the second path at a timing different from a sampling timing of the first additional DA converter, and selects the second path at the sampling timing of the first additional DA converter.

10. The DA conversion device according to claim 9.

12. The selector selects the second path from the first path and the second path at an intermittent timing among sampling timings of the first additional DA converter. The DA conversion device according to claim 11.

13. The first pathway is a first delay unit that delays the target signal output from the first path by a first delay time; a first adder that adds an output of the first delay unit to the target signal input to the first path, The second pathway is a second delay unit that delays the target signal output from the second path by a second delay time different from the first delay time; a second adder that adds the output of the second delay unit to the target signal input to the second path.

10. The DA conversion device according to claim 9.

14. The output unit adds the outputs of the sub DA conversion units with a delay of a third delay time, and adds the output of the first additional DA conversion unit to the added value with a delay of a fourth delay time that is greater than the third delay time, thereby generating the output signal.

2. The DA conversion device according to claim 1.

15. The fourth delay time is equal to the sum of the third delay times at the output section. The DA conversion device according to claim 14.

16. a second additional DA conversion unit that performs DA conversion of the target signal at a third sampling period different from both the first sampling period and the second sampling period; The output unit generates the output signal based on outputs of the plurality of sub DA conversion units, the output of the first additional DA conversion unit, and the output of the second additional DA conversion unit.

2. The DA conversion device according to claim 1.

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