Image forming device

Abstract

To provide an image forming device capable of reducing an influence of variations in a reference potential in generation of a reference voltage input to an LD driver.SOLUTION: An ASIC 72 provided in a color laser printer 10 controls a laser unit 31 and outputs, to an LD substrate 75, a PWM signal PWM1 for instructing a reference voltage Vref1 to an LD driver 79. A main reference potential portion GND1 serving as a reference potential of the ASIC 72 is connected to an LD reference potential portion GND2 via a harness 73. A generation circuit 81 of the LD substrate 75 turns a first transistor TR1 on / off in accordance with the PWM signal PWM1, alternately switches between an ON voltage with the reference potential of the LD reference potential portion GND2 as a reference and an OFF voltage that is the reference potential of the LD reference potential portion GND2, and outputs the voltage as an input voltage Vin1 to a first smoothing circuit 115. The first smoothing circuit 115 smooths the input voltage Vin1 and outputs the smoothed input voltage as the reference voltage Vref1 to the LD driver 79.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present application relates to an image forming apparatus equipped with a laser unit having an LD driver that controls the light emission amount of a semiconductor laser based on a reference voltage. [Background technology]

[0002] Conventionally, there are image forming devices that use a semiconductor laser to expose a photosensitive drum, and adjust the light emission amount of the semiconductor laser based on a reference voltage. In the image forming device described in Patent Document 1 (JP 2018-200427 A) listed below, an engine controller outputs a pulse width modulation (PWM) signal to a drive circuit, and the drive circuit smoothes the voltage that is on / off controlled by the PWM signal to create a reference voltage, and adjusts the light emission amount of a laser diode (corresponding to a semiconductor laser) based on the reference voltage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-200427 Summary of the Invention [Problem to be solved by the invention]

[0004] For example, there is an image forming apparatus that includes a laser unit consisting of a semiconductor laser and an LD driver that controls the light emission amount of the semiconductor laser based on a reference voltage, and a controller that outputs a voltage based on a PWM signal to an LD substrate, in which the LD substrate on which the LD driver is mounted and a main substrate on which the controller is mounted are connected by a harness. When the harness between the main board and the LD board is long, the resistance of the harness and the current flowing through it cause a voltage difference between the reference potential (GND) of the main board and the reference potential (GND) of the LD board. The controller adjusts the value of the reference voltage using the duty ratio of the PWM signal, but this voltage difference causes a reference voltage that deviates from the reference voltage intended by the controller to be input to the LD driver, which could prevent the LD driver from properly adjusting the light intensity.

[0005] The present application has been proposed in view of the above-mentioned problems, and aims to provide an image forming apparatus that can reduce the influence of fluctuations in the reference potential when generating a reference voltage to be input to an LD driver. [Means for solving the problem]

[0006] In order to achieve the above object, an image forming apparatus of the present application comprises a laser unit having a semiconductor laser, a polygon mirror that deflects light from the semiconductor laser, an LD driver that controls the amount of light emitted by the semiconductor laser based on a reference voltage, and an LD substrate on which the LD driver is mounted and which has an LD reference potential section that serves as a reference potential for the LD driver; a photosensitive drum that is exposed by the light deflected by the polygon mirror; a controller that controls the laser unit and outputs a pulse width modulation signal to the LD substrate to instruct the LD driver of the reference voltage; and a main substrate on which the controller is mounted and which has a main reference potential section that serves as a reference potential for the controller, the main reference potential section and the LD reference potential section being electrically connected via a harness, and the LD substrate comprises a voltage generation circuit that generates a predetermined voltage based on the reference potential of the LD driver, and a voltage generation circuit that generates a predetermined voltage based on the reference potential of the LD driver in response to the pulse width modulation signal. a switching circuit that alternately switches between and outputs an ON voltage or an OFF voltage that is a reference potential of the LD driver, and a smoothing circuit that generates the reference voltage by smoothing the ON voltage and the OFF voltage output by the switching circuit and outputs the reference voltage to the LD driver.

[0007] According to this, the LD substrate has a switching circuit that alternately switches between outputting an ON voltage based on a predetermined voltage with respect to the reference potential of the LD reference potential section, and outputting an OFF voltage that is the reference potential of the LD reference potential section, in response to a pulse width modulation signal. The switching circuit outputs to the smoothing circuit voltages where both the ON voltage and the OFF voltage are based on the reference potential of the LD reference potential section. Therefore, the reference voltage is input to the LD driver without deviation from the reference voltage intended by the controller as in the conventional configuration, and the LD driver can appropriately adjust the light intensity.

[0008] Furthermore, the controller may have a first output terminal, and output the pulse width modulation signal from the first output terminal by turning on and off a connection between the main reference potential unit and the first output terminal; the switching circuit may have a semiconductor transistor and a first resistor, an input terminal of the semiconductor transistor is connected to the voltage generating circuit, a control terminal of the semiconductor transistor is connected to the first output terminal via the harness, an output terminal of the semiconductor transistor is connected to the LD reference potential unit via the first resistor, a connection between the output terminal of the semiconductor transistor and the first resistor is connected to the smoothing circuit, and a voltage of the connection unit based on the reference potential of the LD reference potential unit may be output to the smoothing circuit.

[0009] With this, the controller can output a pulse width modulated signal from the first output terminal. A voltage generating circuit is connected to the input terminal of the semiconductor transistor, and a predetermined voltage generated by the voltage generating circuit is applied to the semiconductor transistor. This allows current to flow from the input terminal of the semiconductor transistor to the output terminal. The voltage at the connection point relative to the reference potential of the LD substrate is an on-voltage, which is determined by the predetermined voltage generated by the voltage generation circuit and the magnitude of the first resistor. The switching circuit outputs the on-voltage, which is the voltage at the connection point, to the smoothing circuit. When the controller turns off the connection between the main reference potential section and the first output terminal, no current flows from the voltage generating circuit to the main reference potential section via the input terminal of the semiconductor transistor. No current flows from the input terminal of the semiconductor transistor to the output terminal. The voltage of the connection section, which is based on the reference potential of the LD reference potential section, becomes the off voltage, which is the reference potential of the LD reference potential section. The switching circuit can output the off voltage, which is the voltage of the connection section, to the smoothing circuit.

[0010] The switching circuit may further include a second resistor connected between the output terminal of the semiconductor transistor and the connection portion, and the first resistor connected between the connection portion and the LD reference potential portion.

[0011] According to this, the switching circuit has a first resistor and a second resistor that connect between the LD reference potential part and the output terminal of the semiconductor transistor. The voltage of the connection part output by the switching circuit is a voltage obtained by dividing a predetermined voltage generated by the voltage generating circuit by the first resistor and the second resistor, and the upper limit of the reference voltage can be determined by the first resistor and the second resistor.

[0012] The controller has an internal voltage unit and a second output terminal, and outputs the pulse width modulated signal from the second output terminal by switching between a first connection that disconnects the internal voltage unit from the second output terminal and connects a main reference potential unit to the second output terminal, or a second connection that connects the internal voltage unit to the second output terminal and disconnects the main reference potential unit from the second output terminal, and the switching circuit has a third resistor one end of which is connected to the LD reference potential unit and a semiconductor transistor one end of which is connected in parallel with the third resistor. an output terminal of the semiconductor transistor connected to the voltage generating circuit, a control terminal of the semiconductor transistor connected to the second output terminal via the harness, an input terminal of the semiconductor transistor connected to an LD reference potential section, a connection section at which the output terminal of the semiconductor transistor and the other end of the third resistor are connected in parallel is connected to the smoothing circuit, and a voltage at the connection section based on the reference potential of the LD reference potential section is output to the smoothing circuit.

[0013] According to this, the controller can output a pulse width modulation signal from the second output terminal. The output terminal of the semiconductor transistor is connected to a voltage generating circuit, the control terminal of the semiconductor transistor is connected to the second output terminal via a harness, and the input terminal of the semiconductor transistor is connected to the LD reference potential section. The semiconductor transistor is also connected in parallel with a third resistor, one end of which is connected to the LD reference potential section. When the controller is in the first connection, no current flows from the internal voltage unit in the path from the second output terminal to the LD reference potential unit via the control terminal and input terminal of the semiconductor transistor. No current flows between the output and input terminals of the semiconductor transistor. When a predetermined voltage is applied from the voltage generation unit to the semiconductor transistor, current flows in the path from the voltage generation unit to the LD reference potential unit via the third resistor. This enables the switching circuit to output the voltage of the connection unit referenced to the reference potential of the LD reference potential unit to the smoothing circuit. The voltage of the connection unit referenced to the reference potential of the LD reference potential unit is an on-voltage, and is determined by the predetermined voltage generated by the voltage generation circuit and the magnitude of the third resistor. The switching circuit outputs the on-voltage, which is the voltage of the connection unit, to the smoothing circuit. When the controller is in the second connection, current can flow between the output terminal and input terminal of the semiconductor transistor, and current flows from the voltage generation unit to the LD reference potential unit via the output terminal and input terminal of the semiconductor transistor. No current flows through the third resistor connected in parallel to the semiconductor transistor. The voltage of the connection unit, which is based on the reference potential of the LD reference potential unit, is the off voltage, and becomes the reference potential of the LD reference potential unit. The switching circuit can output the off voltage, which is the voltage of the connection unit, to the smoothing circuit.

[0014] The switching circuit may further include a fourth resistor, and the fourth resistor may be connected between the voltage generating circuit and the output terminal of the semiconductor transistor.

[0015] According to this, the switching circuit has a fourth resistor connected between the voltage generating circuit and the output terminal of the semiconductor transistor, and the voltage at the connection point output by the switching circuit is a voltage obtained by dividing the predetermined voltage generated by the voltage generating circuit by the third resistor and the fourth resistor, and the upper limit of the reference voltage can be determined by the third resistor and the fourth resistor.

[0016] The main board may also have a DC / DC converter, and the voltage generation circuit may be a low-dropout voltage regulator that generates the specified voltage by converting a DC voltage input from the DC / DC converter of the main board via the harness.

[0017] According to this, a low-dropout voltage regulator is provided on the LD substrate. The low-dropout voltage regulator operates based on the reference potential of the LD driver and can convert the DC voltage input from the DC / DC converter via the harness to generate a predetermined voltage. Even if the harness becomes long and a voltage difference occurs between the reference potential of the low-dropout voltage regulator and the reference potential of the main substrate, the voltage difference between the input and output of the low-dropout voltage regulator is prevented from deviating from the desired dropout voltage, allowing the transistors in the low-dropout voltage regulator to operate stably. The output voltage of the low-dropout voltage regulator can be set to a target voltage value.

[0018] The semiconductor laser may also have two light-emitting elements, the LD driver may be connected to each of the two light-emitting elements, and may have two light-intensity adjustment circuits that control the light emission amount of each of the two light-emitting elements, and the switching circuit and the smoothing circuit may be arranged for each of the two light-intensity adjustment circuits.

[0019] This allows simultaneous exposure using two light-emitting elements. Also, it is possible to prevent the reference voltages generated by the switching circuits and smoothing circuits corresponding to the two light-emitting elements from deviating from the reference voltage intended by the controller. For each light-emitting element, the LD driver can appropriately adjust the light intensity.

[0020] The LD driver may also have a light intensity adjustment circuit that adjusts a detection value indicating the amount of light emitted by the light emitting element of the semiconductor laser to a reference value, and the light intensity adjustment circuit may be connected to the LD reference potential section via a fixed resistor.

[0021] According to this, by changing the resistance value of the fixed resistor, the detection value can be changed, and the light emission amount of the light-emitting element can be adjusted by the resistance value of the fixed resistor. Furthermore, after manufacturing the image forming apparatus, the reference voltage can be changed by changing the pulse width modulation signal output by the controller. This eliminates the need to change the resistance value after manufacturing.

[0022] Furthermore, the semiconductor laser, the LD driver, and the photosensitive drum may be arranged corresponding to each of a plurality of colors that form an image, and the resistance value of the fixed resistor that is arranged corresponding to at least one color among the fixed resistors connected to the light amount adjustment circuit of the LD driver that is arranged corresponding to each of the plurality of colors may be different from the resistance values ​​of the fixed resistors that are arranged corresponding to the other colors.

[0023] According to this, the semiconductor laser, the LD driver, and the photosensitive drum are arranged corresponding to each color. By changing the resistance value of the fixed resistor connected to the light amount adjustment circuit arranged corresponding to each color, the light amount of the light emitting element can be adjusted for each color.

[0024] Furthermore, the resistance value of the fixed resistor connected to the light intensity adjustment circuit arranged corresponding to each of the plurality of colors may be set to a value corresponding to the optical characteristics of the optical path from the semiconductor laser arranged corresponding to each of the plurality of colors to the photosensitive drum arranged corresponding to each of the plurality of colors.

[0025] If the distance of the optical path from the semiconductor laser to the photosensitive drum differs for each of the multiple colors, the intensity of the light when it reaches the photosensitive drum will differ for each color even if the same amount of light is emitted. Also, if the number of lenses arranged on the optical path or the characteristics of the lenses differ, the intensity of the light when it reaches the photosensitive drum will differ for each color even if the same amount of light is emitted. Therefore, the resistance value of the fixed resistor for each color is set to a value corresponding to the optical characteristics of the optical path described above. This allows the light emission amount of the light-emitting element to be adjusted according to the distance of the optical path for each color.

[0026] Further, the display device includes a first semiconductor laser that is the semiconductor laser arranged corresponding to black, a first LD driver that is the LD driver arranged corresponding to black, a first voltage generation circuit that is the voltage generation circuit arranged corresponding to black, a second semiconductor laser that is the semiconductor laser arranged corresponding to colors other than black, a second LD driver that is the LD driver arranged corresponding to colors other than black, and a second voltage generation circuit that is the voltage generation circuit arranged corresponding to colors other than black, wherein the LD substrate is formed in a long plate shape along a predetermined direction, the first semiconductor laser and the second semiconductor laser are arranged at the center of the LD substrate in the predetermined direction, The first LD driver may be arranged on the opposite side of the second LD driver in the predetermined direction, with the first semiconductor laser and the second semiconductor laser sandwiched therebetween, and the first voltage generation circuit may be arranged on the opposite side of the second voltage generation circuit in the predetermined direction, with the first semiconductor laser, the second semiconductor laser, the first LD driver, and the second LD driver sandwiched therebetween.

[0027] If the voltage generation circuit and the semiconductor laser are arranged adjacent to each other on the LD substrate, heat generated by the voltage generation circuit may affect the operation of the semiconductor laser, changing the wavelength of the emitted light and the reflection pattern, potentially altering the optical path. This may result in reduced image formation accuracy. Therefore, it is preferable to arrange the heat-generating voltage generation circuit away from the semiconductor laser on the LD substrate. In this configuration, the first voltage generation circuit corresponding to black is arranged on the opposite side of the second voltage generation circuit corresponding to the other colors, sandwiching the first LD driver, first semiconductor laser, second semiconductor laser, and second LD driver in the predetermined longitudinal direction of the LD substrate. This allows the voltage generation circuit to be arranged away from the semiconductor laser, sandwiching the LD driver between them. Furthermore, the heat-generating first and second voltage generation circuits can also be arranged away from each other. This reduces the impact of heat from the voltage generation circuit on the semiconductor laser, improving image formation accuracy. [Effects of the Invention]

[0028] According to the image forming apparatus of the present application, it is possible to reduce the influence of fluctuations in the reference potential in generating the reference voltage input to the LD driver. [Brief explanation of the drawings]

[0029] [Figure 1] 1 is a cross-sectional view showing a schematic configuration of a color laser printer according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a block diagram showing the electrical connection relationship between the main board and the laser unit according to the first embodiment. [Figure 3] FIG. 2 is a diagram showing the laser unit according to the first embodiment as viewed from above, illustrating the path of a beam emitted from a semiconductor laser until it reaches a BD sensor. [Figure 4] FIG. 2 is a plan view of the LD substrate according to the first embodiment, showing the surface on which the LD driver is mounted. [Figure 5] FIG. 2 is a circuit diagram of the LD substrate according to the first embodiment. [Figure 6] 4 is a diagram for explaining an input voltage output from a switching circuit according to the first embodiment to a first smoothing circuit. [Figure 7] FIG. 10 is a circuit diagram for explaining an input voltage input to a first smoothing circuit in a comparative example. [Figure 8] (Top) A diagram showing the input voltage input to the first smoothing circuit and the reference voltage output by the first smoothing circuit in the first embodiment, and (bottom) an input voltage input to the first smoothing circuit and the reference voltage output by the first smoothing circuit in the comparative example. [Figure 9] FIG. 10 is a circuit diagram illustrating a generating circuit according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0030] (First embodiment) A color laser printer according to a first embodiment, which is an embodiment of the image forming apparatus of the present application, will be described below with reference to FIG. 1. FIG. 1 is a cross-sectional view showing the schematic configuration of a color laser printer 10 according to the first embodiment. The color laser printer 10 is an example of the image forming apparatus of the present application. Hereinafter, the color laser printer 10 will be abbreviated to printer 10. The printer 10 includes a main body housing 2, a conveying unit 3, a processing unit 4, and a fixing device 5. For ease of explanation, the up-down direction and the front-rear direction of the printer 10 will be defined as indicated by the arrows in FIG. 1. The front side of the paper will be defined as the right, and the far side of the paper will be defined as the left.

[0031] The main body housing 2 has an openable front cover 11 and a rear cover 12, a supply tray 13, a discharge tray 15, and a transport path 17. The supply tray 13 is detachably attached to the bottom of the main body housing 2. Sheets S are placed on the supply tray 13. The sheets S are standard-sized paper such as A4 size. The sheets S are not limited to paper media such as plain paper or cardboard, and may be other recording media such as overhead projector film. The discharge tray 15 is provided at the top of the main body housing 2, and sheets S on which images have been formed are placed on the discharge tray 15.

[0032] The conveying unit 3 includes a pickup roller 21, a separation roller 22, and a plurality of conveying rollers 23. The pickup roller 21 picks up the sheets S in the supply tray 13 and conveys them toward the conveying path 17. The separation roller 22 separates the sheets S picked up by the pickup roller 21 one by one. The plurality of conveying rollers 23 eject the sheets S separated by the separation roller 22 along the conveying path 17, passing them through the process unit 4 and the fixing device 5 in this order, and onto the discharge tray 15. The conveying unit 3 rotates each roller based on the drive of a main motor (not shown) provided inside the main body housing 2.

[0033] The conveying unit 3 also includes a plurality of switchback rollers 25 that reverse the sheet S printed on one side, and a reverse conveying path 27. The printer 10 can switch the conveying destination of the sheet S between the discharge tray 15 and the reverse conveying path 27 indicated by the dashed line by swinging a flapper 28 provided downstream of the fixing device 5 on the conveying path 17. The conveying unit 3 swings the flapper 28 to the position indicated by the two-dot chain line based on the drive of the main motor, and rotates the plurality of switchback rollers 25, thereby conveying the sheet S upward along the reverse conveying path 27. The conveying unit 3 reversely rotates the switchback rollers 25 to convey the sheet S conveyed upward along the reverse conveying path 27, passing below the supply tray 13 and conveying it to the front side. As a result, the sheet S is reversed and conveyed to the base end of the conveying path 17. The printer 10 performs double-sided printing by printing on the top side of the reversed sheet S (the side opposite to the side printed the first time). Furthermore, the printer 10 is capable of printing even with the rear cover 12 open, and the printed sheet S can be discharged onto the open rear cover 12.

[0034] The process unit 4 has a function of forming an image on the sheet S, and transfers a toner image onto the sheet S. The process unit 4 includes a laser unit 31, a drum unit 32, four developing cartridges 33Y, 33M, 33C, and 33K, and a transfer unit 34.

[0035] The laser unit 31 is disposed in the upper part of the main body housing 2, and exposes the surface of the photosensitive drum 41 by emitting laser light indicated by the dashed line onto the surface of the photosensitive drum 41 of the drum unit 32. Details of the laser unit 31 will be described later.

[0036] The drum unit 32 is disposed between the supply tray 13 and the laser unit 31 inside the main body housing 2, and includes four photosensitive drums 41, four chargers 43, and a support frame 45 that supports the photosensitive drums 41, etc. The drum unit 32 is detachable from the main body housing 2 when the front cover 11 is open.

[0037] The developing cartridges 33Y, 33M, 33C, and 33K correspond to the four colors of yellow (Y), magenta (M), cyan (C), and black (K), respectively, and are detachably mounted in the drum unit 32 in that order from the front to the rear of the printer 10. Each of the developing cartridges 33Y, 33M, 33C, and 33K includes a developing roller 51, a supply roller 52, and a toner storage section 53. Although the four developing cartridges 33Y, 33M, 33C, and 33K differ in toner color, they are otherwise configured the same. Therefore, in the following description, when the four developer cartridges 33Y, 33M, 33C, and 33K corresponding to the four colors are collectively referred to as developer cartridge 33. Similarly to developer cartridge 33, other devices (such as semiconductor laser 77) corresponding to the colors yellow, magenta, cyan, and black will also be described individually with the letters Y, M, C, and K added after their reference numerals, or collectively without any reference numerals.

[0038] The transfer unit 34 is disposed between the supply tray 13 and the drum unit 32 inside the main body housing 2, and includes a drive roller 61, a driven roller 62, a conveyor belt 63, and four transfer rollers 64. The conveyor belt 63 is stretched between the drive roller 61 and the driven roller 62, and its upper surface is in contact with the photosensitive drum 41. The four transfer rollers 64 are disposed inside the conveyor belt 63 so as to sandwich the conveyor belt 63 between themselves and the corresponding photosensitive drum 41.

[0039] The charger 43 is provided above the photosensitive drum 41 and is, for example, a scorotron charger having a charging wire or grid. The process unit 4 generates a corona discharge using the charger 43, uniformly positively charging the surface of the photosensitive drum 41. The laser unit 31 irradiates the surface of the photosensitive drum 41 with laser light to expose it, thereby forming an electrostatic latent image based on image data on the surface of the photosensitive drum 41. Note that the device that charges the photosensitive drum 41 is not limited to a scorotron charger, and may be another device such as a roller-type charging roller. Furthermore, the polarity with which the photosensitive drum 41 is charged is not limited to positive charging, and may be negative charging.

[0040] Furthermore, the process unit 4 supplies toner in the toner storage unit 53 to the supply roller 52, which then supplies the toner to the development roller 51. The toner supplied to the development roller 51 is carried on the development roller 51 as the development roller 51 rotates. The development roller 51 is rotated by the rotational driving force of the main motor, supplies toner to the photosensitive drum 41, develops the electrostatic latent image formed on the surface of the photosensitive drum 41, and carries a toner image. The toner carried on the development roller 51 moves to the electrostatic latent image on the photosensitive drum 41 due to the potential difference between the development roller 51 and the electrostatic latent image formed on the photosensitive drum 41, and forms a toner image. This toner image is transferred to the sheet S by applying a negative voltage to the transfer roller 64 while the photosensitive drum 41 is in contact with the sheet S on the transport path 17.

[0041] The fixing device 5 is disposed behind the process unit 4 within the main body housing 2. The sheet S onto which the toner image has been transferred is transported to the fixing device 5. The fixing device 5 has a heating roller 67 that heats the sheet S and a pressure unit 68 that sandwiches the sheet S between the heating roller 67 and the sheet S. The heating roller 67 has a heater 69 therein that heats the heating roller 67. The pressure unit 68 has an endless belt, a pressure pad that sandwiches the endless belt between the heating roller 67 and the pressure pad, a holder that supports the pressure pad, a belt guide, etc. The pressure unit 68 is rotated by the rotational driving force transmitted from the main motor, and presses the sheet S against the heating roller 67 to apply pressure to the sheet S. In this way, the fixing device 5 fixes the toner image to the sheet S.

[0042] (Regarding laser unit 31) Next, the laser unit 31 will be described. As shown in FIG. 2, the printer 10 is equipped with a main board 71 that controls the laser unit 31. The main board 71 has an ASIC 72. The ASIC 72 is an Application Specific Integrated Circuit and includes a CPU and the like. The ASIC 72 reads and executes a control program from a storage device (RAM, ROM, etc.) not shown, and performs overall control of the printer 10. Note that the configuration of the main board 71 shown in FIG. 2 is just one example. For example, the main board 71 may be equipped with an SoC (System on a Chip) as a controller instead of an ASIC.

[0043] The main board 71 is connected to the laser unit 31 via a harness 73. The harness 73 is, for example, a flexible flat cable. The main board 71 controls the operation of the laser unit 31 via the harness 73.

[0044] The laser unit 31 also has an LD substrate 75, four semiconductor lasers 77Y, 77M, 77C, and 77K corresponding to each color, and a polygon motor substrate 78. The LD substrate 75 has four LD drivers 79Y, 79M, 79C, and 79K corresponding to each color, four generation circuits 81Y, 81M, 81C, and 81K corresponding to each color, a non-volatile memory 82, a first BD sensor 83, and a second BD sensor 84. The LD driver 79 is a driver circuit that causes the semiconductor laser 77 to emit light. The generation circuit 81 is a circuit that generates reference voltages Vref1 and Vref2 that are output to the LD driver 79. Details of the LD driver 79 and the generation circuit 81 will be described later.

[0045] The nonvolatile memory 82 is a rewritable memory such as an EEPROM (Electrically Erasable Programmable Read-Only Memory). The nonvolatile memory 82 is not limited to an EEPROM, and may be other nonvolatile memories such as a flash memory or an EPROM. The nonvolatile memory 82 stores, for example, correction data used for image formation. Specifically, the nonvolatile memory 82 stores correction data for adjusting the light emission amount of the semiconductor laser 77 by changing the duty ratio of a pulse width modulation signal (PWM signals PWM1 and PWM2) described below. The information stored in the nonvolatile memory 82 is not limited to correction data, and may also include information on the serial number of the printer 10, log data storing the operating status of the printer 10, etc.

[0046] A clock signal CLK1, a data signal DATA, and a write protect signal nWP are input to the nonvolatile memory 82 from the ASIC 72 via the harness 73. The clock signal CLK1 is a synchronization signal that synchronizes the timing of writing data to or reading data from the nonvolatile memory 82. The data signal DATA is data to be written to or read from the nonvolatile memory 82. The write protect signal nWP is a control signal that indicates whether writing to the nonvolatile memory 82 is prohibited.

[0047] For example, when a high-level write protect signal nWP is input, the nonvolatile memory 82 permits writing to the nonvolatile memory 82, and when a low-level write protect signal nWP is input, the nonvolatile memory 82 prohibits writing to the nonvolatile memory 82. In the printer 10 of this embodiment, the wiring in the harness 73 that transmits the write protect signal nWP is also used as the wiring that transmits the enable signal ENABLE, which will be described later. This reduces the number of wires included in the harness 73, i.e., the number of wires connecting the main board 71 and the LD board 75. Note that the wiring for the write protect signal nWP and the wiring for the enable signal ENABLE may be separate wires.

[0048] The enable signal ENABLE is a control signal that switches the LD driver 79 between a driving state and a stopped state. For example, the LD driver 79 drives when a high level enable signal ENABLE is input, and stops driving when a low level enable signal ENABLE is input. In the printer 10 of this embodiment, the four LD drivers 79Y, 79M, 79C, and 79K share a wiring for inputting the enable signal ENABLE from the ASIC 72. Specifically, the enable signal ENABLE is output from one output terminal of the ASIC 72, transmitted through one shared wiring in the harness 73, and input to each of the four LD drivers 79Y, 79M, 79C, and 79K by the wiring pattern on the LD board 75. Therefore, in this embodiment, Not only is the wiring for the protection signal nWP and the enable signal ENABLE shared, but the wiring for the enable signal ENABLE of the four LD drivers 79Y, 79M, 79C, and 79K is also shared, thereby reducing the number of wires. Note that the wiring for the enable signal ENABLE of the four LD drivers 79Y, 79M, 79C, and 79K may be separate wires.

[0049] The LD drivers 79 and semiconductor lasers 77 corresponding to each color have the same configuration. Therefore, in the following description, they will be referred to as the LD driver 79 and semiconductor laser 77. As shown in FIG. 2, the semiconductor laser 77 has a first laser diode LD1, a second laser diode LD2, and a photodiode PD. Note that FIG. 2 illustrates the first laser diode LD1 and the like only for the semiconductor laser 77K corresponding to black. The semiconductor laser 77 is, for example, a unit in which the first and second laser diodes LD1 and LD2 and the photodiode PD are housed in a cap and electrically connected to the LD substrate 75. The first and second laser diodes LD1 and LD2 are, for example, edge-emitting elements that emit laser light from two end faces of the element. The first laser diode LD1 emits laser light L from the end face on the polygon mirror 92 side (the upper end face in FIG. 3) and emits back laser light (not shown) from the end face opposite to the first laser diode LD1. The second laser diode LD2 has the same configuration as the first laser diode LD1. The photodiode PD is attached in a position within the unit where it can receive the back laser light from both the first and second laser diodes LD1 and LD2.

[0050] The first and second laser diodes LD1 and LD2 may be separate units. In this case, the photodiode PD that receives the back laser light from the first laser diode LD1 may be provided separately from the photodiode PD that receives the back laser light from the second laser diode LD2. The first and second laser diodes LD1 and LD2 are examples of the semiconductor laser of the present application. The semiconductor laser of the present application is not limited to an edge-emitting element, but may also be a surface-emitting element. The element that receives laser light such as back laser light is not limited to a photodiode, but may also be another light-receiving element that can convert light into an electrical signal, such as a CMOS image sensor.

[0051] The polygon motor board 78 has a motor driver 87 and a polygon motor 89. The polygon motor board 78 is connected to the main board 71 via a harness 73. The harness 73 connecting the LD board 75 and the main board 71 may be a harness separate from the harness 73 connecting the polygon motor board 78 and the main board 71. The motor driver 87 receives an ON signal ON, a clock signal CLK2, and a LOCKn signal LOCKn from the ASIC 72 on the main board 71 via the harness 73. The ON signal ON is a signal that switches the motor driver 87 between a driving state and a driving-stopped state.

[0052] The polygon motor 89 is, for example, a DC brushless motor. The motor driver 87 has, for example, multiple switch elements that switch the current supplied to the windings of the polygon motor 89. The clock signal CLK2 is a control signal for switching the switch elements of the motor driver 87 on and off. For example, when a high-level ON signal ON is input, the motor driver 87 drives each circuit and controls the switch elements on and off based on the clock signal CLK2. This causes the polygon motor 89 to start rotating. The ASIC 72 can control the rotation speed, etc. of the polygon motor 89 by changing the frequency, etc., of the clock signal CLK2. Furthermore, when a low-level ON signal ON is input, the motor driver 87 stops each circuit and enters a drive-stop state. The motor driver 87 may be provided on the main board 71.

[0053] The LOCKn signal LOCKn is a signal indicating whether the polygon motor 89 has rotated to a predetermined number of rotations (a predetermined number of rotations or rotation speed). A LOCKn signal LOCKn of high level is output to the ASIC 72 until the number of rotations per unit time of the motor 89 reaches a predetermined number of rotations, and when it detects that the number of rotations per unit time has reached the predetermined number of rotations, a LOCKn signal LOCKn of low level is output to the ASIC 72. The LOCKn signal LOCKn may be a signal indicating whether or not the rotation speed of the motor has reached the predetermined rotation speed.

[0054] FIG. 3 is a top view of the laser unit 31, showing the path of the beam emitted from the semiconductor laser 77 until it reaches the first and second BD sensors 83 and 84. As shown in FIG. 3, the laser unit 31 includes four collimating lenses (which may also be referred to as coupling lenses) 91Y, 91M, 91C, and 91K, a polygon mirror 92, two fθ lenses (which may also be referred to as scanning lenses) 93YM and 93CK, four reflecting mirrors 94Y, 94M, 94C, and 94K corresponding to each color, a first mirror 95, a second mirror 96, and a frame 97. The collimating lens 91, the polygon mirror 92, the fθ lens 93, the reflecting mirror 94, and the first and second mirrors 95 and 96 are attached to the frame 97. In the following description, a direction parallel to the rotation axis X1 of the polygon mirror 92 (a direction perpendicular to the plane of FIG. 3) is referred to as a "first direction." Furthermore, the direction perpendicular to the first direction, in which the polygon mirror 92 and the fθ lenses 93YM and 93CK are aligned (the left-right direction in FIG. 3), is referred to as the "second direction." Furthermore, the direction perpendicular to the first and second directions is referred to as the "third direction." The third direction corresponds to the main scanning direction, and the first direction corresponds to the sub-scanning direction. Arrows indicating each direction in the drawings point to one side in each direction.

[0055] The frame 97 has a rectangular box shape when viewed from above in the first direction. The LD substrate 75 is attached to a side surface of the frame 97 in the third direction. The LD substrate 75 is fixed to the frame 97 with screws (not shown) inserted into screw holes 99 (see FIG. 4) with its plane aligned with the first and second directions.

[0056] FIG. 4 is a plan view of the LD substrate 75, showing the surface on which the LD driver 79 is mounted. The surface shown in FIG. 4 is the surface on the outside in the third direction (the lower side in FIG. 3). The LD substrate 75 has a substantially rectangular shape with its longer sides in the second direction. The second direction is an example of the predetermined direction in the present application. As shown in FIGS. 3 and 4, the four semiconductor lasers 77 are attached to the surface opposite the LD driver 79, in the center in the first and second directions. Note that FIG. 4 shows the semiconductor lasers 77 on the opposite surface with dashed lines, and shows multiple lead holes 76 into which leads of the semiconductor lasers 77 are inserted with solid lines. The multiple lead holes 76 are provided in groups of four, corresponding to the four leads of one semiconductor laser 77.

[0057] The four semiconductor lasers 77 are arranged around the center of the LD substrate 75. The semiconductor lasers 77C and 77K are arranged side by side in the first direction with a predetermined gap between them. The semiconductor lasers 77M and 77Y are arranged side by side in the first direction with a predetermined gap between them. The semiconductor lasers 77C and 77M are arranged side by side in the second direction with a predetermined gap between them. The semiconductor lasers 77K and 77Y are arranged side by side in the second direction with a predetermined gap between them. The gap between the semiconductor lasers 77 in the first direction is narrower than the gap between them in the second direction.

[0058] Each of the four collimator lenses 91 is disposed at a position facing the semiconductor laser 77 corresponding to each color in the third direction. The polygon mirror 92, collimator lenses 91, and semiconductor laser 77 are disposed side by side along the third direction. The collimator lens 91 converts the laser light L of the semiconductor laser 77 into a beam LB and emits it toward the polygon mirror 92. In the following explanation, to avoid complication, the beam LB may be referred to as laser light L. For example, the laser light L emitted from the semiconductor laser 77 toward the polygon mirror 92 is the beam LB emitted from the semiconductor laser 77 and converted by the collimator lens 91. It means the beam LB emitted to the polygon mirror 92. The above-described configuration of the optical system is an example. The laser unit 31 may also include a diaphragm plate and a condenser lens through which the laser light L passes.

[0059] The laser unit 31 converts the laser light L emitted from the semiconductor laser 77 into a beam LB, and the beam LB is deflected by a polygon mirror 92 and directed toward the photosensitive drum 41 of the developer cartridge 33 to expose the photosensitive drum 41. The polygon mirror 92 is a rotating polygonal mirror, and is shaped, for example, like a regular pentagonal prism, with five reflective surfaces constituting each side of the prism. The polygon mirror 92 is driven to rotate by a polygon motor 89 and deflects the laser light L from the semiconductor laser 77. The polygon mirror 92 rotates, for example, clockwise in FIG. 3, and deflects the beam LB incident from the collimator lens 91 in the main scanning direction.

[0060] The fθ lens 93 focuses the beam LB scanned by the polygon mirror 92. The fθ lens 93 focuses the beam LB emitted from the collimator lens 91 and reflected by the reflecting surface of the polygon mirror 92. The reflecting mirrors 94 are provided corresponding to each color and are arranged side by side in the second direction. As shown in FIG. 3, the four reflecting mirrors 94 are arranged in the order 94Y, 94M, 94C, and 94K from one side in the second direction (the right side in FIG. 3) and are arranged at equal intervals in the second direction. The polygon mirror 92 is arranged between the reflecting mirror 94C and the reflecting mirror 94M in the second direction and equidistant from the two reflecting mirrors 94C and 94M. The fθ lens 93YM is shared by the beams LB of the semiconductor lasers 77Y and 77M and is arranged between the reflecting mirror 94M and the polygon mirror 92 in the second direction. The fθ lens 93CK is shared by the beams LB of the semiconductor lasers 77C and 77K, and is disposed at a position between the reflecting mirror 94C and the polygon mirror 92 in the second direction.

[0061] The four reflecting mirrors 94 are attached, for example, at different positions and in different orientations in the first direction, and focus the beams LB emitted from the four semiconductor lasers 77 and focused by the fθ lenses 93 onto the surfaces of the photosensitive drums 41 of the respective colors. Therefore, the optical distances (optical paths) of the beams LB corresponding to the respective colors from the semiconductor lasers 77 to the photosensitive drums 41 are different. When the polygon mirror 92 rotates in conjunction with the rotation of the polygon motor 89, the angle of the reflecting surface relative to the emission direction of the beam LB from the collimator lens 91 periodically changes. As a result, the beams LB are periodically deflected by the reflecting surface of the polygon mirror 92, forming scan lines on the surface of the photosensitive drums 41.

[0062] The first BD sensor 83 and the second BD sensor 84 are disposed at positions that are opposite ends of the LD substrate 75 in the second direction. The first BD sensor 83 is provided at the right end of the LD substrate 75 in Fig. 4, and is disposed at a position opposite a linear regulator 113CK (described later) in the first direction, with a screw hole 99 therebetween. Similarly, the second BD sensor 84 is provided at the left end of the LD substrate 75 in Fig. 4, and is disposed at a position opposite a linear regulator 113YM (described later) in the first direction, with a screw hole 99 therebetween.

[0063] In addition, the LD drivers 79Y, 79M, and 79C are arranged between the semiconductor lasers 77Y and 77M and the first BD sensor 83 (the screw holes 99 and the linear regulator 113CK) in the second direction. The LD drivers 79Y, 79M, and 79C are arranged at positions that become the vertices of an equilateral triangle, and are arranged at positions that are equally spaced apart from each other. In addition, the nonvolatile memory 82 is arranged between the LD driver 79Y and the first BD sensor 83 in the second direction.

[0064] The LD driver 79K corresponding to black is configured to drive the semiconductor laser 7 7C, 77K and the second BD sensor 84, and is located close to the semiconductor laser 77C. In other words, the LD driver 79K corresponding to black is located on the opposite side in the second direction from the LD drivers 79Y, 79M, 79C of the other colors, with the four semiconductor lasers 77 sandwiched therebetween. Also, the linear regulator 113YM corresponding to black is located on the opposite side in the second direction from the linear regulator 113CK, with the four LD drivers 79 and four semiconductor lasers 77 sandwiched therebetween. Each of the linear regulators 113YM, 113CK is located at a position that becomes an end of the LD substrate 75 in the second direction.

[0065] In addition, in the second direction, a first connector 119 and a second connector 120 are arranged between the second BD sensor 84 and the LD driver 79K. The first connector 119 is a connector for connecting the LD substrate 75 and the polygon motor substrate 78. The second connector 120 is a connector for connecting the harness 73. The second connector 120 is connected to the main substrate 71 via the harness 73, and inputs and outputs the above-mentioned enable signal ENABLE, etc.

[0066] As shown in FIGS. 3 and 4, the first BD sensor 83 detects the beam LBY corresponding to yellow among the beams LB deflected by the polygon mirror 92. The first BD sensor 83 is embedded in the LD substrate 75 and exposed on both sides of the LD substrate 75. The detection surface of the first BD sensor 83 faces the frame 97. The first mirror 95 is disposed between the polygon mirror 92 and the first BD sensor 83 in the third direction. When the reflecting surface of the polygon mirror 92 is at a specific angle, the first mirror 95 reflects the beam LBY, which is emitted from the polygon mirror 92 via the fθ lens 93YM, toward the first BD sensor 83. Note that the first effective scanning range RA1 shown in FIG. 3 indicates the scanning range used to form an image of the beam LBY corresponding to yellow, and the second effective scanning range RA2 indicates the scanning range used to form an image of the beam LBK corresponding to black.

[0067] The first BD sensor 83 includes, for example, a photodiode and a comparison circuit, and outputs a high-level detection signal Vo1 (see FIG. 2) when the amount of light received by the photodiode of the beam LBY is equal to or less than a predetermined threshold, and outputs a low-level detection signal Vo1 when the amount of light received is greater than the predetermined threshold. The first BD sensor 83 outputs the detection signal Vo1 to the ASIC 72 on the main board 71 via the harness 73. The ASIC 72 detects a predetermined timing after writing of the beam LBY to the photosensitive drum 41 corresponding to yellow is completed based on the detection signal Vo1 from the first BD sensor 83.

[0068] Furthermore, the second BD sensor 84 and the second mirror 96 have the same configuration as the first BD sensor 83 and the first mirror 95, and therefore detailed description thereof will be omitted. Similar to the first BD sensor 83, the second BD sensor 84 receives the beam LBK that is irradiated from the polygon mirror 92 via an fθ lens 93CK and reflected by the second mirror 96 when the reflective surface of the polygon mirror 92 is at a specific angle. The second BD sensor 84 outputs a detection signal Vo2 to the ASIC 72 according to the amount of received beam LBK.

[0069] As shown in FIG. 2, the ASIC 72 outputs video signals VS1 and VS2 to each of the four LD drivers 79 via the harness 73. These video signals VS1 and VS2 are signals that switch the light emission state of the semiconductor laser 77, that is, switch the exposure state, as will be described later. For example, the ASIC 72 changes the video signals VS1 and VS2 that are output to the LD drivers 79 of each color based on the time when the second BD sensor 84 detects the beam LBK, and controls the timing when the LD board 75 starts exposing the photosensitive drum 41. This controls the writing of images of each color according to the timing when the beam LBK reaches the second BD sensor 84. By determining the positions, it is possible to reduce positional deviation when forming electrostatic latent images on the photosensitive drums 41.

[0070] The ASIC 72 also corrects thermal expansion of the laser unit 31 (frame 97, lens, etc.) based on the detection signals Vo1 and Vo2 of the first and second BD sensors 83 and 84. The ASIC 72 calculates a correction value for thermal expansion based on the detection timing of the first BD sensor 83 and the second BD sensor 84, for example, and corrects the write timing, etc. The printer 10 may be configured to include only one of the first BD sensor 83 or the second BD sensor 84.

[0071] Fig. 5 shows a circuit diagram of the LD substrate 75. Of the four LD drivers 79 and four generation circuits 81, Fig. 5 only shows the LD driver 79K and generation circuit 81K. The LD drivers 79 and generation circuits 81 for the other colors have the same configuration as the LD driver 79K and generation circuit 81K. Therefore, in the following explanation, each circuit will be referred to as the LD driver 79 and generation circuit 81.

[0072] 2 and 5, the LD driver 79 includes a first light-intensity adjustment circuit 101, a second light-intensity adjustment circuit 102, a first modulation circuit 103, a second modulation circuit 104, and a current mirror circuit 105. The LD driver 79 switches the first and second laser diodes LD1 and LD2 of the semiconductor laser 77 between an on-state and an off-state based on video signals VS1 and VS2 input from the ASIC 72. The second light-intensity adjustment circuit 102, the second modulation circuit 104, and the second laser diode LD2 have the same configurations as the first light-intensity adjustment circuit 101, the first modulation circuit 103, and the first laser diode LD1. Therefore, the following description will mainly focus on the first light-intensity adjustment circuit 101, the first modulation circuit 103, and the first laser diode LD1, and will omit descriptions of the second light-intensity adjustment circuit 102, the second modulation circuit 104, and the second laser diode LD2 as appropriate.

[0073] The main board 71 has a DC / DC converter 106. The DC / DC converter 106 supplies a DC voltage of, for example, 3.3 V to the LD driver 79 via the harness 73. The DC voltage output from the DC / DC converter 106 is input as a drive voltage Vcc1 to the first and second light intensity adjustment circuits 101 and 102 and the current mirror circuit 105. The first light intensity adjustment circuit 101 receives a detection voltage Vpd1 from the current mirror circuit 105. The detection voltage Vpd1 is a voltage corresponding to the magnitude of a photocurrent Ipd that flows through the photodiode PD when the first laser diode LD1 emits light. When the photodiode PD receives back laser light, a photocurrent Ipd is generated. The photocurrent Ipd is a current corresponding to the amount of back laser light received by the photodiode PD.

[0074] The LD substrate 75 has an LD reference potential section GND2 that serves as a reference potential for the LD driver 79, the generation circuit 81, and the semiconductor laser 77. The photocurrent Ipd flows from the cathode of the photodiode PD through the anode toward the LD reference potential section GND2. The main substrate 71 also has a main reference potential section GND1 that serves as a reference potential for the ASIC 72, the DC / DC converter 106, and the DC / DC converter 107 described below. A ground terminal 108 provided on the LD substrate 75 is connected to a ground terminal 110 provided on the main substrate 71 via a ground line 109 included in the harness 73. As a result, the LD reference potential section GND2 of the LD substrate 75 is connected to the main reference potential section GND1 of the main substrate 71 via the ground line 109.

[0075] The current mirror circuit 105 is connected to the cathode of the photodiode PD, and replicates (copies) the photocurrent Ipd flowing through the photodiode PD, and outputs it from first and second output terminals 111 and 112. The first output terminal 111 is connected to the first light amount adjustment circuit 101, and The first output terminal 111 outputs a voltage Vpd1 to the first light amount adjustment circuit 101. The first output terminal 111 is also connected to the LD reference potential section GND2 via a fixed resistor R1. Similarly, the second output terminal 112 is connected to the second light amount adjustment circuit 102 and outputs a detection voltage Vpd2 to the second light amount adjustment circuit 102. The second output terminal 112 is also connected to the LD reference potential section GND2 via a fixed resistor R2.

[0076] When the first laser diode LD1 emits light, a current Ipd' flows from the terminal receiving the drive voltage Vcc1 to the LD reference potential GND2 via the fixed resistor R1 in the current mirror circuit 105, corresponding to the photocurrent Ipd. The current Ipd' flows between the LD reference potential GND2 and the fixed resistor R1, generating a detection voltage Vpd1 (=R1*Ipd'). Therefore, the detection voltage Vpd1 varies depending on the resistance of the fixed resistor R1. The first light-intensity adjustment circuit 101 receives a detection voltage Vpd1 corresponding to the amount of light received by the photodiode PD when the first laser diode LD1 emits light. The first light-intensity adjustment circuit 101 adjusts the light emission intensity of the first laser diode LD1 in accordance with the detection voltage Vpd1. The first light-intensity adjustment circuit 101 of the LD driver 79 for each color is connected to the LD reference potential GND2 via a fixed resistor R1. As shown in FIG. 3, the optical path lengths of the laser beams L for each color are different. Alternatively, the number of lenses through which the laser light L passes and the number of lenses through which it reflects differs depending on the color. Therefore, for example, when manufacturing the printer 10, the resistance value of the fixed resistor R1 can be changed depending on the optical path and the number of lenses for each color. This allows the light intensity of the first laser diode LD1 emitted by the first light intensity adjustment circuit 101 to be adjusted for each color depending on the resistance value of the fixed resistor R1.

[0077] Similarly, when the second laser diode LD2 emits light, a current Ipd" flows in the current mirror circuit 105 from the terminal to which the drive voltage Vcc1 is input to the LD reference potential section GND2 via the fixed resistor R2, and this current corresponds to the photocurrent Ipd. A detection voltage Vpd2 is generated between the LD reference potential section GND2 and the fixed resistor R2 due to the current Ipd" flowing therebetween, and the detection voltage Vpd2 is changed according to the resistance value of the fixed resistor R2. A detection voltage Vpd2 corresponding to the amount of light received by the photodiode PD when the second laser diode LD2 emits light is input to the second light amount adjustment circuit 102.

[0078] The first light amount adjustment circuit 101 is an APC (Automatic Power Control) circuit that adjusts the amount of laser light L emitted by the first laser diode LD1. The first light amount adjustment circuit 101 has a comparator to which a reference voltage Vref1 is input, compares a detection voltage Vpd1 with the reference voltage Vref1, and controls the current that flows so that the voltage value of the detection voltage Vpd1 becomes the reference voltage Vref1. The first light amount adjustment circuit 101 is connected to the anode of the first laser diode LD1 via a first modulation circuit 103.

[0079] During image formation or during adjustment of the light emission amount (described later), a current Ild1 flows from the anode of the first laser diode LD1 through the cathode to the LD reference potential unit GND2. The current Ild1 is adjusted by the first light amount adjustment circuit 101 based on the detection voltage Vpd1, and the light emission amount of the first laser diode LD1 is adjusted. Specifically, the first light amount adjustment circuit 101 operates as follows. If the reference voltage Vref1 is greater than the detection voltage Vpd1, the current Ild1 is increased. When the reference voltage Vref1 is smaller than the detection voltage Vpd1, the current Ild1 is decreased. The first light amount adjustment circuit 101 adjusts the current Ild1 by applying feedback so that the detected voltage Vpd1 and the reference voltage Vref1 always have the same value.

[0080] The second light amount adjustment circuit 102 is connected to the anode of the second laser diode LD2 via the second modulation circuit 104. Similar to the first light amount adjustment circuit 101, the second light amount adjustment circuit 102 compares the reference voltage Vref2 with the detection voltage Vpd2 and adjusts the anode of the second laser diode LD2. 2. Adjust the current Ild2 flowing through

[0081] The first modulation circuit 103 turns on and off the light emission of the first laser diode LD1 by turning on and off the current Ild1 based on the binary video signal VS1 input from the ASIC 72. Similarly, the second modulation circuit 104 turns on and off the light emission of the second laser diode LD2 based on the video signal VS2 of the ASIC 72.

[0082] For example, during printing, the ASIC 72 changes the video signals VS1 and VS2 based on image data and turns on and off the first and second laser diodes LD1 and LD2 to form an electrostatic latent image on the photosensitive drum 41. The printer 10 of this embodiment can simultaneously perform exposure using two laser diodes. Specifically, the first and second laser diodes LD1 and LD2 are, for example, positioned offset from each other. The laser beams L of the first and second laser diodes LD1 and LD2 are reflected by the reflective surfaces of the polygon mirror 92 at positions offset from each other in the rotational axis direction (first direction) of the polygon mirror 92. Therefore, by rotating at high speed, the polygon mirror 92 periodically deflects the laser beams L emitted from the first and second laser diodes LD1 and LD2, thereby simultaneously forming two scanning lines on the surface of the photosensitive drum 41 in a direction perpendicular to the rotational direction of the photosensitive drum 41, i.e., parallel to the main scanning direction. The laser unit 31 may be configured to include only one laser diode, or three or more laser diodes. Therefore, the number of light intensity adjustment circuits, modulation circuits, etc. included in the LD substrate 75 may be changed depending on the number of laser diodes.

[0083] 5, the generating circuit 81 includes a linear regulator 113CK, a first transistor TR1, a second transistor TR2, first resistors R3A and R3B, second resistors R4A and R4B, a first smoothing circuit 115, and a second smoothing circuit 116. The first transistor TR1 and the first and second resistors R3A and R4A are an example of a switching circuit of the present invention. The second transistor TR2 and the first and second resistors R3B and R4B are an example of a switching circuit of the present invention. The main board 71 also includes a DC / DC converter 107. The DC / DC converter 107 outputs, for example, a 5V DC voltage Vcc2 to the linear regulator 113CK of the generating circuit 81 via a harness 73. The DC / DC converter 107 that supplies the 5V DC voltage Vcc2 and the DC / DC converter 106 that supplies the 3.3V DC voltage may be the same circuit. Furthermore, the DC power supply provided on the main board 71 is not limited to a DC / DC converter, but may be another DC power supply such as a linear regulator.

[0084] The first transistor TR1 is a PNP transistor and is connected between the linear regulator 113CK and the second resistor R4A. The first transistor TR1, which is a PNP transistor, is an example of a semiconductor transistor of the present application. Note that the semiconductor transistor of the present application is not limited to a bipolar transistor such as a PNP transistor, and may be a FET (Field-Effect Transistor). The base of the first transistor TR1 is an example of a control terminal of a semiconductor transistor, and is a terminal for controlling the operation of the semiconductor transistor. If the semiconductor transistor is an FET, the control terminal of the semiconductor transistor corresponds to the gate of the FET. The emitter of the first transistor TR1 is an example of an input terminal of a semiconductor transistor, and is a terminal through which a current or voltage is input to the semiconductor transistor. If the semiconductor transistor is a FET, the input terminal of the semiconductor transistor corresponds to the source of the FET. The collector of the first transistor TR1 is an example of an output terminal of a semiconductor transistor, and is a terminal through which a current or voltage is output from the semiconductor transistor. If the semiconductor transistor is an FET, the input terminal of the semiconductor transistor corresponds to the drain of the FET.

[0085] The emitter of the first transistor TR1 is connected to the output terminal of the linear regulator 113CK. The linear regulator 113CK is a low-dropout voltage regulator. A 5V DC voltage Vcc2 is input to the linear regulator 113CK from the DC / DC converter 107. The linear regulator 113CK generates a 3.3V DC voltage from the input DC voltage Vcc2 and outputs the generated DC voltage to the emitter of the first transistor TR1. The linear regulator 113CK is an example of a voltage generation circuit of the present application. Note that the voltage generation circuit is not limited to a linear regulator and may be another DC power supply such as a DC / DC converter.

[0086] The ASIC 72 has a first output terminal 117, which is an open output. In the ASIC 72, the first output terminal 117 is connected to the main reference potential unit GND1 via a first switch SW1. The first output terminal 117 is also connected to the base of a first transistor TR1 on the LD substrate 75 via a harness 73. The base of the first transistor TR1 is also connected to the emitter of the first transistor TR1 via a resistor R5A. When the first switch SW1 of the ASIC 72 is open (off), the first output terminal 117 is electrically disconnected from the main reference potential GND1. No current flows through the resistor R5A from the linear regulator 113CK. Therefore, the same voltage is applied to the emitter and base of the first transistor TR1. A voltage of 3.3V, based on the LD reference potential GND2, is applied to the emitter and base of the first transistor TR1. When the first switch SW1 of the ASIC 72 is closed (on), the first output terminal 117 and the main reference potential section GND1 are electrically connected. A current flows through the resistor R5A from the linear regulator 113CK. As a result, a voltage of 3.3 V based on the LD reference potential section GND2 is applied to the emitter of the first transistor TR1, and the voltage of the main reference potential section GND1 is applied to the base of the first transistor TR1. ASIC72 opens and closes (on and off) the connection between the main reference potential section GND1 and the first output terminal 117 at a predetermined frequency using the first switch SW1, thereby outputting the voltage of the pulse width modulation signal PWM signal PWM1 from the first output terminal 117 (when open, a voltage of 3.3V based on the LD reference potential section GND2, and when closed, the voltage of the main reference potential section GND1). The voltage of the PWM signal PWM1 is input to the base of the first transistor TR1 from the first output terminal 117 by turning on and off the first switch SW1.

[0087] A second resistor R4A is connected to the collector of the first transistor TR1. One end of the second resistor R4A is connected to the collector, and the other end is connected to the LD reference potential part GND2 via the first resistor R3A. A connection part 121 to which the first and second resistors R3A and R4A are connected is connected to the input terminal of a first smoothing circuit 115. The first smoothing circuit 115 receives the voltage at the connection part 121 as an input voltage Vin1. The first smoothing circuit 115 smoothes the input voltage Vin1 and outputs the smoothed voltage to the first light amount adjustment circuit 101 as a reference voltage Vref1.

[0088] The ASIC 72 changes the reference voltage Vref1 by opening (off) and closing (on) the first switch SW1 at a predetermined frequency.

[0089] <Characteristic configuration of the first embodiment> FIG. 6 is a diagram for explaining the input voltage Vin1 output to the first smoothing circuit 115 by a circuit (switching circuit) made up of the first transistor TR1 and the first and second resistors R3A and R4A in the first embodiment. As shown in the top diagram of Figure 6, ASIC72 turns on the first switch SW1, and the main reference When the connection between the potential part GND1 and the first output terminal 117 is made to a connected state, a current flows from the linear regulator 113CK through the emitter of the first transistor TR1 to the main reference potential part GND1 of the ASIC 72. This allows a current to flow from the emitter to the collector of the first transistor TR1, and the first transistor TR1 is turned on. As described above, the emitter of the first transistor TR1 is supplied with a voltage of 3.3V based on the LD reference potential section GND2 of the LD substrate 75, and the base of the first transistor TR1 is supplied with the voltage of the main reference potential section GND1. When the first transistor TR1 is on, a current flows between the emitter and collector of the first transistor TR1, and also through the first and second resistors R3A and R4A. Because the voltage drop across the first transistor TR1 is minimal, a voltage of 3.3 V relative to the LD reference potential GND2 is essentially applied to the collector of the first transistor TR1. Therefore, the voltage (input voltage Vin1) at the connection part 121, which is based on the reference potential of the LD reference potential part GND2 of the LD substrate 75, is the on-voltage (=3.3V*R3A / (R3A+R4A)) obtained by dividing the voltage applied to the emitter (collector) of the first transistor TR1 by the first and second resistors R3A and R4A. The input voltage Vin1 is determined by the voltage generated by the linear regulator 113CK and the resistance values ​​of the first and second resistors R3A and R4A. The first smoothing circuit 115 receives the input voltage Vin1 based on the reference potential of the LD reference potential part GND2.

[0090] On the other hand, as shown in the lower diagram of Figure 6, when the ASIC 72 opens (turns off) the first switch SW1 and disconnects the main reference potential unit GND1 from the first output terminal 117, no current flows from the linear regulator 113CK to the main reference potential unit GND1 via the emitter of the first transistor TR1. No current flows from the emitter to the collector of the first transistor TR1. The first transistor TR1 is turned off. As described above, the emitter of the first transistor TR1 is supplied with a voltage of 3.3 V based on the LD reference potential portion GND2 of the LD substrate 75, and the base of the first transistor TR1 is supplied with a voltage of 3.3 V based on the LD reference potential portion GND2 of the LD substrate 75. Furthermore, since the first transistor TR1 is in the OFF state, no current flows between the emitter and collector of the first transistor TR1, and no current flows through the first and second resistors R3A and R4A. Therefore, the voltage (input voltage Vin1) at the connection part 121, which is based on the reference potential of the LD reference potential part GND2, becomes the voltage of the reference potential of the LD reference potential part GND2 itself. The voltage of the reference potential of the LD reference potential part GND2 itself becomes the off voltage. This off voltage is input to the first smoothing circuit 115.

[0091] A circuit (switching circuit) consisting of the first transistor TR1 and the first and second resistors R3A and R4A alternately switches between an on-voltage (=3.3V*R3A / (R3A+R4A)) based on the reference potential of the LD reference potential section GND2 and an off-voltage, which is the reference potential of the LD reference potential section GND2, and outputs the voltage to the first smoothing circuit 115. The generation circuit 81 smoothes the input voltage Vin1, which fluctuates (is turned on and off) according to the duty ratio of the PWM signal PWM1, in the first smoothing circuit 115 to generate a reference voltage Vref1, and outputs the generated reference voltage Vref1 to the first light amount adjustment circuit 101. As a result, the ASIC 72 can change the duty ratio of the PWM signal PWM1 to change the voltage value of the reference voltage Vref1 output by the generation circuit 81, thereby controlling the light emission amount of the first laser diode LD1.

[0092] <Configuration of Comparative Example> 7 shows an enlarged view of a portion of a generation circuit 131 of a comparative example that differs from the first embodiment. As shown in Fig. 7, the generation circuit 131 of the comparative example does not include a first transistor TR1 on the high-potential side of the second resistor R4A, and the first output terminal 117 of the ASIC 72 is connected to a connection part 121 that is a junction of the first and second resistors R3A and R4A. 7, when the ASIC 72 closes (turns on) the first switch SW1, a current flows from the linear regulator 113CK to the main reference potential section GND1 via the second resistor R4A. The input voltage Vin1 of the connection section 121 becomes the voltage of the reference potential of the main reference potential section GND1 itself.

[0093] On the other hand, as shown in the lower diagram of Figure 7, when the ASIC 72 opens (turns off) the first switch SW1, no current flows from the linear regulator 113CK to the main reference potential section GND1 via the second resistor R4A. The 3.3V voltage applied by the linear regulator 113CK is divided by the first and second resistors R3A and R4A to form the input voltage Vin1 (=3.3V*R3A / (R3A+R4A)). The input voltage Vin1 (=3.3V*R3A / (R3A+R4A)) is a voltage relative to the reference potential of the LD reference potential section GND2.

[0094] <Comparison of input voltage between the first embodiment and the comparative example> The upper diagram in Figure 8 shows the input voltage Vin1 input to the first smoothing circuit 115 in the first embodiment and the reference voltage Vref1 output by the first smoothing circuit 115, and the lower diagram in Figure 8 shows the input voltage Vin1 input to the first smoothing circuit 115 in the comparative example and the reference voltage Vref1 output by the first smoothing circuit 115.

[0095] The LD reference potential section GND2 is connected to the main reference potential section GND1 of the main substrate 71 via a ground line 109 included in the harness 73. When the physical distance between the main substrate 71 and the LD substrate 75 increases and the length of the harness 73, i.e., the length of the ground line 109, increases, the resistance value of the ground line 109 increases. As a result, a potential difference occurs between the reference potential of the main reference potential section GND1 and the reference potential of the LD reference potential section GND2, and so-called GND floating may occur.

[0096] The lower diagram in Fig. 8 shows the input voltage Vin1 in the comparative example shown in Fig. 7. When the ASIC 72 closes (turns on) the first switch SW1, the input voltage Vin1, when viewed with respect to the reference potential of the LD reference potential section GND2, becomes a voltage based on a potential that is lowered by the amount of power loss caused by the resistance of the ground line 109. For example, if the voltage based on the reference potential of the LD reference potential section GND2 is set to 0 V, the input voltage Vin1 will drop by, for example, about -30 mV.

[0097] On the other hand, as shown in the lower diagram of Figure 8, when ASIC72 opens (turns off) the first switch SW1, the input voltage Vin1 becomes a voltage (=3.3V*R3A / (R3A+R4A)) based on the reference potential of the LD reference potential section GND2. Therefore, as shown in the lower diagram of Figure 7, if GND floating occurs, when ASIC72 closes (turns on) the first switch SW1, the input voltage Vin1 will drop by -30mV from the voltage based on the reference potential of the LD reference potential section GND2. As a result, in the comparative example shown in the lower diagram of FIG. 8, the smoothed reference voltage Vref1 becomes lower than the reference voltage Vref1 shown by the dotted line when no GND floating occurs.

[0098] As shown in the upper diagram of FIG. 8, the generation circuit 81 of the first embodiment can output the input voltage Vin1 based on the reference potential of the LD reference potential section GND2 when the first switch SW1 is on or off (on voltage or off voltage). In other words, in this embodiment, the GND can be matched with the reference potential of the LD reference potential section GND2 without deviation at both the off voltage and the on voltage. This makes it possible to output the desired input voltage Vin1 as intended to the first smoothing circuit 115. The same applies to the reference voltage Vref2.

[0099] Also, the second transistor TR2, the first resistor R3B, the second resistor R4B, and the second smoothing circuit The second transistor TR2 has a similar configuration to the first transistor TR1, first resistor R3A, second resistor R4A, and first smoothing circuit 115, and therefore a detailed description thereof will be omitted. The base of the second transistor TR2 is connected to a first output terminal 118 of the ASIC 72 via a harness 73. The base of the first transistor TR1 is connected to the emitter of the first transistor TR1 via a resistor R5B. The first output terminal 118 is connected to the main reference potential GND1 via a second switch SW2. The collector of the second transistor TR2 is connected to the LD reference potential GND2 via a first resistor R3B and a second resistor R4B. ASIC72 opens and closes (on and off) the connection between the main reference potential section GND1 and the first output terminal 118 at a predetermined frequency using the second switch SW2, thereby outputting the voltage of the pulse width modulation signal PWM signal PWM2 from the first output terminal 118 (when open, a voltage of 3.3V based on the LD reference potential section GND2, and when closed, the voltage of the main reference potential section GND1).

[0100] As described above, the second transistor TR2 and the first and second resistors R3B, R4B are an example of a switching circuit. The circuit (switching circuit) consisting of the second transistor TR2 and the first and second resistors R3B, R4B outputs an input voltage Vin2 having a predetermined duty ratio from the connection part 122 to the second smoothing circuit 116. The second smoothing circuit 116 smoothes the input voltage Vin2 and outputs the reference voltage Vref2, which is the smoothed input voltage Vin2, to the second light amount adjustment circuit 102. As a result, the ASIC 72 changes the PWM signal PWM2 to change the reference voltage Vref2 output by the generation circuit 81, thereby controlling the light emission amount of the second laser diode LD2.

[0101] The linear regulator 113CK is shared not only by the black generator circuit 81K but also by the cyan generator circuit 81C. Therefore, the emitters of the first transistor TR1 and the second transistor TR2 of the generator circuit 81C are connected to the linear regulator 113CK, and a DC voltage of 3.3V is supplied. The LD substrate 75 also includes a linear regulator 113YM for yellow and magenta (see FIG. 4). The linear regulator 113YM supplies a DC voltage of 3.3V to the emitters of the first transistor TR1 and the second transistor TR2 of the generator circuit 81Y and the generator circuit 81C. The above-described configuration is merely an example. For example, the main substrate 71 may include a linear regulator 113 for each of the four generator circuits 81.

[0102] (Regarding light intensity adjustment) To keep the light intensity of the beam LB emitted from the semiconductor laser 77 to the photosensitive drum 41 via the polygon mirror 92 within a predetermined range, the light intensity of the first and second laser diodes LD1 and LD2 must be adjusted. When adjusting the light intensity, either the first laser diode LD1 or the second laser diode LD2 selectively emits light. The photodiode PD receives the back laser light from the first laser diode LD1 or the second laser diode LD2, causing a photocurrent Ipd to flow. As described above, the fixed resistors R1 and R2 connected to each LD driver 79 are adjusted according to the optical path length of the laser light L for each color. By adjusting the resistance values ​​of the fixed resistors R1 and R2 and adjusting the detection voltages Vpd1 and Vpd2, the light intensity can be adjusted for each color and laser diode. The fixed resistors R1 and R2 for each color may all have the same resistance value.

[0103] Furthermore, the printer 10 of this embodiment can also adjust the light emission amount by the PWM signals PWM1 and PWM2 output from the ASIC 72. For example, when the printer 10 is shipped from the factory, an operator can adjust the light emission amount of the beam LB that is actually irradiated onto the photosensitive drum 41 while observing the light emission amount of the beam LB, thereby adjusting the duty ratio of the PWM signal PWM1 to a predetermined light emission amount of the laser light L. After being shipped from the factory, the printer 10 is controlled by the PWM signal PWM1 with the duty ratio adjusted by the operator, and the first light amount adjustment circuit 101 adjusts the light emission amount of the laser light L. The PWM signal PWM2 is adjusted so that the light emission amount of the first laser diode LD1 is constant. For example, by increasing the duty ratio of the PWM signal PWM1 and increasing the input voltage Vin1, the reference voltage Vref1 can be increased. As a result, the current Ild1 can be increased and the light emission amount of the first laser diode LD1 can be increased. Conversely, by decreasing the duty ratio of the PWM signal PWM1 and decreasing the input voltage Vin1, the reference voltage Vref1 can be decreased. As a result, the light emission amount of the first laser diode LD1 can be decreased. The PWM signal PWM2 can also be adjusted in the same way as the PWM signal PWM1.

[0104] Furthermore, for example, if a variable resistor is connected between the first output terminal 111 and the LD reference potential section GND2, the detection voltage Vpd1 can be adjusted by changing the resistance value of the variable resistor, even after the printer 10 is manufactured. In other words, the light emission intensity of the first laser diode LD1 can be adjusted. However, a variable resistor is required for each light intensity adjustment circuit and each color, which may increase the number of components and manufacturing costs. In contrast, the printer 10 of this embodiment has a fixed resistor R1 between the first output terminal 111 and the LD reference potential section GND2, and no variable resistor is provided. By adjusting the PWM signal PWM1, the light emission intensity of the first laser diode LD1 can be adjusted even after the printer 10 is manufactured.

[0105] On the other hand, when adjusting the reference voltage Vref1 using the PWM signal PWM1, the input voltage Vin1 must be adjustable to match the range over which the light emission power of the first laser diode LD1 is adjusted. In other words, the adjustable range of the input voltage Vin1 must be widened. Suppose, for example, that the reference voltage Vref1 is adjusted between 1.5V and 0.3V. In this case, the smaller the reference voltage Vref1 is adjusted, i.e., the smaller the input voltage Vin1 is adjusted, the greater the impact of the potential difference deviation (e.g., -30mV) due to the GND floating described above. For example, when adjusting the reference voltage Vref1 to 0.3V, if a deviation of approximately -30mV due to the GND floating occurs, a deviation of approximately -10% from the target value occurs. In contrast, the generation circuit 81 of this embodiment suppresses the occurrence of GND floating by aligning the reference potentials of both the ON voltage and the OFF voltage with the reference potential of the main reference potential section GND1, as described above. This reduces the influence of GND floating even when the duty ratio of the PWM signal PWM1 is lowered and the input voltage Vin1 is reduced, allowing the reference voltage Vref1, i.e., the light emission amount of the first laser diode LD1, to be adjusted accurately.

[0106] As described above, the first embodiment provides the following effects. (1) The generation circuit 81 of this embodiment generates a predetermined voltage (e.g., 3.3 V) based on the reference potential of the LD reference potential section GND2, and, in accordance with the PWM signal PWM1, alternately switches between an ON voltage based on the predetermined voltage based on the reference potential of the LD reference potential section GND2 and an OFF voltage which is the reference potential of the LD reference potential section GND2, and outputs this to the first smoothing circuit 115. The first smoothing circuit 115 generates a reference voltage Vref1 by smoothing the ON voltage and OFF voltage, and outputs the reference voltage Vref1 to the LD driver 79.

[0107] As a result, the LD substrate 75 has a generation circuit 81 (including a first resistor R3A, a second resistor R4A, a first transistor TR1, etc.) that alternately switches and outputs an on-voltage or an off-voltage in response to the PWM signal PWM1. The generation circuit 81 outputs an input voltage Vin1, in which both the on-voltage and the off-voltage are based on the reference potential of the LD reference potential section GND2, to the first smoothing circuit 115. Therefore, the reference voltage Vref1 is input to the LD driver 79 without deviation from the reference voltage Vref1 intended by the ASIC 72, and the LD driver 79 can appropriately adjust the light intensity.

[0108] (2) The ASIC 72 also has an open collector function that outputs a PWM signal PWM1 from the first output terminal 117 by turning on and off the first switch SW1. The emitter of the transistor TR1 is connected to the linear regulator 113CK, the base is connected to the first output terminal 117 via the harness 73, and the collector is connected to the LD reference potential section GND2 via the first resistor R3A. A connection section 121 between the collector of the first transistor TR1 and the first resistor R3A is connected to the first smoothing circuit 115. The voltage at the connection section 121, which is based on the reference potential of the LD reference potential section GND2, is output to the first smoothing circuit 115 as the input voltage Vin1.

[0109] According to this, when the ASIC 72 turns on the connection between the main reference potential section GND1 and the first output terminal 117 (upper diagram in FIG. 6 ), a current flows from the linear regulator 113CK to the emitter of the first transistor TR1 toward the main reference potential section GND1. The input voltage Vin1 of the connection section 121, which is based on the reference potential of the LD reference potential section GND2, is determined by the DC voltage of 3.3 V generated by the linear regulator 113CK and the magnitude of the first resistor R3A. The generation circuit 81 can output an ON voltage to the first smoothing circuit 115. When the ASIC 72 disconnects the main reference potential section GND1 from the first output terminal 117, no current flows from the linear regulator 113CK to the main reference potential section GND1 via the emitter of the first transistor TR1. The input voltage Vin1 of the connection section 121, which is based on the reference potential of the LD reference potential section GND2, becomes an off-voltage, which is the reference potential of the LD reference potential section GND2. The generation circuit 81 can output the off-voltage to the first smoothing circuit 115.

[0110] (3) The second resistor R4A is connected between the collector of the first transistor TR1 and the connection point 121. The first resistor R3A is connected between the connection point 121 and the LD reference potential point GND2.

[0111] According to this, the input voltage Vin1 is a voltage obtained by dividing the 3.3V DC voltage generated by the linear regulator 113CK by the first resistor R3A and the second resistor R4A. The upper limit of the reference voltage Vref1 can be determined by the first and second resistors R3A and R4A.

[0112] (4) Furthermore, the linear regulator 113 converts the 5V DC voltage Vcc2 input from the DC / DC converter 107 on the main board 71 via the harness 73 to generate a 3.3V DC voltage.

[0113] This allows linear regulator 113 to operate based on the reference potential of LD reference potential section GND2, and to convert the 5V DC voltage input from DC / DC converter 107 via harness 73 to generate a 3.3V DC voltage. Even if harness 73 becomes longer and a voltage difference occurs between the reference potential of linear regulator 113 and the reference potential of main board 71, the voltage difference between the input and output of linear regulator 113 is prevented from deviating from the desired dropout voltage, allowing the transistors in linear regulator 113 to operate stably. The output voltage of linear regulator 113 can be set to the target 3.3V.

[0114] (5) Each of the four semiconductor lasers 77 has first and second laser diodes LD1 and LD2. The LD substrate 75 has a first transistor TR1, a first smoothing circuit 115, and a first light amount adjustment circuit 101 corresponding to the first laser diode LD1, and a second transistor TR2, a second smoothing circuit 116, and a second light amount adjustment circuit 102 corresponding to the second laser diode LD2.

[0115] This allows simultaneous exposure using the first and second laser diodes LD1 and LD2. Also, it is possible to prevent the reference voltages Vref1 and Vref2 generated by the first and second transistors TR1 and TR2 and the first and second smoothing circuits 115 and 116 corresponding to the first and second laser diodes LD1 and LD2 from deviating from the reference voltage intended by the ASIC 72. In the first and second laser diodes LD1 and LD2, The light amount can be appropriately adjusted by the D driver 79.

[0116] (6) The first light amount adjustment circuit 101 adjusts a detection voltage Vpd1, which indicates the amount of light emitted by the first laser diode LD1 of the semiconductor laser 77, to a reference voltage Vref1 (an example of the reference value of the present application). The first light amount adjustment circuit 101 is connected to the LD reference potential unit GND2 via a fixed resistor R1.

[0117] This allows the voltage value of the detection voltage Vpd1 to be changed by changing the resistance value of the fixed resistor R1, and the light emission amount of the first laser diode LD1 can be adjusted by the resistance value of the fixed resistor R1. Furthermore, after manufacturing the printer 10, the reference voltage Vref1 can be changed by changing the duty ratio of the PWM signal PWM1 output by the ASIC 72. This eliminates the need to change the resistance value after manufacturing.

[0118] (7) Furthermore, the semiconductor lasers 77, LD drivers 79, and photosensitive drums 41 are arranged corresponding to the respective colors of Y, M, C, and K. Of the fixed resistors R1 connected to the first light amount adjustment circuits 101 corresponding to the respective colors, the resistance value of the fixed resistor R1 arranged corresponding to at least one color may be set to a value different from the resistance values ​​of the fixed resistors R1 arranged corresponding to the other colors.

[0119] This allows the light emission intensity of the first laser diode LD1 to be adjusted for each color by changing the resistance value of the fixed resistor R1 connected to the first light intensity adjustment circuit 101 arranged corresponding to each color.

[0120] (8) Furthermore, the resistance value of the fixed resistor R1 connected to the first light amount adjustment circuit 101 arranged corresponding to each of the multiple colors may be set to a value corresponding to the optical characteristics of the optical path from the semiconductor laser 77 for each of the YMCK colors to the photosensitive drum 41. This allows the resistance value of the fixed resistor R1 for each color to be set to a value corresponding to the distance of the optical path, the number of lenses, etc. This makes it possible to adjust the light emission amount of the first laser diode LD1 according to the distance of the optical path of the laser light L for each color, etc.

[0121] (9) The LD substrate 75 is formed in a plate shape that is long along the second direction (see FIG. 4). The four semiconductor lasers 77Y, 77M, 77C, and 77K are disposed in the center of the LD substrate 75 in the second direction. The LD driver 79K is disposed on the opposite side of the LD drivers 79Y, 79M, and 79C in the second direction, with the four semiconductor lasers 77 sandwiched therebetween. The linear regulator 113CK is disposed on the opposite side of the linear regulator 113YM in the second direction, with the four semiconductor lasers 77 and four LD drivers 79 sandwiched therebetween.

[0122] According to this, the linear regulators 113CK corresponding to black and cyan are arranged on the opposite side of the linear regulators 113YM corresponding to yellow and magenta in the longitudinal direction of the LD substrate 75, with the four semiconductor lasers 77 and four LD drivers 79 sandwiched between them. This allows the two linear regulators 113CK and 113YM to be arranged at positions away from the semiconductor lasers 77, with the LD driver 79 sandwiched between them. Furthermore, the two linear regulators 113CK and 113YM that generate heat can also be arranged at positions away from each other. This reduces the effect of heat from the linear regulators 113CK and 113YM on the semiconductor lasers 77, improving the accuracy of image formation.

[0123] (Second embodiment) Next, a second embodiment of the present invention will be described. In the generating circuit 81 of the first embodiment described above, a circuit having a PNP transistor is used as the semiconductor transistor of the present invention. In contrast, the generating circuit 181 provided in the printer of the second embodiment differs from the generating circuit 81 of the first embodiment in that it includes a circuit having an NPN transistor as a semiconductor transistor. Figure 9 is a diagram corresponding to Figure 6 of the first embodiment, and shows a part of the generating circuit 181 according to the second embodiment. In the following explanation, the same components as those in the first embodiment are given the same reference numerals, and their explanation will be omitted as appropriate.

[0124] As shown in FIG. 9 , the generating circuit 181 includes a third resistor R6A, a fourth resistor R7A, and a first transistor TR3 in addition to the linear regulator 113CK and the first smoothing circuit 115. One end of the fourth resistor R7A is connected to the output terminal of the linear regulator 113CK, and the other end is connected to a connection 183. One end of the third resistor R6A is connected to the connection 183, and the other end is connected to the LD reference potential GND2. The first transistor TR3 is an NPN transistor, and the fourth resistor R7A (connection 183) is connected to its collector. The emitter of the first transistor TR3 is connected to the LD reference potential GND2. Therefore, the first transistor TR3 and the third resistor R6A are connected in parallel between the fourth resistor R7A and the LD reference potential GND2. The collector of the first transistor TR3 is an example of an input terminal of the semiconductor transistor of the present application, and is a terminal through which a current or voltage is input to the semiconductor transistor. The emitter of the first transistor TR3 is an example of an output terminal of a semiconductor transistor, and is a terminal through which a current or voltage is output from the semiconductor transistor. The base of the first transistor TR3 is an example of a control terminal of a semiconductor transistor, and is a terminal for controlling the operation of the semiconductor transistor of the present application.

[0125] The ASIC 72 has a first switch SW1, a third switch SW3, an internal voltage unit 180, and a second output terminal 182. The base of the first transistor TR3 is connected to the second output terminal 182 via the harness 73. The internal voltage unit 180 is a terminal that supplies a DC voltage of, for example, 3.3 V, and is connected to a connection unit 185 via the third switch SW3. The connection unit 185 is connected to the second output terminal 182. The connection unit 185 is also connected to the main reference potential unit GND1 via the first switch SW1.

[0126] The second output terminal 182 is a push-pull output. The ASIC 72 switches between either a first connection (lower diagram in FIG. 9 ) in which the third switch SW3 is turned off to disconnect the internal voltage unit 180 from the second output terminal 182 and the first switch SW1 is turned on to connect the main reference potential unit GND1 to the second output terminal 182, or a second connection (upper diagram in FIG. 9 ) in which the third switch SW3 is turned on to connect the internal voltage unit 180 to the second output terminal 182 and the first switch SW1 is turned off to disconnect the main reference potential unit GND1 from the second output terminal 182. The ASIC 72 switches between the first and second connections by opening and closing (on / off) the first switch SW1 and the third switch SW3 at a predetermined frequency, thereby outputting the voltage of the PWM signal PWM1, which is a pulse-width modulation signal, from the second output terminal 182. The voltage of the PWM signal 1 is input to the base of the second transistor TR2 from the second output terminal 182 by turning on and off the first switch SW1 and the third switch SW3.

[0127] Furthermore, a connection point 183 where the fourth resistor R7A and the collector of the first transistor TR3 are connected is connected to the first smoothing circuit 115. The first smoothing circuit 115 receives the voltage at the connection point 183 as an input voltage Vin1, smooths it, and outputs it to the first light amount adjustment circuit 101 as a reference voltage Vref1.

[0128] When the ASIC 72 is in the second connection shown in the upper diagram of FIG. 9 (when the third switch SW3 is on and the first switch SW1 is off), a current flows from the internal voltage unit 180 to the LD reference potential unit GND2 via the second output terminal 182 and between the base and emitter of the first transistor TR3. The current flows from the collector of the first transistor TR3 to the emitter. A current flows from the linear regulator 113CK to the LD reference potential part GND2 via the collector-emitter of the first transistor TR3. No current flows through the third resistor R6A connected in parallel to the first transistor TR3. Because the voltage drop caused by the first transistor TR3 is minute, the voltage (input voltage Vin1) at the connection point 183, which is essentially based on the reference potential of the LD reference potential section GND2, is the voltage of the reference potential of the LD reference potential section GND2 itself. The voltage of the reference potential of the LD reference potential section GND2 itself is the off-voltage. This off-voltage is input to the first smoothing circuit 115.

[0129] On the other hand, when the ASIC 72 is in the first connection shown in the lower diagram of Figure 9 (when the third switch SW3 is off and the first switch SW1 is on), no current flows from the internal voltage unit 180 to the LD reference potential unit GND2 via the second output terminal 182 and between the base and emitter of the first transistor TR3. No current flows from the collector to the emitter of the first transistor TR3. The first transistor TR3 is in the off state. A current flows from the linear regulator 113CK to the LD reference potential section GND2 via the fourth resistor R7A and the third resistor R6A. The voltage (input voltage Vin1) at the connection section 183, which is based on the reference potential of the LD reference potential section GND2 of the LD substrate 75, is the on-voltage (=3.3V*R6A / (R7A+R6A)) obtained by dividing the output voltage of the linear regulator 113CK by the fourth resistor R7A and the third resistor R6A. The input voltage Vin1 is determined by the voltage generated by the linear regulator 113CK and the magnitude of the resistance values ​​of the fourth resistor R7A and the third resistor R6A. A circuit (switching circuit) consisting of the first transistor TR3, the fourth resistor R7A, and the third resistor R6A alternately switches between an on voltage (=3.3V*R6A / (R7A+R6A)) based on the reference potential of the LD reference potential section GND2, or an off voltage which is the reference potential of the LD reference potential section GND2, and outputs this to the first smoothing circuit 115.

[0130] Therefore, even when the NPN-type first transistor TR3 of the second embodiment is used, the on-voltage of the first connection and the off-voltage of the second connection are both voltages (input voltage Vin1) based on the reference potential of the LD reference potential section GND2, which prevents GND floating and allows the reference voltage Vref1 to be output with high accuracy.

[0131] As described above, the second embodiment provides the same effects as the first embodiment. Furthermore, the second embodiment provides the following effects. (1) The ASIC 72 of the second embodiment outputs a PWM signal PWM1 from the second output terminal 182 by switching between the first connection and the second connection using the first switch SW1 and the third switch SW3. The first transistor TR3 and the third resistor R6A are connected in parallel between the fourth resistor R7A and the LD reference potential unit GND2. The generation circuit 181 outputs an input voltage Vin1 (on voltage, off voltage) of the connection unit 183, which is based on the reference potential of the LD reference potential unit GND2, to the first smoothing circuit 115.

[0132] This makes it possible to output the input voltage Vin1, which is based on the reference potential of the LD reference potential section GND2, from the connection section 183 to the first smoothing circuit 115, regardless of whether the on voltage is the first connection or the off voltage is the second connection.

[0133] (2) Furthermore, the fourth resistor R7A is connected between the linear regulator 113CK and the collector of the first transistor TR3. According to this, the input voltage Vin1 of the connection point 183 output by the generation circuit 181 is a voltage obtained by dividing the 3.3 V DC voltage output by the linear regulator 113CK by the third resistor R6A and the fourth resistor R7A. The upper limit of the reference voltage Vref1 can be determined by the third resistor R6A and the fourth resistor R7A.

[0134] The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Various modifications are possible. For example, the circuit configurations of the above-described embodiments are merely examples. For example, the generating circuit 81 of the first embodiment may be configured without the second resistors R4A and R4B. Furthermore, the semiconductor laser 77 is configured to include two light-emitting elements, the first laser diode LD1 and the second laser diode LD2, but is not limited to this. The semiconductor laser 77 may be configured to include only one light-emitting element, or three or more light-emitting elements. Furthermore, a variable resistor may be connected between the first output terminal 111 of the current mirror circuit 105 and the LD reference potential section GND2, or between the second output terminal 112 and the LD reference potential section GND2. This allows the light emission amounts of the first and second laser diodes LD1 and LD2 to be adjusted by changing the resistance value of the variable resistor. Furthermore, the linear regulator 113CK of the generation circuit 81K is shared with the generation circuit 81C, but may be shared with the generation circuits 81Y and 81M of other colors (yellow (Y) and magenta (M)). 4 is an example. For example, the semiconductor laser 77 may be disposed at an end of the LD substrate 75 in the second direction, and the linear regulators 113CK and 113YM may be disposed at the center of the LD substrate 75.

[0135] Furthermore, in the above-described embodiments, a color laser printer capable of color printing is employed as the image forming apparatus of the present application, but this is not limited thereto. The image forming apparatus of the present application may also be a monochrome laser printer. Therefore, the image forming apparatus of the present application may be configured to include only one set of an LD driver and a semiconductor laser. Furthermore, the laser unit of the present application is not limited to a device used for printing, but may also be a device used for scanning, such as a laser scanner. Therefore, the image forming apparatus of the present application is not limited to a printer, but may also be a scanner or a fax machine. Furthermore, the image forming apparatus of the present application may also be a multifunction device equipped with multiple functions, such as a printing function, a copying function, a fax function, and a scanning function. Therefore, the configuration of the laser unit is appropriately changed depending on the functions of the image forming apparatus. [Explanation of symbols]

[0136] 10 color laser printer (image forming apparatus), 31 laser unit, 41 photosensitive drum, 71 main board, 72 ASIC (controller), 73 harness, 75 LD board, 77 semiconductor laser, 77M, 77C, 77Y semiconductor laser (second semiconductor laser), 77K semiconductor laser (first semiconductor laser), 79 LD driver, 79M, 79C, 79Y LD driver (second LD driver), 79K LD driver (first LD driver), 81, 181 generation circuit, 92 polygon mirror, 101 first light amount adjustment circuit (light amount adjustment circuit), 102 second light amount adjustment circuit (light amount adjustment circuit), 107 DC / DC converter, 113 linear regulator (voltage generation circuit), 113CK linear regulator (voltage generation circuit, first voltage generation circuit), 113YM linear regulator (voltage generation circuit, second voltage generation circuit), 115 First smoothing circuit (smoothing circuit), 116 Second smoothing circuit (smoothing circuit), 117, 118 First output terminal, GND1 Main reference potential section, 121, 122, 185 Connection section, 180 Internal voltage section, 182 Second output terminal, GND2 LD reference potential section, LD1 First laser diode (light-emitting element), LD2 Second laser diode (light-emitting element), PWM1, PWM1K, PWM1M, PWM1C, PWM1Y, PWM2, PWM2K, PWM2M, PWM2C, PWM2Y, PWM signal (pulse width modulation signal), R1 Fixed resistor, R2 Fixed resistor, R3A, R3B First resistor (switching circuit), R4A, R4B Second resistor (switching circuit), R6A Third resistor (switching circuit), R7A Fourth resistor (switching circuit), TR1 First transistor (switching circuit, semiconductor transistor), TR2 Second transistor (switching circuit, semiconductor transistor), TR3 First transistor (switching circuit, semiconductor transistor), Vin1 Input voltage (voltage), Vin2 Input voltage (voltage), Vpd1, Vpd2 Detection voltage (detection value), Vref1, Vref2 Reference voltage (reference value).

Claims

1. a laser unit including a semiconductor laser, a polygon mirror that deflects light from the semiconductor laser, an LD driver that controls the amount of light emitted from the semiconductor laser based on a reference voltage, and an LD substrate on which the LD driver is mounted and which has an LD reference potential section that serves as a reference potential for the LD driver; a photosensitive drum exposed to light deflected by the polygon mirror; a controller that controls the laser unit and outputs a pulse width modulation signal to the LD substrate to indicate the reference voltage to the LD driver; a main board on which the controller is mounted and which has a main reference potential section that serves as a reference potential for the controller, the main reference potential section and the LD reference potential section being electrically connected via a harness; Equipped with The LD substrate is a voltage generating circuit that generates a predetermined voltage based on a reference potential of the LD driver; a switching circuit that alternately switches between an ON voltage based on the predetermined voltage with respect to a reference potential of the LD driver and an OFF voltage that is the reference potential of the LD driver in response to the pulse width modulation signal, and outputs the ON voltage; a smoothing circuit that generates the reference voltage by smoothing the on-voltage and the off-voltage output by the switching circuit and outputs the reference voltage to the LD driver; An image forming apparatus having the same.

2. The controller a first output terminal, and outputting the pulse width modulation signal from the first output terminal by turning on and off a connection between the main reference potential unit and the first output terminal; The switching circuit a semiconductor transistor and a first resistor, an input terminal of the semiconductor transistor connected to the voltage generating circuit, a control terminal of the semiconductor transistor connected to the first output terminal via the harness, an output terminal of the semiconductor transistor connected to the LD reference potential section via the first resistor, and a connection section between the output terminal of the semiconductor transistor and the first resistor connected to the smoothing circuit; a voltage of the connection part based on a reference potential of the LD reference potential part is output to the smoothing circuit; The image forming apparatus according to claim 1 .

3. The switching circuit Further, a second resistor is included, the second resistor is connected between the output terminal of the semiconductor transistor and the connection part; the first resistor is connected between the connection portion and the LD reference potential portion; The image forming apparatus according to claim 2 .

4. The controller an internal voltage unit and a second output terminal; outputting the pulse width modulated signal from the second output terminal by switching to either a first connection that disconnects the internal voltage unit from the second output terminal and connects the main reference potential unit to the second output terminal, or a second connection that connects the internal voltage unit to the second output terminal and disconnects the main reference potential unit from the second output terminal; The switching circuit a third resistor having one end connected to the LD reference potential portion and a semiconductor transistor connected in parallel with the third resistor, and an output terminal of the semiconductor transistor is connected to the voltage generating circuit; a control terminal of the semiconductor transistor is connected to the second output terminal via the harness, and an input terminal of the semiconductor transistor is connected to the LD reference potential section; a connection part where the output terminal of the semiconductor transistor and the other end of the third resistor are connected in parallel is connected to the smoothing circuit; a voltage of the connection part based on a reference potential of the LD reference potential part is output to the smoothing circuit; The image forming apparatus according to claim 1 .

5. The switching circuit Further, a fourth resistor is included, the fourth resistor is connected between the voltage generating circuit and the output terminal of the semiconductor transistor; The image forming apparatus according to claim 4 .

6. The main board is A DC / DC converter is included. The voltage generating circuit a low-dropout voltage regulator that generates the predetermined voltage by converting a DC voltage input from the DC / DC converter of the main board via the harness; The image forming apparatus according to claim 1 .

7. The semiconductor laser is It has two light-emitting elements, The LD driver is two light amount adjustment circuits connected to the two light emitting elements, respectively, for controlling the light amount of each of the two light emitting elements; The switching circuit and the smoothing circuit are provided for each of the two light amount adjustment circuits, The image forming apparatus according to claim 1 .

8. The LD driver is a light amount adjustment circuit that adjusts a detection value indicating the amount of light emitted by the light emitting element of the semiconductor laser to a reference value; The light amount adjustment circuit connected to the LD reference potential unit via a fixed resistor; The image forming apparatus according to claim 1 .

9. The semiconductor laser, the LD driver, and the photosensitive drum are are arranged corresponding to each of the multiple colors that form the image, Among the fixed resistors connected to the light amount adjustment circuit of the LD driver arranged corresponding to a plurality of colors, the resistance value of the fixed resistor arranged corresponding to at least one color is:

9. The image forming apparatus according to claim 8, wherein the resistance value of the fixed resistors arranged corresponding to the other colors is different from that of the fixed resistors arranged corresponding to the other colors.

10. The resistance value of the fixed resistor connected to the light amount adjustment circuit arranged corresponding to each of the plurality of colors is A value is set according to the optical characteristics of the optical path from the semiconductor lasers arranged corresponding to each of the plurality of colors to the photosensitive drums arranged corresponding to each of the plurality of colors.

10. The image forming apparatus according to claim 9.

11. a first semiconductor laser, which is the semiconductor laser arranged corresponding to black; a first LD driver, which is the LD driver arranged corresponding to black; a first voltage generating circuit, which is the voltage generating circuit arranged corresponding to black; a second semiconductor laser, which is the semiconductor laser arranged to correspond to a color other than black; a second LD driver, which is the LD driver arranged corresponding to a color other than black; a second voltage generating circuit, which is the voltage generating circuit arranged corresponding to a color other than black; and The LD substrate is It is formed into a long plate shape along a predetermined direction, The first semiconductor laser and the second semiconductor laser are disposed at the center of the LD substrate in the predetermined direction, The first LD driver the first semiconductor laser and the second semiconductor laser are sandwiched between the first and second LD drivers in the predetermined direction, The first voltage generating circuit 11. The image forming apparatus according to claim 10, wherein the first semiconductor laser, the second semiconductor laser, the first LD driver, and the second LD driver are sandwiched between the first semiconductor laser, the second semiconductor laser, the first LD driver, and the second LD driver, and the second voltage generating circuit is disposed on the opposite side of the second voltage generating circuit in the predetermined direction.

Images