Power conversion control device

Abstract

To suppress a delay of a process for suppressing the generation of a surge voltage.SOLUTION: A control device 4 includes a CPU, a control register, and a DMA controller. The CPU controls a power conversion apparatus 1 including a plurality of power conversion circuits 51 to 56. The control register stores shutdown phase control data for controlling whether to output a shutdown drive signal for transitioning from a drive state to the stop state for each of the plurality of power conversion circuits 51 to 56. When the shutdown condition is satisfied, the DMA controller transfers the shutdown phase control data to the control register without intervention of the CPU every time the shutdown interval elapses, thereby sequentially shifting the plurality of power conversion circuits 51 to 56 to the stop state one by one every time the shutdown interval elapses.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a power conversion control device that controls a power conversion circuit. [Background technology]

[0002] A power conversion device includes a switching circuit including multiple switching elements. When a switching element is turned off or on, a surge voltage occurs. When multiple switching elements are turned off or on simultaneously, the multiple surge voltages are superimposed, resulting in a larger surge voltage.

[0003] Patent Document 1 describes a power conversion device that avoids the occurrence of large surge voltages by correcting the duty ratio so that the timing of occurrence of surge voltages caused by turning on a switching element and the timing of occurrence of surge voltages caused by turning off a switching element are shifted. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-2925 Summary of the Invention [Problem to be solved by the invention]

[0005] In a fail-safe state, all power conversion circuits must be shut down within a predetermined time. However, after detailed investigation by the inventors, it was discovered that if software is used to shift the timing of surge voltages caused by turning off switching elements in order to avoid the generation of large surge voltages, there is a possibility that the processing time may become long depending on the number of processes that call the handler or the prohibition of interrupts from other processes.

[0006] The present disclosure aims to suppress delays in processing for suppressing the occurrence of surge voltages. [Means for solving the problem]

[0007] One aspect of the present disclosure is a power conversion control device (4) including a central processing unit (91), a control register (96), a shutdown determination unit (S10), and a transfer unit (95). The central processing unit is configured to control a power conversion device (1) including a plurality of power conversion circuits (51 to 56).

[0008] The control register is configured to store shutdown control information (111 to 116, 121 to 126) that controls whether or not to output a shutdown signal for each of the plurality of power conversion circuits to transition the power conversion circuit from a drive state in which the power conversion circuit is driven to a stop state in which the power conversion circuit is stopped.

[0009] The shutdown determination unit is configured to determine whether a preset shutdown condition is met. When the shutdown determination unit determines that the shutdown condition is met, the transfer unit is configured to transfer shutdown control information to the control register without going through the central processing unit each time a preset shutdown interval elapses, thereby transitioning the multiple power conversion circuits in a driving state to a stopped state one by one in sequence each time the shutdown interval elapses.

[0010] The power conversion control device of the present disclosure configured as above transitions the multiple power conversion circuits that are in a driving state one by one to a stopped state at the expiration of each shutdown interval, thereby preventing the occurrence of a situation in which multiple surge voltages that are generated by transitioning to a stopped state are superimposed. Furthermore, the power conversion control device of the present disclosure transfers the shutdown control information to the control register without going through the central processing unit, thereby preventing delays in the process of transferring the shutdown control information to the control register.

[0011] As described above, the power conversion control device according to the present disclosure can suppress delays in processing for suppressing the occurrence of surge voltages. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a circuit diagram showing a configuration of a power conversion device. [Figure 2] FIG. 2 is a block diagram showing the configuration of a control device. [Figure 3] FIG. 10 is a diagram showing the configuration of a drive phase setting table. [Figure 4] FIG. 10 is a diagram showing the configuration of a first and second shutdown phase control data group. [Figure 5] 4 is a flowchart showing a process executed by a control device. [Figure 6] 10 is a timing chart showing a specific example of shutdown. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. As shown in FIG. 1, the power conversion device 1 of this embodiment includes a power conversion unit 2, a drive circuit 3, and a control device 4.

[0014] The power conversion device 1 is mounted on, for example, a vehicle, and boosts the battery voltage of an in-vehicle battery 6 and supplies the boosted voltage to an electronic load 7. The in-vehicle battery 6 in this embodiment is, for example, a fuel cell. The power conversion unit 2 includes an input positive terminal 11, an input negative terminal 12, an output positive terminal 13, an output negative terminal 14, a capacitor 15, six reactors 21, 22, 23, 24, 25, 26, six diodes 31, 32, 33, 34, 35, 36, and six switching elements 41, 42, 43, 44, 45, 46.

[0015] The input positive terminal 11 is connected to the positive electrode of the vehicle battery 6. The input negative terminal 12 is connected to the negative electrode of the vehicle battery 6. The output positive terminal 13 is connected to the positive electrode of the electronic load 7. The output negative terminal 14 is connected to the input negative terminal 12 and the negative electrode of the electronic load 7.

[0016] A first end of the capacitor 15 is connected to the output positive terminal 13, and a second end of the capacitor 15 is connected to the output negative terminal . First ends of reactors 21-26 are connected to input positive terminal 11. Second ends of reactors 21, 22, 23, 24, 25, and 26 are connected to anodes of diodes 31, 32, 33, 34, 35, and 36, respectively. Cathodes of diodes 31-36 are connected to output positive terminal 13.

[0017] The switching elements 41 to 46 of this embodiment are N-channel MOSFETs. The sources of the switching elements 41 to 46 are connected to the input negative terminal 12. The drain of switching element 41 is connected to the connection point between reactor 21 and diode 31. Similarly, the drains of switching elements 42 to 46 are connected to the connection points between reactors 22 to 26 and diodes 32 to 36, respectively.

[0018] The gate of switching element 41 is connected to drive circuit 3 via PWM drive signal line 71 and shutdown drive signal line 81. Similarly, the gates of switching elements 42, 43, 44, 45, and 46 are connected to drive circuit 3 via PWM drive signal lines 72, 73, 74, 75, and 76 and shutdown drive signal lines 82, 83, 84, 85, and 86, respectively. PWM stands for Pulse Width Modulation.

[0019] The PWM drive signal lines 71 to 76 are signal lines for transmitting PWM drive signals from the drive circuit 3 to the switching elements 41 to 46, respectively, for switching the switching elements 41 to 46 between an ON state and an OFF state.

[0020] The shutdown drive signal lines 81 to 86 are signal lines for transmitting shutdown drive signals from the drive circuit 3 to the switching elements 41 to 46, respectively, to transition the switching elements 41 to 46 from a state in which they alternate between the on state and the off state to a state in which they maintain the off state.

[0021] The power conversion unit 2 can generate a voltage at the output positive terminal 13 that is higher than the battery voltage of the vehicle battery 6 by switching the switching elements 41 to 46 between the on state and the off state. Specifically, when the switching elements 41 to 46 are first turned on, magnetic energy is stored in the reactors 21 to 26. When the switching elements 41 to 46 are then turned off, the magnetic energy stored in the reactors 21 to 26 increases the voltage at the connection points between the reactors 21 to 26 and the switching elements 41 to 46, and charge is stored in the capacitor 15. By repeating this operation, the voltage at the output positive terminal 13 increases.

[0022] Therefore, reactor 21, diode 31, switching element 41, and capacitor 15 constitute one power conversion circuit 51. Similarly, reactor 22, diode 32, switching element 42, and capacitor 15 constitute one power conversion circuit 52. Reactor 23, diode 33, switching element 43, and capacitor 15 constitute one power conversion circuit 53. Reactor 24, diode 34, switching element 44, and capacitor 15 constitute one power conversion circuit 54. Reactor 25, diode 35, switching element 45, and capacitor 15 constitute one power conversion circuit 55. Reactor 26, diode 36, switching element 46, and capacitor 15 constitute one power conversion circuit 56.

[0023] The control device 4 is configured to output to the drive circuit 3 a PWM control signal for controlling the output of a PWM drive signal by the drive circuit 3, and a shutdown control signal for controlling the output of a shutdown drive signal by the drive circuit 3.

[0024] The power conversion device 1 further includes ammeters 61, 62, 63, 64, 65, and 66, and voltmeters 68 and 69. Ammeters 61, 62, 63, 64, 65, and 66 detect the values ​​of currents flowing through reactors 21, 22, 23, 24, 25, and 26, respectively, and output current detection signals indicating the detection results to control device 4.

[0025] Voltmeter 68 detects the difference between the voltage at input positive terminal 11 and the voltage at input negative terminal 12, and outputs a voltage detection signal indicating the detection result to control device 4. Voltmeter 69 detects the difference between the voltage at output positive terminal 13 and the voltage at output negative terminal 14, and outputs a voltage detection signal indicating the detection result to control device 4.

[0026] Hereinafter, reactor 21 may be referred to as U-phase reactor 21, reactor 22 as V-phase reactor 22, reactor 23 as W-phase reactor 23, reactor 24 as X-phase reactor 24, reactor 25 as Y-phase reactor 25, and reactor 26 as Z-phase reactor 26.

[0027] 2, the control device 4 includes a CPU 91, a ROM 92, a RAM 93, an input / output unit 94, a DMA controller 95, a control register 96, and a bus 97 interconnecting these components. DMA stands for Direct Memory Access.

[0028] The various functions of the control device 4 are realized by the CPU 91 executing a program stored in a non-transitory storage medium. In this example, the ROM 92 corresponds to the non-transitory storage medium storing the program. Execution of this program also results in the execution of a method corresponding to the program. Note that some or all of the functions executed by the CPU 91 may be configured as hardware using one or more ICs, etc. Also, the number of microcomputers constituting the control device 4 may be one or more.

[0029] The input / output unit 94 includes a plurality of input / output ports for inputting and outputting signals. The DMA controller 95 has the function of executing a DMA transfer to transfer data stored in the ROM 92 or RAM 93 without going through the processing of the CPU 91 when a DMA transfer request signal is input from the CPU 91 or when a predetermined interrupt occurs.

[0030] Control data for controlling signal input / output via a plurality of input / output ports provided in the input / output unit 94 is written in the control register 96 . The control device 4 is configured to switch the number of phases to be driven (hereinafter referred to as drive phases) between 0 and 6 according to the current value required by the electronic load 7, so that the number of phases increases as the current value increases. Hereinafter, the number of drive phases will be referred to as the number of drive phases.

[0031] The ROM 92 of the control device 4 stores a driving phase setting table 100 shown in FIG. The drive phase setting table 100 sets a drive phase for each of a plurality of drive phase numbers for each of a plurality of drive phase pattern information. The drive phase pattern information is information for specifying a combination of drive phases. In this embodiment, the drive phase pattern information is either 0 or 1.

[0032] In the drive phase setting table 100 of this embodiment, when the drive phase pattern information is 0, the drive phases are set so that when the number of drive phases is 1, the U and V phases are driven, when the number of drive phases is 2, the U, V and W phases are driven, when the number of drive phases is 3, the U, V, W and X phases are driven, when the number of drive phases is 4, the U, V, W, X and Y phases are driven, when the number of drive phases is 5, and the U, V, W, X, Y and Z phases are driven when the number of drive phases is 6.

[0033] Furthermore, in the drive phase setting table 100 of this embodiment, when the drive phase pattern information is 1, the drive phases are set so that when the number of drive phases is 1, the W phase is driven, when the number of drive phases is 2, the W and X phases are driven, when the number of drive phases is 3, the W, X, and Y phases are driven, when the number of drive phases is 4, the W, X, Y, and Z phases are driven, when the number of drive phases is 5, the W, X, Y, Z, and U phases are driven, and when the number of drive phases is 6, the W, X, Y, Z, U, and V phases are driven.

[0034] The ROM 92 of the control device 4 also stores a first shutdown phase control data group 110 and a second shutdown phase control data group 120 shown in FIG. The first shutdown phase control data group 110 indicates the driving phases to be shut down when the driving phase pattern information is 0. The second shutdown phase control data group 120 indicates the driving phases to be shut down when the driving phase pattern information is 1.

[0035] The first shutdown phase control data group 110 includes shutdown phase control data 111, 112, 113, 114, 115, and 116. The shutdown phase control data 111, 112, 113, 114, 115, and 116 are stored consecutively in a storage area of ​​the ROM 92.

[0036] The shutdown phase control data 111 to 116 are 8-bit data. Each of the 8 bits constituting the shutdown phase control data 111 to 116 is set to either "0" or "1." "1" indicates that a shutdown is to be performed. "0" indicates that a shutdown is not to be performed.

[0037] The eight bits that make up the shutdown phase control data 111 to 116 are "bit0," "bit1," "bit2," "bit3," "bit4," "bit5," "bit6," and "bit7." "bit0," "bit1," "bit2," "bit3," "bit4," and "bit5" correspond to the U phase, V phase, W phase, X phase, Y phase, and Z phase, respectively.

[0038] The shutdown phase control data 111 is "00000001", which indicates that the U phase is to be shut down. The shutdown phase control data 112 is "00000011", which indicates that the U phase and V phase are to be shut down.

[0039] The shutdown phase control data 113 is "00000111", which indicates that the U phase, V phase, and W phase are to be shut down. The shutdown phase control data 114 is "00001111", which indicates that the U phase, V phase, W phase, and X phase are to be shut down.

[0040] The shutdown phase control data 115 is "00011111", which indicates that the U phase, V phase, W phase, X phase, and Y phase are to be shut down. The shutdown phase control data 116 is "00111111", which indicates that the U phase, V phase, W phase, X phase, Y phase, and Z phase are to be shut down.

[0041] The second shutdown phase control data group 120 includes shutdown phase control data 121, 122, 123, 124, 125, and 126. The shutdown phase control data 121, 122, 123, 124, 125, and 126 are stored consecutively in a storage area of ​​the ROM 92.

[0042] The shutdown phase control data 121 to 126 are 8-bit data. Each of the 8 bits constituting the shutdown phase control data 121 to 126 is set to either "0" or "1." "1" indicates that a shutdown is to be performed. "0" indicates that a shutdown is not to be performed.

[0043] The eight bits that make up the shutdown phase control data 121 to 126 are "bit0," "bit1," "bit2," "bit3," "bit4," "bit5," "bit6," and "bit7." "bit0," "bit1," "bit2," "bit3," "bit4," and "bit5" correspond to the U phase, V phase, W phase, X phase, Y phase, and Z phase, respectively.

[0044] The shutdown phase control data 121 is "00000100", which indicates that the W phase is to be shut down. The shutdown phase control data 122 is "00001100", which indicates that the W phase and X phase are to be shut down.

[0045] The shutdown phase control data 123 is "00011100", which indicates that the W phase, X phase, and Y phase are to be shut down. The shutdown phase control data 124 is "00111100", which indicates that the W phase, X phase, Y phase, and Z phase are to be shut down.

[0046] The shutdown phase control data 125 is "00111101", which indicates that the W phase, X phase, Y phase, Z phase, and U phase are to be shut down. The shutdown phase control data 126 is "00111111", which indicates that the W, X, Y, Z, U, and V phases are to be shut down.

[0047] The control device 4 increments (i.e., adds 1 to) the drive phase pattern selection information for selecting a drive phase pattern every time the control device 4 is started. However, if the value of the drive phase pattern selection information after the increment exceeds an upper limit value (1 in this embodiment), the control device 4 sets the drive phase pattern selection information to 0.

[0048] The control device 4 then refers to the drive phase setting table 100 and reads the drive phase pattern corresponding to the drive phase pattern information that matches the value of the drive phase pattern selection information. The control device 4 drives the drive phases according to the number of drive phases in accordance with the read drive phase pattern.

[0049] Furthermore, the control device 4 sets a transfer start address of the DMA controller 95 according to the value of the drive phase pattern selection information. Specifically, when the value of the drive phase pattern selection information is 0, the control device 4 sets the address where the shutdown phase control data 111 of the first shutdown phase control data group 110 is stored as the transfer start address. When the value of the drive phase pattern selection information is 1, the control device 4 sets the address where the shutdown phase control data 121 of the second shutdown phase control data group 120 is stored as the transfer start address.

[0050] Next, a description will be given of the procedure of the process executed by the control device 4. This process is repeatedly executed while the control device 4 is in operation. 5, the CPU 91 of the control device 4 determines whether an overcurrent or an overvoltage has been detected in S10. Specifically, the CPU 91 determines that an overcurrent has been detected when the current value indicated by the current detection signal acquired from the ammeters 61 to 66 is equal to or greater than a preset overcurrent determination value. The CPU 91 also determines that an overvoltage has been detected when the voltage value indicated by the voltage detection signal acquired from the voltmeter 69 is equal to or greater than a preset overvoltage determination value.

[0051] If an overcurrent or an overvoltage is not detected, the CPU 91 ends the process. On the other hand, if an overcurrent or an overvoltage is detected, the CPU 91 activates a transfer timer counter. The transfer timer counter is configured to be set to a value of 0 when activated and to increment every time a predetermined time elapses. When the value of the transfer timer counter exceeds a value corresponding to a preset shutdown interval, an interrupt (hereinafter referred to as a transfer interrupt) is generated. Note that the transfer timer counter is configured to be set to a value of 0 when a transfer interrupt is generated and to increment every time a predetermined time elapses.

[0052] The DMA controller 95 is configured to, each time a transfer interrupt occurs, sequentially move the address from which data is acquired (hereinafter referred to as the data acquisition address) by addresses equivalent to 8 bits of data from the transfer start address, and transfer the data acquired from the data acquisition address to the control register 96. Therefore, the DMA controller 95 sequentially transfers the shutdown phase control data 111 to 116 or the shutdown phase control data 121 to 126 to the control register 96 each time a transfer interrupt occurs.

[0053] When the process of S20 is completed, the CPU 91 determines in S30 whether the value of the transfer timer counter (hereinafter referred to as the transfer timer value) is greater than a value corresponding to a preset shutdown interval (hereinafter referred to as the shutdown interval equivalent value).

[0054] If the transfer timer value is equal to or less than the shutdown interval value, the CPU 91 repeats the process of S30 to wait until the transfer timer value becomes greater than the shutdown interval value. When the transfer timer value becomes greater than the shutdown interval value, the CPU 91 increments the transfer count k stored in the RAM 93 in S40.

[0055] In S50, the CPU 91 determines whether the number of transfers k is greater than the number of drive phases. If the number of transfers k is equal to or less than the number of drive phases, the CPU 91 proceeds to S30. On the other hand, if the number of transfers k is greater than the number of drive phases, the CPU 91 stops the transfer timer counter in S60 and ends the process.

[0056] Next, a specific example of executing shutdown when the drive phase pattern information is 0 and the number of drive phases is 6 will be described. 6, it is assumed that an abnormality occurs at time t0 when the control device 4 detects an overcurrent or an overvoltage, which causes the transfer timer counter to start incrementing.

[0057] At time t1, when the transfer timer value exceeds the value corresponding to the shutdown interval, a transfer interrupt occurs. As a result, the DMA controller 95 transfers the shutdown phase control data 111 (i.e., "00000001") to the control register 96. As a result, the shutdown phase control data 111 is written to the control register 96 as control data.

[0058] When the shutdown phase control data 111 is written to the control register 96, a U-phase shutdown control signal is output from an output port (hereinafter, U-phase shutdown output port) assigned to output a shutdown control signal for shutting down the U phase (hereinafter, U-phase shutdown control signal).

[0059] When the U-phase shutdown control signal output from the U-phase shutdown output port is input to the drive circuit 3, the drive circuit 3 outputs a shutdown drive signal (hereinafter referred to as the U-phase shutdown drive signal) to the gate of the switching element 41 to maintain the switching element 41 in the off state.

[0060] A voltage corresponding to the U-phase shutdown drive signal is applied to the gate of the switching element 41, so that the switching element 41 is maintained in the OFF state. At time t1, the transfer timer value is set to 0, and then the transfer timer counter resumes incrementing. At time t2, when the transfer timer value exceeds the value corresponding to the shutdown interval, a transfer interrupt occurs. This causes the DMA controller 95 to transfer the shutdown phase control data 112 (i.e., "00000011") to the control register 96. This causes the shutdown phase control data 112 to be written to the control register 96 as control data.

[0061] When the shutdown phase control data 112 is written to the control register 96, the output of the U-phase shutdown control signal continues, and a V-phase shutdown control signal is output from an output port (hereinafter, V-phase shutdown output port) assigned to output a shutdown control signal for shutting down the V-phase (hereinafter, V-phase shutdown control signal).

[0062] When the V-phase shutdown control signal output from the V-phase shutdown output port is input to the drive circuit 3, the drive circuit 3 outputs a shutdown drive signal (hereinafter referred to as the V-phase shutdown drive signal) to the gate of the switching element 42 to maintain the switching element 42 in the off state.

[0063] A voltage corresponding to the V-phase shutdown drive signal is applied to the gate of the switching element 42, so that the switching element 42 remains in the off state. At time t2, the transfer timer value is set to 0, and then the transfer timer counter resumes incrementing. At time t3, when the transfer timer value exceeds the value corresponding to the shutdown interval, a transfer interrupt occurs. This causes the DMA controller 95 to transfer the shutdown phase control data 113 (i.e., "00000111") to the control register 96. This causes the shutdown phase control data 113 to be written to the control register 96 as control data.

[0064] When the shutdown phase control data 113 is written to the control register 96, the output of the U-phase shutdown control signal and the V-phase shutdown control signal continues, and a W-phase shutdown control signal is output from an output port (hereinafter, W-phase shutdown output port) assigned to output a shutdown control signal for shutting down the W phase (hereinafter, W-phase shutdown control signal).

[0065] When the W-phase shutdown control signal output from the W-phase shutdown output port is input to the drive circuit 3, the drive circuit 3 outputs a shutdown drive signal (hereinafter referred to as the W-phase shutdown drive signal) to the gate of the switching element 43 to maintain the switching element 43 in the off state.

[0066] A voltage corresponding to the W-phase shutdown drive signal is applied to the gate of the switching element 43, so that the switching element 43 remains in the OFF state. At time t3, the transfer timer value is set to 0, and then the transfer timer counter resumes incrementing. At time t4, when the transfer timer value exceeds the value corresponding to the shutdown interval, a transfer interrupt occurs. This causes the DMA controller 95 to transfer the shutdown phase control data 114 (i.e., "00001111") to the control register 96. This causes the shutdown phase control data 114 to be written to the control register 96 as control data.

[0067] When the shutdown phase control data 114 is written to the control register 96, the output of the U-phase shutdown control signal, the V-phase shutdown control signal, and the W-phase shutdown control signal continues, and an X-phase shutdown control signal is output from an output port (hereinafter, X-phase shutdown output port) assigned to output a shutdown control signal for shutting down the X phase (hereinafter, X-phase shutdown control signal).

[0068] When the X-phase shutdown control signal output from the X-phase shutdown output port is input to the drive circuit 3, the drive circuit 3 outputs a shutdown drive signal (hereinafter referred to as the X-phase shutdown drive signal) to the gate of the switching element 44 to maintain the switching element 44 in the off state.

[0069] A voltage corresponding to the X-phase shutdown drive signal is applied to the gate of the switching element 44, so that the switching element 44 is maintained in the OFF state. At time t4, the transfer timer value is set to 0, and then the transfer timer counter resumes incrementing. At time t5, when the transfer timer value exceeds the value corresponding to the shutdown interval, a transfer interrupt occurs. This causes the DMA controller 95 to transfer the shutdown phase control data 115 (i.e., "00011111") to the control register 96. This causes the shutdown phase control data 115 to be written to the control register 96 as control data.

[0070] When the shutdown phase control data 115 is written to the control register 96, the output of the U-phase shutdown control signal, the V-phase shutdown control signal, the W-phase shutdown control signal, and the X-phase shutdown control signal continues, and a Y-phase shutdown control signal is output from an output port (hereinafter, Y-phase shutdown output port) assigned to output a shutdown control signal for shutting down the Y phase (hereinafter, Y-phase shutdown control signal).

[0071] When the Y-phase shutdown control signal output from the Y-phase shutdown output port is input to the drive circuit 3, the drive circuit 3 outputs a shutdown drive signal (hereinafter referred to as the Y-phase shutdown drive signal) to the gate of the switching element 45 to maintain the switching element 45 in the off state.

[0072] A voltage corresponding to the Y-phase shutdown drive signal is applied to the gate of the switching element 45, so that the switching element 45 is maintained in the OFF state. At time t5, the transfer timer value is set to 0, and then the transfer timer counter resumes incrementing. At time t6, when the transfer timer value exceeds the value corresponding to the shutdown interval, a transfer interrupt occurs. This causes the DMA controller 95 to transfer the shutdown phase control data 116 (i.e., "00111111") to the control register 96. This causes the shutdown phase control data 116 to be written to the control register 96 as control data.

[0073] When the shutdown phase control data 116 is written to the control register 96, the output of the U-phase shutdown control signal, the V-phase shutdown control signal, the W-phase shutdown control signal, the X-phase shutdown control signal, and the Y-phase shutdown control signal continues, and the Z-phase shutdown control signal is output from an output port (hereinafter, Z-phase shutdown output port) assigned to output a shutdown control signal for shutting down the Z phase (hereinafter, Z-phase shutdown control signal).

[0074] When the Z-phase shutdown control signal output from the Z-phase shutdown output port is input to the drive circuit 3, the drive circuit 3 outputs a shutdown drive signal (hereinafter referred to as the Z-phase shutdown drive signal) to the gate of the switching element 46 to maintain the switching element 46 in the off state.

[0075] A voltage corresponding to the Z-phase shutdown drive signal is applied to the gate of the switching element 46, so that the switching element 46 remains in the off state. The control device 4 configured in this manner includes a CPU 91 , a control register 96 , and a DMA controller 95 .

[0076] The CPU 91 is configured to control the power conversion device 1 including a plurality of power conversion circuits 51-56. The control register 96 is configured to store shutdown phase control data 111-116, 121-126 that controls whether or not to output U-Z phase shutdown drive signals for each of the multiple power conversion circuits 51-56, which transitions the power conversion circuits 51-56 from a drive state in which they are driven to a stop state in which they are stopped.

[0077] The control device 4 is configured to determine whether a preset shutdown condition is met. In this embodiment, the shutdown condition is the detection of an overcurrent or an overvoltage.

[0078] When the DMA controller 95 determines that the shutdown conditions are met, it transfers the shutdown phase control data 111-116, 121-126 to the control register 96 without going through the CPU 91, thereby transitioning the multiple power conversion circuits 51-56 that are in a driving state to a stopped state one by one, each time a predetermined shutdown interval has elapsed.

[0079] The control device 4 as described above transitions the power conversion circuits 51-56, which are in a driving state, one by one to a stopped state at the elapse of each shutdown interval, thereby preventing a situation in which multiple surge voltages, which are generated by transitioning to a stopped state, are superimposed on each other. Furthermore, the control device 4 transfers the shutdown phase control data 111-116, 121-126 to the control register 96 without going through the CPU 91, thereby preventing delays in the process of transferring the shutdown phase control data 111-116, 121-126 to the control register 96.

[0080] As a result, the control device 4 can suppress delays in processing for suppressing the occurrence of surge voltages. Specifically, the control device 4 has a timer function, and the DMA controller 95 has a direct memory access function. The timer function generates a transfer interrupt every time the shutdown interval elapses. The direct memory access function also transfers the shutdown phase control data 111-116 and 121-126 to the control register 96 every time the transfer interrupt occurs.

[0081] The CPU 91 is also configured to control the plurality of power conversion circuits 51-56 based on a drive phase setting table 100 that indicates which of the plurality of power conversion circuits 51-56 should be set to a drive state. The DMA controller 95 is configured to transfer the shutdown phase control data 111-116, 121-126 based on the drive phase setting table 100 so as to give priority to transitioning the drive-state power conversion circuits 51-56 to a stopped state. By giving priority to transitioning the drive-state power conversion circuits 51-56 to a stopped state, the control device 4 can further suppress delays in the shutdown process.

[0082] In the embodiment described above, the control device 4 corresponds to a power conversion control device, the CPU 91 corresponds to a central processing unit, S10 corresponds to processing as a shutdown determination unit, and the DMA controller 95 corresponds to a transfer unit.

[0083] Moreover, the shutdown phase control data 111 to 116 and 121 to 126 correspond to the shutdown control information, the U to Z phase shutdown drive signals correspond to the shutdown signals, and the drive phase setting table 100 corresponds to the drive circuit setting information.

[0084] Although one embodiment of the present disclosure has been described above, the present disclosure is not limited to the above embodiment and can be implemented in various modifications. [Variation 1] In the above embodiment, the power conversion circuits 51 to 56 are step-up circuits, but the power conversion circuits may be step-down circuits.

[0085] [Variation 2] In the above embodiment, the total number of power conversion circuits is six, but the total number of power conversion circuits may be any number (ie, two or more).

[0086] [Variation 3] In the above embodiment, there are two types of drive phase pattern information, but there may be three or more types of drive phase pattern information.

[0087] The control device 4 and the methods described herein may be implemented by a special-purpose computer configured with a processor and memory programmed to perform one or more functions embodied in a computer program. Alternatively, the control device 4 and the methods described herein may be implemented by a special-purpose computer configured with a processor comprising one or more dedicated hardware logic circuits. Alternatively, the control device 4 and the methods described herein may be implemented by one or more special-purpose computers configured with a processor and memory programmed to perform one or more functions in combination with a processor configured with one or more hardware logic circuits. Furthermore, the computer program may be stored as instructions executed by a computer on a computer-readable non-transitory tangible storage medium. The methods for implementing the functions of each unit included in the control device 4 do not necessarily need to include software; all of the functions may be implemented using one or more hardware components.

[0088] In the above embodiments, multiple functions of one component may be realized by multiple components, or one function of one component may be realized by multiple components. Furthermore, multiple functions of multiple components may be realized by one component, or one function realized by multiple components may be realized by one component. Furthermore, part of the configuration of the above embodiments may be omitted. Furthermore, at least part of the configuration of the above embodiments may be added to or substituted for the configuration of another of the above embodiments.

[0089] In addition to the control device 4 described above, the present disclosure can also be realized in various forms, such as a system including the control device 4 as a component, a program for causing a computer to function as the control device 4, a non-transient physical recording medium such as a semiconductor memory on which this program is recorded, and a power conversion control method. [Explanation of symbols]

[0090] 1...power conversion device, 4...control device, 51-56...power conversion circuit, 91...CPU, 95...DMA controller, 96...control register, 111-116, 121-126...shutdown phase control data

Claims

1. a central processing unit (91) configured to control a power conversion device (1) having a plurality of power conversion circuits (51 to 56); a control register (96) configured to store shutdown control information (111 to 116, 121 to 126) for controlling whether or not to output a shutdown signal for transitioning each of the plurality of power conversion circuits from an operating state in which the power conversion circuit is operating to a stopped state in which the power conversion circuit is stopped; a shutdown determination unit (S10) configured to determine whether a preset shutdown condition is met; a transfer unit (95) configured to, when the shutdown determination unit determines that the shutdown condition is established, transfer the shutdown control information to the control register without going through the central processing unit each time a preset shutdown interval elapses, thereby causing the plurality of power conversion circuits in the operating state to transition to the stopped state one by one in sequence each time the shutdown interval elapses; A power conversion control device (4) comprising:

2. The power conversion control device according to claim 1, The power conversion control device has a timer function, the transfer unit has a direct memory access function, The timer function generates a transfer interrupt each time the shutdown interval elapses; The power conversion control device is configured to transfer the shutdown control information to the control register by the direct memory access function every time the transfer interrupt occurs.

3. The power conversion control device according to claim 1 or 2, the central processing unit is configured to control the plurality of power conversion circuits based on drive circuit setting information (100) indicating the power conversion circuits to be set in the drive state among the plurality of power conversion circuits; The power conversion control device is configured so that the transfer unit transfers the shutdown control information based on the drive circuit setting information so as to preferentially transition the power conversion circuit that is in the drive state to the stop state.

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