Chattering prevention system

Abstract

To enable suppression of impact of chattering on output without using an RS flip-flop.SOLUTION: A chattering prevention circuit 11 includes: a first D flip-flop 1101 with resetting in which D input is fixed at High and a first digital input signal is input to a CLK terminal; a second D flip-flop 1102 with resetting in which D input is fixed at High and a second digital input signal is input to the CLK terminal; and an exclusive OR element 1103 which outputs a signal generated by taking an exclusive OR of an output signal from the first D flip-flop 1101 with resetting and an output signal from the second D flip-flop 1102 with resetting. The first D flip-flop 1101 with resetting and the second D flip-flop 1102 with resetting reset output signals in accordance with a reset signal output from a state machine 12.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to an anti-chattering system. [Background technology]

[0002] BACKGROUND ART Conventionally, a pulse signal output circuit is known that receives two digital input signals with different input timings and outputs a pulse signal by taking the exclusive OR (XOR) of the two digital input signals. On the other hand, if chattering is contained in the digital input signal input to the pulse signal output circuit, the output pulse signal will also contain small waveforms due to chattering, which will affect subsequent circuits of the pulse signal output circuit.

[0003] Therefore, in the past, instead of inputting a digital input signal directly to an exclusive OR element, an RS flip-flop was inserted between the input and output signals to suppress the effects of chattering on the output signal. A known example of a chattering prevention circuit using this RS flip-flop is the circuit disclosed in Patent Document 1. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 63-257139 Summary of the Invention [Problem to be solved by the invention]

[0005] However, RS flip-flops must be verified separately from other circuits in timing analysis during the development flow of custom ICs, which reduces verification efficiency. Therefore, when considering the verification efficiency in custom IC development, it is not desirable to use RS flip-flops in the chattering prevention circuit.

[0006] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a chattering prevention system that can suppress the effect of chattering on output without using an RS flip-flop. [Means for solving the problem]

[0007] The chattering prevention system according to the present disclosure includes a chattering prevention circuit that receives a first digital input signal and a second digital input signal whose High periods do not overlap and outputs a pulse signal, and a state machine that outputs a reset signal based on the pulse signal output by the chattering prevention circuit, wherein the chattering prevention circuit includes a first reset-equipped D flip-flop whose D input is fixed to High, whose CLK terminal receives the first digital input signal, and which outputs an output signal from its output terminal in response to the input of the first digital input signal; The state machine includes a second D flip-flop with reset that receives a second digital input signal at its CLK terminal and outputs an output signal from its output terminal in response to the second digital input signal, and an exclusive OR element that outputs a pulse signal that is an exclusive OR of the output signal from the first D flip-flop with reset and the output signal from the second D flip-flop with reset, and the first D flip-flop with reset and the second D flip-flop with reset reset their output signals in response to a reset signal output by the state machine. [Effects of the Invention]

[0008] According to the present disclosure, with the above configuration, it is possible to suppress the effect of chattering on the output without using an RS flip-flop. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a diagram illustrating an example of the configuration of a chattering prevention system according to a first embodiment. [Figure 2]3 shows an example of a timing chart of various signals handled by the chattering prevention system according to the first embodiment. [Figure 3] FIG. 2 is a diagram for explaining an example of state transition of a state machine in the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments will be described in detail with reference to the drawings. Embodiment 1 FIG. 1 is a diagram showing an example of the configuration of a chattering prevention system 1 according to the first embodiment. 1, the chattering prevention system 1 includes a chattering prevention circuit 11 and a state machine 12. In addition to the chattering prevention system 1, a subsequent circuit 2 connected to the chattering prevention system 1 is also shown in FIG.

[0011] The chattering prevention circuit 11 is a circuit that receives a first digital input signal (IN_1) and a second digital input signal (IN_2) and outputs a pulse signal (pulse). The High periods of the first digital input signal (IN_1) and the second digital input signal (IN_2) do not overlap (see FIG. 2). This chattering prevention circuit 11 has a chattering prevention function that prevents a waveform due to chattering from being mixed into the pulse signal (pulse) when chattering is included in the first digital input signal (IN_1) and the second digital input signal (IN_2).

[0012] As shown in FIG. 1, the chattering prevention circuit 11 includes a first reset D flip-flop 1101, a second reset D flip-flop 1102, and an exclusive OR element 1103 (XOR).

[0013] The first reset D flip-flop 1101 has a D input (D1) fixed to High, a first digital input signal (IN_1) input to the CLK terminal (clk), and outputs an output signal (Q1) from the output terminal in response to the input of the first digital input signal (IN_1). That is, when a first digital input signal (IN_1) is input to the CLK terminal (clk), the output of this first reset D flip-flop 1101 rises in response to the rising edge of the input, and thereafter continues to output an output signal (Q1) until a reset signal (Reset) is input from the state machine 12.

[0014] The first digital input signal (IN_1) may be a signal synchronized with the CLK of the first D flip-flop with reset 1101, or may be a signal asynchronous with the CLK of the first D flip-flop with reset 1101.

[0015] The second reset D flip-flop 1102 has its D input (D2) fixed to High, a second digital input signal (IN_2) input to its CLK terminal (clk), and outputs an output signal (Q2) from its output terminal in response to the input of the second digital input signal (IN_2). That is, when a second digital input signal (IN_2) is input to the CLK terminal (clk), the output of this second reset D flip-flop 1102 rises in response to the rising edge of the input, and thereafter continues to output an output signal (Q2) until a reset signal (Reset) is input from the state machine 12.

[0016] The second digital input signal (IN_2) may be a signal synchronized with the CLK of the second D flip-flop with reset 1102, or may be a signal asynchronous with the CLK of the second D flip-flop with reset 1102.

[0017] The exclusive OR element 1103 has a pair of input terminals, one of which is connected to the output terminal of the first reset D flip-flop 1101, and the other of which is connected to the output terminal of the second reset D flip-flop 1102. The exclusive OR element 1103 outputs a pulse signal (pulse) by taking the exclusive OR of the output signal (Q1) from the first reset D flip-flop 1101 and the output signal (Q2) from the second reset D flip-flop 1102. This pulse signal (pulse) is input to the subsequent circuit 2 and the state machine 12.

[0018] The state machine 12 inputs the pulse signal (pulse) output by the chattering prevention circuit 11 (exclusive OR element 1103), and outputs a reset signal (Reset) to the first reset D flip-flop 1101 and the second reset D flip-flop 1102 based on the input of the pulse signal (pulse). More specifically, after the pulse signal falls, the state machine 12 waits a predetermined number of CLKs and then outputs a reset signal (Reset). Note that the predetermined number of CLKs is a period that includes the period from when the second digital input signal rises to when it falls.

[0019] Next, an example of the operation of the chattering prevention system 1 according to the first embodiment shown in FIG. 1 will be described. In the chattering prevention system 1 according to the first embodiment shown in FIG. 1, first, the first reset D flip-flop 1101, whose D input (D1) is fixed to High, outputs an output signal (Q1) from its output terminal in response to the input of a first digital input signal (IN_1) to its CLK terminal (clk). That is, when a first digital input signal (IN_1) is input to the CLK terminal (clk), the output of this first reset D flip-flop 1101 rises in response to the rising edge of the input, and thereafter continues to output an output signal (Q1) until a reset signal (Reset) is input from the state machine 12.

[0020] In addition, a second reset D flip-flop 1102, whose D input (D2) is fixed to High, outputs an output signal (Q2) from its output terminal in response to the input of a second digital input signal (IN_2) to its CLK terminal (clk). That is, when a second digital input signal (IN_2) is input to the CLK terminal (clk), the output of this second reset D flip-flop 1102 rises in response to the rising edge of the input, and thereafter continues to output an output signal (Q2) until a reset signal (Reset) is input from the state machine 12.

[0021] Next, the exclusive OR element 1103 outputs a pulse signal (pulse) by taking the exclusive OR of the output signal (Q1) from the first reset D flip-flop 1101 and the output signal (Q2) from the second reset D flip-flop 1102. This pulse signal (pulse) is input to the subsequent circuit 2 and the state machine 12.

[0022] Next, the state machine 12 receives the pulse signal (pulse) output by the chattering prevention circuit 11 (exclusive OR element 1103) and, based on the input of the pulse signal (pulse), outputs a reset signal (Reset) to the first reset D flip-flop 1101 and the second reset D flip-flop 1102. That is, the state machine 12 receives the pulse signal (pulse) output by the chattering prevention circuit 11 (exclusive OR element 1103) to create reset timing internally and reset the first reset D flip-flop 1101 and the second reset D flip-flop 1102. The first reset-enabled D flip-flop 1101 resets the output signal (Q1) in response to a reset signal (Reset) from the state machine 12. Similarly, the second reset-enabled D flip-flop 1102 resets the output signal (Q2) in response to a reset signal (Reset) from the state machine 12.

[0023] 2 shows an example of a timing chart of various signals handled by the chattering prevention system 1 according to embodiment 1. Note that "State" in FIG. 2 indicates the state of the state machine 12 (state 0 to state 3).

[0024] As shown in Fig. 2, chattering occurs when the first digital input signal (IN_1) and the second digital input signal (IN_2) both change, as indicated by reference numerals 11 and 12. Fig. 2 shows a case where the first digital input signal (IN_1) and the digital input signal (IN_2) are both signals synchronized with the CLK of the first reset D flip-flop 1101 and the second reset D flip-flop 1102.

[0025] 2, Q1 is an output signal of the first reset D flip-flop 1101. This Q1 becomes High when the first digital input signal (IN_1) is High when CLK rises, as indicated by reference numeral 13. Thereafter, Q1 remains High until the reset signal (Reset) from the state machine 12 is input to the first reset D flip-flop 1101. 2, Q2 is the output signal of the second reset D flip-flop 1102. This Q2 becomes High if the second digital input signal (IN_2) is High when CLK rises. Thereafter, Q2 remains High until the reset signal (Reset) from the state machine 12 is input to the second reset D flip-flop 1102.

[0026] This first reset D flip-flop 1101 and second reset D flip-flop 1102 make it possible to obtain stable output signals (Q1, Q2) that do not contain waveforms due to chattering, even when first and second digital input signals (IN_1, IN_2) that contain chattering are input.

[0027] On the other hand, when the output signal (Q1) of the first reset D flip-flop 1101 goes high, the output signal (Q1) remains high until it is reset. Similarly, when the output signal (Q2) of the second reset D flip-flop 1102 goes high, the output signal (Q2) remains high until it is reset. Therefore, when counting pulse signals continuously, the chattering prevention circuit 11 cannot be used as is, and a mechanism for resetting the chattering prevention circuit 11 is required.

[0028] Therefore, in the chattering prevention system 1 according to the first embodiment, the chattering prevention circuit 11 is reset using a state machine 12 that monitors the pulse signal (pulse) output by the chattering prevention circuit 11.

[0029] Here, as shown in FIGS. 2 and 3, for example, the state machine 12 has four states (states 0 to 3). 3, State 0 is a state in which the state waits for the rising edge of the pulse signal (pulse) output by the chattering prevention circuit 11. In State 0, when the pulse signal (pulse) output by the chattering prevention circuit 11 rises, the state transitions to State 1. State 1 is a state in which the circuit waits for the falling edge of the pulse signal (pulse) output by the chattering prevention circuit 11. In State 1, when the pulse signal (pulse) output by the chattering prevention circuit 11 falls, the circuit transitions to State 2. State 2 is a state in which the reset signal (Reset) falls after waiting for a predetermined CLK. The predetermined CLK is a period that includes the period from when the second digital input signal (IN_2) rises to when it falls. In State 2, after the reset signal (Reset) falls, the state automatically transitions to State 3. Furthermore, the reset signal (Reset) is raised in state 3. In state 3, the state automatically transitions to state 0 after the reset signal (Reset) is raised.

[0030] As shown in Figures 2 and 3, when the state machine 12 is in state 0 or state 3, the chattering prevention circuit 11 is in a region (measurement region) in which it measures fluctuations in the first digital input signal (IN_1) and the second digital input signal (IN_2). Also, as shown in Figures 2 and 3, when the state machine 12 is in state 1 or state 2, even if the first digital input signal (IN_1) or the second digital input signal (IN_2) changes, the reset signal (Reset) for the first reset-enabled D flip-flop 1101 and the second reset-enabled D flip-flop 1102 is High, so the output signals (Q1, Q2) do not change (pulse generation region). On the other hand, as shown in Figures 2 and 3, when the state machine 12 is in state 3, the reset signal (Reset) for the first reset D flip-flop 1101 and the second reset D flip-flop 1102 is Low, so the first reset D flip-flop 1101 and the second reset D flip-flop 1102 reset their output signals (Q1, Q2) to Low.

[0031] In this way, by using the state machine 12 that monitors the pulse signal (pulse) output by the chattering prevention circuit 11, the output signals (Q1, Q2) of the first reset D flip-flop 1101 and the second reset D flip-flop 1102 can be reset at appropriate timing. Thereafter, the chattering prevention circuit 11 can generate a pulse signal (pulse) again from the changes in the first and second digital input signals (IN_1, IN_2) in the next pulse generation period.

[0032] It should be noted that if there is no need to continuously count pulse signals (pulses), the state machine 12 does not need to reset the chattering prevention circuit 11.

[0033] As described above, according to the first embodiment, the chattering prevention system 1 includes the chattering prevention circuit 11 that receives a first digital input signal and a second digital input signal whose High periods do not overlap and outputs a pulse signal, and the state machine 12 that outputs a reset signal based on the pulse signal output by the chattering prevention circuit 11. The chattering prevention circuit 11 includes a first reset-equipped D flip-flop 1101 whose D input is fixed to High, whose CLK terminal receives the first digital input signal, and whose output terminal outputs an output signal in response to the input of the first digital input signal, and a second reset-equipped D flip-flop 1102 whose D input is fixed to High. a second D flip-flop 1102 with a reset, which receives a second digital input signal at its CLK terminal and outputs an output signal from its output terminal in response to the input of the second digital input signal; and an exclusive OR element 1103 which outputs a pulse signal which is an exclusive OR of the output signal from the first D flip-flop 1101 with a reset and the output signal from the second D flip-flop 1102 with a reset, and the first D flip-flop 1101 with a reset and the second D flip-flop 1102 with a reset reset their output signals in response to the reset signal output by the state machine 12. Furthermore, according to this embodiment 1, when the state machine 12 determines that the pulse signal output by the chattering prevention circuit 11 has fallen, it outputs a reset signal to the first reset D flip-flop 1101 and the second reset D flip-flop 1102. Furthermore, according to this embodiment 1, the state machine 12 has a zeroth state which is a state of waiting for the rising edge of the pulse signal output by the chattering prevention circuit 11, a first state which is a state to which the state machine transitions from the zeroth state when the pulse signal output by the chattering prevention circuit 11 rises and is a state of waiting for the falling edge of the pulse signal output by the chattering prevention circuit 11, a second state which is a state to which the state machine transitions from the first state when the pulse signal output by the chattering prevention circuit 11 falls and is a state to which the reset signal falls after waiting a predetermined CLK, and a third state which is a state to which the state machine transitions from the second state after the reset signal falls and is a state to which the reset signal rises, and the zeroth state is transitioned from the third state after the reset signal rises. Furthermore, according to the first embodiment, the predetermined CLK is a period that includes the period from when the second digital input signal rises to when it falls. As a result, the chattering prevention system 1 according to the first embodiment can suppress the effect of chattering on the output without using an RS flip-flop.

[0034] Any of the components of the embodiments may be modified or omitted. [Explanation of symbols]

[0035] 1. Anti-chattering system 2. Subsequent circuit 11 Anti-chattering circuit 12 State Machines 1101 First D Flip-Flop with Reset 1102 D flip-flop with second reset 1103 Exclusive OR element (XOR)

Claims

1. a chattering prevention circuit that receives a first digital input signal and a second digital input signal whose High periods do not overlap, and outputs a pulse signal; a state machine that outputs a reset signal based on the pulse signal output by the chattering prevention circuit; The chattering prevention circuit includes: a first reset-equipped D flip-flop having a D input fixed to High, a first digital input signal input to a CLK terminal, and outputting an output signal from an output terminal in response to the input of the first digital input signal; a second reset-equipped D flip-flop having a D input fixed to High and a second digital input signal input to a CLK terminal, which outputs an output signal from an output terminal in response to the input of the second digital input signal; an exclusive OR element that outputs a pulse signal that is an exclusive OR of an output signal from the first reset D flip-flop and an output signal from the second reset D flip-flop; The first reset-enabled D flip-flop and the second reset-enabled D flip-flop reset their output signals in response to a reset signal output by the state machine. A chattering prevention system comprising:

2. When the state machine determines that the pulse signal output by the chattering prevention circuit has fallen, it outputs a reset signal to the first reset-enabled D flip-flop and the second reset-enabled D flip-flop.

2. The chattering prevention system according to claim 1.

3. The state machine a zeroth state in which the rising edge of a pulse signal output by the chattering prevention circuit is awaited; a first state, which transitions from the 0th state when the pulse signal output by the chattering prevention circuit rises, and which is a state of waiting for the falling edge of the pulse signal output by the chattering prevention circuit; a second state, which is a state transitioned from the first state by the falling edge of the pulse signal output by the chattering prevention circuit, and which is a state in which the reset signal falls after waiting for a predetermined CLK; a third state, which is a state transitioned from the second state after the reset signal is lowered and is a state in which the reset signal is raised; The 0th state is transitioned from the 3rd state after the reset signal rises.

3. The chattering prevention system according to claim 1 or 2.

4. The predetermined CLK is a period including the period from when the second digital input signal rises to when it falls.

4. The chattering prevention system according to claim 3.

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