Signal transmission device, electronic apparatus, and vehicle

Abstract

To transmit not only a data signal but a clock signal and prevent increase in current consumption, EMI, and mounting area due to the transmission of the clock signal.SOLUTION: A signal transmission device (101) comprises: a transmission unit (4) configured to generate and transmit a first transmission signal and a second transmission signal according to a first clock signal and a first data signal synchronized with the first clock signal; an isolator (5) configured to insulate and transmit the first transmission signal and the second transmission signal as a first received signal and a second received signal, respectively; and a receiving unit (6) configured to receive the first received signal and the second received signal, generate a second clock signal according to the first received signal and the second received signal, and generate a second data signal according to the first received signal and the second received signal.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a signal transmission device, an electronic device, and a vehicle. [Background technology]

[0002] Conventionally, signal transmission devices that transmit signals between a primary circuit system and a secondary circuit system while electrically insulating the primary circuit system and the secondary circuit system have been used in various applications (such as power supply devices and motor drive devices) (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 5926003

[0004] [overview] When the signal transmission device is configured to require clock signals synchronized with both the primary and secondary circuit systems, it is necessary to transmit not only data signals but also clock signals from the primary circuit system to the secondary circuit system. It is desirable to suppress the current consumption, EMI (Electro Magnetic Interference), and increase in mounting area due to the transmission of the clock signal.

[0005] The signal transmission device disclosed in this specification comprises a transmitting unit configured to generate and transmit a first transmission signal and a second transmission signal corresponding to a first clock signal and a first data signal synchronized with the first clock signal; an isolator configured to transmit the first transmission signal and the second transmission signal in an isolated manner as a first reception signal and a second reception signal, respectively; and a receiving unit configured to receive the first reception signal and the second reception signal, generate a second clock signal corresponding to the first reception signal and the second reception signal, and generate a second data signal corresponding to the first reception signal and the second reception signal.

[0006] The electronic device disclosed in this specification includes a signal transmission device having the above-described configuration.

[0007] The vehicle disclosed in this specification is equipped with the electronic device having the above-described configuration. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing the configuration of a signal transmission device according to a comparative example. [Figure 2] FIG. 2 is a signal waveform diagram in the signal transmission device shown in FIG. [Figure 3] FIG. 3 is a diagram showing the configuration of a signal transmission device according to an embodiment. [Figure 4] FIG. 4 is a signal waveform diagram in the signal transmission device shown in FIG. [Figure 5] FIG. 5 is a diagram illustrating an example of the configuration of a transmitter, an isolator, and a receiver. [Figure 6] FIG. 6 is a signal waveform diagram in the signal transmission device shown in FIG. 3 in which the configuration example shown in FIG. 5 is adopted. [Figure 7] FIG. 7 is a diagram showing the configuration of a signal transmission device according to a modified example. [Figure 8] FIG. 8 is a perspective view of the exterior of the vehicle.

[0009] [Detailed explanation] <Comparative Example> Fig. 1 is a diagram showing the configuration of a signal transmission device 100 according to a comparative example (=a general configuration to be compared with the embodiments described later). Fig. 2 is a signal waveform diagram of the signal transmission device 100 shown in Fig. 1.

[0010] The signal transmission device 100 is mounted on an electronic device A together with a signal processing device 200 that supplies an input signal SIN and a signal processing device 300 that receives an output signal SOUT. Similar to the signal transmission device 100, signal transmission devices 101 and 102, which will be described later, are also mounted on an electronic device together with a device that supplies an input signal SIN and a device that receives an output signal SOUT.

[0011] The signal transmission device 100 includes an amplifier 1, an AD converter 2, an oscillator 3, transmission units 4A and 4B, isolators 5A and 5B, reception units 6A and 6B, a digital filter circuit 7, a current DA converter 8, and an IV conversion unit 9. The oscillator 3 may be provided in the signal processing device 200 instead of the signal transmission device 100.

[0012] The amplifier 1 amplifies the input signal SIN and supplies the amplified input signal SIN to the AD converter 2 .

[0013] The AD converter 2 performs ΔΣ modulation on the analog output signal of the amplifier 1 based on the clock signal SCK1 output from the oscillator 3, converting the analog output signal of the amplifier 1 into a digital data signal SD1. The data signal SD1 is synchronized with the clock signal SCK1. The timing of edge appearance of the data signal SD1 is slightly delayed with respect to the timing of edge appearance of the clock signal SCK1.

[0014] The transmitter 4A generates a transmission signal ST11 having an edge indicating a transition of the data signal SD1 from low level to high level. The transmitter 4A generates a transmission signal ST12 having an edge indicating a transition of the data signal SD1 from high level to low level. The transmitter 4A outputs the transmission signals ST11 and ST12 to the isolator 5A.

[0015] The transmitter 4B generates a transmission signal ST13 having an edge indicating a transition of the clock signal SCK1 from low level to high level. The transmitter 4A generates a transmission signal ST14 having an edge indicating a transition of the clock signal SCK1 from high level to low level. The transmitter 4A outputs the transmission signals ST13 and ST14 to the isolator 5A.

[0016] The signal transmission device 100 includes two isolators, namely isolators 5A and 5B. The isolator 5A transmits the transmission signals ST11 and ST12 as reception signals SR11 and SR12, respectively, in an isolated manner. The isolator 5B transmits the transmission signals ST13 and ST14 as reception signals SR13 and SR14, respectively, in an isolated manner.

[0017] The receiver 6A receives the reception signals SR11 and SR12 output from the isolator 5A, and generates a data signal SD2 from the reception signals SR11 and SR12. The data signal SD2 is a signal obtained by restoring the data signal SD1.

[0018] The receiver 6B receives the reception signals SR13 and SR14 output from the isolator 5AB, and generates a clock signal SCK2 from the reception signals SR13 and SR14. The clock signal SCK2 is a signal obtained by restoring the clock signal SCK1.

[0019] The digital filter circuit 7 performs filtering on the data signal SD2 based on the clock signal SCK2.

[0020] The current DA converter 8 generates a current corresponding to the filtered data signal SD2 and outputs the generated current to the IV conversion unit 9. The IV conversion unit 9 converts the current output from the current DA converter 8 into a voltage. Note that another DA converter may be used instead of the current DA converter 8. An example of the other DA converter is a resistive division type DA converter.

[0021] Since the signal transmission device 100 has a configuration including two isolators, it is difficult to suppress increases in current consumption, EMI, and mounting area due to clock signal transmission. In other words, it is difficult to suppress increases in current consumption, EMI, and mounting area in the isolator 5B.

[0022] <Embodiment> Fig. 3 is a diagram showing the configuration of a signal transmission device 101 according to an embodiment. Fig. 4 is a signal waveform diagram of the signal transmission device 101 shown in Fig. 3. Note that descriptions of parts similar to those in the comparative example will be omitted as appropriate.

[0023] The signal transmission device 101 has a configuration in which the transmitters 4A and 4B in the signal transmission device 100 are replaced with a transmitter 4, the isolators 5A and 5B are replaced with an isolator 5, and the receivers 6A and 6B are replaced with a receiver 6.

[0024] The transmitter 4 generates and transmits transmission signals ST1 and ST2 in response to the clock signal SCK1 and the data signal SD1. The transmission signal ST1 is a signal having an edge indicating that the data signal SD1 is at a high level at the timing of the rising edge of the clock signal SCK1. The transmission signal ST2 is a signal having an edge indicating that the data signal SD1 is at a low level at the timing of the rising edge of the clock signal SCK1. Unlike the present embodiment, the transmission signal ST1 may be a signal having an edge indicating that the data signal SD1 is at a high level at the timing of the falling edge of the clock signal SCK1, and the transmission signal ST2 may be a signal having an edge indicating that the data signal SD1 is at a low level at the timing of the falling edge of the clock signal SCK1.

[0025] The signal transmission device 101 includes one system of isolators, that is, the isolator 5. The isolator 5 transmits the transmission signals ST1 and ST2 as reception signals SR1 and SR2, respectively, in an isolated manner.

[0026] The receiver 6 receives the reception signals SR1 and SR2 output from the isolator 5 and generates a clock signal SCK2 and a data signal SD2 from the reception signals SR1 and SR2. The clock signal SCK2 is a signal corresponding to the reception signals SR1 and SR2, and the data signal SD2 is also a signal corresponding to the reception signals SR1 and SR2.

[0027] The rising edges of clock signal SCK2 appear at the same timing as the edges of received signal SR1 and received signal SR2. In other words, clock signal SCK2 is a signal that corresponds to each edge of received signals SR1 and SR2, and has a pulse that corresponds to the rising edge of clock signal SCK1. Therefore, clock signal SCK2 is a signal that restores at least a portion of clock signal SCK1. The clock signal SCK2 with the waveform shown in FIG. 4 is a signal that restores the timing of the rising edges of clock signal SCK1 but does not restore the pulse width of clock signal SCK1.

[0028] The rising edge of data signal SD2 appears at the same timing as the edge of received signal SR1, and after the rising edge of data signal SD2 appears, the high level state of data signal SD2 is maintained until the edge of received signal SR2 appears.The falling edge of data signal SD2 appears at the same timing as the edge of received signal SR2, and after the falling edge of data signal SD2 appears, the low level state of data signal SD2 is maintained until the edge of received signal SR1 appears.

[0029] The data signal SD2 is a restored version of the data signal SD1. However, the data signal SD2 is delayed by one cycle of the clock signal SCK1 relative to the data signal SD1. The interval between edges of the data signal SD2 is the same as the interval between edges of the data signal SD1. More specifically, the interval between adjacent rising and falling edges of the data signal SD1 is the same as the interval between adjacent rising and falling edges of the data signal SD2 one cycle later of the clock signal SCK1.

[0030] Since the signal transmission device 101 is configured to simultaneously transmit a clock signal and a data signal by transmitting transmission signals ST1 and ST2, the isolator can be configured as a single system (only the isolator 5) that transmits the transmission signals ST1 and ST2. Therefore, compared to the signal transmission device 100 configured with two isolators (isolators 5A and 5B), one for transmitting a clock signal and the other for transmitting a data signal, the signal transmission device 101 can suppress increases in current consumption, EMI, and mounting area due to the transmission of clock signals.

[0031] Fig. 5 is a diagram showing an example of the configuration of the transmitter 4, the isolator 5, and the receiver 6. Fig. 6 is a signal waveform diagram in a signal transmission device 101 in which the example of the configuration shown in Fig. 5 is adopted.

[0032] The transmitting unit 4 of the configuration example shown in Fig. 5 includes AND gates 41 and 42, and driver circuits 43 and 44. The isolator 5 of the configuration example shown in Fig. 5 includes pulse transformers 51 and 52. The receiving unit 6 of the configuration example shown in Fig. 5 includes high-pass filter circuits 61 and 62, envelope circuits 63 and 64, comparators 65 and 66, an SR latch circuit 67, an OR gate 68, and an adjustment circuit 69.

[0033] The AND gate 41 outputs the logical sum of the clock signal SCK1 and the data signal SD1 at the timing when the rising edge of the clock signal SCK1 appears, and outputs a low level at times other than when the rising edge of the clock signal SCK1 appears. The AND gate 42 outputs the logical sum of the clock signal SCK1 and the inverted signal of the data signal SD1 at the timing when the rising edge of the clock signal SCK1 appears, and outputs a low level at times other than when the rising edge of the clock signal SCK1 appears.

[0034] The driver circuit 43 drives the transmission coil of the pulse transformer 51 in response to an edge of the transmission signal ST1. The driver circuit 44 drives the transmission coil of the pulse transformer 52 in response to an edge of the transmission signal ST2.

[0035] The high-pass filter circuit 61 extracts the high-frequency components of the received signal SR1 supplied from the receiving coil of the pulse transformer 51 and outputs the extracted components to an envelope circuit 63. The high-pass filter circuit 62 extracts the high-frequency components of the received signal SR2 supplied from the receiving coil of the pulse transformer 52 and outputs the extracted components to an envelope circuit 64.

[0036] The envelope circuit 63 performs envelope processing on the signal output from the high-pass filter circuit 61 to generate a signal S1. The envelope circuit 64 performs envelope processing on the signal output from the high-pass filter circuit 62 to generate a signal S2.

[0037] The comparator 65 compares the signal S1 with the threshold voltage VTH and generates a signal S3 representing the comparison result. The comparator 66 compares the signal S2 with the threshold voltage VTH and generates a signal S4 representing the comparison result.

[0038] The SR latch circuit 67 receives the signal S3 at its set input terminal, receives the signal S4 at its reset input terminal, and outputs a data signal SD2 from its output terminal.

[0039] OR gate 68 generates signal S5, which is the logical sum of signals S3 and S4.

[0040] The adjustment circuit 69 generates a clock signal SCK2 from the signal S5. The timing of the appearance of the rising edge of the clock signal SCK2 coincides with the timing of the appearance of the rising edge of the signal S5, and the pulse width W2 of the clock signal SCK2 is adjusted by the adjustment circuit 69. In the signal waveforms shown in FIG. 6, the pulse width W1 of the clock signal SCK2 is adjusted by the adjustment circuit 69 so that the pulse width W2 of the clock signal SCK2 coincides with the pulse width W1 of the clock signal SCK1. Note that the receiving unit 6 may not be configured to include the adjustment circuit 69. Furthermore, even if the receiving unit 6 is configured to include the adjustment circuit 69, the pulse width W2 of the clock signal SCK2 does not have to coincide with the pulse width W1 of the clock signal SCK1.

[0041] <Modification> 7 is a diagram showing the configuration of a signal transmission device 102 according to a modified example. The signal transmission device 102 has a configuration in which a detection circuit DET1 is added to the signal transmission device 101.

[0042] The detection circuit DET1 detects a state in which a pulse of the clock signal SCK2 is not being generated. Therefore, the detection circuit DET1 can detect a case in which the transmitting side (the amplifier 1, the AD converter 2, the oscillator 3, and the transmitter 4) of the signal transmission device 102 has stopped operating, and can also detect a case in which the isolator 5 is broken and insulated communication is no longer possible. For example, when the detection circuit DET1 detects a state in which a pulse of the clock signal SCK2 is not being generated, the receiving side (the receiver 6, the digital filter circuit 7, the current DAC 8, and the IV converter 9) of the signal transmission device 102 may stop operating. Then, when the detection circuit DET1 no longer detects a state in which a pulse of the clock signal SCK2 is not being generated, the receiving side (the receiver 6, the digital filter circuit 7, the current DAC 8, and the IV converter 9) of the signal transmission device 102 may resume operating.

[0043] One method for detecting a state in which a pulse of the clock signal SCK2 is not generated is to count the number of edges of the received signals SR1 and SR2 over a certain period of time, and detect a state in which a pulse of the clock signal SCK2 is not generated when the number of edges is less than a predetermined value. Another detection method is to perform envelope processing on the clock signal SCK2, and detect a state in which a pulse of the clock signal SCK2 is not generated when the clock signal SCK2 after envelope processing is less than a threshold value.

[0044] <Application to vehicles> 8 is a diagram showing the exterior of a vehicle. Vehicle B of this configuration example is equipped with various electronic devices that operate by receiving power supply from a battery.

[0045] Vehicle B includes not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs / PHVs), or xEVs such as fuel cell electric vehicles (FCEVs / FCVs)).

[0046] The electronic devices described above can be applied to any of the electronic devices mounted on the vehicle B.

[0047] <Other> The above-described embodiments should be considered to be illustrative in all respects and not restrictive. The technical scope of the present disclosure is indicated by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0048] For example, the signal transmission devices 101 and 102 may not include the amplifier 1. Furthermore, for example, the receiving unit 6 may not include the high-pass filter circuits 61 and 62 and the envelope circuits 63 and 64.

[0049] <Additional Notes> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0050] The signal transmission device (101) of the present disclosure has a configuration (first configuration) including a transmitting unit (4) configured to generate and transmit a first transmission signal and a second transmission signal corresponding to a first clock signal and a first data signal synchronized with the first clock signal, an isolator (5) configured to transmit the first transmission signal and the second transmission signal in an isolated manner as a first reception signal and a second reception signal, respectively, and a receiving unit (6) configured to receive the first reception signal and the second reception signal, generate a second clock signal corresponding to the first reception signal and the second reception signal, and generate a second data signal corresponding to the first reception signal and the second reception signal.

[0051] The signal transmission device of the first configuration described above is configured to simultaneously transmit a clock signal and a data signal by transmitting the first transmission signal and the second transmission signal, and therefore can use a single isolator system for transmitting the first transmission signal and the second transmission signal. Therefore, the signal transmission device of the first configuration described above can suppress increases in current consumption, EMI, and mounting area due to clock signal transmission, compared to a signal transmission device configured with two isolators (isolators 5A and 5B) for transmitting clock signals and data signals.

[0052] In the signal transmission device of the first configuration, the second clock signal may have a pulse corresponding to one edge of the first clock signal (second configuration).

[0053] In the signal transmission device of the first or second configuration, the interval between edges of the second data signal may be the same as the interval between edges of the first data signal (third configuration).

[0054] The signal transmission device of any of the first to third configurations may be configured (fourth configuration) to include a signal processing unit (7) configured to perform signal processing on the second data signal based on the second clock signal.

[0055] The signal transmission device of any of the first to fourth configurations may be configured (fifth configuration) to include an AD converter (2) configured to AD convert an input signal or an analog signal based on the input signal based on the first clock signal to generate the first data signal.

[0056] In the signal transmission device of any of the above first to fifth configurations, the first transmission signal may be a signal having an edge indicating that the first data signal is at a first level at the timing when one edge of the first clock signal appears, and the second transmission signal may be a signal having an edge indicating that the first data signal is at a second level at the timing when the one edge of the first clock signal appears (sixth configuration).

[0057] In the signal transmission device of the sixth configuration, the receiving unit may be configured to generate the second clock signal in accordance with each edge of the first received signal and the second received signal (seventh configuration).

[0058] In the signal transmission device of the seventh configuration, the receiving section may be configured (eighth configuration) to include an adjustment circuit (69) configured to adjust the pulse width of the second clock signal.

[0059] In the signal transmission device of any of the first to eighth configurations above, the receiving unit may be configured (ninth configuration) to include a latch circuit (67) configured to be set by the first receiving signal or a signal based on the first receiving signal, and to be reset by the second receiving signal or a signal based on the second receiving signal.

[0060] The signal transmission device of any of the first to ninth configurations may be configured (tenth configuration) to include a detection circuit (DET1) configured to detect a state in which a pulse of the second clock signal is not generated.

[0061] The electronic device (A) of the present disclosure may have a configuration (eleventh configuration) including a signal transmission device having any one of the first to tenth configurations.

[0062] The vehicle (B) of the present disclosure has a configuration (twelfth configuration) that includes the electronic device of the eleventh configuration. [Explanation of symbols]

[0063] 1 amplifier 2 AD converters 3. Oscillators 4, 4A, 4B Transmitter 5, 5A, 5B Isolators 6, 6A, 6B Receiver 7 Digital filter circuit 8 Current DA Converter 9 IV conversion section 41, 42 AND gate 43, 44 Driver circuit 51, 52 Pulse transformer 61, 62 High-pass filter circuit 63, 64 Envelope circuit 65, 66 Comparator 67 SR latch circuit 68 OR gate 69 Adjustment circuit 100 Signal transmission device according to comparative example 101 Signal transmission device according to an embodiment 102 Signal transmission device according to modified example 200 Signal Processing Device A Electronic equipment B vehicle DET1 detection circuit

Claims

1. a transmitter configured to generate and transmit a first transmission signal and a second transmission signal in response to a first clock signal and a first data signal synchronized with the first clock signal; an isolator configured to insulate and transmit the first transmission signal and the second transmission signal as a first reception signal and a second reception signal, respectively; a receiving unit configured to receive the first received signal and the second received signal, generate a second clock signal corresponding to the first received signal and the second received signal, and generate a second data signal corresponding to the first received signal and the second received signal.

2. 2. The signal transmission device according to claim 1, wherein the second clock signal has a pulse corresponding to one edge of the first clock signal.

3. 2. The signal transmission device according to claim 1, wherein the interval between edges of the second data signal is the same as the interval between edges of the first data signal.

4. The signal transmission device according to claim 1 , further comprising a signal processing unit configured to perform signal processing on the second data signal based on the second clock signal.

5. 2. The signal transmission device according to claim 1, further comprising an AD converter configured to perform AD conversion of an input signal or an analog signal based on the input signal based on the first clock signal to generate the first data signal.

6. the first transmission signal is a signal having an edge indicating that the first data signal is at a first level at the timing of appearance of one edge of the first clock signal; 2. The signal transmission device according to claim 1, wherein the second transmission signal is a signal having an edge indicating that the first data signal is at a second level at the timing when the edge on one side of the first clock signal appears.

7. The signal transmission device according to claim 6 , wherein the receiving section is configured to generate the second clock signal in response to each edge of the first received signal and the second received signal.

8. The signal transmission device according to claim 7 , wherein the receiver comprises an adjustment circuit configured to adjust a pulse width of the second clock signal.

9. 2. The signal transmission device according to claim 1, wherein the receiving unit comprises a latch circuit configured to be set by the first received signal or a signal based on the first received signal, and to be reset by the second received signal or a signal based on the second received signal.

10. 2. The signal transmission device according to claim 1, further comprising a detection circuit configured to detect a state in which a pulse of the second clock signal is not generated.

11. An electronic device comprising the signal transmission device according to any one of claims 1 to 10.

12. A vehicle comprising the electronic device according to claim 11.

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