Reservoir computer and control method of reservoir computer

Abstract

To provide a reservoir computer that includes a gate voltage generation circuit for generating a triangular wave and can control a polarization state and a charge trap state.SOLUTION: A reservoir computer is provided, comprising a semiconductor device including a gate electrode connected to a gate voltage generation circuit that generates gate voltage in the form of a triangular wave with positive and negative voltages. The gate voltage generation circuit includes a pulse generator that generates a triangular wave on the basis of input data, a charge pump circuit for applying positive voltage, a reference voltage regulator, and a charge pump circuit for applying negative voltage.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to a reservoir computer and a method for controlling a reservoir computer. [Background technology]

[0002] Patent Document 1 describes a semiconductor device equipped with a ferroelectric memory cell. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-161307 Summary of the Invention [Problem to be solved by the invention]

[0004] However, when using related semiconductor devices, there is a problem in that the polarization state and the charge trap state are not controlled. Therefore, an object of the present disclosure is to provide a reservoir computer that includes a gate voltage generation circuit that generates a triangular wave and can control the polarization state and the charge trap state.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] According to one embodiment, the reservoir computer is configured with a semiconductor device having a gate electrode connected to a gate voltage generating circuit that generates a gate voltage that is a triangular wave having positive and negative voltages. [Effects of the Invention]

[0007] According to the embodiment, it is possible to provide a reservoir computer that includes a gate voltage generating circuit that generates a triangular wave and that can control the polarization state and the charge trap state. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 2 is a diagram illustrating a reservoir computer according to an embodiment. [Figure 2] 1A and 1B are diagrams illustrating the polarization state and charge trap state of a reservoir computer according to an embodiment. [Figure 3] 10 is a flowchart illustrating a control method of a reservoir computer according to an embodiment. [Figure 4] FIG. 1 is a diagram illustrating the configuration of a reservoir computer including an FeFET having AlN according to an embodiment. [Figure 5] FIG. 2 is a diagram illustrating details of a gate voltage generating circuit of a reservoir computer according to an embodiment. [Figure 6] FIG. 1 is a first diagram illustrating measurement of charge traps by the PUND method according to an embodiment. [Figure 7] FIG. 10 is a second diagram illustrating measurement of charge traps by the PUND method according to the embodiment. [Figure 8] FIG. 10 is a diagram illustrating optimization of a voltage pulse width according to an embodiment. [Figure 9] FIG. 10 is a diagram illustrating the nonlinear interaction between polarization and charge traps in an FeFET with AlN and an FeFET without AlN according to an embodiment. [Figure 10] FIG. 10 is a diagram showing a comparative example of data retention characteristics (STM (Short Term Memory)) of an FeFET having AlN according to an embodiment and in which a control method is optimized, and an FeFET not having AlN. DETAILED DESCRIPTION OF THE INVENTION

[0009] For clarity of explanation, the following description and drawings have been omitted and simplified as appropriate. Furthermore, each element shown in the drawings as a functional block performing various processes can be configured, for example, in hardware terms by a CPU (Central Processing Unit), memory, or other circuits, and in software terms by a program loaded into memory. Therefore, these functional blocks can be realized by hardware, software running on hardware, or a combination thereof. In addition, the same elements are designated by the same reference numerals in each drawing, and redundant explanations are omitted as necessary.

[0010] The above-described program can be stored and supplied to a computer using various types of non-transitory computer-readable media. Non-transitory computer-readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic storage media (e.g., flexible disks, magnetic tapes, hard disk drives), magneto-optical storage media (e.g., magneto-optical disks), CD-ROMs (Read Only Memory), CD-Rs, CD-R / Ws, and semiconductor memories (e.g., mask ROMs, PROMs (Programmable ROMs), EPROMs (Erasable PROMs), flash ROMs, and RAMs (Random Access Memory)). The program can also be supplied to a computer by various types of transitory computer-readable media. Examples of transitory computer-readable media include electrical signals, optical signals, and electromagnetic waves. The transitory computer-readable media can supply the program to a computer via a wired communication path such as an electric wire or optical fiber, or via a wireless communication path.

[0011] (Description of Reservoir Computer and Problems According to the Embodiment) Fig. 1 is a diagram illustrating a reservoir computer according to an embodiment. Fig. 2 is a diagram illustrating a polarization state and a charge trap state of the reservoir computer according to an embodiment. The reservoir computer according to the embodiment and the problems will be described with reference to Figs. 1 and 2.

[0012] As shown in FIG. 1, the reservoir computer system 100 includes a preprocessing unit 101, a reservoir computer 102, and a readout circuit 103. The original data may be audio, images, or bit strings. By inputting this original data to the preprocessing unit 101, a gate voltage is input multiple times to a node of a semiconductor device, a ferroelectric field effect transistor (FeFET). The reservoir computer 102 is an assembly of multiple FeFETs. The FeFET includes a gate, a drain, a source, and a back. The drain and source are formed in a semiconductor layer. The back is formed between the source and drain. The back is, for example, a P-type well region. The back is, for example, at the same potential as the source. The FeFET includes a stack of a paraelectric film and a ferroelectric film between a gate electrode and a semiconductor layer.

[0013] The source is grounded. For example, input data, Input 1, is input to Node 1 of the gate electrode, and a voltage is applied to the drain, resulting in a drain current of 1 between the source and drain. Here, Input 1 is the gate voltage input count. The FeFET with Node 1 indicates reservoir state 1 by drain current 1.

[0014] Similarly, drain current 2 is detected by inputting input data, input 2, to node 2 of the gate electrode. An FeFET with node 2 indicates reservoir state 2 with drain current 2. The same applies to an FeFET with input 3. The states that can be stored vary depending on the number of cells in the FeFET.

[0015] The state of the reservoir computer is read out by the readout circuit 103 by detecting the drain currents 1, 2, 3 . . .

[0016] As shown in Figure 2, the internal state of the FeFET can be divided into the polarization state of the ferroelectric film and the charge trap state. Due to this polarization state and charge trap state, the drain current exhibits hysteresis with respect to the gate voltage and does not change linearly. This allows the FeFET to have a memory function.

[0017] The performance of a reservoir computer, such as the realization of complex tasks or recognition rate, depends on the performance of the physical reservoir. In conventional FeFETs, the amount of information that one cell can process, known as the memory capacity (MC), is small, so it is necessary to increase the number of data inputs to the reservoir and the number of FeFET cells used in the reservoir. This results in problems such as increased area, inference speed, and power consumption.

[0018] In particular, the control method for the reservoir computer of the related FeFET controls the internal state of the reservoir by applying a sufficiently large voltage to change the polarization state. This method focuses on the polarization state that determines the internal state of the FeFET and the charge trap state, but does not control the charge traps related to nonlinearity.

[0019] (Description of a reservoir computer control method according to an embodiment) 3 is a flowchart showing a control method of a reservoir computer according to an embodiment. The control method of a reservoir computer according to an embodiment will be described with reference to FIG.

[0020] As shown in Figure 3, we first use the PUND (Positive Up Negative Down) method to investigate the voltages Vh and Vl at which polarization reversal and charge detrapping occur. The PUND method is a method for measuring the voltages at which polarization reversal and charge detrapping occur, and will be described in detail later.

[0021] Next, the maximum amplitude of the gate voltage is set to Vh and Vl. The maximum voltage Vh and minimum voltage Vl of the gate voltage are determined based on the results of the PUND method.

[0022] Next, the voltage pulse width Tp is optimized to maximize the current separation relative to the input history. The time width of the voltage pulse is adjusted to maximize the responsiveness to the input history.

[0023] By determining the gate voltage input conditions in this way, the effects of polarization and charge trapping become more pronounced.

[0024] (Description of a Gate Voltage Generation Circuit of a Reservoir Computer According to an Embodiment) Fig. 4 is a configuration diagram of a reservoir computer including an FeFET having AlN according to an embodiment. Fig. 5 is a diagram showing details of a gate voltage generation circuit of the reservoir computer according to an embodiment. The gate voltage generation circuit of the reservoir computer according to an embodiment will be described with reference to Figs. 4 and 5.

[0025] As shown in Figure 4, the FeFET preferably includes HZO (Hafnium Zirconium Oxide), a ferroelectric film having Al (Aluminum) or AlN (Aluminum Nitride), as the charge storage layer. The polarization capacity can be further increased by using an HZO film doped with Al or ALN as the charge storage layer. The ferroelectric film is disposed between the gate electrode and a paraelectric film, which is an interlayer (IL).

[0026] A gate voltage based on binary data consisting of 0 or 1 is generated by a gate voltage generation circuit. As shown in the right diagram of Figure 4, the gate voltage waveform is a triangular wave with positive and negative voltages. The gate voltage has a maximum value Vh and a minimum value Vl. A sense circuit connected to the drain detects the drain current.

[0027] 5, the gate voltage generating circuit 501 includes a charge pump circuit 502 that applies a positive voltage, a pulse generator 503, a Vref regulator 504, and a charge pump circuit 505 that applies a negative voltage. The Vref regulator has a function of adjusting the reference voltage Vref.

[0028] As shown in (a) on the right side of Fig. 5, when data is input, pulse generator 503 generates a triangular pulse. As shown in (b) on the right side of Fig. 5, a desired gate voltage is obtained when charge pump circuit 502, which applies a positive voltage to the triangular wave output from pulse generator 503, pulse generator 503, Vref regulator 504, and charge pump circuit 505, which applies a negative voltage, operate. The desired gate voltage is, for example, a triangular wave with a maximum value of 4V and a minimum value of -2V, with 1V as the reference.

[0029] With this configuration, it is possible to provide a reservoir computer that includes a gate voltage generating circuit that generates a triangular wave and that can control the polarization state and the charge trap state.

[0030] (Description of the PUND Act According to an Embodiment) Fig. 6 is a first diagram illustrating measurement of charge traps by the PUND method according to the embodiment. Fig. 7 is a second diagram illustrating measurement of charge traps by the PUND method according to the embodiment. The PUND method according to the embodiment will be described with reference to Figs. 6 and 7.

[0031] The upper diagram in Figure 6 shows the relationship between gate current and gate voltage. As shown in Figure 6, when Vh is applied to the gate electrode, polarization A and electrons induced by charge trapping are generated. When a negative voltage is applied to the gate electrode, detrapping of unstable charges B occurs. Furthermore, when a negative voltage is applied, polarization C and detrapping of charges occur.

[0032] The maximum gate voltage, Vh, is the voltage at which sufficient polarization reversal occurs. The minimum gate voltage, Vl, is the voltage at which charge trapping occurs. Therefore, Vh is set to a voltage that is 1V higher than the voltage at A to cause sufficient polarization reversal. Vl is set to the voltage at B at which charge trapping occurs. By setting an appropriate gate voltage, the polarization reversal and charge trapping phenomena can be controlled.

[0033] As shown in the upper right diagram of Figure 7, the PUND method is a technique that can measure the amount of polarization generated in the ferroelectric at each gate voltage and the amount of unstable charge traps by inputting two gate voltages and measuring the amount of charge from the gate current.

[0034] By inputting two triangular waves of the same voltage and pulse width shown as (1), (1)', (2), and (2)' and calculating the difference in the gate current that flows when the two voltage pulses are applied, the amount of charge change due to polarization and charge trapping can be calculated, excluding the contribution of gate leakage current.

[0035] Furthermore, by providing a wait period before applying charge, the amount of charge can be calculated without the contribution of charge traps. This is because charge traps are detrapped during the wait period. In other words, by measuring with and without a wait period in the PUND method, the charge change due to charge traps and the charge change due to polarization can be measured separately.

[0036] (Explanation of Optimization of Voltage Pulse Width According to an Embodiment) 8 is a diagram showing the optimization of the voltage pulse width according to the embodiment, with reference to which the optimization of the voltage pulse width according to the embodiment will be described.

[0037] As shown in Figure 8, the voltage pulse width Tp of the gate voltage is set to a value that increases the current separation depending on the past history. If the pulse width is too short, the polarization reversal and charge trapping of the FeFET may not occur. If the pulse width is too long, polarization saturation and excessive polarization trapping may occur.

[0038] By selecting an appropriate pulse width, the balance between polarization reversal and charge trapping can be optimized, improving the reservoir's hysteresis response. Figure 8 shows a graph of drain current Id versus time. As shown in Figure 8, the pulse width that produces the largest Id difference or the largest area difference can be selected.

[0039] (Example description of AlN-doped FeFET) Fig. 9 is a diagram showing the nonlinear interaction between polarization and charge traps in an FeFET doped with AlN according to an embodiment and an FeFET not doped with AlN. Fig. 10 is a diagram showing a comparison example of the data retention characteristics (STM (Short Term Memory)) of an FeFET doped with AlN according to an embodiment and having an optimized control method, and an FeFET not doped with AlN. An example of an FeFET doped with AlN will be described with reference to Figs. 9 and 10.

[0040] As shown in Figure 9, the AlN-containing FeFET exhibits increased polarization compared to the non-AlN-containing FeFET. Furthermore, when the AlN-containing FeFET is operated under appropriate gate input conditions, the number of reservoir states increases, improving reservoir performance. Furthermore, the nonlinear interaction between polarization and charge trapping increases, enhancing the reservoir nonlinearity and improving reservoir performance.

[0041] As shown in FIG. 10, an FeFET (Optimized) with AlN and an appropriate gate voltage applied has a larger STM (Short Term Memory) than an FeFET without AlN. The FeFET according to the embodiment improves MC(STM) from 2.2 to 3.2. Therefore, a reservoir computer using an FeFET with AlN and an appropriate gate voltage applied can reduce the number of inputs to two-thirds. Therefore, the reservoir computer of the present disclosure can reduce power consumption and inference time by two-thirds compared to related technologies.

[0042] The invention made by the inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible within the scope of the gist of the invention. [Explanation of symbols]

[0043] 100 reservoir computer system, 101 preprocessing, 102 reservoir computer, 103 readout circuit, 501 gate voltage generation circuit, 502 charge pump circuit for applying positive voltage, 503 pulse generator, 504 Vref regulator, 505 charge pump circuit for applying negative voltage

Claims

1. A reservoir computer is configured with a semiconductor device having a gate electrode connected to a gate voltage generating circuit that generates a gate voltage that is a triangular wave having positive and negative voltages.

2. 2. The reservoir computer according to claim 1, wherein the gate voltage generating circuit comprises a pulse generator that generates a triangular wave based on input data, a charge pump circuit that applies a positive voltage, a Vref regulator, and a charge pump circuit that applies a negative voltage.

3. 2. The reservoir computer according to claim 1, wherein the positive voltage Vh at which sufficient polarization reversal of the semiconductor device occurs and the negative voltage Vl at which charge detrapping occurs are determined using a PUND (Positive Up Negative Down) method.

4. 4. The reservoir computer according to claim 3, wherein the gate voltage is applied to the gate electrode with Vh as a maximum voltage and Vl as a minimum voltage.

5. 2. The reservoir computer according to claim 1, wherein a time width Tp of the triangular wave of said gate voltage is determined so as to maximize responsiveness to an input history.

6. 2. The reservoir computer according to claim 1, wherein the semiconductor device is a FeFET (Ferroelectric Field Effect Transistor) using HZO (Hafnium Zirconium Oxide) having Al or AlN in a charge storage layer.

7. A control method for a reservoir computer configured with a semiconductor device having a gate electrode connected to a gate voltage generating circuit that generates a gate voltage that is a triangular wave having positive and negative voltages.

8. 8. The reservoir computer control method according to claim 7, wherein the gate voltage generating circuit comprises: a pulse generator that generates a triangular wave based on input data; a charge pump circuit that applies a positive voltage; a Vref regulator; and a charge pump circuit that applies a negative voltage.

9. 8. The reservoir computer control method according to claim 7, wherein the positive voltage Vh at which sufficient polarization reversal of the semiconductor device occurs and the negative voltage Vl at which charge detrapping occurs are determined using a PUND (Positive Up Negative Down) method.

10. 10. The reservoir computer control method according to claim 9, wherein the gate voltage is applied to the gate electrode with Vh as a maximum voltage and Vl as a minimum voltage.

11. 8. The reservoir computer control method according to claim 7, wherein the time width Tp of the triangular wave of the gate voltage is determined so as to maximize responsiveness to an input history.

12. 8. The reservoir computer control method according to claim 7, wherein the semiconductor device is an FeFET (Ferroelectric Field Effect Transistor) using HZO (Hafnium Zirconium Oxide) having Al or AlN in a charge storage layer.

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