Switching circuit

Abstract

To suppress a change in a generation loss in a transistor, which may occur due to an action of a current collapse.SOLUTION: A switching circuit (1) includes a driver (20) that turns on a target transistor (10) by supplying an ON voltage (Von) to a gate of the target transistor and turns off the target transistor by supplying an OFF voltage (Voff) to the gate of the target transistor, and a voltage adjustment circuit (30) that suppresses a change in an ON resistance (Ron) of the target transistor by adjusting the ON voltage based on a drain-source voltage (Vds) of the target transistor and a drain current (Id) of the target transistor in an ON period of the target transistor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to switching circuits. [Background technology]

[0002] Switching circuits having switching transistors are mounted on various devices (see, for example, Patent Document 1 below). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2021 / 054027

[0004] [overview] In a switching circuit, a change in the on-resistance of a switching transistor causes a change in the loss generated in the switching transistor and in the efficiency of the switching circuit, which is undesirable.

[0005] A switching circuit according to one aspect of the present disclosure includes a target transistor having a drain, a source, and a gate; a driver configured to turn on the target transistor by supplying an on-voltage to the gate of the target transistor and to turn off the target transistor by supplying an off-voltage to the gate of the target transistor; and a voltage adjustment circuit configured to suppress changes in the on-resistance of the target transistor by adjusting the on-voltage based on the drain-source voltage of the target transistor and the drain current of the target transistor during an on-period of the target transistor. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is an overall configuration diagram of a circuit system according to an embodiment of the present disclosure. [Figure 2]FIG. 2 is a waveform diagram of a control signal and a gate voltage of a target transistor according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is a diagram illustrating the adjustment range of the on-voltage according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is an operation flowchart of the switching circuit according to an embodiment of the present disclosure. [Figure 5] FIG. 5 is a diagram illustrating a configuration example of a voltage detection circuit according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is a diagram showing another configuration example of the voltage detection circuit according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is a diagram illustrating a configuration example of a voltage adjustment circuit according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a diagram illustrating another configuration example of a voltage adjustment circuit according to an embodiment of the present disclosure. [Figure 9] FIG. 9 is a flowchart illustrating a modified operation of the switching circuit according to an embodiment of the present disclosure. [Figure 10] FIG. 10 is a diagram illustrating the overall configuration of a switching power supply device according to an embodiment of the present disclosure. [Figure 11] FIG. 11 is an external perspective view of a power supply control device according to an embodiment of the present disclosure. [Figure 12] FIG. 12 is a waveform diagram of two control signals generated within a power supply control device according to an embodiment of the present disclosure. [Figure 13] FIG. 13 is a diagram illustrating an example of the configuration of a current detection circuit in a power supply control device according to an embodiment of the present disclosure. [Figure 14] FIG. 14 is a diagram illustrating another configuration example of a current detection circuit in a power supply control device according to an embodiment of the present disclosure.

[0007] [Detailed explanation] Hereinafter, examples of embodiments of the present disclosure will be described in detail with reference to the drawings. In each of the drawings, identical parts are designated by the same reference numerals, and redundant descriptions of identical parts will be omitted as a general rule. For the sake of simplicity, the present specification may use symbols or signs referring to information, signals, physical quantities, functional units, circuits, elements, or components, and may omit or abbreviate the names of the information, signals, physical quantities, functional units, circuits, elements, or components corresponding to the symbols or signs. For example, the target transistor referred to by "10" below (see FIG. 1) may be written as target transistor 10 or abbreviated as transistor 10, but these all refer to the same thing.

[0008] First, some terms used in describing the embodiments of the present disclosure will be explained. Ground refers to a reference conductor having a reference potential of 0V (zero volts), or refers to the 0V potential itself. The reference conductor may be formed using a conductor such as metal. The 0V potential is sometimes referred to as ground potential. In the embodiments of the present disclosure, a voltage indicated without a particular reference represents a potential seen from ground. Level refers to the level (height) of the potential.

[0009] For any transistor configured as a FET (field-effect transistor), such as a MOSFET or HEMT, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, MOSFETs are understood to be enhancement-type MOSFETs. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." Also, unless otherwise specified, the back gate of any MOSFET can be considered shorted to the source. HEMT is an abbreviation for "High Electron Mobility Transistor."

[0010] Any switch can be constituted by one or more FETs (field effect transistors). When a certain switch is in the on state, the two ends of the switch are conductive, while when a certain switch is in the off state, the two ends of the switch are non-conductive. Hereinafter, for any transistor or switch, the on state and the off state may also be simply expressed as on and off. For any transistor or switch, the period during which the transistor or switch is in the on state is referred to as the on period, and the period during which the transistor or switch is in the off state is referred to as the off period.

[0011] The connection between a plurality of parts forming a circuit, such as any circuit element, wiring, node, etc., may be understood to refer to an electrical connection unless otherwise specified.

[0012] When any two voltages to be compared are voltage v1 and v2, "v1>v2" represents that voltage v1 is higher than voltage v2, "v1<v2" represents that voltage v1 is lower than voltage v2, and "v1=v2" represents that the value of voltage v1 is the same as the value of voltage v2. The same applies to other expressions including physical quantities other than voltage.

[0013] FIG. 1 shows an overall configuration diagram of a circuit system SYS according to the present embodiment. The circuit system SYS includes a switching circuit 1, a target circuit 2, a controller 3, and an external device 4. The switching circuit 1 includes a target transistor 10, a driver 20, a voltage adjustment circuit 30, a voltage detection circuit 40, and a current detection circuit 50.

[0014] The switching circuit 1 operates based on the power supply voltage VDD. The power supply voltage VDD has a predetermined positive DC voltage value higher than the source potential of the target transistor 10. The switching circuit 1 may be connected to the ground, and the source potential of the target transistor 10 may be the ground potential.

[0015] The target transistor 10 is a switching element (switching transistor) made of a semiconductor. The semiconductor material forming the target transistor 10 is GaN (gallium nitride). The target transistor 10 is a HEMT (High Electron Mobility Transistor) having a drain, a source, and a gate. The drain and source of the target transistor 10 are connected to a target circuit 2. The drain current of the target transistor 10 is hereinafter referred to as the drain current Id or simply the current Id. The drain current Id may flow from the drain to the source of the target transistor 10, or may flow from the source to the drain of the target transistor 10. The drain-source voltage of the target transistor 10 is hereinafter referred to as the drain-source voltage Vds or simply the voltage Vds. The drain-source voltage Vds represents the voltage of the drain of the target transistor 10 relative to the source potential of the target transistor 10. The gate-source voltage of the target transistor 10 is hereinafter referred to as the gate-source voltage Vgs or simply the voltage Vgs. The gate-source voltage Vgs represents the voltage of the gate of the target transistor 10 as viewed from the source potential of the target transistor 10. The voltage of the gate of the target transistor 10 will hereinafter be referred to as the gate voltage Vg. The gate voltage Vg represents the voltage of the gate of the target transistor 10 as viewed from the ground potential. The source of the target transistor 10 may be connected to ground or may be connected to a node having a potential other than 0V. When the source of the target transistor 10 is connected to ground, the gate voltage Vg is equal to the gate-source voltage Vgs.

[0016] The target circuit 2 includes at least a circuit that supplies a drain current Id to the target transistor 10 and a circuit that supplies a voltage Vds to the target transistor 10, and may also include various other circuits. In any case, the drain current Id flows through the target transistor 10 and the target circuit 2. The target circuit 2 may also be connected to ground.

[0017] The controller 3 is connected to ground and operates based on a power supply voltage having a predetermined positive DC voltage value with respect to the ground potential or the source potential of the target transistor 10. The controller 3 supplies a control signal Scnt to the switching circuit 1. The control signal Scnt is a binary signal having a value of "1" or "0," and the value of the control signal Scnt is determined by the level of the control signal Scnt. Here, it is assumed that the controller 3 is provided separately from the switching circuit 1, but the controller 3 may also be considered to be included as a component of the switching circuit 1. The value of any binary signal is expressed by the voltage (level) of the binary signal. For example, when the control signal Scnt has a voltage of 5V (volts), the control signal Scnt has a value of "1," and when the control signal Scnt has a voltage of 0V (volts), the control signal Scnt has a value of "0" (or vice versa). The same applies to binary signals other than the control signal Scnt.

[0018] The external device 4 is a microcomputer or the like that is provided outside the switching device 1. The external device 4 is connected to ground and operates based on a power supply voltage that has a predetermined positive DC voltage value with respect to the ground potential or the source potential of the target transistor 10. The external device 4 has a terminal that receives the signal Salt output from the switching circuit 1. Like the control signal Scnt, the signal Salt is a binary signal that has a value of "1" or "0," and the value of the signal Salt is determined by the level of the signal Salt.

[0019] The driver 20 is connected to a wiring WRh to which an on-voltage Von is applied, a wiring WRs to which an off-voltage Voff lower than the on-voltage Von is applied, and a gate wiring WRg. The gate wiring WRg is connected to the gate of the target transistor 10. Therefore, the voltage on the gate wiring WRg is the gate voltage Vg. The wiring WRs is connected to the source of the target transistor 10. Therefore, the voltage on the wiring WRs (i.e., the off-voltage Voff) is the voltage at the source of the target transistor 10. The gate threshold voltage of the target transistor 10 is called the gate threshold voltage Vth. The on-voltage Von is higher than the voltage that is higher than the source potential of the target transistor 10 by the gate threshold voltage Vth. Therefore, when the gate voltage Vg is equal to the on-voltage Von, the gate-source voltage Vgs is higher than the gate threshold voltage Vth, and the target T10 is on. On the other hand, when the gate voltage Vg is equal to the turn-off voltage Voff, the gate-source voltage Vgs is 0 V, which is lower than the gate threshold voltage Vth, and the target transistor 10 is therefore turned off.

[0020] A control signal Scnt is supplied from the controller 3 to the driver 20. When the control signal Scnt has a value of "1", the driver 20 supplies an on-voltage Von to the gate of the target transistor 10 (i.e., sets the on-voltage Von to the gate voltage Vg), thereby setting the target transistor 10 to an on state. When the control signal Scnt has a value of "0", the driver 20 supplies an off-voltage Voff to the gate of the target transistor 10 (i.e., sets the off-voltage Voff to the gate voltage Vg), thereby setting the target transistor 10 to an off state.

[0021] The voltage adjustment circuit 30 is connected to the wirings WRH and WRs, generates an on-voltage Von based on the source potential of the target transistor 10, and outputs it to the wiring WRH. The voltage adjustment circuit 30 has a function of adjusting the on-voltage Von based on a voltage detection signal Svd and a current detection signal Sid from the voltage detection circuit 40 and the current detection circuit 50 (details will be described later). The control signal Scnt from the controller 3 is also supplied to the voltage adjustment circuit 30.

[0022] The voltage detection circuit 40 is connected to the drain and source of the target transistor 10. The voltage detection circuit 40 detects the drain-source voltage Vds of the target transistor 10 during the on-period of the target transistor 10, and outputs a voltage detection signal Svd indicating the detection result to the voltage adjustment circuit 30. The voltage detection signal Svd indicates a voltage value |Vds|. The voltage value |Vds| indicated by the voltage detection signal Svd is the detection value of the drain-source voltage Vds by the voltage detection circuit 40, and indicates the magnitude (absolute value) of the drain-source voltage Vds of the target transistor 10.

[0023] The current detection circuit 50 has a sense resistor (not shown) inserted in series with the flow path of the drain current Id, and detects the drain current Id based on the voltage drop across the sense resistor during the on-period of the target transistor 10. The insertion position of the sense resistor is arbitrary as long as the drain current Id flows through the sense resistor. For example, the sense resistor may be inserted in series with the source or drain of the target transistor 10. The current detection circuit 50 outputs a current detection signal Sid indicating the detection result of the drain current Id to the voltage adjustment circuit 30. The current detection signal Sid indicates a current value |Id|. The current value |Id| indicated by the current detection signal Sid is the detection value of the drain current Id by the current detection circuit 50 and indicates the magnitude (absolute value) of the drain current Id of the target transistor 10.

[0024] Referring to FIG. 2 , the controller 3 controls the switching of the target transistor 10. In controlling the switching of the target transistor 10, the controller 3 alternately and repeatedly sets the value of the control signal Scnt to “1” and “0” to alternately and repeatedly turn the target transistor 10 on and off using the driver 20. A frame is a period from when the value of the control signal Scnt changes from “0” to “1” to immediately before the value of the control signal Scnt changes from “0” to “1” again. One frame includes one period during which the value of the control signal Scnt is “1” (i.e., the on-period of the target transistor 10) and one period during which the value of the control signal Scnt is “0” (i.e., the off-period of the target transistor 10). The lengths of multiple consecutive frames may all be the same, in which case each frame has a length equal to the reciprocal of the switching frequency of the target transistor 10. Alternatively, the lengths of multiple consecutive frames may differ from one another.

[0025] In each frame, the timing after a predetermined waiting time ΔT has elapsed since the value of the control signal Scnt changes from "0" to "1" is referred to as sampling time ts. In each frame, the sampling time ts belongs to the on-period of the target transistor 10. A lower limit is set for the length of the on-period of the target transistor 10 in each frame, and the waiting time ΔT is shorter than this lower limit. In each frame, the voltage adjustment circuit 30 samples the voltage detection signal Svd and the current detection signal Sid at the sampling time ts, thereby obtaining the voltage value |Vds| and the current value |Id| at the sampling time ts.

[0026] Generally, the on-resistance of a transistor made of GaN tends to increase over time during the period in which the transistor is switched due to the effect of current collapse. The on-resistance of the transistor also increases in conjunction with an increase in the temperature (junction temperature) of the transistor made of GaN. An increase in the on-resistance of a switching transistor increases the loss generated by the transistor.

[0027] In this embodiment, the change in the on-resistance of the target transistor 10 due to the effect of current collapse is suppressed by adjusting the on-voltage Von. Hereinafter, the on-resistance of the target transistor 10 will be referred to as on-resistance Ron. The on-resistance Ron is the resistance between the drain and source of the target transistor 10 during the on-period of the target transistor 10. More specifically, the on-resistance Ron is the resistance between the drain and source of the target transistor 10 during the period during which the on-voltage Von is supplied to the gate voltage Vg by the driver 20.

[0028] The target circuit 2 supplies a drain current Id to the target transistor 10 during the on-period of the target transistor 10, while applying a higher voltage to the drain of the target transistor 10 than to the source of the target transistor 10 during the off-period of the target transistor 10. If it is assumed that the on-voltage Von is fixed at a predetermined voltage during the period in which switching control of the target transistor 10 is continuously performed, then the on-resistance Ron may increase over time due to the effect of current collapse in the target transistor 10. However, even under the above assumption, the on-resistance Ron does not unconditionally increase indefinitely.

[0029] The voltage adjustment circuit 30 determines the on-resistance Ron of the target transistor 10 based on the voltage detection signal Svd and the current detection signal Sid during the on-period of the target transistor 10, and performs a process (hereinafter referred to as the voltage adjustment process) to adjust the on-voltage Von so that the on-resistance Ron is kept approximately constant. Referring to FIG. 3, the voltage adjustment circuit 30 adjusts the on-voltage Von within a predetermined voltage adjustment range RNG. The voltage adjustment range RNG ranges from a predetermined lower limit voltage Von_min to a predetermined upper limit voltage Von_max. The upper limit voltage Von_max is higher than the lower limit voltage Von_min. The lower limit voltage Von_min is even higher than the voltage that is higher than the source potential of the target transistor 10 by the gate threshold voltage Vth. In the following description, when the value of the on-resistance Ron is particularly noted, the resistance value of the on-resistance Ron will be referred to as the on-resistance value Ron. The symbol "Ron" in the formula indicates the resistance value of the on-resistance Ron.

[0030] FIG. 4 shows an operation flowchart of the switching circuit 1. The operation flow of the switching circuit 1, including the voltage adjustment process, will be described with reference to FIG. 4. After the target transistor 10 is maintained off for a sufficiently long time, the initial state of step S11 is reached. Alternatively, after the target transistor 10 is maintained off for a sufficiently long time, the initial state of step S11 is reached after multiple frames have passed. In either case, the control signal Scnt has a value of "0" in the initial state, and therefore the off voltage Voff is set relative to the gate voltage Vg. The on voltage Von in the initial state is referred to as the initial voltage Von_int. The initial voltage Von_int belongs to the voltage adjustment range RNG. The initial voltage Von_int is at least lower than the upper limit voltage Von_max. The initial voltage Von_int may be equal to the lower limit voltage Von_min. The value of the signal Salt in the initial state is "0." For ease of explanation, a variable j is introduced here. The variable j has an integer value. At step S11, j=1. It may be considered that the value of the variable j is managed by the voltage adjustment circuit 30. After step S11, the process proceeds to step S12.

[0031] In step S12, the driver 20 monitors whether the value of the control signal Scnt switches from "0" to "1," and if the value of the control signal Scnt switches from "0" to "1" (Y in step S12), the process proceeds to step S13. In step S13, in response to the switch in the value of the control signal Scnt from "0" to "1," the driver 20 switches the gate voltage Vg from the OFF voltage Voff to the ON voltage Von. This switches the state of the target transistor 10 from the OFF state to the ON state. Then, the process proceeds to step S14.

[0032] In step S14, the voltage adjustment circuit 30 samples the voltage detection signal Svd and the current detection signal Sid at sampling time ts to obtain the voltage value |Vds| and the current value |Id| at the sampling time ts, and determines the on-resistance value Ron[j] based on the obtained voltage value |Vds| and current value |Id|. After step S11, the process of step S14 is repeatedly executed, and the frame in which the process of step S14 is executed for the i-th time is referred to as the i-th frame (where i represents any natural number). Therefore, when "j=1," the process of step S14 is executed in the first frame, and the on-resistance value Ron[1] is the on-resistance value Ron of the first frame. Similarly, when "j=2," the process of step S14 is executed in the second frame, and the on-resistance value Ron[2] is the on-resistance value Ron of the second frame. The same applies to the state where "j≧3."

[0033] In this way, the on-resistance value Ron[j] indicates the on-resistance value Ron of the jth frame. The on-resistance value Ron[j] is expressed as the ratio "|Vds| / |Id|" of the voltage value |Vds| and the current value |Id| at the sampling timing ts of the jth frame. The on-resistance value Ron[1] can be considered as the initial value of the on-resistance value Ron. After step S14, proceed to step S15.

[0034] In step S15, it is confirmed whether the value of variable j is "1" (for example, this is confirmed by the voltage adjustment circuit 30). If "j=1" (Y in step S15), proceed to step S16, and if "j=1" is not (N in step S15), proceed to step S21.

[0035] In step S16, the reference resistance Rref is set by the voltage adjustment circuit 30. The resistance value of the reference resistance Rref is referred to as the reference resistance value Rref. Setting the reference resistance Rref and setting the reference resistance value Rref are synonymous. Here, it is assumed that the on-resistance value Ron[1], which is the initial value of the on-resistance value Ron, is set as the reference resistance value Rref. However, the reference resistance value Rref may be different from the on-resistance value Ron[1]. A predetermined resistance value may also be the reference resistance value Rref. After step S16, proceed to step S17.

[0036] In step S17, the driver 20 monitors whether the value of the control signal Scnt switches from "1" to "0", and if the value of the control signal Scnt switches from "1" to "0" (Y in step S17), the process proceeds to step S18. In step S18, in response to the switch of the value of the control signal Scnt from "1" to "0", the driver 20 switches the gate voltage Vg from the ON voltage Von to the OFF voltage Voff. This switches the state of the target transistor 10 from the ON state to the OFF state. Then, the process proceeds to step S19. In step S19, "1" is added to the value of the variable j (for example, by the voltage adjustment circuit 30), and then the process returns to step S12.

[0037] In step S21, the voltage adjustment circuit 30 compares the on-resistance value Ron[j] with the reference resistance value Rref to determine whether the first inequality "Ron[j]>Rref" is true. If the first inequality is true (i.e., if "Ron[j]>Rref" is true; Y in step S21), the process proceeds from step S21 to step S22. If the first inequality is false (i.e., if "Ron[j]>Rref" is not true; N in step S21), the process proceeds from step S21 to step S31. The first inequality may be "Ron[j]>Rref+ΔR", where ΔR represents a predetermined minute resistance value.

[0038] In step S22, the voltage adjustment circuit 30 determines whether the current on-voltage Von has reached the upper limit voltage Von_max. If the current on-voltage Von has not reached the upper limit voltage Von_max (i.e., if the current on-voltage Von is lower than the upper limit voltage Von_max; N in step S22), the process proceeds from step S22 to step S23. If the current on-voltage Von has reached the upper limit voltage Von_max (i.e., if the current on-voltage Von is equal to the upper limit voltage Von_max; Y in step S22), the process proceeds from step S22 to step S24.

[0039] In step S23, the voltage adjustment circuit 30 increases the on-voltage Von by a predetermined voltage ΔV within the voltage adjustment range RNG. Therefore, the on-voltage Von after the increase correction is higher by the predetermined voltage ΔV compared to the on-voltage Von before the increase correction. However, if a voltage higher than the on-voltage Von before the increase correction by the predetermined voltage ΔV exceeds the upper limit voltage Von_max of the voltage adjustment range RNG, the upper limit voltage Von_max is set for the on-voltage Von in step S23. After step S23, the process proceeds to step S17.

[0040] In step S24, the voltage adjustment circuit 30 determines whether the on-resistance value Ron[j] is greater than a predetermined alert resistance threshold Ralt. When "Ron[j]>Ralt" holds (Y in step S24), the process proceeds to step S25. In step S25, the voltage adjustment circuit 30 performs an alert process. In the alert process, the voltage adjustment circuit 30 switches the value of the signal Salt from "0" to "1". Thereafter, the value of the signal Salt may be maintained at "1" unless a predetermined reset condition is satisfied. The signal Salt with a value of "1" is an alert signal indicating that the on-resistance Ron of the target transistor 10 is excessive (an alert signal indicating "Ron>Ralt") and is transmitted to the external device 4. The signal Salt with a value of "0" does not function as an alert signal. After step S25, the process transitions to step S17. When "Ron[j]>Ralt" does not hold in step S24 (N in step S24), the process transitions to step S17 without performing the alert process.

[0041] In step S31, the voltage adjustment circuit 30 determines the validity of the second inequality "Ron[j]<Rref" by comparing the on-resistance value Ron[j] with the reference resistance value Rref. When the second inequality holds (that is, when "Ron[j]<Rref" holds; Y in step S31), the process proceeds from step S31 to step S32. On the other hand, when the second inequality does not hold (that is, when "Ron[j]<Rref" does not hold; N in step S31), the process transitions from step S31 to step S17. Note that the second inequality may be "Ron[j]<Rref - ΔR".

[0042] In step S32, the voltage adjustment circuit 30 determines whether the current on-voltage Von matches the lower limit voltage Von_min. When the current on-voltage Von does not match the lower limit voltage Von_min (that is, when the current on-voltage Von is higher than the lower limit voltage Von_min; N in step S32), the process proceeds from step S32 to step S33. When the current on-voltage Von matches the lower limit voltage Von_min (Y in step S32), the process transitions from step S32 to step S17.

[0043] In step S33, the voltage adjustment circuit 30 corrects the on-use voltage Von by a predetermined voltage ΔV within the voltage adjustment range RNG. Therefore, the on-use voltage Von after the correction is lower by the predetermined voltage ΔV compared to the on-use voltage Von before the correction. However, if the voltage lower than the on-use voltage Von before the correction by the predetermined voltage ΔV is lower than the lower limit voltage Von_min of the voltage adjustment range RNG, the lower limit voltage Von_min is set for the on-use voltage Von in step S33. After step S33, the process proceeds to step S17.

[0044] 4, the voltage adjustment process described above is realized by the processes of steps S12 to S19, steps S21 to S25, and steps S31 to S33. After the transition from step S11 to step S12, if the on-resistance Ron remains unchanged even if the on-voltage Von is constant, the process of steps S12 to S14 and S17 to S19 is repeated without transitioning to steps S22 and S32 (thus, with the on-voltage Von remaining unchanged).

[0045] However, in reality, if the on-voltage Von is maintained constant after the transition from step S11 to step S12, the on-resistance Ron may increase due to the action of current collapse as the process groups of steps S12 to S14 and S17 to S19 are repeated. If the on-resistance Ron increases as the process groups of steps S12 to S14 and S17 to S19 are repeated, the first inequality may be satisfied in step S21, and the on-voltage Von is increased in response to the first inequality being satisfied. An increase in the on-voltage Von during the on-period of the target transistor 10 decreases the on-resistance Ron. Depending on factors such as changes in the ambient temperature of the switching circuit 1, the second inequality may also be satisfied. If the second inequality is satisfied in step S31, the on-voltage Von is decreased in response to the second inequality being satisfied. A decrease in the on-voltage Von during the on-period of the target transistor 10 increases the on-resistance Ron.

[0046] In this way, if there is a difference between the on-resistance Ron and the reference resistance Rref, the voltage adjustment circuit 30 changes the on-voltage Von in a direction that reduces that difference. As a result, the difference between the on-resistance Ron and the reference resistance Rref is maintained near zero. This makes it possible to resist the effect of current collapse and suppress an increase in the on-resistance Ron and an increase in the loss generated in the target transistor 10.

[0047] However, there is an upper limit to the increase caused by adjusting the on-voltage Von. If the on-resistance Ron exceeds the alert resistance threshold Ralt even when the on-voltage Von is set to the upper limit voltage Von_max, the voltage adjustment circuit 30 outputs a signal Salt (alert signal) of “1” to the external device 4. This notifies the external device 4 that the on-resistance Ron of the target transistor 10 is excessive. The external device 4 receives the signal Salt of “1” and can take necessary corrective action. In this corrective action, the external device 4 can, for example, send a necessary command signal to the controller 3 to stop switching control of the target transistor 10, thereby preventing adverse effects caused by continuing switching control when the target transistor 10 generates excessive loss.

[0048] 5 shows the configuration of the voltage detection circuit 40. The voltage detection circuit 40 in FIG. 5 includes a voltage sensor 41 having a first input terminal and a second input terminal connected to the source of the target transistor 10, and a switch 42 inserted in series between the drain of the target transistor 10 and the first input terminal of the voltage sensor 41. The switch 42 is turned on only during the period when the control signal Scnt has a value of "1" (i.e., the on period of the target transistor 10), and the voltage Vds is applied between the first input terminal and the second input terminal of the voltage sensor 42. The voltage sensor 41 generates and outputs a voltage detection signal Svd that indicates the detected value of the voltage between the first input terminal and the second input terminal of the voltage sensor 42 (i.e., the voltage Vds).

[0049] Specifically, for example, the voltage detection circuit 40 may be a voltage detection circuit 40a shown in Fig. 6. The voltage detection circuit 40a includes a voltage sensor 43, a transistor 44, and a resistor 45. The transistor 44 is an N-channel MOSFET. The drain of the transistor 44 is connected to the drain of the target transistor 10, and the gate of the transistor 44 is connected to the gate of the target transistor 10. The source of the transistor 44 is connected to a first terminal of a resistor 45, and the second terminal of the resistor 45 is connected to the source of the target transistor 10. A first input terminal and a second input terminal of the voltage sensor 43 are connected to a first terminal and a second terminal of the resistor 45, respectively.

[0050] The transistor 44 is made of GaN (gallium nitride) like the target transistor 10. The transistors 10 and 44 are formed on the same semiconductor substrate and have the same structure. When an on-voltage Von is set relative to the gate voltage Vg, both the transistors 10 and 44 are on, and when an off-voltage Voff is set relative to the gate voltage Vg, both the transistors 10 and 44 are off. However, the source area of ​​the transistor 44 is much smaller than the source area of ​​the target transistor 10, and during the on-period of the target transistor 10, the transistor 44 has kΩ of the drain current Id of the target transistor 10. 44 The transistor 44 is formed so that a drain current that is twice as large as the target transistor 10 flows through it. That is, the magnitude of the drain current of the transistor 44 during the ON period of the target transistor 10 is (Id×k 44 ), where k has a predetermined positive value that is much smaller than 1 (for example, several thousandths to several hundredths). Therefore, if the resistance value of the resistor 45 is represented by the symbol "R45", a voltage drop (Id×k 44 ×R45) occurs, and the voltage sensor 43 detects a voltage drop (Id×k 44 ×R45), a voltage detection signal Svd indicating the detected value of the voltage Vds is generated and output. 44 ×R45) to configure the voltage sensor 43. In addition, any circuit configuration that can detect the voltage Vds may be applied to the voltage detection circuit 40.

[0051] FIG. 7 shows an example configuration of a voltage adjustment circuit 30. The voltage adjustment circuit 30a in FIG. 7 can be used as the voltage adjustment circuit 30 in FIG. 1. The voltage adjustment circuit 30a in FIG. 7 includes a voltage source 31a, an operational amplifier 32a, resistors 33a and 34a, and a control circuit 35a. The voltage source 31a supplies a voltage higher than the potential of the wiring WRs by a voltage Va to the non-inverting input terminal of the operational amplifier 32a. The voltage Va has a fixed voltage value. The output terminal of the operational amplifier 32a is connected to a first terminal of the resistor 33a, and the second terminal of the resistor 33a and the first terminal of the resistor 34a are commonly connected to the inverting input terminal of the operational amplifier 32a. The second terminal of the resistor 34a is connected to the wiring WRs. Therefore, the operational amplifier 32a and the resistors 33a and 34a form a non-inverting amplifier circuit, and a voltage determined by the resistance ratio between the resistors 33a and 34a and the voltage Va is output from the output terminal of the operational amplifier 32a. When the voltage adjustment circuit 30a is used as the voltage adjustment circuit 30, the output terminal of the operational amplifier 32a is connected to the wiring Wrh, and therefore the output voltage from the output terminal of the operational amplifier 32a is the on-voltage Von. Here, the resistor 33a is a fixed resistor having a fixed resistance value, while the resistor 34a is a variable resistor. Under the control of the control circuit 35a, the resistance value of the resistor 34a can be changed and set in multiple stages. In the voltage adjustment circuit 30a, the on-voltage Von is changed by changing the resistance value of the resistor 34a. The control circuit 35a adjusts the on-voltage Von by adjusting the resistance value of the resistor 34a based on the voltage detection signal Svd and the current detection signal Sid to achieve the operation shown in FIG. 4.

[0052] FIG. 8 shows another example of the configuration of the voltage adjustment circuit 30. The voltage adjustment circuit 30b in FIG. 8 can be used as the voltage adjustment circuit 30 in FIG. 1. The voltage adjustment circuit 30b in FIG. 8 includes a voltage source 31b, an operational amplifier 32b, resistors 33b and 34b, and a control circuit 35b. The voltage source 31b supplies a voltage higher than the potential of the wiring WRs by a voltage Vb to the non-inverting input terminal of the operational amplifier 32b. The output terminal of the operational amplifier 32b is connected to a first terminal of the resistor 33b, and the second terminal of the resistor 33b and the first terminal of the resistor 34b are commonly connected to the inverting input terminal of the operational amplifier 32b. The second terminal of the resistor 34b is connected to the wiring WRs. Therefore, the operational amplifier 32b and the resistors 33b and 34b form a non-inverting amplifier circuit, and a voltage determined by the resistance ratio between the resistors 33b and 34b and the voltage Vb is output from the output terminal of the operational amplifier 32b. When the voltage adjustment circuit 30b is used as the voltage adjustment circuit 30, the output terminal of the operational amplifier 32b is connected to the wiring Wrh, and therefore the output voltage from the output terminal of the operational amplifier 32b is the on-voltage Von. Unlike the voltage adjustment circuit 30a of FIG. 7, the resistors 33b and 34b are both fixed resistors with fixed resistance values. However, the voltage source 31b is a variable voltage source, and under the control of the control circuit 35b, the voltage source 31b can change and set the voltage Vb in multiple stages. In the voltage adjustment circuit 30b, the on-voltage Von is changed by changing the voltage Vb. The control circuit 35b adjusts the on-voltage Von by adjusting the voltage Vb (adjusting the value of the voltage Vb) based on the voltage detection signal Svd and the current detection signal Sid to achieve the operation shown in FIG. 4.

[0053] Below, several specific configuration examples, operation examples, application techniques, modified techniques, etc. related to the switching circuit 1 will be described among multiple embodiments. The matters described above in this embodiment are applied to each of the following embodiments unless otherwise specified and unless there is a contradiction. If there are any matters in each embodiment that contradict the matters described above, the description in that embodiment may take precedence. Furthermore, unless there is a contradiction, matters described in any of the multiple embodiments described below can also be applied to any other embodiment (i.e., any two or more of the multiple embodiments can be combined).

[0054] <<First Example>> A first embodiment will be described. In the circuit system SYS, in an application in which the maximum value of the drain current Id during the ON period of the target transistor 10 is known or in which the drain current Id is substantially constant, the decision as to whether to output an alert signal may be made based on the result of comparing the drain-source voltage Vds during the ON period of the target transistor 10 with a predetermined alert voltage threshold alt.

[0055] 9, the voltage adjustment circuit 30 according to the first embodiment determines in step S24 whether the voltage value |Vds| is greater than the alert voltage threshold Valt. If "|Vds|>Valt" holds (Y in step S24), the process proceeds to step S25 to perform alert processing, and if "|Vds|>Valt" does not hold (N in step S24), the process proceeds to step S17 without proceeding to step S25. |Vds| in the inequality "|Vds|>Valt," the success or failure of which is determined in the j-th frame, indicates the voltage value |Vds| at the sampling timing ts of the j-th frame.

[0056] As described above, in the first embodiment, when the drain-source voltage Vds exceeds the alert voltage threshold alt even when the on-voltage Von is set to the upper limit voltage Von_max, the voltage adjustment circuit 30 outputs a signal Salt (alert signal) of “1” to the external device 4. This makes it possible to notify the external device 4 that the on-resistance Ron of the target transistor 10 is excessively large.

[0057] <<Second Example>> A second embodiment will now be described. In the operations shown in Figures 4 and 9, the on-resistance Ron is determined for each frame, and the on-voltage Von can be corrected (increased or decreased) for each frame. However, the voltage adjustment circuit 30 may determine the on-resistance Ron every Q frames, in which case it is determined every Q frames whether to correct (increase or decrease) the on-voltage Von. Q represents any integer equal to or greater than 2.

[0058] <<Third Example>> A third embodiment will now be described. FIG. 10 is an overall configuration diagram of a switching power supply 100 according to the third embodiment. The switching power supply 100 of FIG. 10 includes a power supply control device 200 and a plurality of discrete components externally connected to the power supply control device 200. The plurality of discrete components include a coil L1 serving as an output coil, a capacitor C1 serving as an output capacitor, and resistors R1 and R2 serving as feedback resistors. The switching power supply 100 is configured as a step-down switching power supply (DC / DC converter) that generates a desired output voltage Vout from an input voltage Vin supplied from a voltage source VS. The output voltage Vout is generated at an output terminal OUT. That is, the output terminal OUT is the application terminal of the output voltage Vout (the terminal to which the output voltage Vout is applied). The output voltage Vout is supplied to a load LD connected to the output terminal OUT.

[0059] Except in a transient state, the input voltage Vin and the output voltage Vout are positive DC voltages, and the output voltage Vout is lower than the input voltage Vin. For example, when the input voltage Vin is 12 V, the output voltage Vout can be stabilized at a desired positive voltage value (e.g., 3.3 V or 5 V) less than 12 V by adjusting the resistance values ​​of resistors R1 and R2.

[0060] FIG. 11 is an external perspective view of the power supply control device 200. The power supply control device 200 is an electronic component that includes a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) that houses the semiconductor chip, and multiple external terminals that are exposed to the outside of the power supply control device 200 from the housing. The power supply control device 200 is formed by sealing the semiconductor chip in a housing (package) made of resin. Note that the number of external terminals of the power supply control device 200 and the type of housing for the power supply control device 200 shown in FIG. 11 are merely examples and can be designed as desired. FIG. 10 shows an input terminal IN, a switch terminal SW, a ground terminal GND, and a feedback terminal FB as some of the multiple external terminals. Other external terminals are also provided in the power supply control device 200.

[0061] The external configuration of the power supply control device 200 will now be described. An input voltage Vin is supplied to an input terminal IN from a voltage source VS provided external to the power supply control device 200. A coil L1 is connected in series between a switch terminal SW and an output terminal OUT. That is, a first terminal of the coil L1 is connected to the switch terminal SW, and a second terminal of the coil L1 is connected to the output terminal OUT. The output terminal OUT is also connected to ground via a capacitor C1. That is, a first terminal of the capacitor C1 is connected to the output terminal OUT, and a second terminal of the capacitor C1 is connected to ground. Furthermore, the output terminal OUT is connected to a first terminal of a resistor R1, a second terminal of the resistor R1 is connected to a first terminal of a resistor R2, and a second terminal of the resistor R2 is connected to ground. A feedback voltage Vfb is generated at a connection node between resistors R1 and R2. The connection node between resistors R1 and R2 is connected to a feedback terminal FB, thereby inputting the feedback voltage Vfb to the feedback terminal FB. The ground terminal GND is connected to ground. The current flowing through the coil L1 is referred to as a coil current IL.

[0062] The internal configuration of the power supply control device 200 will now be described. The power supply control device 200 comprises two switching circuits 1 and a controller 3. Each of the two switching circuits 1 has the same configuration and operates in the same manner as the switching circuit 1 in FIG. 1. Of the two switching circuits 1 in the switching power supply device 100, one is referred to as switching circuit 1[1] and the other is referred to as switching circuit 1[2]. The power supply control device 200 is provided with an internal power supply circuit (not shown) that generates an internal power supply voltage based on the input voltage Vin. Each circuit in the switching circuits 1[1] and 1[2] and the controller 3 are driven based on the input voltage Vin or the internal power supply voltage.

[0063] The target transistor 10, driver 20, voltage adjustment circuit 30, voltage detection circuit 40, and current detection circuit 50 in the switching circuit 1[i] are respectively referred to as the target transistor 10[i], driver 20[i], voltage adjustment circuit 30[i], voltage detection circuit 40[i], and current detection circuit 50[i] (where i is 1 or 2). The control signal Scnt supplied from the controller 3 to the switching circuit 1[i] is particularly referred to as the control signal Scnt[i] (where i is 1 or 2). The gate voltage Vg, gate-source voltage Vgs, drain-source voltage Vds, drain current Id, on-voltage Von, and off-voltage Voff in the switching circuit 1[i] are respectively referred to as the gate voltage Vg[i], gate-source voltage Vgs[i], drain-source voltage Vds[i], drain current Id[i], on-voltage Von[i], and off-voltage Voff[i] (where i is 1 or 2). The voltage detection signal Svd and current detection signal Sid in the switching circuit 1[i] are respectively referred to as the voltage detection signal Svd[i] and the current detection signal Sid[i]. The wiring WRg, WRh, and WRs in the switching circuit 1[i] are respectively referred to as the wiring WRg[i], WRh[i], and WRs[i] (where i is 1 or 2). The signal Salt in the switching circuit 1[i] is specifically referred to as the signal Salt[i] (where i is 1 or 2). The on-voltage Von[1] is higher than the input voltage Vin. By configuring a well-known boost circuit (bootstrap circuit) in the switching power supply device 100, a voltage higher than the input voltage Vin can be obtained.

[0064] The target circuit 2 (see Figure 1) for the switching circuit 1 [1] can be considered to include a switching circuit 1 [2], a voltage source VS, a coil L1, a capacitor C1, a resistor R1, a resistor R2, and a load LD. The target circuit 2 (see Figure 1) for the switching circuit 1 [2] can be considered to include a switching circuit 1 [1], a voltage source VS, a coil L1, a capacitor C1, a resistor R1, a resistor R2, and a load LD.

[0065] The target transistors 10[1] and 10[2] are a pair of switching elements connected in series between the input terminal IN and the ground terminal GND (i.e., ground). When they are switched, a rectangular-wave switch voltage Vsw appears at the switch terminal SW. The target transistor 10[1] is located at a higher potential than the target transistor 10[2]. Specifically, the drain of the target transistor 10[1] is connected to the input terminal IN, which is the application terminal of the input voltage Vin, and receives the input voltage Vin. However, a sense resistor (shunt resistor) for current detection may be inserted between the drain of the target transistor 10[1] and the input terminal IN. The source of the target transistor 10[1] and the drain of the target transistor 10[2] are commonly connected to the switch terminal SW. The source of the target transistor 10[2] is connected to the ground terminal GND (and therefore to ground). However, a sense resistor (shunt resistor) for current detection may be inserted between the source of the target transistor 10[2] and the ground terminal GND.

[0066] The target transistor 10[1] functions as an output element (output transistor), and the target transistor 10[2] functions as a rectifier element (synchronous rectifier transistor). Under the control of the controller 3, the output element (10[1]) and the rectifier element (10[2]) are alternately turned on and off. The coil L1 and capacitor C1 form a rectifying and smoothing circuit that rectifies and smoothes the square-wave switch voltage Vsw that appears at the switch terminal SW to generate the output voltage Vout. The resistors R1 and R2 form a feedback voltage generating circuit that divides the output voltage Vout to generate a feedback voltage Vfb that corresponds to the output voltage Vout. The feedback voltage Vfb is proportional to the output voltage Vout, and the feedback voltage Vfb also rises and falls as the output voltage Vout rises and falls.

[0067] Alternatively, the output voltage Vout itself may be used as the feedback voltage Vfb. In either case, the feedback voltage Vfb is a voltage corresponding to the output voltage Vout. The feedback voltage generating circuit (R1, R2) may be provided within the power supply control device 200. In this case, the feedback terminal FB is a node within the power supply control device 200 rather than an external terminal.

[0068] Basically, the target transistors 10[1] and 10[2] are alternately turned on and off, but both the target transistors 10[1] and 10[2] may be maintained in the off state. That is, the state of the output stage consisting of the target transistors 10[1] and 10[2] is one of the following: output high state, output low state, or both off state. In the output high state, the target transistor 10[1] is on and the target transistor 10[2] is off. In the output low state, the target transistor 10[1] is off and the target transistor 10[2] is on. In the both off state, the target transistors 10[1] and 10[2] are both off. The target transistors 10[1] and 10[1] are never turned on at the same time. Note that either or both of the target transistors 10[1] and 10[2] may be provided outside the power supply control device 200.

[0069] During the ON period of the target transistor 10[1], the coil current IL flows through the channel (between the drain and source) of the target transistor 10[1]. During the OFF period of the target transistor 10[1], the coil current IL flows through the channel of the target transistor 10[2] or the parasitic diode of the target transistor 10[2].

[0070] The controller 3 is connected to a feedback terminal FB and receives a feedback voltage Vfb through the feedback terminal FB. The power supply control device 200 also includes a reference voltage generation circuit (not shown) that generates a reference voltage Vref based on the input voltage Vin, and supplies the reference voltage Vref to the controller 3. The reference voltage Vref has a predetermined positive DC voltage value. Based on the feedback voltage Vfb and the reference voltage Vref, the controller 3 generates and outputs control signals Scnt[1] and Scnt[2] to control the on / off states of the target transistors 10[1] and 10[2], respectively, thereby generating a desired output voltage Vout at the output terminal OUT. In this case, the controller 3 generates and outputs the control signals Scnt[1] and Scnt[2] to reduce the difference between the feedback voltage Vfb and the reference voltage Vref (ideally, to maintain this difference at zero).

[0071] Figure 12 shows the waveforms of the control signals Scnt[1] and Scnt[2]. The controller 3 alternately sets the control signals Scnt[1] and Scnt[2] to "1" and "0" to turn on and off the target transistors 10[1] and 10[2]. The controller 3 keeps the value of the control signal Scnt[2] at "0" while the control signal Scnt[1] is "1," and keeps the value of the control signal Scnt[1] at "0" while the control signal Scnt[2] is "1." Each frame for the switching circuit 1[1] can be considered to begin when the value of the control signal Scnt[1] changes from "0" to "1" (see Figure 2). Similarly, each frame for the switching circuit 1[2] can be considered to begin when the value of the control signal Scnt[2] changes from "0" to "1" (see Figure 2).

[0072] The controller 3 may control the switching of the output stage consisting of the target transistors 10[1] and 10[2] by pulse width modulation or pulse frequency modulation. The controller 3 may also control the switching of the output stage by further referring to information about the coil current IL. In either case, the power supply control device 200 controls the operation of the switching power supply device 100 through control of the output stage based on the output voltage Vout (specifically, based on the feedback voltage Vfb corresponding to the output voltage Vout).

[0073] The driver 20[1] supplies an on-voltage Von[1] or an off-voltage Voff[1] to the gate of the target transistor 10[1]. The off-voltage Voff[1] has the source potential of the target transistor 10[1]. The target transistor 10[1] is on during the period when the gate voltage Vg[1] of the target transistor 10[1] is set to the on-voltage Von[1], and the target transistor 10[1] is off during the period when the gate voltage Vg[1] of the target transistor 10[1] is set to the off-voltage Voff[1]. During the on-period of the target transistor 10[1], a drain current Id[1] flows from the drain to the source of the target transistor 10[1].

[0074] The voltage detection circuit 40[1] is connected to the drain and source of the target transistor 10[1]. The voltage detection circuit 40[1] detects the drain-source voltage Vds[1] of the target transistor 10[1] during the ON period of the target transistor 10[1] and outputs a voltage detection signal Svd[1] indicating the detection result to the voltage adjustment circuit 30[1]. The current detection circuit 50[1] detects the drain current Id[1] during the ON period of the target transistor 10[1] and outputs a current detection signal Sid[1] indicating the detection result of the drain current Id[1] to the voltage adjustment circuit 30. The voltage adjustment circuit 30[1] identifies the on-resistance Ron of the target transistor 10[1] based on the voltage detection signal Svd[1] and the current detection signal Sid[1] during the on-period of the target transistor 10[1], and performs a voltage adjustment process (first voltage adjustment process) to adjust the on-voltage Von[1] so that the on-resistance Ron of the target transistor 10[1] is kept approximately constant.

[0075] The driver 20[2] supplies an on-voltage Von[2] or an off-voltage Voff[2] to the gate of the target transistor 10[2]. The off-voltage Voff[2] has the source potential of the target transistor 10[2]. The target transistor 10[2] is on during the period when the gate voltage Vg[2] of the target transistor 10[2] is set to the on-voltage Von[2], and is off during the period when the gate voltage Vg[2] of the target transistor 10[2] is set to the off-voltage Voff[2]. While FIG. 10 shows the drain current Id[2] flowing from the drain to the source of the target transistor 10[2], during the on-period of the target transistor 10[2], the drain current I[2] can flow from the drain to the source of the target transistor 10[2], or from the source to the drain of the target transistor 10[2].

[0076] The voltage detection circuit 40[2] is connected to the drain and source of the target transistor 10[2]. The voltage detection circuit 40[2] detects the drain-source voltage Vds[2] of the target transistor 10[2] during the ON period of the target transistor 10[2] and outputs a voltage detection signal Svd[2] indicating the detection result to the voltage adjustment circuit 30[2]. The current detection circuit 50[2] detects the drain current Id[2] during the ON period of the target transistor 10[2] and outputs a current detection signal Sid[2] indicating the detection result of the drain current Id[2] to the voltage adjustment circuit 30. The voltage adjustment circuit 30[2] identifies the on-resistance Ron of the target transistor 10[2] based on the voltage detection signal Svd[2] and the current detection signal Sid[2] during the on-period of the target transistor 10[2], and performs a voltage adjustment process (second voltage adjustment process) to adjust the on-voltage Von[2] so that the on-resistance Ron of the target transistor 10[2] is kept approximately constant.

[0077] The voltage adjustment method using the voltage adjustment circuits 30[1] and 30[2] is as described above, and the operation shown in FIG. 4 or FIG. 9 is executed by each of the switching circuits 1[1] and 1[2]. The initial state of step S11 may be a state in which the target transistors 10[1] and 10[2] have never been turned on after the input voltage Vin starts to be supplied to the power supply control device 200. Alternatively, the state at any timing after the input voltage Vin starts to be supplied to the power supply control device 200 and switching control of the target transistors 10[1] and 10[2] starts, and the feedback voltage Vfb reaches the reference voltage Vref may be regarded as the initial state of step S11, and the operation shown in FIG. 4 or FIG. 9 may be executed. The voltage adjustment method using the voltage adjustment circuits 30[1] and 30[2] can suppress an increase in the on-resistance Ron of each target transistor 10 and an increase in the loss generated in each target transistor 10 against the effect of current collapse, thereby suppressing a decrease in the efficiency of the switching power supply device 100.

[0078] When alert processing is executed in the switching circuit 1[i], the voltage adjustment circuit 30[i] outputs a signal Salt[i] having a value of “1.” The voltage adjustment circuit 30[i] may output the signal Salt[i] having a value of “1” as an alert signal to the external device 4. At this time, the alert signal is output to the external device 4 through a diagnostic output terminal (not shown), which is an external terminal of the power supply control device 200. The power supply control device 200 may be provided with an alert output circuit (not shown). The signals Salt[1] and Salt[2] are input to the alert output circuit. When at least one of the signals Salt[1] and Salt[2] has a value of “1,” the alert output circuit can output an alert signal indicating that at least one of the on-resistances Ron of the target transistors 10[1] and 10[2] is excessive to the external device 4 (see FIG. 1) through the diagnostic output terminal.

[0079] The configuration of each of the voltage detection circuits 40[1] and 40[2] may be the same as the configuration shown in Figure 5 or Figure 6. The configuration of each of the voltage adjustment circuits 30[1] and 30[2] may be the same as the configuration shown in Figure 7 or Figure 8.

[0080] 13 shows an example of the configuration of the current detection circuits 50[1] and 50[2]. The current detection circuit 50[1] in FIG. 13 includes a sense resistor Rsns1 connected in series between the input terminal IN and the drain of the target transistor 10[1], and a sense amplifier Samp1 connected across the sense resistor Rsns1 to output an amplified signal of the voltage across the sense resistor Rsns1 as a current detection signal Sid[1]. During the on-period of the target transistor 10[1], the drain current Id[1] flows through the sense resistor Rsns1, and a voltage (voltage drop) proportional to the drain current Id[1] is generated across the sense resistor Rsns1. 13 includes a sense resistor Rsns2 connected in series between the drain of the target transistor 10[2] and the ground terminal GND, and a sense amplifier Samp2 connected across the sense resistor Rsns2 to output an amplified signal of the voltage across the sense resistor Rsns2 as a current detection signal Sid[2]. During the on-period of the target transistor 10[2], the drain current Id[2] flows through the sense resistor Rsns2, and a voltage (voltage drop) proportional to the drain current Id[2] is generated across the sense resistor Rsns2.

[0081] As long as the drain current Id[1] flows through the sense resistor Rsns1, the insertion position of the sense resistor Rsns1 is arbitrary. As long as the drain current Id[2] flows through the sense resistor Rsns2, the insertion position of the sense resistor Rsns2 is arbitrary.

[0082] As shown in FIG. 14, instead of the sense amplifiers Samp1 and Samp2 and the sense resistors Rsns1 and Rsns2, a sense amplifier Samp3 and a sense resistor Rsns3 may be provided in the switching power supply device 100. The sense amplifier Samp3 is built into the power supply control device 200 and is shared by the current detection circuits 50[1] and 50[2] as a component of the current detection circuits 50[1] and 50[2]. The sense resistor Rsns3 is connected in series with the coil L1. In the example of FIG. 14, a first end of the coil L1 is connected to the switch terminal SW, a second end of the coil L1 is connected to a first end of the sense resistor Rsns3, a second end of the sense resistor Rsns3 is connected to the output terminal OUT and a first end of the capacitor C1, and a second end of the capacitor C1 is connected to ground. However, a sense resistor Rsns3 may be inserted between the connection node between the source of the target transistor 10[1] and the drain of the target transistor 10[2] and the switch terminal SW, or a sense resistor Rsns3 may be inserted between the switch terminal SW and the coil L1.

[0083] In either case, during the ON period of the target transistor 10[1], the drain current Id[1] flows through the coil L1 and the sense resistor Rsns3, and during the ON period of the target transistor 10[2], the drain current Id[2] flows through the coil L1 and the sense resistor Rsns3. The sense amplifier Samp3 is connected across the sense resistor Rsns3 and outputs an amplified signal of the voltage across the sense resistor Rsns3. The output signal of the sense amplifier Samp3 during the ON period of the target transistor 10[1] functions as the current detection signal Sid[1], and the output signal of the sense amplifier Samp3 during the ON period of the target transistor 10[2] functions as the current detection signal Sid[2].

[0084] <<Fourth Example>> A fourth embodiment will now be described.

[0085] 1 is applied to a step-down switching power supply device in the third embodiment, the switching circuit 1 can also be applied to a step-up switching power supply device (DC / DC converter) or a step-up / step-down switching power supply device (DC / DC converter). The switching circuit 1 can also be used in an isolated power supply device having a transformer, in which case, for example, the target transistor 10 can be connected in series to the primary winding of the transformer.

[0086] The technology (switching circuit 1) according to the present disclosure can be applied to any AC / DC adapter, as well as to power supply devices in data centers, servers, or base stations, and can also be applied to on-board chargers or automotive DC / DC converters. The technology (switching circuit 1) according to the present disclosure can also be applied to motor drivers, LED drivers, etc. In addition, the technology (switching circuit 1) according to the present disclosure can be applied to any application requiring a switching element.

[0087] The effect of current collapse becomes significant when the semiconductor forming the target transistor 10 is GaN (gallium nitride). However, even if the semiconductor forming the target transistor 10 is other than GaN, the on-resistance Ron can fluctuate due to various factors if the on-voltage Von is fixed. Therefore, the semiconductor forming the target transistor 10 may be other than GaN, such as Si (silicon), SiC (silicon carbide), or GaAs (gallium arsenide).

[0088] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0089] <<Additional Notes>> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0090] A switching circuit (1) according to one aspect of the present disclosure has a configuration (first configuration) including: a target transistor (10) having a drain, a source, and a gate; a driver (20) configured to turn on the target transistor by supplying an on-voltage (Von) to the gate of the target transistor and to turn off the target transistor by supplying an off-voltage (Voff) to the gate of the target transistor; and a voltage adjustment circuit (30) configured to suppress changes in the on-resistance (Ron) of the target transistor by adjusting the on-voltage based on a drain-source voltage (Vds) of the target transistor and a drain current (Id) of the target transistor during an on-period of the target transistor.

[0091] This makes it possible to suppress a change in the loss generated in the target transistor due to a change in the on-resistance of the target transistor.

[0092] In the switching circuit according to the first configuration, the voltage adjustment circuit may be configured to compare the on-resistance (Ron) of the target transistor, which is determined based on the drain-source voltage of the target transistor and the drain current of the target transistor during the on-period of the target transistor, with a reference resistance (Rref), and, if there is a difference between the on-resistance of the target transistor and the reference resistance, change the on-voltage in a direction that reduces the difference (second configuration).

[0093] The switching circuit according to the second configuration may be provided with a voltage detection circuit (40) configured to detect the drain-source voltage of the target transistor during the on-period of the target transistor, and a current detection circuit (50) configured to detect the drain current of the target transistor during the on-period of the target transistor, and the voltage adjustment circuit may be configured to determine the on-resistance of the target transistor based on the detection results of the voltage detection circuit and the current detection circuit (third configuration).

[0094] In the switching circuit according to any one of the first to third configurations, the voltage adjustment circuit may be configured (fourth configuration) to suppress a change in the on-resistance of the target transistor due to the action of current collapse by adjusting the on-voltage.

[0095] In the switching circuit according to any one of the first to fourth configurations, the target transistor may be formed from GaN (fifth configuration).

[0096] In a switching circuit according to any one of the first to fifth configurations, the on-resistance of the target transistor decreases as the on-voltage increases during the on-period of the target transistor, and the voltage adjustment circuit may be configured to output an alert signal to an external device (4) of the switching circuit when the on-resistance of the target transistor is greater than an alert resistance threshold (Ralt) during the on-period of the target transistor in a state where the on-voltage is set to the upper limit of the adjustment range of the on-voltage.

[0097] By outputting an alert signal, for example, it is possible to notify an external device that the on-resistance of the target transistor is excessive, and it becomes possible to take measures such as stopping the switching of the target transistor under the control of the external device.

[0098] In the switching circuit according to any one of the first to fifth configurations, the on-resistance of the target transistor decreases as the on-voltage increases during the on-period of the target transistor, and the voltage adjustment circuit may be configured to output an alert signal to an external device (4) of the switching circuit when, during the on-period of the target transistor, the drain-source voltage of the target transistor in a state in which the on-voltage is set to the upper limit of the adjustment range of the on-voltage is greater than an alert voltage threshold (Valt) (seventh configuration).

[0099] By outputting an alert signal, for example, it is possible to notify an external device that the on-resistance of the target transistor is excessive, and it becomes possible to take measures such as stopping the switching of the target transistor under the control of the external device. [Explanation of symbols]

[0100] SYS Circuit System 1, 1[1], 1[2] Switching circuit 2 Target circuit 3 Controller 4 External device 10, 10[1], 10[2] Target transistor 20, 20[1], 20[2] Driver 30, 30[1], 30[2] Voltage regulation circuit 40, 40[1], 40[2] Voltage detection circuit 50, 50[1], 50[2] Current detection circuit Vds, Vds[1], Vds[2] Drain-source voltage Vgs, Vgs[1], Vgs[2] Gate-source voltage Vg, Vg[1], Vg[2] Gate voltage Von, Von[1], Von[2] On voltage Voff, Voff[1], Voff[2] Off voltage VDD power supply voltage Id, Id[1], Id[2] Drain current Svd, Svd[1], Svd[2] Voltage detection signals Sid, Sid[1], Sid[2] Current detection signal Scnt, Scnt[1], Scnt[2] control signals Salt, Salt[1], Salt[2] signals WRh, WRh[1], WRh[2] wiring WRs, WRs[1], WRs[2] wiring WRg, WRg[1], WRg[2] wiring ts Sampling timing RNG voltage adjustment range Von_min Lower limit voltage Von_max upper limit voltage 31a, 31b voltage source 32a, 32b operational amplifiers 33a, 33b, 34a, 34b resistor 35a, 35b control circuit 41, 43 Voltage sensor 42 Switch 44 transistors 45 Resistance 100 Switching power supply 200 Power supply control device L1 coil C1 capacitor R1, R2 resistance LD load VS voltage source IN input terminal SW Switch terminal GND Ground terminal FB Feedback terminal OUT output terminal Vin Input voltage Vout Output voltage Vfb Feedback voltage Vref Reference voltage Vsw Switch voltage IL Coil current Rsns1, Rsns2, Rsns3 sense resistors Samp1, Samp2, Samp3 sense amplifiers

Claims

1. a target transistor having a drain, a source, and a gate; a driver configured to supply a turn-on voltage to a gate of the target transistor to turn on the target transistor and to supply a turn-off voltage to the gate of the target transistor to turn off the target transistor; a voltage adjusting circuit configured to suppress a change in the on-resistance of the target transistor by adjusting the on-voltage based on the drain-source voltage of the target transistor and the drain current of the target transistor during an on-period of the target transistor. , switching circuits.

2. The voltage adjustment circuit compares the on-resistance of the target transistor, which is determined based on the drain-source voltage of the target transistor and the drain current of the target transistor during an on-period of the target transistor, with a reference resistance, and, if there is a difference between the on-resistance of the target transistor and the reference resistance, changes the on-voltage in a direction that reduces the difference.

10. The switching circuit of claim 1.

3. a voltage detection circuit configured to detect a drain-source voltage of the target transistor during an on-period of the target transistor; a current detection circuit configured to detect a drain current of the target transistor during an on-period of the target transistor; The voltage adjustment circuit identifies the on-resistance of the target transistor based on the detection results of the voltage detection circuit and the current detection circuit.

3. The switching circuit of claim 2.

4. The voltage adjustment circuit suppresses a change in the on-resistance of the target transistor due to the action of current collapse by adjusting the on-voltage.

4. A switching circuit according to claim 1.

5. The target transistor is formed of GaN 4. A switching circuit according to claim 1.

6. During the on-period of the target transistor, the on-resistance of the target transistor decreases due to the increase in the on-voltage; The voltage adjustment circuit outputs an alert signal to an external device of the switching circuit when the on-resistance of the target transistor is greater than an alert resistance threshold in a state in which the on-voltage is set to the upper limit of an adjustment range of the on-voltage during an on-period of the target transistor.

4. A switching circuit according to claim 1.

7. During the on-period of the target transistor, the on-resistance of the target transistor decreases due to the increase in the on-voltage; The voltage adjustment circuit outputs an alert signal to an external device of the switching circuit when the drain-source voltage of the target transistor is greater than an alert voltage threshold in a state in which the turn-on voltage is set to the upper limit of an adjustment range of the turn-on voltage during an on-period of the target transistor.

4. A switching circuit according to claim 1.

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