Semiconductor device, motor control system and motor control method

Abstract

To reduce power consumption while ensuring control accuracy in a method where a controller controls a motor via a semiconductor device.SOLUTION: A semiconductor device comprises a timer circuit that generates carrier cycle events (CTE) with random modulation and a feedback (FB) signal generation circuit that generates a feedback signal corresponding to a motor rotation angle and outputs it to the controller. In the FB signal generation circuit, a register stores the number of next steps corresponding to the motor rotation amount between two adjacent CTEs. A remaining step count control circuit obtains a first remaining step count by subtracting the number of steps processed for generating the FB signal between the first CTE and the subsequent second CTE from the first next step count at the time of the first CTE occurrence. The total step count control circuit obtains a second total step count by adding the second next step count and the first remaining step count when the second CTE occurs. An output circuit generates the FB signal based on the second total step count.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, a motor control system, and a motor control method. [Background technology]

[0002] One known method for controlling a motor is to have a controller control the motor via a semiconductor device, as described in, for example, Patent Document 1. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-88185 Summary of the Invention [Problem to be solved by the invention]

[0004] In a method in which a controller controls a motor via a semiconductor device, there is a demand for reducing power consumption while ensuring control accuracy. [Means for solving the problem]

[0005] A representative embodiment includes a processor that generates and outputs a signal for controlling a motor based on instruction information input from an external controller, and generates and outputs rotation amount information of the motor based on rotation angle information input from the motor side; a timer circuit that generates randomly modulated carrier period events; and a feedback signal generation circuit that generates a feedback signal corresponding to the rotation angle of the motor based on the rotation amount information of the motor input from the processor and the carrier period events generated by the timer circuit, and outputs the feedback signal to the controller, wherein the feedback signal generation circuit generates a next step number corresponding to the rotation amount of the motor between two temporally adjacent carrier period events. a remaining step number control circuit that obtains a first remaining number of steps by subtracting the number of steps that could be processed for generating the feedback signal between the first carrier period event and a second carrier period event that occurs immediately thereafter from a first next step number stored in the register at the time when a first carrier period event occurs; a total step number control circuit that obtains a second total number of steps by adding the second next step number stored in the register to the first remaining step number at the time when the second carrier period event occurs; and an output circuit that generates and outputs the feedback signal based on the second total step number.

[0006] A representative embodiment is a motor control system including the semiconductor device, the controller, and the motor.

[0007] A representative embodiment includes a processor generating and outputting a signal for controlling a motor based on instruction information input from a controller, and generating and outputting rotation amount information of the motor based on rotation angle information input from the motor side; a timer circuit generating a randomly modulated carrier period event; and a feedback signal generation circuit generating a feedback signal corresponding to the rotation angle of the motor based on the rotation amount information of the motor input from the processor and the carrier period event generated by the timer circuit, and outputting the feedback signal to the controller, wherein the feedback signal generation circuit generating and outputting the feedback signal means that a register is configured to generate a signal corresponding to the rotation angle of the motor between two temporally adjacent carrier period events. a remaining step number control circuit obtains a first remaining number of steps by subtracting the number of steps that could be processed for generating the feedback signal between the first carrier period event and a second carrier period event immediately thereafter from the first next step number stored in the register at the time when a first carrier period event occurs; a total step number control circuit obtains a second total number of steps by adding the second next step number stored in the register to the first remaining step number at the time when the second carrier period event occurs; and an output circuit generates and outputs the feedback signal based on the second total number of steps. [Effects of the Invention]

[0008] According to one embodiment, in a method in which a controller controls a motor via a semiconductor device, it is possible to reduce power consumption while ensuring control accuracy. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram illustrating an example of the configuration of a motor control system. [Figure 2] FIG. 10 is a diagram for explaining switching loss. [Figure 3] FIG. 10 is a diagram illustrating a configuration example of an FB signal generating circuit according to the reference technology. [Figure 4] FIG. 10 is a diagram illustrating an example of an operation flow of an FB signal generating circuit according to the reference technology. [Figure 5] 10 is a diagram showing an example of a timing chart of signals or values ​​relating to the operation of the FB signal generating circuit according to the reference technology. FIG. [Figure 6] 10A and 10B are diagrams illustrating an example of a carrier period event and a carrier waveform when random modulation is applied to the carrier period. [Figure 7] 10 is a diagram showing an example of a timing chart of each signal in the FB signal generating circuit when random modulation is applied to the carrier period. FIG. [Figure 8] 1 is a diagram illustrating an example of the configuration of a motor control system and a semiconductor device according to a first embodiment. [Figure 9] 2 is a diagram illustrating a configuration example of an FB signal generating circuit according to the first embodiment. FIG. [Figure 10] FIG. 4 is a diagram showing an example of an operation flow of the FB signal generating circuit according to the first embodiment. [Figure 11] 4 is a diagram showing an example of a timing chart of signals in the FB signal generating circuit according to the first embodiment; FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] (Background of the study by the inventors) <Motor control system configuration> Motor control systems are known in which a controller controls the rotation of a motor via a semiconductor device. Here, an example of the configuration and operation of such a motor control system will be described. In this specification, the rotation, rotation amount, rotation angle position, rotation speed, etc. of a rotating shaft of a motor are also simply referred to as the rotation, rotation amount, rotation angle position, rotation speed, etc. of the motor. In this specification, the rotation angle position of a motor is also simply referred to as the rotation angle of the motor.

[0011] 1 is a diagram showing an example of the configuration of a motor control system. As shown in Fig. 1, the motor control system 1 includes, for example, a controller 2, a semiconductor device 3, a drive circuit 4, and a motor 5.

[0012] The controller 2 is provided outside the semiconductor device 3 and inputs instruction information CMF related to the rotation of the motor 5 to the semiconductor device 3. The controller 2 is, for example, a higher-level controller positioned higher than the semiconductor device 3. The semiconductor device 3 generates a motor control signal MCS based on the input instruction information CMF and inputs it to the drive circuit 4. The drive circuit 4 supplies drive power (drive signal) DPW to the motor 5 based on the input motor control signal MCS. The drive circuit 4 is, for example, an IGBT (Insulated Gate Bipolar Transistor). The motor 5 is driven in accordance with the supplied drive power DPW, and the amount of rotation, rotation angle, rotation speed, etc. of the motor 5 are controlled. The motor 5 has an encoder 51. The encoder 51 outputs rotation angle information AF indicating the rotation angle of the motor 5. The motor 5 is, for example, a DC motor.

[0013] The semiconductor device 3 not only controls the rotation of the motor 5, but also monitors in high real-time the rotation angle of the motor 5. Based on the rotation angle of the motor 5 that it is monitoring, the semiconductor device 3 generates a signal representing the rotation angle or amount of rotation of the motor 5 as a feedback (hereinafter also referred to as FB) signal FBS to the controller 2 and outputs it to the controller 2 sequentially.

[0014] The semiconductor device 3 will be described in more detail below. As shown in Fig. 1, the semiconductor device 3 is, for example, an MCU (Micro Controller Unit). The semiconductor device 3 also includes, for example, a processor 31, a timer circuit 32, a PWM (Pulse Width Modulation) generation circuit 33, a rotation angle monitor circuit 34, and an FB signal generation circuit 35.

[0015] The processor 31 generates a signal for controlling the motor 5 based on command information CMF input from the controller 2 provided outside the semiconductor device 3, and outputs the signal to the PWM generation circuit 33. The processor 31 also generates rotation amount information RF of the motor 5 based on rotation angle information AF input from the motor 5 side, and outputs the information to the FB signal generation circuit 35. The processor 31 is, for example, a CPU (Central Processing Unit).

[0016] The timer circuit 32 generates a carrier cycle event CTE at a predetermined carrier cycle, i.e., at time intervals. The timer circuit 32 outputs the generated carrier cycle event CTE to the processor 31 and the FB signal generation circuit 35. The carrier cycle event CTE is a pulse-like signal generated at a predetermined carrier cycle. The carrier cycle is the period of a reference signal used when generating a PWM signal from a modulated wave.

[0017] The rotation angle monitor circuit 34 sequentially acquires the rotation angle information AF output from the encoder 51 and outputs it to the processor 31. The processor 31 controls the PWM generation circuit 33 based on the instruction information CMF input from the controller 2 and the rotation angle information AF input from the encoder 51.

[0018] The PWM generating circuit 33 generates a PWM signal as the motor control signal MCS under the control of the processor 31. The PWM generating circuit 33 outputs the generated PWM signal to the drive circuit 4.

[0019] The processor 31 generates rotation amount information RF representing the amount of rotation of the motor 5 per carrier period based on the input carrier period event CTE and rotation angle information AF, and outputs the information to the FB signal generation circuit .

[0020] The FB signal generation circuit 35 generates an FB signal FBS corresponding to the rotation angle of the motor 5 based on the rotation amount information RF of the motor 5 input from the processor 31 and the carrier period event CTE input from the timer circuit 32, and outputs the FB signal FBS to the controller 2. The FB signal FBS is a signal equivalent to the output signal of a rotary encoder using, for example, an incremental system or a pseudo-absolute system.

[0021] According to the motor control system 1 configured as described above, the controller 2 can realize feedback control of the rotation of the motor 5 via the semiconductor device 3, which contributes to the expansion of the design of the motor control system, cost reduction, miniaturization, etc.

[0022] Recently, there has been a demand for reducing power consumption in the motor control system 1 described above. One possible method for achieving this is to reduce the carrier frequency, i.e., lengthen the carrier period, thereby reducing the switching loss of the drive circuit 4. Here, the switching loss of the drive circuit 4 will be explained with reference to the drawings.

[0023] FIG. 2 is a diagram for explaining switching loss. As shown in FIG. 2, the semiconductor device 3 can be considered to have a comparator COMP as part of the PWM generation circuit 33. A modulated wave DW signal is input to the + input terminal of the comparator COMP, and a carrier wave CW signal is input to the - input terminal of the comparator COMP. The comparator COMP outputs an on / off signal, which is a PWM signal. The IGBT serving as the drive circuit 4 performs a switching operation of the switch SW1 based on the PWM signal output from the semiconductor device 3. The drive power DPW (drive signal DV) output from the drive circuit 4 is supplied to the motor.

[0024] Here, if the frequency of the carrier wave CW is high, the frequency of switching of the switch SW1 in the IGBT serving as the drive circuit 4 increases. Furthermore, the increase in the amount of current due to voltage changes near the switch SW1 also increases its loss. Therefore, as mentioned above, lowering the carrier frequency is one possible way to reduce the switching loss of the drive circuit 4. However, if the carrier frequency is lowered to sufficiently reduce the switching loss of the drive circuit 4, the carrier frequency tends to fall into the audible range. If the carrier frequency falls into the audible range, measures to reduce noise will also be necessary.

[0025] Therefore, in the semiconductor device 3, it is possible to adopt not only a standard technique in which the carrier period is constant, but also a technique in which the carrier period changes randomly (random modulation technique). In this case, it is necessary to output an FB signal to the controller 2 in response to a variable carrier period event.

[0026] <Configuration of FB signal generation circuit based on reference technology> Here, an example of the configuration and operation of an FB signal generating circuit according to the reference technology will be described. 3 is a diagram showing an example of the configuration of an FB signal generation circuit according to the reference technology. As shown in Fig. 3, the FB signal generation circuit 35 according to the reference technology includes, for example, a register 351, an event receiving circuit 352, a step number control circuit 353, an update timing control circuit 354, a position counter control circuit 355, and an output control circuit 356.

[0027] The register 351 stores the next step number NSN and the set carrier period SCT. The next step number NSN is the amount of rotation of the motor 5 between the two most recent carrier period events CTE that are adjacent in time, expressed in terms of the number of steps. The processor 31 calculates the next step number NSN based on the input carrier period event CTE and the rotation angle information AF of the motor 5 obtained from the rotation angle monitor circuit 34. The set carrier period SCT is the period of the carrier period event CTE output by the timer circuit 32.

[0028] The event receiving circuit 352 receives the carrier cycle event CTE output from the timer circuit 32 and transmits the reception timing RTM to the step number control circuit 353 .

[0029] The step number control circuit 353 acquires the next step number NSN stored in the register 351 as the step number SN in synchronization with the reception timing RTM of the carrier cycle event CTE. The step number control circuit 353 transmits the acquired step number SN and the calculation completion timing CTM to the update timing control circuit 354.

[0030] The update timing control circuit 354 calculates the time interval Δt of the update timing FTM to be output based on the number of steps SN and the set carrier period SCT stored in the register 351. The update timing FTM is a timing signal that serves as a trigger when updating the position counter value PC, which will be described later. The update timing control circuit 354 calculates the time interval Δt of the update timing FTM, for example, by dividing the set carrier period SCT by the number of steps SN. The update timing control circuit 354 outputs the update timing FTM to the position counter control circuit 355 in synchronization with the calculation completion timing CTM and at the calculated time interval Δt.

[0031] The position counter control circuit 355 is equipped with a position counter that indicates the rotational angle position of the motor 5. When the update timing FTM is input, the position counter control circuit 355 updates the position counter value PC, which is the value of the position counter. When the motor 5 is rotating in a predetermined rotational direction, the position counter control circuit 355 increments and updates the position counter, and when the motor 5 is rotating in the opposite direction to the predetermined rotational direction, the position counter value PC is decremented and updated. The position counter value PC returns to a reference value, for example, 0, when the motor 5 makes one rotation. For example, if a value of 1 is assigned to one degree of rotational angle, the position counter will take on values ​​from 0 to 359.

[0032] The output control circuit 356 generates and outputs the FB signal FBS based on the position counter value PC. The output control circuit 356 generates, as the FB signal FBS, a pseudo signal waveform obtained by, for example, an incremental or pseudo-absolute rotary encoder. That is, when the signal waveform of an incremental rotary encoder is pseudo-generated, an on-off waveform is generated for each of the A phase and the B phase. When the signal waveform of a pseudo-absolute rotary encoder is pseudo-generated, an on-off waveform is generated for each of the A phase, the B phase, and the Z phase.

[0033] As can be seen from the above, the FB signal generation circuit 35 reproduces the movement of the motor 5 as an FB signal FBS based on the carrier period event CTE and the step number SN (rotation amount information of the motor 5). In order to reproduce the movement of the motor 5 from the carrier period event CTE and the step number SN, it is necessary to determine when to update the FB signal. In the standard technology, since the carrier period event CTE is constant, the position counter value PC is counted up (or down) at equal intervals based on the set carrier period SCT (register value) by the number of times equal to the value of the next step number NSN (rotation angle information), and an FB signal FBS corresponding to the position counter value PC is output.

[0034] <Operation flow of the FB signal generation circuit based on the reference technology> Next, an example of the operation flow of the FB signal generating circuit 35 according to the reference technology and an example of a timing chart of each signal related to the operation of the FB signal generating circuit 35 will be described.

[0035] Fig. 4 is a diagram showing an example of the operation flow of the FB signal generation circuit according to the reference technology. Note that the operation flow shown in Fig. 4 shows the operation flow per carrier period CT, and in reality, the operation flow is repeated for each carrier period CT.

[0036] 4, in step S1, a process of taking in the next step number as the step number is executed. Specifically, the step number control circuit 353 takes in the next step number NSN stored in the register 351 as the step number SN inside the step number control circuit 353.

[0037] In step S2, a process of calculating the time interval of the update timing is executed. Specifically, the update timing control circuit 354 acquires the number of steps SN from the step number control circuit 353 and stores it inside the update timing control circuit 354. The update timing control circuit 354 calculates the time interval Δt of the update timing FTM based on the set carrier period SCT stored in the register 351 and the number of steps SN acquired from the step number control circuit 353. Furthermore, the update timing control circuit 354 outputs the update timing FTM to the position counter control circuit 355 at time intervals Δt in synchronization with the calculation completion timing CTM input from the step number control circuit 353.

[0038] In step S3, a process of writing the next step number to the register 351 is executed. Specifically, the processor 31 writes the next step number NSN, which corresponds to the rotation amount of the motor 5 between the two most recent carrier cycle events CTE, to the register 351.

[0039] In step S4, a process is executed to determine whether the number of steps is a value different from 0 (number of steps ≠ 0). Specifically, the update timing control circuit 354 determines whether the number of steps SN stored inside the update timing control circuit 354 is 0. If it is determined that the number of steps SN ≠ 0 (step S4: Yes), the process proceeds to step S5. On the other hand, if it is determined that the number of steps SN ≠ 0 is not (step S4: No), the process proceeds to step S6.

[0040] In step S5, a process of adding or subtracting 1 from the position counter value is executed. Specifically, when the update timing FTM is input, the position counter control circuit 355 adds 1 to (counts up) or subtracts 1 from (counts down) the position counter value PC, which indicates the rotation angle of the motor 5. For example, if the number of steps SN is a positive value (SN>0), the position counter control circuit 355 adds 1 to the position counter value PC. Also, if the number of steps SN is a negative value (SN<0), the position counter control circuit 355 subtracts 1 from the position counter value PC.

[0041] In step S6, a process is executed to output an FB signal corresponding to the position counter value. Specifically, the output control circuit 356 generates and outputs an FB signal FBS corresponding to the rotation angle of the motor 5 represented by the current position counter value PC.

[0042] In step S7, a process is executed to determine whether the next carrier cycle event has occurred (or is occurring). Specifically, the step number control circuit 353 determines whether the next carrier cycle event CTE has occurred. If it is determined that the next carrier cycle event CTE has occurred (step S7: Yes), the FB signal generation process for one carrier cycle CT ends. On the other hand, if it is determined that the next carrier cycle event CTE has not occurred (step S7: No), the process proceeds to step S8.

[0043] In step S8, a process is executed to determine whether or not update timings for the number of steps have been output. Specifically, the update timing control circuit 354 determines whether or not update timings FTM have been output for the number of steps SN. Here, if it is determined that update timings FTM have been output for the number of steps SN (step S8: Yes), the process returns to step S6. On the other hand, if it is determined that update timings FTM have not been output for the number of steps SN (step S8: No), the process proceeds to step S9.

[0044] In step S9, a process is executed to determine whether or not update timing has occurred (or is occurring). Specifically, the update timing control circuit 354 determines whether or not update timing FTM has occurred. Here, if it is determined that update timing FTM has occurred (step S9: Yes), the process returns to step S5, and the position counter value is updated. On the other hand, if it is determined that update timing FTM has not occurred (step S9: No), the process returns to step S6.

[0045] <Signals in the FB signal generation circuit based on the standard technology> Fig. 5 is a diagram showing an example of a timing chart of each signal or value related to the operation of the feedback signal generation circuit according to the reference technology. The example shown in Fig. 5 shows each signal etc. in a state in which the rotating shaft of the motor 5 is rotating in a predetermined rotation direction while changing the rotation speed. The example shown in Fig. 5 also shows the time changes of the [rotation angle monitor value (APM)] in the rotation angle monitor circuit 34, the [carrier period event (CTE)] output from the timer circuit 32, the [rotation amount counter value (RC)] in the processor 31, and various signals and values ​​related to the internal processing of the feedback signal generation circuit 35, [FB signal (FBS)].

[0046] The various signals and values ​​related to the internal processing of the FB signal generation circuit 35 are specifically the "next step number (NSN)," "step number (SN)," "computation completion timing CTM," "update timing (FTM)," and "position counter value (PC)." Note that the "rotation angle monitor value (APM)" is assumed to be generated by an absolute encoder. The "FB signal (FBS)" is assumed to be generated by an incremental encoder.

[0047] The [rotation angle monitor value] takes on values ​​ranging from 0 to 359, for example, and corresponds to the rotation angle of the motor 5 expressed in increments of 1 degree (1°). In this example, the [rotation angle monitor value] gradually changes from 0 to a larger value over time.

[0048] [Carrier period events] are output from the timer circuit 32 at time intervals of the set carrier period SCT stored in the register 351. In this example, the set carrier period SCT is 0.5 ms. That is, the carrier frequency is 2 kHz (2000 cycles per second). In the example of FIG. 5, five carrier period events CTE are listed, from carrier period event CTE1 to carrier period event CTE5.

[0049] The [rotation amount counter value] corresponds to the rotation angle amount of the motor 5. A value of 1 in the [rotation amount counter value] corresponds to one degree (1°) of the rotation angle amount of the motor 5. However, the [rotation amount counter value] sequentially represents the rotation angle amount of the motor 5 between carrier period events CTE that are adjacent in time. Therefore, the [rotation amount counter value] is reset and starts counting again from 1 every time a carrier period event CTE is output. The [rotation amount counter value] is stored by the processor 31.

[0050] The [next step number] represents the rotation angle of the motor 5 between the two most recent carrier cycle events CTE. The [next step number] is the value of the [rotation amount counter value] at the time when the carrier cycle event CTE is output, which is taken in and stored after the carrier cycle event CTE is output.

[0051] [Number of steps] is the value of [Number of next steps] at the time when the carrier cycle event CTE is output, and is a value that is taken in and stored immediately after the carrier cycle event CTE is output.

[0052] The [Calculation Completion Timing] is output when the [Number of Steps] is updated and the calculation to find the time interval Δt for outputting the [Update Timing] is completed. Because this calculation is performed at high speed, the [Calculation Completion Timing] is almost synchronized with the [Carrier Cycle Event].

[0053] The [update timing] is triggered by the [calculation completion timing] and is output according to the calculated time interval Δt.

[0054] Like the [Rotation Angle Monitor Value], the [Position Counter Value] represents the rotation angle of the motor 5 in increments of 1 degree (1°). The [Position Counter Value] is updated sequentially in response to the [Update Timing]. Therefore, the [Position Counter Value] reflects the [Rotation Angle Monitor Value] at the point two cycles before the carrier cycle event CTE.

[0055] As shown in Figure 5, if the [rotation angle monitor value] is 5 when the carrier cycle event CTE2 is output, the [position counter value] will be 5 two carrier cycles later, that is, when the carrier cycle event CTE4 is output (see the part indicated by the symbol AT1 in Figure 5). Similarly, if the [rotation angle monitor value] is 12 when the carrier cycle event CTE3 is output, the [position counter value] will be 12 two carrier cycles later, that is, when the carrier cycle event CTE5 is output (see the part indicated by the symbol AT2 in Figure 5).

[0056] The [FB signal] is a signal that corresponds to the rotation angle position of the motor 5 based on the [position counter value]. The [FB signal] is designed so that 90 pulses are output in each of phases A and B while the rotating shaft of the motor 5 makes one rotation, and the phase difference between phases A and B is 90 degrees (90°).

[0057] <New problem discovered by the inventor> In the reference technology, the carrier period CT is constant. However, as mentioned above, a method of randomly modulating the carrier period CT can be considered to reduce power consumption. The reason for adopting this method is as follows: To reduce power consumption, it is necessary to reduce the switching loss in the drive circuit 4. Lowering the carrier frequency CF is an effective way to reduce switching loss. To sufficiently reduce switching loss, it is necessary to lower the carrier frequency CF to the audible range. When the carrier frequency CF enters the audible range, the operating frequency of the drive circuit 4 also enters the audible range, making noise at specific frequencies more noticeable. Therefore, by randomly modulating the carrier frequency CF, the operating energy is dispersed and noise at specific frequencies is reduced.

[0058] As described above, the present inventor has newly discovered that when random modulation is applied to the carrier period CT in the motor control system 1, there is a problem that does not exist in the method according to the reference technology. The problem that the present inventor has newly discovered will be described below.

[0059] In the reference technology, PWM can be performed at a constant carrier frequency CF outside the audible range in a motor control system 1 that transmits the rotation amount of a motor 5 to a controller 2. Therefore, in the design of the semiconductor device 3, particularly the FB signal generation circuit 35, a design based on equally spaced carrier period events CTE was sufficient. However, when random modulation is applied to the carrier period CT, the time intervals between the carrier period events CTE naturally do not become equally spaced.

[0060] Figure 6 shows an example of carrier period events and carrier waveforms when random modulation is applied to the carrier period. As shown in Figure 6, when random modulation is applied to the carrier period CT, the time intervals of the carrier period events CTE fluctuate, becoming shorter or longer, and the waveform of the carrier wave CW also becomes narrower or wider along the time axis.

[0061] When the number of steps SN captured by the step number control circuit 353 is relatively large and the time interval of the carrier period event CTE is quite short, the update timing control circuit 354 may not be able to output all of the update timings FTM for the number of steps SN. This may occur, for example, when calculating the time interval of the update timings FTM using the fixed set carrier period SCT stored in register 351, and the required number of update timings FTM cannot fit within the time interval of the carrier period event CTE. It may also occur, for example, when the operating speed of the update timing control circuit 354 when continuously generating the update timings FTM cannot keep up with the required operating speed.

[0062] If the update timing control circuit 354 is unable to output all of the update timings FTM for the number of steps SN, the number of steps that were not output is not compensated for and is lost. This can be easily understood by considering the processing of step S1 in the operation flow of Figure 4. This is because in step S1, regardless of whether or not the update timings FTM for the number of steps SN have been output, the next number of steps NSN is taken in as the number of steps SN when the carrier period event CTE occurs (Figure 4, step S7: Yes → End → Start).

[0063] 7 is a diagram showing an example of a timing chart of signals in the FB signal generation circuit when random modulation is applied to the carrier period. As shown in FIG. 7, if the [rotation angle monitor value] is 5 when the carrier period event CTE2 is output, the [number of steps] immediately after the next carrier period event CTE3 is output will be 5. The time interval Δt between the [update timings] is the set carrier period SCT divided by 5, which is the value of the [number of steps]. In other words, assuming that the carrier period CT is constant, the [update timings] are planned so that five [update timings] are output between the carrier period event CTE3 and the next carrier period event CTE4.

[0064] However, in reality, the carrier cycle CT is randomly modulated, so that, for example, the time between the carrier cycle event CTE3 and the next carrier cycle event CTE4 may be shorter than the set carrier cycle SCT.

[0065] For example, as shown in Figure 7, if the [Rotation Angle Monitor Value] is 5 when the carrier cycle event CTE2 is output, five [Update Timings] must be output between the carrier cycle events CTE3 and CTE4. However, it is conceivable that, for example, only three [Update Timings] are output between the carrier cycle events CTE3 and CTE4, and two are not output.

[0066] In this case, two cycles after the carrier cycle event CTE2, that is, when the carrier cycle event CTE4 is output, the [position counter value] becomes 3 (see the part indicated by the symbol AT3 in Figure 7). In other words, the [number of steps] is 5, and five steps' worth of processing are required, but two steps remain unprocessed. When the carrier cycle event CTE4 is output, the [number of next steps] at that time is taken in as the value of [number of steps]. Therefore, the two unprocessed steps out of the five steps are lost.

[0067] Also, as shown in FIG. 7, if the [rotation angle monitor value] is 12 when the carrier period event CTE3 is output, two periods after that carrier period event CTE3, that is, when the carrier period event CTE5 is output, the [position counter value] will not recover the two lost steps and will become 10 (see the part indicated by the symbol AT4 in FIG. 7).

[0068] In this way, if some steps out of the number of steps SN are lost, the rotational operation of the motor 5 is not reproduced as information in the FB signal generation circuit 35. In other words, an FB signal FBS corresponding to a rotation angle that is deviated from the actual rotation angle of the motor 5 is output, and information on the erroneous rotation angle is transmitted to the controller 2. As a result, the controller 2 is unable to accurately control the motor 5.

[0069] (Embodiment 1) The present inventors have invented the present invention as a result of extensive research to solve the above problems. Now, embodiments of the present invention will be described. A semiconductor device according to a first embodiment of the present invention manages the number of unprocessed steps among the number of steps SN as the number of remaining steps RSN, calculates the total number of steps TSN by adding the number of remaining steps RSN to the number of next steps NSN, and generates and outputs an FB signal based on the total number of steps TSN.

[0070] <Configurations of Motor Control System and Semiconductor Device According to First Embodiment> Fig. 8 is a diagram showing an example configuration of a motor control system and a semiconductor device according to embodiment 1. As shown in Fig. 8, motor control system 1A according to embodiment 1 is different from motor control system 1 according to the reference technology in that it includes semiconductor device 3A instead of semiconductor device 3. Compared to semiconductor device 3 according to the reference technology, semiconductor device 3A according to embodiment 1 is different from semiconductor device 3 according to the reference technology in that it includes timer circuit 32A instead of timer circuit 32 and includes FB signal generation circuit 35A instead of FB signal generation circuit 35.

[0071] The timer circuit 32 according to the reference technology generates carrier period events CTE at a constant carrier period. On the other hand, the timer circuit 32A according to the first embodiment generates carrier period events CTE to which random modulation is applied. That is, the timer circuit 32A generates carrier period events CTE such that the time intervals (carrier periods) between carrier period events CTE vary randomly. At least a portion of the longer carrier periods CT in the carrier period events CTE generated by the timer circuit 32A are long enough to fall within the human audible range. This reduces the switching loss of the drive circuit 4 and suppresses noise.

[0072] <Configuration of FB signal generating circuit according to first embodiment> Fig. 9 is a diagram showing an example of the configuration of the FB signal generation circuit according to embodiment 1. As shown in Fig. 9, the FB signal generation circuit 35A according to embodiment 1 differs from the FB signal generation circuit 35 according to the reference technology in the following respects.

[0073] In the FB signal generation circuit 35A, the register 351 stores a reference carrier period RCT instead of the set carrier period SCT. The reference carrier period RCT refers to a representative carrier period in a random modulation carrier period event CTE. The reference carrier period RCT is, for example, a period corresponding to the average or median of the fluctuating carrier period CT. Alternatively, it is, for example, the reciprocal of the central frequency in the fluctuation range of the carrier frequency CF. If the carrier frequency CF fluctuates between 6 kHz and 10 kHz, the reference carrier frequency RCF is, for example, 8 kHz, and the reference carrier period RCT is the reciprocal of the reference carrier frequency RCF of 8 kHz.

[0074] As in the case of the reference technique, the register 351 also stores the next step number NSN corresponding to the amount of rotation of the motor 5 between two temporally adjacent carrier period events CTE, but there is no difference in this function.

[0075] Furthermore, the FB signal generating circuit 35A is newly provided with a remaining step number control circuit 357. Furthermore, instead of the step number control circuit 353, a total step number control circuit 358 is provided.

[0076] The remaining step number control circuit 357 stores the number of steps that remain unprocessed among the number of steps that should be processed to generate the FB signal FBS between the two most recent carrier cycle events CTE as the remaining step number RSN.

[0077] When a carrier cycle event CTE is input, the total step number control circuit 358 takes in the number of steps obtained by adding the next step number NSN stored in the register 351 and the remaining step number RSN stored in the remaining step number control circuit 357 as the total step number TSN. The total step number control circuit 358 outputs the total step number TSN to the update timing control circuit 354.

[0078] The update timing control circuit 354 calculates the time interval Δt of the update timing FTM based on the reference carrier period RCT stored in the register 351 and the total number of steps TSN input from the total step number control circuit 358. The time interval Δt of the update timing FTM is obtained, for example, by dividing the reference carrier period RCT by the total number of steps TSN. The update timing control circuit 354 outputs the update timing FTM for the total number of steps TSN to the position counter control circuit 355 at the calculated time interval Δt.

[0079] When the update timing FTM is input, the position counter control circuit 355 updates the internal position counter value PC.

[0080] The output control circuit 356 generates an FB signal FBS based on the position counter value PC inside the position counter control circuit 355 and outputs it to the controller 2.

[0081] Here, we will explain how each of the remaining step number control circuit 357, total step number control circuit 358, update timing control circuit 354, position counter control circuit 355, and output control circuit 356 functions within a series of processing flows based on the occurrence of a carrier period event CTE.

[0082] The remaining step number control circuit 357 obtains the first remaining step number RSN_1 by subtracting the number of steps that could be processed to generate the FB signal FBS between the first carrier period event CTE_1 and the second carrier period event CTE_2 immediately following it from the first next step number NSN_1 stored in the register 351 at the time the first carrier period event CTE_1 occurs.

[0083] For example, in response to the occurrence of a first carrier cycle event CTE_1, the remaining step number control circuit 357 captures the value of the first total number of steps TSN_1 immediately before the second total number of steps TSN_2 as an internal counter value. Then, the remaining step number control circuit 357 obtains the first remaining number of steps RSN_1 by subtracting 1 from the internal counter value every time update timing FTM is input.

[0084] However, when the first update timing FTM_1 of the multiple update timings FTM corresponding to the first total number of steps TSN_1 is output in response to the occurrence of the first carrier cycle event CTE_1, a value obtained by subtracting 1 from the value of the first total number of steps TSN_1 may be set as the initial value of the remaining number of steps RSN. That is, when the carrier cycle event CTE is input, the remaining step number control circuit 357 stores the value of the total number of steps TSN-1 as the initial value of the remaining number of steps RSN. Then, thereafter, every time an update timing FTM is output, that is, every time the position counter value PC is updated, the remaining step number control circuit 357 subtracts 1 from the stored remaining number of steps RSN to update it. By the above operation, the remaining step number control circuit 357 always stores the number of unprocessed steps as the remaining number of steps RSN.

[0085] In addition, the remaining step number control circuit 357 obtains the first remaining step number RSN_1 when the number of steps that can be processed to generate the FB signal FBS within the first time ΔT1 is smaller than the first next step number NSN_1 because the first time ΔT1 between the first carrier period event CTE_1 and the second carrier period event CTE_2 is shorter than the reference carrier period RCT.

[0086] The total step number control circuit 358 obtains the second total step number TSN_2 by adding the second next step number NSN_2 stored in the register 351 and the first remaining step number RSN_1 at the time when the second carrier period event CTE_2 occurs.

[0087] The update timing control circuit 354 receives the second total number of steps TSN_2 as an input from the total step number control circuit 358. The update timing control circuit 354 determines the time interval Δt of the update timing FTM based on the reference carrier period RCT and the second total number of steps TSN_2, and outputs the update timing FTM at the determined time interval Δt to the remaining step number control circuit 357. The update timing control circuit 354 obtains and determines the time interval Δt of the update timing FTM, for example, by dividing the reference carrier period RCT by the second total number of steps TSN_2.

[0088] The position counter control circuit 355 updates the position counter value PC, which reproduces the rotational angle position of the motor 5, in synchronization with the update timing FTM.

[0089] The output control circuit 356 generates the FB signal FBS based on the updated position counter value PC.

[0090] The update timing control circuit 354, the position counter control circuit 355, and the output control circuit 356 are examples of the "output circuit" in this application. The processor 31, the timer circuit 32, and the FB signal generation circuit 35A may be formed on a semiconductor chip.

[0091] According to this FB signal generation circuit 35A, in the FB signal generation process corresponding to one carrier period event CTE, the number of unprocessed steps among the number of steps SN representing the amount of rotation of the motor 5 is managed as the number of remaining steps RSN. Then, in the FB signal generation process corresponding to the next carrier period event CTE, the number of remaining steps RSN is added to the number of steps SN representing the amount of rotation of the motor 5. This process makes it possible to avoid the loss of the number of unprocessed steps.

[0092] <Operation Flow of the FB Signal Generation Circuit According to the First Embodiment> An example of the operation flow of the FB signal generating circuit 35A according to the first embodiment and an example of a timing chart of each signal related to the operation of the FB signal generating circuit 35A will be described.

[0093] Fig. 10 is a diagram showing an example of the operation flow of the FB signal generation circuit according to the first embodiment. As shown in Fig. 10, in the operation flow of the FB signal generation circuit according to the first embodiment, steps S10 and S11 are added instead of step S1, step S12 is added between steps S5 and S6, and step S13 is further added instead of step S8, compared to the operation flow of the FB signal generation circuit according to the reference technology in Fig. 4. The processing of steps S2 to S5, steps S6 to S7, S13, and S9 according to the first embodiment is substantially the same as steps S2 to S5 and steps S6 to S9 according to the reference technology. However, the number of steps SN needs to be read as the total number of steps TSN.

[0094] 10, in step S10, a process of acquiring the number of remaining steps is executed. Specifically, the total step number control circuit 358 acquires the remaining step number RSN stored in the remaining step number control circuit 357 from the remaining step number control circuit 357. Thereafter, the process proceeds to step S11.

[0095] In step S11, a process is executed to calculate the total number of steps to be processed before the next carrier period event. Specifically, the total step number control circuit 358 calculates the total number of steps TSN by adding the remaining number of steps RSN obtained from the remaining step number control circuit 357 to the next step number NSN stored in the register 351. The remaining step number control circuit 357 stores the calculated total number of steps TSN as the remaining number of steps RSN. Thereafter, the process proceeds to step S2.

[0096] In step S2, a process of calculating the time interval of the update timing is executed. Specifically, the update timing control circuit 354 acquires the total number of steps TSN from the total step number control circuit 358 and stores it inside the update timing control circuit 354. The update timing control circuit 354 calculates the time interval Δt of the update timing FTM based on the reference carrier period RCT stored in the register 351 and the total number of steps TSN acquired from the total step number control circuit 358. For example, the time interval Δt is calculated by dividing the reference carrier period RCT by the total number of steps TSN. Furthermore, the update timing control circuit 354 transmits the update timing FTM to the position counter control circuit 355 at intervals of the time interval Δt in synchronization with the calculation completion timing CTM received from the total step number control circuit 358.

[0097] In step S3, a process of writing the next step number to the register 351 is executed. Specifically, the processor 31 writes the next step number NSN, which corresponds to the rotation amount of the motor 5 between the two most recent carrier cycle events CTE, to the register 351.

[0098] In step S4, a process is executed to determine whether the total number of steps is a value different from 0 (total number of steps≠0). Specifically, the update timing control circuit 354 determines whether the total number of steps TSN stored in the processing unit of the update timing control circuit 354 is 0 or not. Here, if it is determined that the total number of steps TSN≠0 (step S4: Yes), the process proceeds to step S5. On the other hand, if it is determined that the total number of steps TSN is not 0 (step S4: No), the process proceeds to step S6.

[0099] In step S5, a process of adding 1 to or subtracting 1 from the position counter value is executed. Specifically, each time the position counter control circuit 355 receives the update timing FTM, it adds 1 to (counts up) or subtracts 1 from (counts down) the position counter value PC, which indicates the rotational angle position of the motor 5. For example, if the total number of steps TSN is a positive value (TSN>0), the position counter control circuit 355 adds 1 to the position counter value PC. Also, if the total number of steps TSN is a negative value (TSN<0), the position counter control circuit 355 subtracts 1 from the position counter value PC. Thereafter, the process proceeds to step S12.

[0100] In step S12, the remaining number of steps is decremented by 1 and stored. Specifically, the remaining step number control circuit 357 decrements the remaining step number RSN stored in the remaining step number control circuit 357 by 1, and stores the resulting number of steps as a new remaining step number RSN. Thereafter, the processing proceeds to step S6.

[0101] In step S6, a process is executed to generate and output an FB signal corresponding to the position counter value. Specifically, the output control circuit 356 generates and outputs an FB signal FBS corresponding to the rotational angle position of the motor 5 represented by the current position counter value PC.

[0102] In step S7, a process is executed to determine whether the next carrier cycle event has occurred (or is occurring). Specifically, the step number control circuit 353 determines whether the next carrier cycle event CTE has occurred. If it is determined that the next carrier cycle event CET has occurred (step S7: Yes), the FB signal generation process for one carrier cycle CT ends. On the other hand, if it is determined that the next carrier cycle event CTE has not occurred (step S7: No), the process proceeds to step S13.

[0103] In step S13, a process is executed to determine whether or not update timings for the total number of steps have been output. Specifically, the update timing control circuit 354 determines whether or not update timings FTM have been output for the total number of steps TSN. Here, if it is determined that update timings FTM have been output for the total number of steps TSN (step S13: Yes), the process proceeds to step S6. On the other hand, if it is determined that update timings FTM have not been output for the total number of steps TSN (step S13: No), the process proceeds to step S9.

[0104] In step S9, a process is executed to determine whether or not update timing has occurred. Specifically, the update timing control circuit 354 determines whether or not update timing FTM has occurred. Here, if it is determined that update timing FTM has occurred (step S9: Yes), the process returns to step S5, and the position counter value is updated. On the other hand, if it is determined that update timing FTM has not occurred (step S9: No), the process returns to step S6.

[0105] <Timing chart of signals etc. according to the first embodiment> 11 is a diagram showing an example of a timing chart of signals in the FB signal generation circuit according to the first embodiment. As shown in FIG. 11, for example, assume that the time between the carrier cycle event CTE3 and the carrier cycle event CTE4 is shorter than the reference carrier cycle RCT. Also assume that three [Update Timings] are output between the carrier cycle event CTE3 and the carrier cycle event CTE4, and two are not output. In other words, the [Number of Steps] is 5, and five steps of processing are required, but two steps are not processed.

[0106] However, when the carrier cycle event CTE4 is output, the [remaining number of steps] is 2, representing the two unprocessed steps. Also, at this point, the [total number of steps] is 9, calculated by adding the [next step number] value of 7 to the [remaining number of steps] value of 2. If the time between the carrier cycle events CTE4 and CTE5 is long enough, nine [update timing] pulse signals will be output, based on the [total number of steps] value of 9. Even if the time between the carrier cycle events CTE4 and CTE5 is not long enough and unprocessed steps occur again, the unprocessed steps will be carried over as the remaining number of steps RSN. Then, the unprocessed steps can be processed when the time between subsequent carrier cycle events CTE becomes long enough.

[0107] In the example shown in Figure 11, the [rotation angle monitor value] is 5 at the time corresponding to carrier cycle event CTE2, and the [position counter value] is 3 at the time corresponding to carrier cycle event CTE4 two cycles later (see the part indicated by reference symbol AT5 in Figure 11). However, the [rotation angle monitor value] is 12 at the time corresponding to carrier cycle event CTE3, and the [position counter value] is 12 at the time corresponding to carrier cycle event CTE5 two cycles later (see the part indicated by reference symbol AT6 in Figure 11). There is a time when the [position counter value] and the [rotation angle monitor value] are out of sync, but then the lag is resolved.

[0108] Thus, according to the first embodiment, even if random modulation is applied to the carrier period event CTE to suppress switching loss, it is possible to avoid the loss of unprocessed steps among the number of steps SN, and the rotational operation of the motor 5 is reproduced as information. As a result, an FB signal corresponding to the actual rotational angle position of the motor 5 is output, and information on the correct rotational angle is transmitted to the controller 2. This allows the controller 2 to accurately control the motor 5.

[0109] (Embodiment 2) The method of controlling a motor described above is also one embodiment of the present invention. That is, the motor control method according to embodiment 2 of the present invention can be described as follows.

[0110] The motor control method according to the second embodiment includes the processor 31 generating and outputting a signal for controlling the motor 5 based on instruction information CMF input from the controller 2, and generating and outputting rotation amount information RF of the motor 5 based on rotation angle information AF input from the motor 5 side, the timer circuit 32 generating a randomly modulated carrier period event CTE, and the FB signal generation circuit 35 generating an FB signal FBS corresponding to the rotation angle of the motor 5 based on the rotation amount information RF of the motor 5 input from the processor 31 and the carrier period event CTE generated by the timer circuit 32, and outputting the FB signal FBS to the controller 2. Furthermore, the generation and output of the FB signal FBS by the FB signal generation circuit 35 is also performed by the register 351 registering a next step number NS corresponding to the rotation amount of the motor 5 between two temporally adjacent carrier period events CTE. a remaining step number control circuit 357 obtaining a first remaining number of steps RSN_1 by subtracting the number of steps that could be processed for generating a feedback signal FBS between the first carrier period event CTE_1 and a second carrier period event CTE_2 immediately thereafter from a first next step number NSN_1 stored in the register 351 at the time the first carrier period event CTE_1 occurred; a total step number control circuit 358 obtaining a second total number of steps TSN_2 by adding the second next step number NSN_2 stored in the register 351 and the first remaining step number RSN_1 at the time the second carrier period event CTE_2 occurred; and an output control circuit 356 generating and outputting a feedback signal FBS based on the second total number of steps TSN_2.

[0111] According to the second embodiment, as in the first embodiment, even if random modulation is applied to the carrier period event CTE to suppress switching loss, it is possible to avoid the loss of unprocessed steps among the number of steps SN, and the rotational operation of the motor 5 is reproduced as information. As a result, an FB signal corresponding to the actual rotational angle position of the motor 5 is output, and information on the correct rotational angle is transmitted to the controller 2. This allows the controller 2 to accurately control the motor 5.

[0112] The invention made by the inventor has been described above based on the embodiments, but the present invention is not limited to the above embodiments and various modifications are possible within the scope of the present invention. For example, at least some of the elements constituting the semiconductor device 3 may be provided outside the semiconductor device 3. In this case, the elements provided outside the semiconductor device 3 may be configured using other semiconductors or may be configured by discrete circuits, etc. [Explanation of symbols]

[0113] 1,1A...motor control system, 2...controller, 3,3A...semiconductor device, 4...drive circuit, 5...motor, 31...processor, 32,32A...timer circuit, 33...PWM generation circuit, 34...rotation angle monitor circuit, 35,35A...FB signal generation circuit, 51...encoder, 351...register, 352...event receiving circuit, 353...step number control circuit, 354...update timing control circuit, 355...position counter control circuit, 356...output control circuit, 357...remaining step number control circuit, 358...total step number control circuit

Claims

1. a processor that generates and outputs a signal for controlling the motor based on instruction information input from an external controller, and generates and outputs rotation amount information of the motor based on rotation angle information input from the motor side; a timer circuit for generating a randomly modulated carrier period event; a feedback signal generating circuit that generates a feedback signal corresponding to the rotation angle of the motor based on the rotation amount information of the motor input from the processor and the carrier period event generated by the timer circuit, and outputs the feedback signal to the controller; Equipped with The feedback signal generating circuit a register for storing the next step number corresponding to the rotation amount of the motor between two temporally adjacent carrier period events; a remaining step number control circuit that obtains a first remaining step number by subtracting the number of steps that could be processed for generating the feedback signal between the first carrier cycle event and a second carrier cycle event that occurs immediately thereafter from a first next step number stored in the register at the time the first carrier cycle event occurs; a total step number control circuit that, at the time when the second carrier cycle event occurs, obtains a second total step number by adding the second next step number stored in the register to the first remaining step number; an output circuit that generates and outputs the feedback signal based on the second total number of steps; having Semiconductor device.

2. 2. The semiconductor device according to claim 1, the remaining step number control circuit obtains the first remaining step number when a first time between the first carrier period event and the second carrier period event is shorter than a reference carrier period, and therefore the number of steps that can be processed for generating the feedback signal within the first time is smaller than the first next step number; Semiconductor device.

3. 3. The semiconductor device according to claim 2, The reference carrier period is a representative carrier period in the carrier period event of the random modulation. Semiconductor device.

4. 4. The semiconductor device according to claim 3, the remaining step number control circuit, in response to the occurrence of the first carrier cycle event, takes in the value of the first total number of steps immediately before the second total number of steps as an internal counter value, and obtains the first remaining number of steps by subtracting and updating the internal counter value by one each time an update timing is input; Semiconductor device.

5. 5. The semiconductor device according to claim 4, the feedback signal generation circuit includes an update timing control circuit to which the second total number of steps is input from the total step number control circuit; the update timing control circuit determines a time interval of the update timing based on the reference carrier period and the second total number of steps, and outputs the update timing at the determined time interval to the remaining step number control circuit. Semiconductor device.

6. 6. The semiconductor device according to claim 5, the update timing control circuit determines the time interval of the update timing by dividing the reference carrier period by the second total number of steps. Semiconductor device.

7. 6. The semiconductor device according to claim 5, the feedback signal generation circuit generates the feedback signal by updating a position counter value that reproduces the angular position of the motor in synchronization with the update timing. Semiconductor device.

8. 2. The semiconductor device according to claim 1, a PWM generating circuit that generates a PWM signal based on a signal for controlling the motor and outputs the PWM signal to a drive circuit of the motor; Semiconductor device.

9. 2. The semiconductor device according to claim 1, the processor, the timer circuit, and the feedback signal generating circuit are formed on a semiconductor chip; Semiconductor device.

10. A motor control system comprising: the semiconductor device according to claim 1; the controller; and the motor.

11. The processor generates and outputs a signal for controlling the motor based on instruction information input from the controller, and generates and outputs rotation amount information of the motor based on rotation angle information input from the motor side; a timer circuit generating a randomly modulated carrier period event; a feedback signal generation circuit generating a feedback signal corresponding to the rotation angle of the motor based on the rotation amount information of the motor input from the processor and the carrier period event generated by the timer circuit, and outputting the feedback signal to the controller; The feedback signal generating circuit generates and outputs the feedback signal, a register storing a next step number corresponding to the amount of rotation of the motor between two temporally adjacent carrier period events; a remaining step number control circuit obtains a first remaining step number by subtracting the number of steps that could be processed for generating the feedback signal between the first carrier cycle event and a second carrier cycle event that occurs immediately thereafter from a first next step number stored in the register at the time when the first carrier cycle event occurs; a total step number control circuit, at a time point when the second carrier cycle event occurs, adding the second next step number stored in the register to the first remaining step number to obtain a second total step number; an output circuit generating and outputting the feedback signal based on the second total number of steps; Motor control methods.

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