Contact-over-active gate structure with widened, low capacitance insulating cap layer for fabrication of advanced integrated circuit structure

Abstract

To provide a contact-over-active-gate (COAG) structure with an extended, low-capacitance gate insulating cap layer and a method for manufacturing the same.SOLUTION: An integrated circuit structure 320 includes a vertical stack, or fin, of horizontal nanowires 324. An epitaxial source or drain structure 326 is coupled to the vertical stack, or fin, of horizontal nanowires. A gate stack 328 is above the vertical stack, or fin, of horizontal nanowires, and the gate stack includes a gate dielectric and a gate electrode. Gate dielectric spacers 330 are located along the sides of the gate stack. A gate insulating cap layer is above the gate stack, extends laterally beyond the gate stack, and extends vertically above the gate dielectric spacers, and includes a dielectric liner 338A and a dielectric filler 338B.SELECTED DRAWING: Figure 3B

Description

[Background technology]

[0001] Over the past few decades, feature scaling in integrated circuits has been the driving force behind the ever-growing semiconductor industry. Scaling to smaller and smaller features allows for an increased density of functional units on the limited real estate of a semiconductor chip. For example, shrinking transistor dimensions allows more memory or logic devices to be packed onto a chip, increasing the capacity of manufactured products. However, this push to ever greater capacity is not without challenges. The need to optimize the performance of each device is becoming increasingly important.

[0002] Variabilities in traditional and currently known manufacturing processes may limit the ability to advance further into the 10 nanometer node or sub-10 nanometer node range. Consequently, fabrication of functional components required for future technology nodes may require the introduction of new methods or the integration of new technologies into current manufacturing processes or the replacement of current manufacturing processes.

[0003] In the fabrication of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more widely used as device dimensions continue to shrink. Tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some cases, bulk silicon substrates are preferred due to their lower cost and compatibility with existing high-yield bulk silicon substrate infrastructure.

[0004] However, multi-gate transistors cannot be scaled without impact. As the dimensions of these building blocks of microelectronic circuits decrease, and as the number of building blocks that can be fabricated in a given area increases, the constraints on the semiconductor processes used to fabricate these building blocks become greater. [Brief explanation of the drawings]

[0005] [Figure 1A] 1 illustrates a plan view of a semiconductor device having a gate contact disposed over an inactive portion of a gate electrode. [Figure 1B] 1 illustrates a cross-sectional view of a non-planar semiconductor device having a gate contact disposed over an inactive portion of a gate electrode.

[0006] [Figure 2A] 1 illustrates a plan view of a semiconductor device having a gate contact via disposed above an active portion of a gate electrode according to an embodiment of the present disclosure. [Figure 2B] FIG. 2 illustrates a cross-sectional view of a non-planar semiconductor device having a gate contact via disposed above an active portion of a gate electrode according to an embodiment of the present disclosure.

[0007] [Figure 3A] 1 shows a cross-sectional view illustrating an integrated circuit structure having a gate structure with a conventional gate insulating cap layer.

[0008] [Figure 3B] 1 shows a cross-sectional view illustrating an integrated circuit structure having a gate structure with a widened, low capacitance gate insulating cap layer according to one embodiment of the present disclosure.

[0009] [Figure 3C] 1A-1C illustrate cross-sectional views illustrating various steps in a method of manufacturing an integrated circuit structure having a gate structure with a widened, low capacitance gate insulating cap layer according to an embodiment of the present disclosure. [Figure 3D] 1A-1C illustrate cross-sectional views illustrating various steps in a method of manufacturing an integrated circuit structure having a gate structure with a widened, low capacitance gate insulating cap layer according to an embodiment of the present disclosure. [Figure 3E] 1A-1C illustrate cross-sectional views illustrating various steps in a method of manufacturing an integrated circuit structure having a gate structure with a widened, low capacitance gate insulating cap layer according to an embodiment of the present disclosure.

[0010] [Figure 4-1] 4A and 4B show cross-sectional views illustrating various steps in a method of manufacturing an integrated circuit structure having a gate contact structure disposed above an active portion of the gate, according to one embodiment of the present disclosure. [Figure 4-2] 4C and 4D show cross-sectional views illustrating various steps in a method of manufacturing an integrated circuit structure having a gate contact structure disposed above an active portion of the gate according to one embodiment of the present disclosure.

[0011] [Figure 5] 1A-1C illustrate a plan view and corresponding cross-sectional views of an integrated circuit structure with a trench contact including an overlying insulating cap layer according to one embodiment of the present disclosure.

[0012] [Figure 6-1] 6A and 6B show cross-sectional views of various integrated circuit structures, each having a trench contact including an overlying insulating cap layer and a gate stack including an overlying insulating cap layer, according to one embodiment of the present disclosure. [Figure 6-2] 6C and 6D show cross-sectional views of various integrated circuit structures, each having a trench contact including an overlying insulating cap layer and a gate stack including an overlying insulating cap layer, according to one embodiment of the present disclosure. [Figure 6-3] 6E and 6F show cross-sectional views of various integrated circuit structures, each having a trench contact including an overlying insulating cap layer and a gate stack including an overlying insulating cap layer, according to one embodiment of the present disclosure.

[0013] [Figure 7] 7A and 7B show plan views of another semiconductor device having a gate contact via disposed above an active portion of a gate and a trench contact via coupling a pair of trench contacts, respectively, in accordance with another embodiment of the present disclosure.

[0014] [Figure 8-1] 8A, 8B and 8C show cross-sectional views illustrating various steps in a method for fabricating an integrated circuit structure with a gate stack having an overlying insulating cap layer with different architectures.

[0015] [Figure 8-2] 8D and 8E show cross-sectional views illustrating various steps in a method of manufacturing an integrated circuit structure with a gate stack having an overlying insulating cap layer with different architectures.

[0016] [Figure 9] 1 illustrates a computing device according to one implementation of the present disclosure.

[0017] [Figure 10] 1 illustrates an interposer including one or more embodiments of the present disclosure.

[0018] [Figure 11] FIG. 1 is an isometric view of a mobile computing platform employing an IC manufactured according to one or more processes described herein or including one or more features described herein, in accordance with one embodiment of the present disclosure.

[0019] [Figure 12] FIG. 1 illustrates a cross-sectional view of a flip-chip mounted die according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0020] A contact over active gate (COAG) structure with an extended, low-capacitance gate insulating cap layer and a method for fabricating a contact over active gate (COAG) structure using an extended, low-capacitance gate insulating cap layer are described. In the following description, numerous specific details are set forth, such as specific integration and material configurations, to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to those skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as the design layout of integrated circuits, are not described in detail in order to avoid unnecessarily obscuring embodiments of the present disclosure. Furthermore, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0021] The following Detailed Description is merely exemplary in nature and is not intended to limit the subject embodiments or the application and uses of such embodiments. As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding Technical Field, Background, or Summary or the Detailed Description below.

[0022] This specification includes references to "one embodiment" or "an embodiment." The appearances of the phrases "in one embodiment" or "in an embodiment" do not necessarily refer to the same embodiment. The particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.

[0023] [term] The following paragraphs provide definitions or context for terms found in this disclosure (including the appended claims).

[0024] "Comprising" - This term is open-ended. When this term is used in the following claims, it does not exclude additional structures or steps.

[0025] "Configured to" - Various units or components may be described or claimed as "configured to" perform one or more tasks. In such contexts, "configured to" is used to connote structure by indicating that the unit or component includes structure that performs one or more tasks during operation. Thus, a unit or component may be said to be configured to perform a task even when the specified unit or component is not currently running (e.g., not powered on or active). Describing a unit or circuit or component as "configured to" perform one or more tasks expressly does not intend to invoke 35 U.S.C. 112, paragraph 6, with respect to that unit or component.

[0026] "First," "second," etc. As used herein, these terms are used as designators for the nouns that follow them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.).

[0027] "Coupled" - the following statement refers to elements or nodes or features that are "coupled" together. As used herein, unless expressly stated otherwise, "coupled" means that one element or node or feature is directly or indirectly connected to (or in direct or indirect communication with) another element or node or feature, not necessarily by a mechanical coupling.

[0028] Additionally, certain terminology may also be used in the following description for reference purposes only and, therefore, is not intended to be limiting. For example, terms such as "upper," "lower," "upper," and "lower" refer to directions in the drawings to which reference is made. Terms such as "front," "back," "rear," "side," "outward," and "inward" describe the orientation and / or location of parts of a component in a consistent, but arbitrary, coordinate system that becomes apparent by reference to the text and associated drawings that describe the component being described. Such terms may include the words specifically mentioned above, derivatives thereof, and words of similar import.

[0029] "Inhibit" - As used herein, inhibit is used to describe a reduced or minimized effect. When a component or feature is described as inhibiting an action, operation, or condition, it may completely prevent that result or outcome or future condition. Additionally, "inhibit" may also refer to a decrease or reduction in a result, performance, or effect that would otherwise occur. Thus, when a component, element, or feature is said to inhibit a result or condition, it is not necessary to completely prevent or eliminate the result or condition.

[0030] Embodiments described herein may relate to semiconductor processing and construction at the substrate end of line (FEOL). FEOL is the first part of integrated circuit (IC) manufacturing, where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned into a semiconductor substrate or layer. FEOL generally encompasses everything up to, but not including, the deposition of metal interconnect layers. After the final FEOL step, the result typically is a wafer with isolated (e.g., free of any wires) transistors.

[0031] The embodiments described herein may relate to semiconductor processes and structures at the back-end of the wiring (BEOL). BEOL is the second part of IC manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, e.g., one or more metallization layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL part of the manufacturing stage, contacts (pads), interconnect wires, vias, and dielectric structures are formed. In modern IC processes, more than 10 metal layers can be added at the BEOL.

[0032] The embodiments described below may be applied to FEOL processes and structures, BEOL processes and structures, or both FEOL and BEOL processes and structures. In particular, while example processing schemes may be illustrated using FEOL processing scenarios, such approaches may also be applicable to BEOL processing. Similarly, while example processing schemes may be illustrated using BEOL processing scenarios, such approaches may also be applicable to FEOL processing.

[0033] According to one embodiment of the present disclosure, a contact-over-active-gate (COAG) structure and process are described. In one embodiment, a gate insulating cap layer is described. One or more embodiments of the present disclosure relate to an integrated circuit structure or device having one or more gate contact structures (e.g., as gate contact vias) disposed above an active portion of a gate electrode of the integrated circuit structure or device. One or more embodiments of the present disclosure relate to a method of fabricating an integrated circuit structure or device having one or more gate contact structures formed above an active portion of a gate electrode of the integrated circuit structure or device. The approaches described herein can be used to reduce standard cell area by enabling gate contact formation above the active gate region. In one or more embodiments, the gate contact structure fabricated to contact the gate electrode is a self-aligned via structure. According to one or more embodiments of the present disclosure, a wide-width, low-k liner of a gate etch stop cap for yield and performance is described. One or more embodiments described herein relate to a gate-all-around device. It should be understood that unless otherwise indicated, a reference to a nanowire may refer to a nanowire, nanoribbon, or nanosheet. One or more embodiments described herein relate to FinFET devices.

[0034] For background, gate etch stop cap structures (also called gate insulating layers (GILA) or gate insulating cap layers) are commonly used as contact etch stop layers to enable self-aligned source or drain (S / D) contacts. Gate etch stop caps are typically formed by gate tungsten (W) recess, nitride liner deposition, etchback, nitride fill, and planarization (CMP). This approach can lead to both potential yield issues and suboptimal fringing capacitance due to nitride over the gate metal. One potential yield issue is gate metal etchout. Nitride liner deposition and etchback of the gate etch stop cap are typically required to create a larger gate opening / surface for better nitride fill. Resputtering of the W gate metal during the liner etch can occur, resulting in the formation of W stringers on the liner sidewalls, which can undesirably provide a gate W etch path for subsequent trench contact (TCN) S / D contact etch cleans and potentially cause yield issues due to missing gate metal. Additionally, the fringing capacitance between the gate metal and the TCN is partly related to the high-k nitride on top of the gate metal.

[0035] Previous approaches to address the gate metal etch-out problem have been to use thicker liner deposition and less etch-back processes to avoid exposing the gate W metal and thus avoid re-sputtering of the gate W metal. While this process significantly improves the fail mode, it still leaves a process window limit and potential yield risk due to process variations. Previous solutions did not require spacer replacement to reduce fringing capacitance. The thicker liner deposition / less etch-back process may still leave a process window limit and potential yield risk due to process variations. Tungsten stringers can leave lateral paths that can lead to shorts.

[0036] According to one embodiment of the present disclosure, a gate etch-stop cap approach is described to achieve a structure using a low-k liner, which can eliminate yield issues and provide improved (reduced) fringing capacitance due to the low-k liner. In one embodiment, a lateral etch of a spacer / nitride etch stop layer (NESL) is added after gate tungsten (W) metal recess to remove the spacer, trim the NESL thinner, backfill with a low-k liner without etchback, and then form a gate cap with nitride. In one embodiment, this approach does not rely on liner etchback and therefore can eliminate the gate etch-out fail mode due to W resputtering. In one embodiment, the low-k liner and thinner NESL help reduce fringing capacitance.

[0037] Benefits of implementing the embodiments described herein may include the reduction or elimination of gate etch-out failure modes due to resputtering of W. The low-k liner and thinner NESL can be detected in cross-section and may help reduce fringing capacitance.

[0038] By way of background, in technologies with somewhat relaxed space and layout constraints compared to those of current generations, contact to a gate structure may be made by contacting a portion of the gate electrode that is disposed above an isolation region. As an example, Figure 1A shows a plan view of a semiconductor device having a gate contact disposed above an inactive portion of the gate electrode.

[0039] Referring to FIG. 1A, an integrated circuit structure or device 100A includes a diffusion or active region 104 disposed in a substrate 102 and within an isolation region 106. One or more gate lines (also known as poly lines), such as gate lines 108A, 108B, and 108C, are disposed over the diffusion or active region 104 and over a portion of the isolation region 106. Source or drain contacts (also known as trench contacts), such as contacts 110A and 110B, are disposed over the source and drain regions of the integrated circuit structure or device 100A. Trench contact vias 112A and 112B provide contact to trench contacts 110A and 110B, respectively. An isolation gate contact 114 and an overlying gate contact via 116 provide contact to gate line 108B. In contrast to the source or drain trench contacts 110A or 110B, the gate contact 114 is, from a plan view perspective, located above the isolation region 106 but not above the diffusion or active region 104. Furthermore, neither the gate contact 114 nor the gate contact via 116 is located between the source or drain trench contacts 110A and 110B.

[0040] 1B illustrates a cross-sectional view of a non-planar semiconductor device having a gate contact disposed over an inactive portion of a gate electrode. Referring to FIG. 1B, an integrated circuit structure or device 100B, e.g., a non-planar version of device 100A of FIG. 1A, includes a non-planar diffusion or active region 104B (e.g., a fin structure) formed from a substrate 102 within an isolation region 106. A gate line 108B is disposed over the non-planar diffusion or active region 104B and over a portion of the isolation region 106. As shown, gate line 108B includes a gate electrode 150 and a gate dielectric layer 152, along with a dielectric cap layer 154. Gate contact 114 and overlying gate contact via 116 are also seen from this perspective, along with overlying metal interconnect 160, all of which are disposed in interlevel dielectric stack or layer 170. Also, from the perspective of Figure 1B, gate contact 114 is disposed over isolation region 106, but not over non-planar diffusion or active region 104B.

[0041] 1A and 1B, integrated circuit structures or devices 100A and 100B, respectively, are configured such that the gate contact is placed above the isolation region. Such configurations waste layout space. However, placing the gate contact above the active region requires very tight alignment tolerances or otherwise increases the gate dimensions to provide sufficient space for the gate contact to land. Furthermore, contacting a gate above a diffusion region has traditionally been avoided due to the risk of perforating other gate materials (e.g., polysilicon) and contacting the underlying active region. One or more embodiments described herein address the above-mentioned problems by providing a feasible approach to fabricating a contact structure, and resulting structure, that contacts a portion of a gate electrode formed above a diffusion or active region.

[0042] As an example, Figure 2A illustrates a plan view of a semiconductor device having a gate contact via disposed over an active portion of a gate electrode, according to one embodiment of the present disclosure. Referring to Figure 2A, an integrated circuit structure or device 200A includes a diffusion or active region 204 disposed in a substrate 202 and within an isolation region 206. One or more gate lines, such as gate lines 208A, 208B, and 208C, are disposed over the diffusion or active region 204 and over a portion of the isolation region 206. Source or drain trench contacts, such as trench contacts 210A and 210B, are disposed over the source and drain regions of the integrated circuit structure or device 200A. Trench contact vias 212A and 212B provide contact to trench contacts 210A and 210B, respectively. Gate contact via 216, without an intervening isolation gate contact layer, provides contact to gate line 208B. In contrast to FIG. 1A, gate contact 216 is located, from a plan view perspective, above diffusion or active region 204 and between source or drain contacts 210A and 210B.

[0043] FIG. 2B illustrates a cross-sectional view of a non-planar semiconductor device having a gate contact via disposed over an active portion of a gate electrode, according to one embodiment of the present disclosure. Referring to FIG. 2B, an integrated circuit structure or device 200B, e.g., a non-planar version of device 200A of FIG. 2A, includes a non-planar diffusion or active region 204B (e.g., a fin structure) formed from a substrate 202 within an isolation region 206. A gate line 208B is disposed over the non-planar diffusion or active region 204B and over a portion of the isolation region 206. As shown, gate line 208B includes a gate electrode 250 and a gate dielectric layer 252, along with a dielectric cap layer 254. A gate contact via 216 is also seen from this perspective, along with an overlying metal interconnect 260, both of which are disposed in an interlayer dielectric stack or layer 270. Also from the perspective of FIG. 2B, the gate contact via 216 is disposed over the non-planar diffusion or active region 204B.

[0044] Thus, referring again to FIGS. 2A and 2B, in one embodiment, trench contact vias 212A, 212B and gate contact via 216 are formed in the same layer and are essentially coplanar. Compared to FIGS. 1A and 1B, contact to the gate lines would otherwise include an additional gate contact layer (e.g., which may extend perpendicular to the corresponding gate line). However, in the structures described in connection with FIGS. 2A and 2B, fabrication of structures 200A and 200B, respectively, allows for landing contacts directly from the metal interconnect layer on the active gate portion without shorting to adjacent source-drain regions. In one embodiment, such a configuration provides a significant reduction in area in the circuit layout by eliminating the need to extend the transistor gate separately to form a reliable contact. In one embodiment, as used throughout, reference to the active portion of the gate refers to the portion of the gate line or structure that is disposed (from a plan view perspective) above the active or diffusion region of the underlying substrate. In one embodiment, reference to a non-active portion of a gate refers to a portion of a gate line or structure that is disposed (from a plan view perspective) above an isolation region of the underlying substrate.

[0045] In one embodiment, integrated circuit structure or device 200 is a non-planar device, such as, but not limited to, a FinFET or a Tri-Gate device. In one such embodiment, the corresponding semiconductor channel region is comprised of or formed in a three-dimensional object. In one such embodiment, the gate electrode stacks of gate lines 208A and 208B surround at least a top surface of the three-dimensional object and a pair of its sidewalls. In another embodiment, at least the channel region is fabricated as a separate three-dimensional object, such as in a gate-all-around device (e.g., a nanowire, nanoribbon, or nanosheet device). In one such embodiment, the gate electrode stacks of gate lines 208A and 208B each completely surround the channel region.

[0046] Generally, one or more embodiments relate to approaches for landing gate contact vias directly on top of active transistor gates, and structures formed therefrom. Such an approach may eliminate the need for extending a separate gate line for contact purposes. Such an approach may also eliminate the need for a separate gate contact (GCN) layer to conduct signals from the gate line or structure. In one embodiment, this elimination can be achieved by recessing the gate metal in the gate structure, and in further embodiments, by introducing an additional dielectric material (e.g., a gate insulating layer (GILA)) into the process flow. This additional dielectric material is included as a gate dielectric cap layer to prevent shorting when creating vias to adjacent trench contacts.

[0047] According to one or more embodiments of the present disclosure, a wide and low dielectric constant liner of a gate etch stop cap for yield and performance is described.

[0048] For comparison, Figure 3A shows a cross-sectional view of an integrated circuit structure having a gate structure with a conventional gate insulating cap layer. Figure 3B shows a cross-sectional view of an integrated circuit structure having a gate structure with a widened, low-capacitance gate insulating cap layer according to one embodiment of the present disclosure. It should be understood that embodiments can be implemented using fin structures instead of nanowire stacks.

[0049] Referring to FIG. 3A, an integrated circuit structure 300 includes a substrate 302, which may include or be an upper sub-fin portion. A vertical stack of horizontal nanowires 304 is above the substrate 302. Epitaxial source or drain structures 306 are located between adjacent ones of the vertical stack of horizontal nanowires 304 and may rest on an insulating layer 307, such as a residual inner spacer material. Gate stacks 308 (e.g., a stack of high-k material and conductive electrode material including an upper tungsten portion) are located above and interposed between corresponding ones of the vertical stack of horizontal nanowires 304. Gate dielectric spacers 310 are located along the sides of the gate stacks 308 and interposed between the vertical stack of horizontal nanowires 304. An etch stop layer 314, such as a nitride etch stop layer (NESL), is located outside the gate dielectric spacers 310 and above the epitaxial source or drain structures 306. A silicide or silicide-forming material 315, such as a titanium layer, is within the etch stop layer 314 and over the epitaxial source or drain structures 306. A trench contact conductive fill material 316 is above the silicide or silicide-forming material 315. A gate insulation cap layer 318 is above its counterpart in the gate stack 308. An interlevel dielectric layer 319 may eventually cover the structure and may be the first layer in a back-end metallization structure.

[0050] Referring to FIG. 3B, an integrated circuit structure 320 includes a substrate 322, which may include or be an upper sub-fin portion. A vertical stack of horizontal nanowires 324 is disposed above the substrate 322. Epitaxial source or drain structures 326 are located between adjacent ones of the vertical stack of horizontal nanowires 324 and may rest on an insulating layer 327, such as a residual interior spacer material. Gate stacks 328 (e.g., a stack of high-k material and conductive electrode material including an upper tungsten portion) are located above and interposed between corresponding ones of the vertical stack of horizontal nanowires 324. Gate dielectric spacers 330 are located along the sides of the gate stacks 328 and interposed between the vertical stack of horizontal nanowires 324. An etch stop layer 334, such as a nitride etch stop layer (NESL), is located outside the gate dielectric spacers 330 and above the epitaxial source or drain structures 326. A silicide or silicide-forming material 335, such as a titanium layer, resides within the etch stop layer 334 and above the epitaxial source or drain structures 326. A trench contact conductive fill material 336 resides above the silicide or silicide-forming material 335. Gate insulating cap layers 338A / 338B reside above a corresponding one of the gate stacks 328. Each insulating cap layer 338A / 338B includes a low-k dielectric liner 338A and a separate, distinct dielectric fill material 338B, such as a silicon nitride fill material. Each insulating cap layer 338A / 338B may extend laterally beyond the corresponding gate structure 328 and vertically above the corresponding gate spacer 330, effectively reducing the height of the gate spacer 330. An interlevel dielectric layer 339 may ultimately cover the structure and may be the first layer of a back-end metallization structure.

[0051] 3C-3E illustrate cross-sectional views of various steps in a method for fabricating an integrated circuit structure having a gate structure with a widened, low-capacitance gate insulating cap layer according to one embodiment of the present disclosure. It should be understood that the described approach is also applicable, or alternatively applicable, to forming a conformal insulating cap layer for a conductive trench contact (also referred to as a conductive trench contact insulating cap layer). It should also be understood that embodiments can be implemented using fin structures instead of stacks of nanowires.

[0052] Referring to FIG. 3C , the initial structure 350 includes a substrate 352, which may include or be an upper sub-fin portion. A vertical stack of horizontal nanowires 354 is disposed above the substrate 352. Epitaxial source or drain structures 356 are located between adjacent ones of the vertical stack of horizontal nanowires 354 and may rest on an insulating layer 357, such as a residual inner spacer material. Gate stacks 358 (e.g., stacks of high-k material and conductive electrode material including upper tungsten portions) are located above and interposed between corresponding ones of the vertical stack of horizontal nanowires 354. Gate dielectric spacers 360 are located along the sides of the gate stacks 358 and interpose between the vertical stack of horizontal nanowires 354. At this stage, the tungsten recessing of the gate stacks 358 has already been performed, so that the top surface of the gate stacks 358 is below the top surface of the gate dielectric spacers 360. An etch stop layer 364, such as a nitride etch stop layer (NESL), is outside the gate dielectric spacer 360 and above the epitaxial source or drain structure 356. A placeholder dielectric layer 366 is within the etch stop layer 364 and overlies the epitaxial source or drain structure 356.

[0053] 3D, an isotropic etch is performed to remove exposed portions of gate dielectric spacers 360 to form recessed gate dielectric spacers 360 A. The etching process may also attack etch stop layer 364 and placeholder dielectric layer 366 to form a partially etched etch stop layer 364 A and recessed placeholder dielectric layer 366 A as shown.

[0054] Referring to Figure 3E, a structure 380 is formed by forming a gate insulation cap material in the recess of the structure of Figure 3D and then planarizing the structure. Structure 380 includes gate insulation cap structure 368 / 370 and placeholder dielectric 366B as the exposed overlying structure. In one embodiment, gate insulation cap structure 368 / 370 includes low-k dielectric liner 368 and a separate, distinct dielectric fill material 370. Further processing of structure 380 may include removal of placeholder dielectric 366B and replacement with a silicide or silicide-forming material, such as a titanium layer, and a trench contact conductive fill material.

[0055] As another exemplary fabrication scheme, FIGS. 4A-4D illustrate cross-sectional views illustrating various steps in a method for fabricating an integrated circuit structure having a gate contact structure disposed above an active portion of the gate, in accordance with one embodiment of the present disclosure.

[0056] Referring to FIG. 4A, an integrated circuit structure 400 is provided following trench contact (TCN) formation. It should be understood that the particular configuration of the structure 400 is used for illustrative purposes only, and that a variety of possible layouts can benefit from the embodiments of the present disclosure described herein. The integrated circuit structure 400 includes one or more gate stack structures, such as gate stack structures 408A-408E, disposed on a substrate 402. The gate stack structures can include a gate dielectric layer and a gate electrode. Trench contacts, e.g., contacts to diffusion regions of the substrate 402, e.g., trench contacts 410A-410C, are also included in the structure 400 and are spaced from the gate stack structures 408A-408E by dielectric spacers 420. As also shown in FIG. 4A, an insulating cap layer 422 (e.g., GILA) can be disposed on the gate stack structures 408A-408E. In one embodiment, the insulating cap layer 422 can be fabricated as a widened, low-capacitance gate insulating cap layer, as described above in connection with FIGS. 3B-3E. As also shown in FIG. 4A, contact obstruction regions or "contact plugs," such as region 423 fabricated from interlevel dielectric material, may be included in areas where contact formation is to be inhibited.

[0057] In one embodiment, providing structure 400 involves forming a contact pattern that is essentially perfectly aligned with an existing gate pattern, while eliminating the use of lithography steps with very tight alignment tolerances. In one such embodiment, this approach inherently enables the use of highly selective wet etches (e.g., relative to dry etches or plasma etches) to create the contact openings. In one embodiment, the contact pattern is formed by utilizing the existing gate pattern in combination with a contact plug lithography step. In one such embodiment, this approach enables the elimination of the need for an otherwise significant lithography step to create the contact pattern, as used in other approaches. In one embodiment, the trench contact grid is formed between poly (gate) lines rather than being separately patterned. For example, in one such embodiment, the trench contact grid is formed after gate grid patterning but before the gate grid cut.

[0058] Additionally, the gate stack structures 408A-408E can be fabricated using a replacement gate process. In such a scheme, dummy gate material, such as polysilicon or silicon nitride pillar material, can be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process rather than being carried over from previous processing. In one embodiment, the dummy gate is removed using a dry or wet etching process. In one embodiment, the dummy gate is comprised of polycrystalline or amorphous silicon and is removed using a dry etching process including SF. In another embodiment, the dummy gate is comprised of polycrystalline or amorphous silicon and is removed using a wet etching process including aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is comprised of silicon nitride and is removed using a wet etching process including aqueous phosphoric acid.

[0059] In one embodiment, one or more approaches described herein substantially contemplate a dummy and replacement gate process in combination with a dummy and replacement contact process to arrive at structure 400. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow for a high temperature anneal of at least a portion of the permanent gate stack. For example, in one particular such embodiment, the anneal of at least a portion of the permanent gate structure is performed at a temperature greater than about 600° C., e.g., after the gate dielectric layer is formed. The anneal is performed before the formation of the permanent contacts.

[0060] 4B, the trench contacts 410A-410C of the structure 400 are recessed into spacers 420 to provide recessed trench contacts 411A-411C having a height less than the top surfaces of the spacers 420 and the insulating cap layer 422. An insulating cap layer 424 (e.g., TILA) is then formed over the recessed trench contacts 411A-411C. According to one embodiment of the present disclosure, the insulating cap layer 424 over the recessed trench contacts 411A-411C is composed of a material having different etch characteristics than the insulating cap layer 422 over the gate stack structures 408A-408E. As seen in subsequent processing steps, such differences can be exploited to selectively etch one of 422 / 424 from the other of 422 / 424.

[0061] The trench contacts 410A-410C may be recessed by a process selective to the material of the spacers 420 and the insulating cap layer 422. For example, in one embodiment, the trench contacts 410A-410C are recessed by an etching process, such as a wet or dry etching process. The insulating cap layer 424 may be formed by a process suitable for providing a conformal sealing layer over the exposed portions of the trench contacts 410A-410C. For example, in one embodiment, the insulating cap layer 424 is formed as a conformal layer over the entire structure by a chemical vapor deposition (CVD) process. The conformal layer is then planarized, for example by chemical mechanical polishing (CMP), to provide the insulating cap layer 424 material only over the trench contacts 410A-410C and re-expose the spacers 420 and the insulating cap layer 422.

[0062] Regarding suitable material combinations for the insulating cap layer 422 / 424, in one embodiment, one of the pair 422 / 424 is composed of silicon oxide and the other is composed of silicon nitride. In another embodiment, one of the pair 422 / 424 is composed of silicon oxide and the other is composed of carbon-doped silicon nitride. In another embodiment, one of the pair 422 / 424 is composed of silicon oxide and the other is composed of silicon carbide. In another embodiment, one of the pair 422 / 424 is composed of silicon nitride and the other is composed of carbon-doped silicon nitride. In another embodiment, one of the pair 422 / 424 is composed of silicon nitride and the other is composed of silicon carbide. In another embodiment, one of the pair 422 / 424 is composed of carbon-doped silicon nitride and the other is composed of silicon carbide.

[0063] Referring to Figure 4C, a first dielectric etch stop layer 450 and a second dielectric etch stop layer 452 are formed above the structure of Figure 4B. An inter-layer dielectric (ILD) 430 and hard mask 432 stack is then formed and patterned to provide, for example, a patterned metal (0) trench 434 above the structure of Figure 4B.

[0064] The interlayer dielectric (ILD) 430 may be composed of a material suitable for electrically isolating metal features ultimately formed therein while maintaining a robust structure during front-end and back-end processing. Furthermore, in one embodiment, the composition of the ILD 430 is selected to match the via etch selectivity for trench contact dielectric cap layer patterning, as described in more detail below in connection with FIG. 4D . In one embodiment, the ILD 430 is composed of one or more layers of silicon oxide or one or more layers of carbon-doped oxide (CDO) material. However, in other embodiments, the ILD 430 has a bilayer composition, with the top layer being composed of a different material than the bottom layer of the ILD 430. The hard mask layer 432 may be composed of a material suitable for functioning as a subsequent sacrificial layer. For example, in one embodiment, the hard mask layer 432 is composed substantially of carbon (e.g., as a layer of a cross-linked organic polymer). In other embodiments, a silicon nitride or carbon-doped silicon nitride layer is used as the hard mask 432. The stack of inter-layer dielectric (ILD) 430 and hard mask 432 can be patterned by lithography and etching processes.

[0065] 4D, a via opening 436 (e.g., VCT) is formed in interlayer dielectric (ILD) 430, extending from metal (0) trench 434 to one or more of recessed trench contacts 411A-411C. Via opening 436 may be formed using a multiple etch process in which second dielectric etch stop layer 452 and first dielectric etch stop layer 450 are sequentially patterned to form second patterned dielectric etch stop layer 452A and first patterned dielectric etch stop layer 450A.

[0066] 4D , a via opening is formed to expose recessed trench contacts 411A and 411C. Formation of via opening 436 includes etching both inter-layer dielectric (ILD) 430 and respective portions of insulating cap layer 424. In one such embodiment, a portion of insulating cap layer 422 is exposed during patterning of inter-layer dielectric (ILD) 430 (e.g., a portion of insulating cap layer 422 above gate stack structures 408B and 408E is exposed). In that embodiment, insulating cap layer 424 is etched to form via opening 436 selectively to (i.e., without significantly etching or affecting) insulating cap layer 422.

[0067] In one embodiment, the via opening pattern is finally transferred to the insulating cap layer 424 (i.e., trench contact insulating cap layer) by an etching process without etching the insulating cap layer 422 (i.e., gate insulating cap layer). The insulating cap layer 424 (TILA) can be composed of any of, or a combination comprising, silicon oxide, silicon nitride, silicon carbide, carbon-doped silicon nitride, carbon-doped silicon oxide, amorphous silicon, and various metal oxides and silicates, including zirconium oxide, hafnium oxide, lanthanum oxide, or a combination thereof. The layer can be deposited by using any of techniques including CVD, ALD, PECVD, PVD, HDP-assisted CVD, and low-temperature CVD. The corresponding plasma dry etch is developed as a combination of chemical and physical sputtering principles. Simultaneous polymer deposition can be used to control the material removal rate, etch profile, and film selectivity. The dry etch is typically performed using a gas mixture containing NF, CHF, C4F, HBr, and O2 at a pressure ranging from 30 to 100 mTorr and a plasma bias of 50 to 1000 Watts. The dry etch can be designed to achieve significant etch selectivity between the insulating cap layer 424 (TILA) and 422 (GILA) layers to minimize loss of the insulating cap layer 422 (GILA) during the dry etch of the insulating cap layer 424 (TILA) to form contacts to the source / drain regions of the transistor.

[0068] Referring again to FIG. 4D , it should be appreciated that a similar approach can be implemented to fabricate a via opening pattern that is ultimately transferred to insulating cap layer 424 (i.e., trench contact insulating cap layer) by an etching process without etching insulating cap layer 422 (i.e., gate insulating cap layer).

[0069] To further illustrate the concept of contact over active gate (COAG) technology, FIG. 5 shows a plan view and corresponding cross-sectional view of an integrated circuit structure with trench contacts including an overlying insulating cap layer, according to one embodiment of the present disclosure.

[0070] Referring to FIG. 5, an integrated circuit structure 500 includes a gate line 504 above a semiconductor substrate or fin 502, such as a silicon fin. The gate line 504 includes a gate stack 505 (e.g., including a gate dielectric layer or stack and a gate electrode over the gate dielectric layer or stack) and a gate insulation cap layer 506 over the gate stack 505. In one embodiment, the gate insulation cap layer 506 can be fabricated to be a widened, low capacitance gate insulation cap layer, as described above in connection with FIGS. 3B-3E. Dielectric spacers 508 are along the sidewalls of the gate stack 505 and, in one embodiment, along the sidewalls of the gate insulation cap layer 506, as shown.

[0071] The trench contacts 510 are adjacent to the sidewalls of the gate lines 504, with dielectric spacers 508 between the gate lines 504 and the trench contacts 510. Each of the trench contacts 510 includes a conductive contact structure 511 and a trench contact insulating cap layer 512 over the conductive contact structure 511.

[0072] 5, gate contact vias 514 are formed in openings in gate insulation cap layer 506 and make electrical contact with gate stacks 505. In one embodiment, gate contact vias 514 electrically contact gate stacks 505 above semiconductor substrate or fin 502 at lateral locations between trench contacts 510, as shown. In one such embodiment, trench contact insulation cap layer 512 on conductive contact structures 511 prevents gate-to-source or gate-to-drain shorts caused by gate contact vias 514.

[0073] 5, trench contact vias 516 are formed in openings in trench contact insulation cap layer 512 to electrically contact respective conductive contact structures 511. In one embodiment, trench contact vias 516 are in electrical contact with respective conductive contact structures 511 above semiconductor substrate or fin 502 and laterally adjacent gate stacks 505 of gate lines 504, as shown. In one such embodiment, gate insulation cap layer 506 on gate stacks 505 prevents source-to-gate or drain-to-gate shorts caused by trench contact vias 516.

[0074] It should be understood that different structural relationships between the insulating gate cap layer and the insulating trench contact cap layer can be fabricated. By way of example, Figures 6A-6F show cross-sectional views of various integrated circuit structures, each having a trench contact including an overlying insulating cap layer and a gate stack including an overlying insulating cap layer, in accordance with an embodiment of the present disclosure.

[0075] Referring to Figures 6A, 6B, and 6C, integrated circuit structures 600A, 600B, and 600C each include a fin 602, such as a silicon fin. While illustrated as a cross-section, it should be understood that the fin 602 has a top 602A and sidewalls (into and out of the page of the perspective shown). A first gate dielectric layer 604 and a second gate dielectric layer 606 are above the top 602A of the fin 602 and laterally adjacent the sidewalls of the fin 602. A first gate electrode 608 and a second gate electrode 610 are above the first gate dielectric layer 604 and the second gate dielectric layer 606, respectively, and above the top 602A of the fin 602 and laterally adjacent the sidewalls of the fin 602. The first gate electrode 608 and the second gate electrode 610 each include a conformal conductive layer 609A, such as a work function setting layer, and a conductive fill material 609B overlying the conformal conductive layer 609A. Both the first gate electrode 608 and the second gate electrode 610 have a first side 612 and a second side 614 opposite the first side 612. Both the first gate electrode 608 and the second gate electrode 610 also have an insulating cap 616 with a top surface 618. In one embodiment, the insulating cap 616 can be fabricated as a widened, low capacitance gate insulating cap layer, as described above in connection with Figures 3B-3E.

[0076] A first dielectric spacer 620 is adjacent to a first side 612 of the first gate electrode 608. A second dielectric spacer 622 is adjacent to a second side 614 of the second gate electrode 610. A semiconductor source or drain region 624 is adjacent to the first dielectric spacer 620 and the second dielectric spacer 622. A trench contact structure 626 is above the semiconductor source or drain region 624 adjacent to the first dielectric spacer 620 and the second dielectric spacer 622.

[0077] The trench contact structure 626 includes an insulating cap 628 over the conductive structure 630. The insulating cap 628 of the trench contact structure 626 has a top surface 629 that is substantially coplanar with the top surfaces 618 of the insulating caps 616 of the first gate electrode 608 and the second gate electrode 610. In one embodiment, the insulating cap 628 of the trench contact structure 626 extends laterally into the recesses 632 in the first dielectric spacer 620 and the second dielectric spacer 622. In one such embodiment, the insulating cap 628 of the trench contact structure 626 covers the conductive structure 630 of the trench contact structure 626. However, in other embodiments, the insulating cap 628 of the trench contact structure 626 does not extend laterally into the recesses 632 in the first dielectric spacer 620 and the second dielectric spacer 622 and therefore does not cover the conductive structure 630 of the trench contact structure 626.

[0078] In one embodiment, the insulating cap 628 of the trench contact structure 626 has a different composition than the insulating cap 616 of the first gate electrode 608 and the second gate electrode 610. In one such embodiment, the insulating cap 628 of the trench contact structure 626 comprises a carbide material, such as a silicon carbide material. The insulating cap 616 of the first gate electrode 608 and the second gate electrode 610 comprises a nitride material, such as a silicon nitride material.

[0079] In one embodiment, as shown in Figure 6A, the insulating cap 616 of both the first gate electrode 608 and the second gate electrode 610 has a bottom surface 617A that is below a bottom surface 628A of the insulating cap 628 of the trench contact structure 626. In another embodiment, as shown in Figure 6B, the insulating cap 616 of both the first gate electrode 608 and the second gate electrode 610 has a bottom surface 617B that is substantially coplanar with a bottom surface 628B of the insulating cap 628 of the trench contact structure 626. In another embodiment, as shown in Figure 6C, the insulating cap 616 of both the first gate electrode 608 and the second gate electrode 610 has a bottom surface 617C that is above a bottom surface 628C of the insulating cap 628 of the trench contact structure 626.

[0080] 6D , in one embodiment, a conductive via 660 overlies and is electrically connected to a portion of the first gate electrode 608 above the top 602A of the fin 602. The conductive via 660 is within the openings in the first dielectric etch stop layer 650 and the second dielectric etch stop layer 652, and is also within the opening 627 in the insulating cap 616 of the first gate electrode 608. In one such embodiment, the conductive via 660 overlies a portion of the insulating cap 628 of the trench contact structure 626, but is not electrically connected to the conductive structure 630 of the trench contact structure 626. In one particular such embodiment, the conductive via 660 is within the eroded portion 654 of the insulating cap 628 of the trench contact structure 626.

[0081] 6E , in one embodiment, a conductive via 680 overlies and is electrically connected to a portion of the trench contact structure 626. The conductive via 680 is within the openings in the first and second dielectric etch stop layers 650 and 652, and is also within the opening 662 in the insulating cap 628 of the trench contact structure 626. In one such embodiment, the conductive via 680 overlies a portion of the insulating cap 616 of the first and second gate electrodes 608 and 610, but is not electrically connected to the first and second gate electrodes 608 and 610. In one particular such embodiment, the conductive via 680 is within the eroded portion 664 of the insulating cap 616 of the first and second gate electrodes 608 and 610.

[0082] Referring again to Figure 6E, in one embodiment, conductive via 680 is a second conductive via of the same structure as conductive via 660 of Figure 6D. In one such embodiment, such second conductive via 680 is separate from conductive via 660. In another such embodiment, such second conductive via 680 is integrated with conductive via 660 to form electrically shorting contact 670, as illustrated in Figure 6F.

[0083] The approaches and structures described herein may enable the formation of other structures or devices that are impossible or difficult to manufacture using other methods. In a first example, FIG. 7A shows a plan view of another semiconductor device having a gate contact via disposed above the active portion of the gate in accordance with another embodiment of the present disclosure. Referring to FIG. 7A, an integrated circuit structure or device 700 includes multiple gate structures 708A-708C interdigitated with multiple trench contacts 710A and 710B (these features are disposed above the active region of the substrate, although not shown). A gate contact via 780 is formed on the active portion of gate structure 708B. The gate contact via 780 is further disposed on the active portion of gate structure 708C, coupling gate structures 708B and 708C. It should be understood that the intervening trench contact 710B may be isolated from the contact 780 by the use of a trench contact isolation cap layer (e.g., TILA). 7A may provide an easier approach to strapping adjacent gate lines in a layout, eliminating the need to route the straps through an upper metallization layer, thus allowing for a smaller cell area, a less complex wiring scheme, or both. In one embodiment, each gate structure 708A-708C may include a widened, low capacitance gate insulation cap layer, as described above in connection with FIGS. 3B-3E.

[0084] In a second example, FIG. 7B illustrates a plan view of another semiconductor device having a trench contact via coupling a pair of trench contacts in accordance with another embodiment of the present disclosure. Referring to FIG. 7B, an integrated circuit structure or device 750 includes multiple gate structures 758A-758C interdigitated with multiple trench contacts 760A and 760B (these features are disposed above the active region of the substrate, although not shown). A trench contact via 790 is formed over trench contact 760A. Trench contact via 790 is further disposed over trench contact 760B, coupling trench contacts 760A and 760B. It should be understood that intervening gate structure 758B can be isolated from trench contact via 790 using a gate isolation cap layer (e.g., by a GILA process), which can be fabricated as a widened, low-capacitance gate insulation cap layer, as described above in connection with FIGS. 3B-3E. The contact configuration of FIG. 7B may provide an easier approach to strapping adjacent trench contacts in a layout, eliminating the need to route the straps through upper layers of metallization, thus allowing for smaller cell areas, or less complex wiring schemes, or both.

[0085] As discussed above in connection with Figures 3B-3E, as an example of a possible fill for a widened, low-capacitance gate insulating cap layer, a portion of the insulating cap layer for the gate electrode can be fabricated using multiple deposition steps. For example, Figures 8A-8E show cross-sectional views illustrating various steps in a method for fabricating an integrated circuit structure with a gate stack having an upper insulating cap layer with different architectures.

[0086] Referring to FIG. 8A , the initial structure 800 includes a gate stack 804 above a substrate or fin 802. The gate stack 804 includes a gate dielectric layer 806, a conformal conductive layer 808, and a conductive fill material 810. In one embodiment, the gate dielectric layer 806 is a high-k gate dielectric layer formed using an atomic layer deposition (ALD) process, and the conformal conductive layer is a work function layer formed using an ALD process. In one such embodiment, a thermal or chemical oxidation layer 812, such as a thermal or chemical silicon dioxide or silicon oxide layer, exists between the substrate or fin 802 and the gate dielectric layer 806. Dielectric spacers 814, such as silicon nitride spacers, are adjacent to the sidewalls of the gate stack 804. The dielectric gate stack 804 and the dielectric spacers 814 are contained in an interlayer dielectric (ILD) layer 816. In one embodiment, the gate stack 804 is formed using a replacement gate and replacement gate dielectric processing scheme. A mask 818 is patterned above the gate stack 804 and ILD layer 816 to provide an opening 820 exposing the gate stack 804 .

[0087] 8B, using one or more selective etching processes, gate stack 804, including gate dielectric layer 806, conformal conductive layer 808, and conductive fill material 810, is recessed relative to dielectric spacers 814 and layer 816. Mask 818 is then removed. The recessing provides a cavity 822 above recessed gate stack 824.

[0088] In another embodiment, not shown, the conformal conductive layer 808 and conductive fill material 810 are recessed relative to the dielectric spacers 814 and layer 816, but the gate dielectric layer 806 is not recessed or is only minimally recessed. It should be understood that in other embodiments, a maskless approach based on high etch selectivity is used for recessing.

[0089] Referring to FIG. 8C, a first deposition process in a multi-layer deposition process for fabricating a gate insulation cap layer is performed. The first deposition process is used to form a first insulation layer 826 conformal to the structure of FIG. 8B. In one embodiment, the first insulation layer 826 includes silicon and nitrogen. For example, the first insulation layer 826 is a silicon nitride (SiN) layer, a silicon-rich silicon nitride layer, a silicon-poor silicon nitride layer, or a carbon-doped silicon nitride layer. In one embodiment, as shown, the first insulation layer 826 only partially fills the cavity 822 above the recessed gate stack 824.

[0090] 8D, the first insulating layer 826 undergoes an etch-back process, such as an anisotropic etching process, to provide a first portion of an insulating cap layer 828. The first portion of the insulating cap layer 828 only partially fills the cavity 822 above the recessed gate stack 824.

[0091] Referring to Figure 8E, additional alternating deposition and etch-back processes are performed until cavity 822 is filled with insulating gate cap structure 830 above recessed gate stack 824. Seams 832 may be evident in cross-sectional analysis and may indicate the number of alternating deposition and etch-back processes used to isolate insulating gate cap structure 830. In the example shown in Figure 8E, the presence of three sets of seams 832A, 832B, and 832C indicates four alternating deposition and etch-back processes used to isolate insulating gate cap structure 830. In one embodiment, materials 830A, 830B, 830C, and 830D of insulating gate cap structure 830 separated by seams 832 all have the same or substantially the same composition.

[0092] As described throughout this application, the substrate may be composed of a semiconductor material that can withstand the fabrication process and through which charge can travel. In one embodiment, the substrate described herein is a bulk substrate composed of a crystalline silicon, silicon / germanium, or germanium layer doped with charge carriers, such as, but not limited to, phosphorus, arsenic, boron, or a combination thereof, to form an active region. In one embodiment, the concentration of silicon atoms in such a bulk substrate is greater than 97%. In another embodiment, the bulk substrate is composed of an epitaxial layer grown on a separate crystalline substrate, for example, a silicon epitaxial layer grown on a boron-doped bulk silicon single crystal substrate. The bulk substrate may alternatively be composed of a III-V material. In one embodiment, the bulk substrate is composed of a III-V material, such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimony, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one embodiment, the bulk substrate is composed of a III-V material and the charge carrier dopant impurity atoms are such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0093] As described throughout this application, an isolation region, such as a shallow trench isolation region or a sub-fin isolation region, may ultimately be composed of a suitable material that electrically isolates or contributes to the isolation of portions of a permanent gate structure from the underlying bulk substrate, or that isolates an active region formed in the underlying bulk substrate, such as isolating the active region of a fin. For example, in one embodiment, the isolation region is composed of one or more layers of a dielectric material, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, carbon-doped silicon nitride, or a combination thereof.

[0094] As described throughout this application, a gate line or gate structure can be composed of a gate electrode stack including a gate dielectric layer and a gate electrode layer. In one embodiment, the gate electrode of the gate electrode stack is composed of a metal gate, and the gate dielectric layer is composed of a high-k material. For example, in one embodiment, the gate dielectric layer is composed of a material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, tantalum scandium lead oxide, lead zinc niobate, or a combination thereof. Furthermore, a portion of the gate dielectric layer can include a layer of native oxide formed from the top few layers of a semiconductor substrate. In one embodiment, the gate dielectric layer is composed of a top high-k portion and a bottom portion composed of an oxide of the semiconductor material. In one embodiment, the gate dielectric layer is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In some implementations, a portion of the gate dielectric is a "U" shaped structure that includes a bottom that is substantially parallel to the surface of the substrate and two sidewalls that are substantially perpendicular to the top surface of the substrate.

[0095] In one embodiment, the gate electrode is composed of a metal layer, such as, but not limited to, a metal nitride, a metal carbide, a metal silicide, a metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or a conductive metal oxide. In a particular embodiment, the gate electrode is composed of a non-work function setting fill material formed on a metal work function setting layer. The gate electrode layer may be composed of a P-type work function metal or an N-type work function metal, depending on whether the transistor is a PMOS transistor or an NMOS transistor. In some implementations, the gate electrode layer may be composed of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a conductive fill layer. In a PMOS transistor, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, such as ruthenium oxide. The P-type metal layer enables the formation of a PMOS gate electrode having a work function between about 4.9 eV and about 5.2 eV. In an NMOS transistor, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. The N-type metal layer enables the formation of an NMOS gate electrode having a work function between about 3.9 eV and about 4.2 eV. In some implementations, the gate electrode can be comprised of a "U"-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers forming the gate electrode can be simply a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the present disclosure, the gate electrode may be comprised of a combination of U-shaped and planar, non-U-shaped structures. For example, the gate electrode may be comprised of one or more U-shaped metal layers formed on one or more planar, non-U-shaped layers.

[0096] As described throughout this application, spacers associated with gate lines or gate electrode stacks may be composed of any suitable material that ultimately electrically isolates or contributes to the isolation of a permanent gate structure from adjacent conductive contacts, such as self-aligned contacts. For example, in one embodiment, the spacers are composed of a dielectric material, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0097] In one embodiment, as used throughout this specification, an interlayer dielectric (ILD) material consists of or includes a layer of dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, silicon oxide (e.g., silicon dioxide (SiO2)), or low-k materials (dielectric constant less than 4.0, e.g., less than SiO2), such as doped silicon oxide, fluorinated silicon oxide, carbon-doped silicon oxide, various low-k dielectric materials known in the art, and combinations thereof. Interlayer dielectric materials can be formed by techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or other deposition methods.

[0098] In one embodiment, as used similarly throughout this specification, metal line or interconnect line material (and via material) is composed of one or more metals or other conductive structures. A common example is the use of copper lines and structures, which may or may not include a barrier layer between the copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect line may include a barrier layer (e.g., a layer including one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, etc. Thus, the interconnect line may be a single layer of material or may be formed from multiple layers, including conductive liner layers and fill layers. Any suitable deposition process, such as electroplating, chemical vapor deposition, or physical vapor deposition, may be used to form the interconnect line. In one embodiment, the interconnect lines are composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof, and are sometimes referred to in the art as wiring, wires, lines, metals, or simply interconnects.

[0099] In one embodiment, the hard mask material, as used interchangeably throughout this specification, is composed of a dielectric material that is different from the interlayer dielectric material. In one embodiment, different hard mask materials may be used in different regions to provide different growth or etch selectivities to each other and to the underlying dielectric and metal layers. In some embodiments, the hard mask layer includes a layer of silicon nitride (e.g., silicon nitride) or a layer of silicon oxide, or both, or a combination thereof. Other suitable materials may include carbon-based materials. In another embodiment, the hard mask material includes a metal species. For example, the hard mask or other overlying material may include a layer of titanium nitride or another metal (e.g., titanium nitride). Potentially, other materials, such as smaller amounts of oxygen, may be included in one or more of these layers. Alternatively, other hard mask layers known in the art may be used depending on the particular implementation. The hard mask layer may be formed by CVD, PVD, or other deposition methods.

[0100] In one embodiment, as used interchangeably throughout this specification, the lithography process is performed using 193 nm immersion lithography (i193), extreme ultraviolet (EUV) lithography, or electron beam direct write (EBDW) lithography, or the like. Positive-tone or negative-tone resists may be used. In one embodiment, the lithography mask is a three-layer mask consisting of a topography masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In one particular such embodiment, the topography masking portion is a carbon hard mask (CHM) layer, and the anti-reflective coating layer is a silicon ARC layer.

[0101] In one embodiment, the approach described herein may involve the formation of a contact pattern that is highly aligned to an existing gate pattern while eliminating the use of lithography steps with very tight alignment tolerances. In one such embodiment, this approach inherently enables the use of highly selective wet etches (e.g., relative to dry or plasma etches) to create the contact openings. In one embodiment, the contact pattern is formed by utilizing the existing gate pattern in combination with a contact plug lithography step. In one such embodiment, this approach allows for the elimination of the need for an otherwise significant lithography step to create the contact pattern, as used in other approaches. In one embodiment, the trench contact grid is formed between poly (gate) lines rather than being separately patterned. For example, in one such embodiment, the trench contact grid is formed after gate grid patterning but before the gate grid cut.

[0102] Additionally, the gate stack structure can be fabricated using a replacement gate process. In such a scheme, dummy gate materials, such as polysilicon or silicon nitride pillar materials, can be removed and replaced with permanent gate electrode materials. In one such embodiment, a permanent gate dielectric layer is also formed in this process rather than being carried over from previous processing. In one embodiment, the dummy gates are removed using a dry or wet etching process. In one embodiment, the dummy gates are comprised of polycrystalline or amorphous silicon and are removed using a dry etching process including the use of SF. In another embodiment, the dummy gates are comprised of polycrystalline or amorphous silicon and are removed using a wet etching process including the use of aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gates are comprised of silicon nitride and are removed using a wet etching process including aqueous phosphoric acid.

[0103] In one embodiment, one or more approaches described herein essentially contemplate a dummy and replacement gate process in combination with a dummy and replacement contact process to arrive at a structure. In one such embodiment, the replacement contact process is performed after the replacement gate process to enable high-temperature annealing of at least a portion of the permanent gate stack. For example, in one such embodiment, the annealing of at least a portion of the permanent gate structure is performed at a temperature greater than about 600° C., e.g., after the gate dielectric layer is formed. The annealing is performed before the formation of the permanent contact.

[0104] In some embodiments, an integrated circuit structure or device configuration places a gate contact above a portion of a gate line or gate stack above an isolation region. However, such a configuration may be considered an inefficient use of layout space. In another embodiment, a semiconductor device has a contact structure that contacts a portion of a gate electrode formed above an active region. Generally, prior to (e.g., in addition to) forming a gate contact structure (e.g., via) above the active portion of the gate and in the same layer as the trench contact via, one or more embodiments of the present disclosure first include using a gate-aligned trench contact process. Such a process may be implemented to form trench contact structures for the fabrication of integrated circuit structures, e.g., integrated circuits. In one embodiment, a trench contact pattern is formed to align with an existing gate pattern. In contrast, other approaches typically involve additional lithography processes, involving critical alignment of the lithographic contact pattern to the existing gate pattern, combined with selective contact etching. For example, another process may include patterning a poly(gate) grid with separate patterning of contact features.

[0105] It should be understood that pitch division processes and patterning schemes may be implemented to enable or be included as part of the embodiments described herein. Pitch division patterning typically refers to pitch division by two, pitch division by four, etc. Pitch division schemes may be applicable to FEOL processing, BEOL processing, or both FEOL (device) and BEOL (metallization) processing. According to one or more embodiments described herein, optical lithography is first implemented to print unidirectional (e.g., either strictly unidirectional or predominantly unidirectional) lines at a predefined pitch. In this case, pitch division processes are implemented as a technique to increase line density.

[0106] In one embodiment, the term "grid structure" for a fin, gate line, metal line, ILD line, or hardmask line is used herein to refer to a dense pitch grating structure. In one such embodiment, the dense pitch is not directly achievable through selective lithography. For example, a pattern based on selective lithography may be initially formed, but the pitch may be divided by two by using spacer mask patterning, as known in the art. Furthermore, the original pitch may be divided by four by a second spacer mask patterning. Thus, the grid-like patterns described herein may have metal lines, ILD lines, or hardmask lines with substantially consistent widths spaced at a substantially consistent pitch. For example, in some embodiments, the pitch may vary by less than 10 percent and the width may vary by less than 10 percent, and in some embodiments, the pitch may vary by less than 5 percent and the width may vary by less than 5 percent. The pattern may be fabricated by pitch-dividing, pitch-dividing, or pitch-dividing, or by other pitch-dividing approaches. In one embodiment, the grating is not necessarily a single pitch.

[0107] In one embodiment, the blanket film is patterned using lithography and etch processes that may include, for example, spacer-based double-patterning (SBDP) or pitch division by 2, or spacer-based quadruple-patterning (SBQP) or pitch division by 4. It should be understood that other pitch division approaches may also be implemented. In any event, in one embodiment, a grid layout may be fabricated using a selected lithography approach, such as 193 nm immersion lithography (193i). The pitch division may be implemented to increase the linear density of the grid layout by a factor of n. A grid layout formed using 193i lithography and an n-fold pitch division may be expressed as 193i+P / n pitch division. In one such embodiment, 193 nm immersion scaling can be extended to many generations with cost-effective pitch division.

[0108] It should also be understood that not all aspects of the above process need be practiced to fall within the spirit and scope of embodiments of the present disclosure. For example, in one embodiment, a dummy gate need not be formed at all before fabricating a gate contact over the active portion of the gate stack. The gate stack may in fact be a permanent gate stack as initially formed. The processes described herein may also be used to fabricate one or more semiconductor devices. The semiconductor device may be a transistor or similar device. For example, in one embodiment, the semiconductor device is a metal-oxide-semiconductor (MOS) transistor for logic or memory, or a bipolar transistor. Also, in one embodiment, the semiconductor device has a three-dimensional architecture, e.g., a gate-all-around (GAA) device such as a tri-gate device, an independently accessed double-gate device, a FinFET, a nanowire-based device, a nanoribbon-based device, or a nanosheet-based device. One or more embodiments may be particularly useful for fabricating semiconductor devices at the ten nanometer (10 nm) technology node and sub-ten nanometer (10 nm) technology nodes.

[0109] Additional or intermediate steps for the fabrication of FEOL layers or structures may include standard microelectronic fabrication processes such as lithography, etching, deposition, planarization (such as chemical mechanical polishing (CMP)), diffusion, metrology, use of sacrificial layers, use of etch stop layers, use of planarization stop layers, or any other measures associated with microelectronic component fabrication. It should also be understood that the process steps described in the preceding process flows may be practiced in an alternate order, that not all steps need to be performed, and / or that additional process steps may be performed.

[0110] The embodiments disclosed herein can be used to manufacture a wide variety of different types of integrated circuits or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, semiconductor memories can be manufactured. Furthermore, integrated circuits or other microelectronic devices can be used in a wide variety of electronic devices known in the art, such as computer systems (e.g., desktops, laptops, servers), cellular telephones, personal electronic devices, etc. The integrated circuits can be coupled with buses and other components of the system. For example, a processor can be coupled with memory, chipsets, etc. by one or more buses. Each of the processors, memories, and chipsets can potentially be manufactured using the approaches disclosed herein.

[0111] 9 illustrates a computing device 900 according to one implementation of the present disclosure. The computing device 900 houses a board 902. The board 902 may include numerous components, including, but not limited to, a processor 904 and at least one communications chip 906. The processor 904 is physically and electrically coupled to the board 902. In some implementations, the at least one communications chip 906 is also physically and electrically coupled to the board 902. In further implementations, the communications chip 906 is part of the processor 904.

[0112] Depending on its application, computing device 900 may include other components that may or may not be physically and electrically coupled to board 902. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touchscreen displays, touchscreen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (e.g., hard disk drives, compact discs (CDs), digital versatile discs (DVDs), etc.).

[0113] The communications chip 906 enables wireless communication for the transfer of data to and from the computing device 900. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that may communicate data through the use of modulated electromagnetic radiation over a non-solid medium. The term does not imply that the associated devices do not include any wires, although in some embodiments they may not. The communications chip 906 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, variants thereof, and any other wireless protocols designated as 3G, 4G, 5G, and later generations. The computing device 900 may include multiple communication chips 906. For example, a first communication chip 906 may be dedicated to short-range wireless communications such as Wi-Fi® and Bluetooth®, and a second communication chip 906 may be dedicated to long-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX®, LTE, and Ev-DO.

[0114] The processor 904 of the computing device 900 includes an integrated circuit die packaged within the processor 904. In some implementations of the embodiments of the present disclosure, the processor's integrated circuit die includes one or more structures, such as integrated circuit structures, constructed according to implementations of the present disclosure. The term "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that can be stored in registers and / or memory.

[0115] The communications chip 906 also includes an integrated circuit die packaged within the communications chip 906. According to another implementation of the present disclosure, the integrated circuit die of the communications chip is constructed according to an implementation of the present disclosure.

[0116] In further implementations, other components housed within computing device 900 may include an integrated circuit die constructed in accordance with implementations of the presently disclosed embodiments.

[0117] In various embodiments, computing device 900 may be a laptop, netbook, notebook, ultrabook, smartphone, tablet, personal digital assistant (PDA), ultra mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In further implementations, computing device 900 may be any other electronic device that processes data.

[0118] FIG. 10 illustrates an interposer 1000 that includes one or more embodiments of the present disclosure. The interposer 1000 is an intervening substrate used to bridge a first substrate 1002 and a second substrate 1004. The first substrate 1002 may be, for example, an integrated circuit die. The second substrate 1004 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of the interposer 1000 is to spread connections to a wider pitch or to reroute connections to different connections. For example, the interposer 1000 may bond an integrated circuit die to a ball grid array (BGA) 1006, which may then be bonded to the second substrate 1004. In some embodiments, the first substrate and the second substrate 1002 / 1004 are attached to opposite sides of the interposer 1000. In other embodiments, the first substrate and the second substrate 1002 / 1004 are attached to the same side of the interposer 1000. And in further embodiments, three or more substrates are interconnected through interposer 1000.

[0119] Interposer 1000 may be formed of a polymeric material such as epoxy, fiberglass reinforced epoxy, ceramic material, or polyimide. In further implementations, interposer 1000 may be formed of alternating rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials.

[0120] The interposer 1000 may include metal wiring 1008 and vias 1010, including, but not limited to, through-silicon vias (TSVs) 1012. The interposer 1000 may further include embedded devices 1014, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices, may also be formed on the interposer 1000. According to embodiments of the present disclosure, the apparatus or processes disclosed herein may be used in the manufacture of the interposer 1000 or components included in the interposer 1000.

[0121] FIG. 11 is an isometric view of a mobile computing platform 1100 employing integrated circuits (ICs) fabricated according to one or more processes described herein or including one or more features described herein, in accordance with one embodiment of the present disclosure.

[0122] The mobile computing platform 1100 may be any portable device configured for electronic data display, electronic data processing, or wireless electronic data transmission. For example, the mobile computing platform 1100 may be a tablet, smartphone, laptop computer, or the like, and may include a display screen 1105, which in an exemplary embodiment is a touchscreen (capacitive, inductive, resistive, etc.), a chip-level (SoC) or package-level integrated system 1110, and a battery 1113. As shown, the greater the level of integration in the integrated system 1110 enabled by higher transistor packing density, the larger the portion of the mobile computing platform 1100 that can be occupied by non-volatile storage such as the battery 1113 or a solid-state drive, or the larger the transistor gate count for improved platform functionality. Similarly, the higher the carrier mobility of each transistor in the system 1110, the higher the functionality. Thus, the techniques described herein may enable improved performance and form factor in the mobile computing platform 1100.

[0123] Integrated system 1110 is further shown in exploded view 1120. In an exemplary embodiment, packaged device 1177 includes at least one memory chip (e.g., RAM) or at least one processor chip (e.g., a multi-core microprocessor and / or a graphics processor) manufactured by one or more processes described herein or including one or more features described herein. Packaged device 1177 is further coupled to board 1160 along with one or more of: a power management integrated circuit (PMIC) 1115; an RF (radio frequency) integrated circuit (RFIC) 1125 including a wideband RF (radio frequency) transmitter and / or receiver (e.g., including a digital baseband and analog front-end module further including a power amplifier on the transmit path and a low-noise amplifier on the receive path); and their controllers 1111. Functionally, PMIC 1115 performs battery power control, DC-DC conversion, etc., and thus has an input coupled to battery 1113 and an output providing a current supply to all other functional modules. As further shown, in the exemplary embodiment, RFIC 1125 has an output coupled to an antenna provided to implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, their derivatives, and any other wireless protocols designated as 3G, 4G, and 5G and beyond. In alternative implementations, each of these board-level modules may be integrated on separate ICs coupled to the package substrate of packaged device 1177 or within a single IC (SoC) coupled to the package substrate of packaged device 1177.

[0124] In another aspect, semiconductor packages are used to protect integrated circuit (IC) chips or dies and to provide the dies with an electrical interface to external circuitry. As the demand for smaller electronic devices increases, semiconductor packages must be designed to be even smaller and support greater circuit density. Furthermore, the demand for higher performance devices results in a need for improved semiconductor packages that enable a thin packaging profile and low overall warpage that is compatible with subsequent assembly processes.

[0125] In one embodiment, wire bonding to a ceramic or organic package substrate is used. In another embodiment, a C4 process is used to mount the die to the ceramic or organic package substrate. In particular, C4 solder ball connections can be implemented to provide flip-chip interconnections between the semiconductor device and the substrate. Flip-chip or controlled collapse chip connection (C4) is a type of mount used for semiconductor devices, such as integrated circuit (IC) chips, MEMS, or components, that utilizes solder bumps instead of wire bonds. Solder bumps are deposited on C4 pads located on the top surface of the substrate package. To mount the semiconductor device to the substrate, the semiconductor device is flipped over onto the mounting area, active side down. Solder bumps are used to directly connect the semiconductor device to the substrate.

[0126] FIG. 12 illustrates a cross-sectional view of a flip-chip mounted die according to one embodiment of the present disclosure.

[0127] 12 , device 1200 includes a die 1202, such as an integrated circuit (IC), manufactured according to one or more processes described herein or including one or more features described herein, in accordance with an embodiment of the present disclosure. Die 1202 includes metallized pads 1204 thereon. Package substrate 1206, such as a ceramic or organic substrate, includes connections 1208 thereon. Die 1202 and package substrate 1206 are electrically connected by solder balls 1210 bonded to metallized pads 1204 and connections 1208. Underfill material 1212 surrounds solder balls 1210.

[0128] Flip-chip processing can be similar to traditional IC manufacturing, with a few additional steps. Late in the manufacturing process, the mounting pads are metallized to make them more receptive to solder. This typically involves multiple processes. Small dots of solder are then deposited on each of the metallized pads. The chip is then cut from the wafer as usual. To attach the flip-chip to a circuit, the chip is inverted and the solder dots are placed face-down in contact with connectors on the underlying electronic or circuit board. The solder is then remelted, typically using an ultrasonic or alternatively a reflow soldering process, to create an electrical connection. This also leaves a small space between the chip's circuitry and the underlying mount. In most cases, an electrically insulating adhesive is then "underfilled" to provide a stronger mechanical connection and a thermal bridge, ensuring that the solder joints are not stressed due to differential heating of the chip and the rest of the system.

[0129] In other embodiments, newer packaging and die-to-die interconnect approaches, such as through silicon vias (TSVs) and silicon interposers, are implemented to produce high performance multi-chip modules (MCMs) and systems-in-packages (SiPs) incorporating integrated circuits (ICs) manufactured according to one or more processes described herein or including one or more features described herein, in accordance with an embodiment of the present disclosure.

[0130] Accordingly, embodiments of the present disclosure include a contact over active gate (COAG) structure with a widened, low capacitance gate insulation cap layer, and a method for fabricating a contact over active gate (COAG) structure using a widened, low capacitance gate insulation cap layer.

[0131] The above description of illustrated implementations of embodiments of the present disclosure, including those described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. Specific implementations and examples of the present disclosure have been described herein for illustrative purposes, and those skilled in the art will recognize that various equivalent modifications are possible within the scope of the present disclosure. These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and claims.

[0132] Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the present disclosure, even if only a single embodiment is described with respect to a particular feature. The example features provided in this disclosure are intended to be illustrative rather than limiting, unless otherwise specified. The above description is intended to cover such alternatives, modifications, and equivalents as would be apparent to one skilled in the art having the benefit of this disclosure.

[0133] The scope of the present disclosure includes any feature or combination of features disclosed herein (explicitly or implicitly), or any generalization thereof, regardless of whether it alleviates any or all of the problems addressed herein. Accordingly, new claims may be formulated to any such combination of features during prosecution of this application (or an application claiming priority thereto). In particular, with reference to the appended claims, features from the dependent claims may be combined with features from the independent claims, and features from each independent claim may be combined in any suitable manner, not just in the specific combinations recited in the appended claims.

[0134] Various embodiments or aspects of the present disclosure are described herein. In some implementations, different embodiments are implemented separately. However, the embodiments are not limited to being implemented alone. For example, two or more different embodiments may be combined together to implement a single device, process, structure, or the like. In some cases, the entirety of various embodiments may be combined together. In other examples, portions of a first embodiment may be combined with portions of one or more different embodiments. For example, portions of a first embodiment may be combined with portions of a second embodiment, or portions of a first embodiment may be combined with portions of a second embodiment and a third embodiment. The following examples relate to further embodiments: The various features of the different embodiments can be combined in various ways, with some features included and other features excluded, to suit a variety of different applications.

[0135] Exemplary embodiment 1: An integrated circuit structure includes a vertical stack of horizontal nanowires. An epitaxial source or drain structure is coupled to the vertical stack of horizontal nanowires. A gate stack is above the vertical stack of horizontal nanowires, the gate stack including a gate dielectric and a gate electrode. Gate dielectric spacers are along sides of the gate stack. A gate insulation cap structure is above the gate stack and extends laterally beyond the gate stack, the gate insulation cap structure extends vertically above the gate dielectric spacers, and the gate insulation cap structure includes a dielectric liner and a dielectric filler.

[0136] Exemplary Embodiment 2: The integrated circuit structure of Exemplary Embodiment 1, wherein the dielectric liner comprises a low-k material and the dielectric filler comprises silicon and nitrogen.

[0137] Exemplary Embodiment 3: The integrated circuit structure of Exemplary Embodiment 1 or 2, wherein the dielectric liner has a top surface that is flush with the top surface of the dielectric fill material.

[0138] Exemplary embodiment 4: The integrated circuit structure of exemplary embodiment 1, 2, or 3, further comprising a conductive trench contact structure above the epitaxial source or drain structure, the conductive trench contact structure having a top surface that is flush with the top surface of the gate insulating cap structure.

[0139] Exemplary Embodiment 5: The integrated circuit structure of Exemplary Embodiment 1, 2, 3, or 4, wherein the gate dielectric comprises a high-k dielectric layer.

[0140] Exemplary Embodiment 6: An integrated circuit structure includes a fin. An epitaxial source or drain structure is coupled to the fin. A gate stack is above the fin, the gate stack including a gate dielectric and a gate electrode. Gate dielectric spacers are along sides of the gate stack. A gate insulation cap structure is above the gate stack and extends laterally beyond the gate stack, the gate insulation cap structure extends vertically above the gate dielectric spacer, and the gate insulation cap structure includes a dielectric liner and a dielectric fill.

[0141] Exemplary Embodiment 7: The integrated circuit structure of Exemplary Embodiment 6, wherein the dielectric liner comprises a low-k material and the dielectric filler comprises silicon and nitrogen.

[0142] Exemplary Embodiment 8: The integrated circuit structure of Exemplary Embodiment 6 or 7, wherein the dielectric liner has a top surface that is flush with the top surface of the dielectric fill material.

[0143] Exemplary embodiment 9: The integrated circuit structure of exemplary embodiment 6, 7, or 8, further comprising a conductive trench contact structure above the epitaxial source or drain structure, the conductive trench contact structure having a top surface that is the same height as the top surface of the gate insulating cap structure.

[0144] Exemplary Embodiment 10: The integrated circuit structure of Exemplary Embodiment 6, 7, 8, or 9, wherein the gate dielectric comprises a high-k dielectric layer.

[0145] Exemplary embodiment 11: A computing device includes a substrate and a component coupled to the substrate. The component includes an integrated circuit structure including a vertical stack or fin of horizontal nanowires. An epitaxial source or drain structure is coupled to the vertical stack or fin of horizontal nanowires. A gate stack is above the vertical stack or fin of horizontal nanowires, the gate stack including a gate dielectric and a gate electrode. Gate dielectric spacers are along sides of the gate stack. A gate insulation cap structure is above the gate stack and extends laterally beyond the gate stack, the gate insulation cap structure extends vertically above the gate dielectric spacer, and the gate insulation cap structure includes a dielectric liner and a dielectric filler.

[0146] Exemplary embodiment 12: The computing device of exemplary embodiment 11, comprising a vertical stack of horizontal nanowires.

[0147] Exemplary embodiment 13: The computing device of exemplary embodiment 11, including a fin.

[0148] Exemplary Embodiment 14: The computing device of Exemplary Embodiment 11, 12, or 13, further comprising a memory coupled to the substrate.

[0149] Exemplary embodiment 15: The computing device of exemplary embodiment 11, 12, 13, or 14, further comprising a communications chip coupled to the substrate.

[0150] Exemplary Embodiment 16: The computing device of Exemplary Embodiments 11, 12, 13, 14, or 15, further comprising a battery coupled to the substrate.

[0151] Exemplary Embodiment 17: The computing device of exemplary embodiments 11, 12, 13, 14, 15, or 16, further comprising a camera coupled to the substrate.

[0152] Exemplary Embodiment 18: The computing device of Exemplary Embodiments 11, 12, 13, 14, 15, 16, or 17, further comprising a display coupled to the substrate.

[0153] Exemplary Embodiment 19: The computing device of Exemplary Embodiment 11, 12, 13, 14, 15, 16, 17, or 18, wherein the component is a packaged integrated circuit die.

[0154] Exemplary Embodiment 20: The computing device of exemplary embodiment 11, 12, 13, 14, 15, 16, 17, 18, or 19, wherein the component is selected from the group consisting of a processor, a communication chip, and a digital signal processor.

Claims

1. vertical stacks of horizontal nanowires; an epitaxial source or drain structure coupled to the vertical stack of horizontal nanowires; a gate stack above the vertical stack of horizontal nanowires, the gate stack having a gate dielectric and a gate electrode; gate dielectric spacers along the sides of the gate stack; and a gate insulation cap structure overlying the gate stack and extending laterally beyond the gate stack, the gate insulation cap structure extending vertically above the gate dielectric spacer, the gate insulation cap structure having a dielectric liner and a dielectric filler; 1. An integrated circuit structure comprising:

2. 2. The integrated circuit structure of claim 1, wherein said dielectric liner comprises a low-k material and said dielectric fill comprises silicon and nitrogen.

3. 2. The integrated circuit structure of claim 1, wherein said dielectric liner has a top surface that is flush with a top surface of said dielectric fill.

4. a conductive trench contact structure above the epitaxial source or drain structure, the conductive trench contact structure having a top surface that is flush with a top surface of the gate insulating cap structure; 10. The integrated circuit structure of claim 1 further comprising:

5. 5. The integrated circuit structure of claim 1, wherein the gate dielectric comprises a high-k dielectric layer.

6. fin; an epitaxial source or drain structure coupled to the fin; a gate stack above the fin, the gate stack having a gate dielectric and a gate electrode; gate dielectric spacers along the sides of the gate stack; and a gate insulation cap structure overlying the gate stack and extending laterally beyond the gate stack, the gate insulation cap structure extending vertically above the gate dielectric spacer, the gate insulation cap structure having a dielectric liner and a dielectric filler; 1. An integrated circuit structure comprising:

7. 7. The integrated circuit structure of claim 6, wherein said dielectric liner comprises a low-k material and said dielectric fill comprises silicon and nitrogen.

8. 7. The integrated circuit structure of claim 6, wherein said dielectric liner has a top surface that is flush with a top surface of said dielectric fill.

9. a conductive trench contact structure above the epitaxial source or drain structure, the conductive trench contact structure having a top surface that is flush with a top surface of the gate insulating cap structure; 7. The integrated circuit structure of claim 6, further comprising:

10. 10. The integrated circuit structure of claim 6, 7, 8 or 9, wherein the gate dielectric comprises a high-k dielectric layer.

11. a substrate; and a component bonded to the substrate, the component comprising: vertical stacks or fins of horizontal nanowires; an epitaxial source or drain structure coupled to the vertical stack of horizontal nanowires or to the fin; a gate stack above the vertical stack of horizontal nanowires or the fin, the gate stack including a gate dielectric and a gate electrode; gate dielectric spacers along the sides of the gate stack; and a gate insulation cap structure overlying the gate stack and extending laterally beyond the gate stack, the gate insulation cap structure extending vertically above the gate dielectric spacer, the gate insulation cap structure including a dielectric liner and a dielectric filler; an integrated circuit structure including A computing device comprising:

12. The computing device of claim 11 comprising a vertical stack of the horizontal nanowires.

13. The computing device of claim 11 comprising fins.

14. a memory coupled to the substrate; The computing device of claim 11 further comprising:

15. a communications chip coupled to the substrate The computing device of claim 11 further comprising:

16. a battery coupled to the substrate The computing device of claim 11 further comprising:

17. a camera coupled to the substrate The computing device of claim 11 further comprising:

18. a display coupled to the substrate The computing device of claim 11 further comprising:

19. The computing device of claim 11 , wherein the component is a packaged integrated circuit die.

20. 20. The computing device of claim 11, 12, 13, 14, 15, 16, 17, 18, or 19, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

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