Method and apparatus for icp etching of trench features in compound semiconductor wafer

Abstract

To reduce microtrench formation in etching a compound semiconductor substrate.SOLUTION: The present invention provides a method of plasma etching a compound semiconductor substrate. The method comprises steps of: providing a substrate 29 on a substrate support 28 within a chamber 21, wherein the substrate comprises a compound semiconductor material; introducing an etchant gas or gas mixture into the chamber; sustaining a plasma of the etchant gas or gas mixture within the chamber to plasma etch the compound semiconductor material; and applying a pulsed electrical bias power to the substrate support while the plasma is being sustained, in which the pulsed electrical bias power has a pulse frequency of less than or equal to about 160 Hz and a duty ratio of less than or equal to about 50%.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a method for plasma etching a compound semiconductor substrate, and also to an apparatus for plasma etching a compound semiconductor substrate. [Background technology]

[0002] Compound semiconductors are used in optical, high frequency RF, power, and MEMs applications. Device fabrication typically requires the formation of features, such as trenches, in compound semiconductor substrates and / or epitaxial films deposited on the substrate. Plasma etching technology can be used to create such features.

[0003] Current plasma etching technologies use helicon plasma, electron cyclotron resonance (ECR), reactive ion etching (RIE), and / or inductively coupled plasma (ICP). Although application conditions depend on the specific application, achieving optimal results requires controlling the etch rate, etch uniformity, mask selectivity, etch profile, and defect avoidance, such as micro-trenches.

[0004] ICP technology has several advantages. For example, it allows plasma density to be controlled independently of ion energy, providing a uniform plasma over a large area. However, when using an ICP system to plasma etch features, such as trenches, into compound semiconductor substrates, a compromise can be made between etch rate and other application requirements, such as the formation of defects (e.g., microtrenches).

[0005] In optical waveguide and power semiconductor applications, it is essential to avoid microtrenches. A microtrench is a deeply etched region at the bottom edge or corner of an etched feature (e.g., a trench). Without being bound by any theory or speculation, it is believed that microtrenches are formed when excessive ion bombardment occurs at the bottom edge of the feature, resulting in a higher vertical etch rate in that region. FIG. 1 shows a cross-sectional image of a compound semiconductor substrate 10 containing a trench 12. The trench 12 has a deeply etched region, or microtrench 14, at the bottom of the trench 12. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] U.S. Patent Application Publication No. 2016 / 0118256 [Patent Document 2] U.S. Patent Application Publication No. 2011 / 0177669 [Patent Document 3] U.S. Patent Application Publication No. 2011 / 0073564 [Patent Document 4] International Publication No. 2020 / 243342 Summary of the Invention [Problem to be solved by the invention]

[0007] It would be desirable to develop a method for plasma etching compound semiconductor substrates while reducing micro-trenching. It would further be desirable to reduce micro-trenching without compromising etch rate and / or etch selectivity or any other application conditions.

[0008] Known methods that help suppress microtrenching include employing hydrogen (H) gas as a process gas. However, the use of H gas when etching compound semiconductors is often undesirable. For example, when etching materials such as InP and InGaAs, hydrogen-based plasmas can react with phosphorous acid and arsenic to produce highly volatile by-products (PH and AsH, respectively). This can result in undesirable surface characteristics and implantation of H atoms into the substrate surface, ultimately leading to unwanted near-surface dopant passivation. It would be desirable to develop a method for suppressing microtrenching during plasma etching of compound semiconductors that does not use hydrogen as a process gas.

[0009] The present method, at least some embodiments thereof, addresses the problems, wants, and needs described above. Specifically, the present invention provides a method for reducing micro-trenching while providing a correspondingly high etch rate and / or excellent etch selectivity. [Means for solving the problem]

[0010] According to a first aspect of the present invention, there is provided a method for plasma treating a compound semiconductor substrate, comprising the steps of: providing a substrate containing a compound semiconductor material on a substrate support within the chamber; introducing an etchant gas or gas mixture into the chamber; sustaining a plasma of the etchant gas or gas mixture in the chamber to plasma etch the compound semiconductor material; applying a pulsed bias power to the substrate support while sustaining the plasma; wherein the pulsed bias power has a pulse frequency of about 160 Hz or less and a duty cycle of about 50% or less.

[0011] The inventors have discovered that pulsing the bias power to the substrate while maintaining a plasma unexpectedly reduces microtrenching. In particular, the combination of a low pulse frequency and a low duty ratio improves the reduction of microtrenching. Furthermore, the combination of applying a pulsed bias power to the substrate with a low pulse frequency and a low duty ratio significantly improves the etch selectivity.

[0012] The duty cycle can be 40% or less, optionally 35% or less, optionally 30% or less, optionally 25% or less, or optionally about 20%. The duty cycle can be 5% or more, optionally 10% or more, or optionally 15% or more. The duty cycle can be any combination of these upper and lower limits.

[0013] The pulse frequency can be 150 Hz or less, optionally 125 Hz or less, optionally 100 Hz or less, optionally 75 Hz or less, optionally 50 Hz or less, optionally 25 Hz or less, optionally 20 Hz or less, optionally 15 Hz or less, optionally 10 Hz or less, optionally 5 Hz or less, optionally 2 Hz or less, or optionally 1 Hz or less. The pulse frequency can be 0.1 Hz or more, optionally 0.5 Hz or more, or optionally 0.75 Hz or more. The pulse frequency can be any combination of these upper and lower limits.

[0014] The pulsed bias power typically alternates between high and low power (or 0 power). The high power can be in the range of 50-250 W, optionally 60-200 W, optionally 75-150 W, and optionally approximately 100 W. The low power can be in the range of 0-25 W, preferably approximately 0 W. The bias power can be any combination of these upper and lower limits.

[0015] The pulsed bias power may be a pulsed RF bias power, and the frequency of the RF bias power may be set to 2 to 20 MHz, preferably 13.56 MHz.

[0016] The etchant gas or gas mixture may include a chemical etchant gas. A plasma of the chemical etchant gas may chemically etch the substrate. The chemical etchant gas may be a chlorine-containing chemical etchant gas. The chemical etchant gas may be SiCl4.

[0017] The etchant gas or gas mixture may contain an inert sputtering gas. The substrate may be sputter-etched by a plasma of the inert sputtering gas. The inert sputtering gas may be a noble gas. A noble gas is an element belonging to Group 18 of the periodic table. Preferably, the inert sputtering gas is argon gas.

[0018] The etchant gas mixture can include a chlorine-containing chemical etchant gas, such as SiCl4, and an inert sputter gas, such as argon gas. The etchant gas mixture can consist exclusively or essentially of SiCl4 and argon gas. The etchant gas or gas mixture can be free of a hydrogen (H) source. For example, the etchant gas or gas mixture can be free of hydrogen gas (H2).

[0019] The etchant gas or gas mixture may be introduced into the chamber at a total flow rate of less than 200 sccm (standard cc / minute), optionally less than 150 sccm, optionally less than 100 sccm, optionally less than 80 sccm, optionally 60 sccm, and optionally about 45 sccm.

[0020] The chemical etchant gas may be introduced into the chamber at a flow rate in the range of 1-50 sccm, optionally 2-25 sccm, optionally 3-10 sccm, optionally 4-8 sccm, and optionally about 5 sccm.

[0021] The inert sputtering gas can be introduced into the chamber at a flow rate in the range of 10-150 sccm, optionally 20-100 sccm, optionally 25-75 sccm, optionally 30-50 sccm, and optionally about 40 sccm.

[0022] The ratio of the flow rates (in sccm) of the chemical etchant gas and the inert sputter gas introduced into the chamber can be in the range of 1:1 to 1:50, optionally 1:2 to 1:25, optionally 1:3 to 1:20, optionally 1:4 to 1:15, optionally 1:5 to 1:10, and optionally about 1:8.

[0023] The plasma is preferably an inductively coupled plasma. The method can be carried out using an inductively coupled plasma device.

[0024] The substrate support may comprise an electrostatic chuck (ESC), which provides sufficient heat removal to the substrate during a plasma etching process.

[0025] The compound semiconductor material can include a Group IV-IV, Group III-V, or Group II-VI compound semiconductor. Microtrenching is particularly problematic in high bandgap Group 14 compound semiconductors (e.g., SiC), Group III-V compound semiconductors, and Group II-VI compound semiconductors. A prominent application of the method is in suppressing microtrenching in such compound semiconductors.

[0026] The compound semiconductor material may contain a material selected from the group consisting of InGaAs, InP, GaN, GaP, AlGaAs, and SiC. The substrate may comprise a layer stack, each layer made of a compound semiconductor material. For example, the layer stack may comprise InP / InGaAs / InP. The substrate may be an epitaxial wafer.

[0027] The plasma etching can form features, such as trenches, whose sidewalls can have a slope angle in the range of about 88.0 to 90.0 degrees, preferably about 89.0 to 90.0 degrees (i.e., the trench can be slightly sloped toward its base).

[0028] According to a second aspect of the present invention, there is provided an apparatus for plasma etching a compound semiconductor substrate using the method of the present invention, comprising: a chamber; a substrate support disposed within the chamber; a plasma generator for sustaining a plasma within the chamber; a power supply that provides bias power to the substrate support; a controller configured to control the power supply such that a pulsed bias power is applied to the substrate support while the plasma is sustained; wherein the pulsed bias power has a pulse frequency of about 160 Hz or less and a duty cycle of about 50% or less.

[0029] The plasma generator may be a device for sustaining inductively coupled plasma in the chamber. The plasma generator may include a coil. By supplying RF power to the coil from an RF power source, inductively coupled plasma can be sustained in the chamber. The frequency of the RF power supplied to the coil may be 2 to 20 MHz, and is preferably 13.56 MHz.

[0030] The invention has been described above and extends to any and all inventive combinations of the features set out above or in the following description, drawings or claims. For example, any feature disclosed in connection with one aspect of the invention can be combined with any feature disclosed in connection with any other aspect of the invention.

[0031] Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which: [Brief explanation of the drawings]

[0032] [Figure 1] 1 is a schematic cross-sectional view of a trench in a compound semiconductor substrate. [Figure 2] FIG. 1 is a schematic cross-sectional view of an inductively coupled plasma device. [Figure 3] FIG. 1 is a representational diagram of bias power applied to a substrate support during plasma etching in accordance with one embodiment. [Figure 4] FIG. 1 is a representation of a trench etched using conventional methods. [Figure 5] FIG. 2 is a representation of a trench etched using a method according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0033] 2 shows an apparatus 20 suitable for plasma etching compound semiconductor substrates. A suitable apparatus for carrying out the methods of the present invention is an adapted SPTS® Omega ICP Etch System, commercially available from SPTS Technologies Limited, Newport, South Wales, UK. All of the exemplary embodiments and comparative examples described below were carried out using this adapted apparatus.

[0034] Apparatus 20 comprises a chamber 21 and a plasma generator for sustaining a plasma within the chamber. Chamber 21 comprises a dielectric cylindrical wall 22, typically made of Al2O3. The chamber further comprises a gas inlet 23 through which process gases can be introduced into chamber 21 and a gas outlet 24 through which gases can be removed from the chamber using a suitable pump.

[0035] The plasma generator includes a coil 25 that can be electrically driven by an RF power supply 26 via an impedance matching network 27. The coil 25 is disposed around the dielectric wall 22. The RF power supply 26 typically supplies RF power to the coil 25 at a frequency of 2 to 20 MHz, although a lower frequency (e.g., 380 kHz) can also be used.

[0036] The apparatus 20 further includes a substrate support 28 on which a compound semiconductor substrate 29 can be placed for processing. The substrate 29 can be a substrate composed of a IV-IV compound semiconductor (e.g., SiC), a III-V compound semiconductor (e.g., InGaAs, InP, GaN, GaP, or AlGaAs), or a II-VI compound semiconductor. The substrate support 28 can be an electrostatic chuck (ESC). The ESC can exert an electrostatic clamping force on the substrate 29 and can also remove heat from the substrate 29 during plasma processing. Alternatively or additionally, a mechanical clamp (not shown) can be used to clamp the substrate 29 in place. The substrate support 28 is connected to a power source, e.g., an RF power source 30, via a ceramic break 31 and an impedance matching network 32. The power source 30 can provide an electrical bias, e.g., an RF electrical bias, to the substrate support 28. The RF power supply 30 typically provides RF power having a frequency of 2-20 MHz, optionally 13.56 MHz, although lower frequencies (e.g., 380 kHz) can also be employed. A controller (not shown) is configured to pulse the electrical bias power applied to the substrate support 28 during the plasma etching process.

[0037] According to one embodiment of the method, a compound semiconductor substrate 29 is provided on a substrate support 28. An etchant gas or gas mixture is introduced into chamber 21 at a flow rate through gas inlet 23. A plasma of the etchant gas or gas mixture is sustained within chamber 21 by supplying RF bias power from power supply 26 through impedance match network 27 to coil 25. Pulsed RF bias power is applied to substrate support 28 from power supply 30.

[0038] The inventors have discovered that pulsing the electrical bias to the substrate support 28 during part or all of the plasma etching procedure can significantly reduce defect formation, such as micro-trenching.

[0039] The power of this pulsed RF bias power alternates between low and high power. The low power is typically less than 25 W, preferably about 0 W. The high power is typically in the range of 50-250 W, optionally about 100 W, although other values ​​are also possible. The pulse frequency of the pulsed RF bias power is about 160 Hz or less. The duty ratio of the pulsed RF bias power is about 50% or less. The duty ratio (as a percentage) is the time per pulse during which the applied bias power is at high power (as shown schematically in Figure 3). high , the applied bias power is low or 0 power, and the pulse is generated every time t low If so, it can be calculated using Equation 1. Duty ratio (%) = t high / (t high +t low )×100 (1)

[0040] t high and t low The sum of these corresponds to the period of the pulse, and therefore corresponds to the reciprocal of the pulse frequency.

[0041] Without being bound by any theory or speculation, it is believed that pulsing the electrical bias to the substrate support, particularly at a low frequency (e.g., 160 Hz or less) and a low duty cycle (e.g., 50% or less), while keeping the bias power low, dissipates any charge buildup at the bottom edge of the trench, which helps prevent excessive ion bombardment at the bottom edge or corner of the etched feature and helps suppress microtrenching.

[0042] For illustrative purposes only, trenches were plasma etched into InGaAs substrates using the method of the present invention. The trench width was 25 μm and the etch depth was 3 μm. The InGaAs substrates had a patterned SiO2 hard mask layer with a thickness of 0.5 μm. The mask layer was more resistant to the plasma etching conditions than the exposed areas of the InGaAs material. The etchant gas contained a mixture of SiCl4 and argon gas. The process conditions used for the plasma etching procedures in these examples are listed in Table 1.

[0043] [Table 1]

[0044] Table 2 shows how the etch rate (μm / min), compound semiconductor material to SiO2 etch selectivity, sidewall angle, and microtrench ratio (MTR) varied as a function of the pulse frequency and duty cycle of the electrical bias applied to the substrate support. All other parameters were held constant. The microtrench etch ratio (MTR) is the ratio of the etch depth (ED) to the microtrench depth (MD). Higher MTR values ​​correspond to less severe microtrench formation, so the MTR value can be used to quantify the severity of microtrench formation. Example 1, which relates to a plasma etching treatment in which a continuous RF bias (100 W) is applied to the substrate support during the plasma etching process, is presented for comparison.

[0045] [Table 2]

[0046] FIG. 4 shows a schematic perspective cross-section of a trench etched using Example 1. The inset in FIG. 4 shows a magnified view of a microtrench defect. Substrate 40 includes a 0.5 μm thick SiO2 mask layer 41. A trench 42 is formed in the area not covered by the patterned mask layer 41. The sidewalls 43 of trench 42 are substantially aligned with the edges of mask layer 41; no notching (i.e., lateral etching resulting in undercutting) is observed. The etch angle of sidewall 43 is 87.7°. For optical waveguide applications, a sidewall angle of approximately 89° (or as close to 90° as possible) is desired. A microtrench 44 is formed where the sidewall 43 intersects with the bottom surface 45 of the trench. Microtrench 44 is aligned with the sidewall and corresponds to the over-etched area of ​​bottom wall 45.

[0047] Figure 5 shows a schematic perspective cross-section of a trench etched into a compound semiconductor substrate 50 using the processing conditions of Example 6. The inset in Figure 5 shows a close-up view of the intersection of the sidewall 53 and bottom surface 55 of trench 52. Features labeled with the same reference number correspond to similar features.

[0048] Examples 3, 4, and 5 show improved MTR values ​​compared to Comparative Example 1. Examples 2, 6, and 7 eliminate microtrenching, resulting in further improvements. When no microtrenches are visible (as measured by SEM), the MTR is set to infinite. Examples 2-7 all show significantly higher etch selectivity than Comparative Example 1, allowing for deeper etching with thinner mask layers. Examples 2-7 all beneficially show sidewall angles closer to 90°, resulting in better quality devices for optical waveguide applications.

[0049] In Examples 2 to 7, the etching rate is lower than that of Comparative Example 1. However, this small decrease in etching rate is outweighed by the significant improvements in etching selectivity, sidewall angle, and MTR value.

[0050] Due to the complete absence of micro-trench formation and the optimum sidewall angle, the conditions of Example 6 are believed to be the most favorable for optical waveguide applications.

[0051] In particular, a pulsed electrical (RF) bias supply, combined with a low pulse frequency and low duty cycle, provides optimal conditions that significantly reduce (or eliminate) microtrenching while providing beneficial improvements in etch selectivity and sidewall etch angle. Without being bound by any theory or speculation, it appears that pulsing the electrical (RF) bias applied to the substrate support reduces charge buildup on the features being etched while maintaining excellent process performance. The low-power portion of the pulse allows any accumulated charge to be (at least partially) dissipated, resulting in more uniform vertical etching and thus significantly reducing microtrenching. This effect is enhanced by the combination of a low pulse frequency (e.g., 160 Hz or less) and a low duty cycle (e.g., 50% or less).

[0052] By way of further example only, trenches were etched into a group of different compound semiconductor substrates using the method of the present invention (Table 3). These substrates included bulk InP substrates and epitaxial wafers. An epitaxial wafer is a silicon wafer on which one or more layers of compound semiconductor material are deposited. For example, a silicon wafer can have a GaN layer deposited on it. An epitaxial wafer can have multiple (stacked) compound semiconductor layers deposited thereon. In one embodiment, an epitaxial wafer has a first layer made of InP, a second layer made of InGaAs, and a third layer made of InP (hereinafter referred to as an "InP / InGaAs / InP substrate"). Epitaxial wafers can have various numbers of layers and can be composed of various compound semiconductor materials.

[0053] [Table 3]

[0054] The results in Table 3 demonstrate that the method of the present invention can eliminate microtrenching when etching a variety of different compound semiconductor materials, including etching bulk compound semiconductor materials, etching through multiple layers of different compound semiconductor materials, and etching substrates with epitaxial structures (e.g., epitaxial wafers). The method can also be used to eliminate microtrenching when etching other compound semiconductor materials, including, but not limited to, SiC, GaP, and AlGaAs.

[0055] Embodiments of the present method are particularly suited for plasma etching of substrates containing compound semiconductor materials because micro-trenching can be suppressed without relying on hydrogen-based chemistries that can lead to the formation of highly volatile H-related by-products (e.g., PH3 and AsH3) that create undesirable surface properties, resulting in implantation of H atoms into the surface of the compound semiconductor material, and ultimately near-surface dopant passivation.

Claims

1. 1. A method for plasma etching a compound semiconductor substrate, comprising: providing a substrate containing a compound semiconductor material on a substrate support within the chamber, the compound semiconductor material comprising a IV-IV, III-V, or II-VI compound semiconductor; introducing an etchant gas or gas mixture into the chamber, the etchant gas or gas mixture comprising a chemical etchant gas; plasma etching the compound semiconductor material by sustaining a plasma of the etchant gas or gas mixture in the chamber, the plasma being an inductively coupled plasma; applying a pulsed bias power to the substrate support while sustaining a plasma of the etchant gas or gas mixture; wherein the pulsed bias power has a pulse frequency of 160 Hz or less and a duty cycle of 50% or less.

2. 2. The method according to claim 1, wherein the duty ratio is 40% or less.

3. 3. The method according to claim 2, wherein the duty ratio is 25% or less.

4. 2. The method according to claim 1, wherein the duty ratio is 5% or greater.

5. 5. The method according to claim 4, wherein the duty ratio is 15% or greater.

6. 10. The method of claim 1, wherein the pulse frequency is less than or equal to about 150 Hz.

7. 7. The method according to claim 6, wherein the pulse frequency is less than or equal to 1 Hz.

8. 2. The method according to claim 1, wherein the pulse frequency is 0.1 Hz or greater.

9. 2. The method according to claim 1, wherein the pulsed bias power alternates between high and low power, the high power being in the range of 50-250 W and the low power being in the range of 0-25 W.

10. 2. The method of claim 1, wherein the pulsed bias power is a pulsed RF bias power.

11. 10. The method of claim 1, wherein the chemical etchant gas is SiCl ４ How to be.

12. 10. The method of claim 1, wherein the etchant gas or gas mixture further comprises an inert sputter gas.

13. 13. The method of claim 12, wherein the inert sputter gas is argon gas.

14. 2. The method of claim 1, wherein the etchant gas or gas mixture is SiCl ４ and argon gas.

15. 2. The method of claim 1, wherein the compound semiconductor material comprises a material selected from the group consisting of InGaAs, InP, GaN, GaP, AlGaAs, and SiC.

16. 2. The method of claim 1, wherein the plasma etching forms a feature, the feature being a trench.

17. 2. A method according to claim 1, comprising: The pulsed bias power is a pulsed RF bias power, and the pulsed bias power alternates between high power and low power, the high power being in the range of 50 to 250 W and the low power being in the range of 0 to 25 W.

18. 2. The method according to claim 1, wherein the compound semiconductor substrate is used as an optical waveguide, and the duty ratio is 20 to 22% or less.

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