Power semiconductor device and manufacturing method

Abstract

In at least one embodiment, a power semiconductor device (1) comprises a semiconductor body (2), a gate electrode (31), and an extraction electrode (34), the semiconductor body (2) comprising a source region (21) of a first conductivity type, a well region (22) of a second conductivity type different from the first conductivity type in the gate electrode (31), a drift region (23) of the first conductivity type, and a barrier region (28) of the first conductivity type, the barrier region (28) being located between the drift region (23) and the extraction electrode (34).

Description

[Technical field]

[0001] A power semiconductor device is provided, as well as a method for manufacturing such a power semiconductor device. [Background technology]

[0002] US Pat. No. 9,825,158 discloses an insulated gate bipolar transistor.

[0003] US Pat. No. 8,210,098 refers to a trench insulated gate bipolar transistor.

[0004] European Patent Application Publication No. 2 953 166, US Patent Application Publication No. 2017 / 033206, US Patent Application Publication No. 2019 / 019861, US Patent Application Publication No. 2016 / 359026 and US Patent Application Publication No. 2016 / 247910 relate to semiconductor devices. Summary of the Invention [Problem to be solved by the invention]

[0005] The problem to be solved is to provide a power semiconductor device with improved electrical behavior. [Means for solving the problem]

[0006] Embodiments of the present disclosure refer to a power semiconductor device and a method as defined in the independent claims. Exemplary further developments form the subject matter of the dependent claims.

[0007] For example, a power semiconductor device may include an extraction electrode separated from a drift region by a barrier region that allows for an improved trade-off between long-term stability, particularly in terms of robustness against gate dielectric degradation, and static losses.

[0008] In at least one embodiment, a power semiconductor device comprises a semiconductor body, a gate electrode, and an extraction electrode, the semiconductor body comprising: a source region of a first conductivity type, the source electrode being located on the source region; a well region of a second conductivity type different from the first conductivity type in the gate electrode; a drift region of a first conductivity type; a barrier region of a first conductivity type, the barrier region being located between the drift region and an extraction electrode, the extraction electrode being assigned to the barrier region; Equipped with.

[0009] For example, assignment of an extraction electrode to a barrier region can mean that the respective extraction electrode is located in a closed ring formed by the assigned barrier region in a top view of the upper surface of the semiconductor body. Alternatively or additionally, the respective extraction electrode is the electrode that is in direct electrical contact with the semiconductor body and is closest to the barrier region.

[0010] The gate electrode is insulated from the semiconductor body by a gate dielectric. The gate dielectric is made of any electrically insulating material, which may be an oxide. For example, the gate dielectric may be at least one of the following materials: SiO2, Si3N4, Al2O3, Y2O3, ZrO2, HfO2, La2O3, Ta2O5, TiO2. The gate dielectric may therefore also be referred to as a gate oxide. For example, the gate dielectric has a thickness of at least 50 nm and / or at most 0.5 μm.

[0011] For example, the semiconductor body is silicon, or Si for short. However, the semiconductor body may alternatively be a wide bandgap semiconductor material such as SiC, Ga2O3 or GaN.

[0012] The first conductivity type is, for example, n-conductivity type, and therefore the source and drift regions and the barrier region are n-doped. In this case, the second conductivity type is p-conductivity type, and therefore the well region is p-doped. In another embodiment, the first conductivity type is p-type and the second conductivity type is n-type. In the following, we focus on the first case, i.e., the first conductivity type is n-conductivity type and the second conductivity type is p-conductivity type, but all the following statements also apply to the case where the first conductivity type is p-conductivity type and the second conductivity type is n-conductivity type. It is possible that the maximum doping concentration of the well region is less than the maximum doping concentration of the source region and / or is greater than the maximum doping concentration of the drift region.

[0013] When the power semiconductor device is in an on-state, the well region is configured to cooperate with the gate insulating film and the gate electrode to provide a channel region. For example, the well region is in direct contact with the gate insulating film. The channel region is therefore part of the well region and may have the same doping concentration. In operation, and when the second conductivity type is p-type, electrons flow in the channel region from the source region to the drift region along the gate insulating film. The channel region has a thickness in a direction perpendicular to the interface between the gate insulating film and the well region, for example in the nanometer range, illustratively between 1 nm and 50 nm.

[0014] According to at least one embodiment, the power semiconductor device is configured for a maximum voltage of at least 0.6 kV or at least 1.2 kV or at least 3 kV. This voltage is applied during normal use of the device, for example between the drain and emitter electrodes or between the source and drain electrodes. That is, by using the gate electrode to have a respective voltage between the source / emitter and drain / collector electrodes, the flow of current through the power semiconductor device can be controlled, in particular switched on and off.

[0015] Power semiconductor devices are used, for example, in vehicle power modules to convert direct current from a battery or fuel cell to alternating current for an electric motor, for example in a vehicle such as a hybrid or plug-in electric vehicle, or in a railway such as a commuter train.

[0016] According to at least one embodiment, the power semiconductor device is a metal-insulator-semiconductor field-effect transistor (MISFET), a metal-oxide-semiconductor field-effect transistor (MOSFET), or an insulated-gate bipolar transistor (IGBT), or a reverse-conducting insulated-gate bipolar transistor (RC-IGBT).

[0017] According to at least one embodiment, the semiconductor body further comprises an extraction region. For example, the extraction region is located at the extraction electrode. The extraction electrode can only contact the semiconductor body via the extraction region. Thus, the extraction region can be located between the barrier region and the extraction electrode and can be in direct contact with both the barrier region and the extraction electrode. The extraction region is of the second conductivity type.

[0018] According to at least one embodiment, the semiconductor body further comprises a deep doped region of the second conductivity type. For example, the deep doped region is located between the barrier region and at least a portion of the drift region. It is possible that the deep doped region is located directly on the barrier region, with the barrier region separating the deep doped region from the extraction region and the extraction electrode. Furthermore, it is possible that a portion of the drift region is located between the barrier region and the deep doped region, such that the deep doped region can be sandwiched between different portions of the drift region.

[0019] According to at least one embodiment, the depth of the deep doped region into the semiconductor body is equal to or greater than the depth of the well region, for example, the depth of the deep doped region exceeds the depth of the well region by at least 1.5 times, or at least 2 times, and / or by up to 20 times, or by up to 10 times.

[0020] The term "depth" may refer to the extent of the respective component in a direction perpendicular to a top surface of the semiconductor body, for example the top surface facing a collector or drain electrode of a power semiconductor device.

[0021] According to at least one embodiment, the bottom surface of the barrier region is partially or completely free of deep doped regions. The bottom surface is the surface of the barrier region that faces outward from the top surface. In other words, the region below the barrier region can be completely or partially free of deep doped regions.

[0022] According to at least one embodiment, the semiconductor body further comprises an enhancement region of the first conductivity type. For example, the enhancement region is located directly on the bottom surface of the well region, such that the enhancement region is located between the drift region and the well region. That is, the well region can be assigned the enhancement region. If the enhancement region is not present, the well region can be in direct contact with the drift region, for example at the bottom surface of the well region.

[0023] In accordance with at least one embodiment, the gate electrode is partially or completely contained within the trench, e.g., the trench is completely filled with the gate electrode and a gate insulating film between the gate electrode and the semiconductor body.

[0024] According to at least one embodiment, the gate electrode and trench extend deeper into the semiconductor body than the well region, for example, the depth to the gate electrode exceeds the depth of the well region by at least 1.5 times, or at least 2 times, and / or by up to 10 times, or by up to 5 times.

[0025] According to at least one embodiment, the depth of the deep doped region is equal to or greater than the depth of the gate electrode.

[0026] According to at least one embodiment, in a top view of the semiconductor body, the gate electrode comprises 2N stripes or 2N+1 stripes, where N is a natural number equal to or greater than 1. For example, 2≦N≦200 or 5≦N≦50. The stripes define N active cells of the power semiconductor device. In other words, each active cell or a plurality of active cells comprises two of the stripes and associated source and well regions.

[0027] According to at least one embodiment, the extraction electrode comprises a plurality of contacts. For example, in a top view of the semiconductor body, the contacts are arranged in each case between two adjacent active cells. It is possible that the contact between each two active cells is arranged along an arrangement line, which may be a straight line. For example, the arrangement line is, in a top view, a mirror symmetry line of the two assigned active cells.

[0028] According to at least one embodiment, the contacts occupy at most 10% or at most 5% of the length of the placement line, so that the contacts form only a small portion of the placement line.

[0029] According to at least one embodiment, the length of each of the contacts along the alignment line is at most 70%, or at most 50%, or at most 30% of the distance between adjacent active cells. Alternatively or additionally, the same may apply to the width of the contacts perpendicular to the alignment line.

[0030] According to at least one embodiment, the source region and the extraction electrode are configured to have the same potential, for example, the source region is in ohmic electrical contact with the extraction electrode, so that the extraction electrode and the source electrode can be electrically shorted.

[0031] A method for manufacturing a power semiconductor device is additionally provided, for example, by the method producing a power semiconductor device as shown in relation to at least one of the above-mentioned embodiments. Accordingly, features of the power semiconductor device are also disclosed in relation to the method, and vice versa.

[0032] In at least one embodiment, the method includes, for example, in the order listed: providing a semiconductor body having a drift region of a first conductivity type; creating an enhancement region and / or a barrier region of a first conductivity type; creating a well region and / or an extension region of a second conductivity type different from the first conductivity type; forming a source region of a first conductivity type; applying a gate electrode to the well region and the extraction electrode, the barrier region being located between the drift region and the extraction electrode; Includes.

[0033] According to at least one embodiment, the enhancement region and the barrier region are created simultaneously, i.e., the enhancement region and the barrier region can be produced by the same doping step, for example by implanting ions to introduce doping.

[0034] According to at least one embodiment, the well region and the draw-out region are created simultaneously, i.e., the well region and the draw-out region can be produced by the same doping step, for example by implanting ions to introduce doping.

[0035] For example, the enhancement and barrier regions on the one hand and the well and extraction regions on the other hand each have the same dopants and / or the same maximum doping concentration and / or the same doping depth profile.

[0036] The power semiconductor device and method described herein will be described in more detail below by way of exemplary embodiments with reference to the drawings. Parts that are the same in the various figures are indicated by the same reference numerals. However, the relationship between elements is not shown to scale, and rather, individual elements may be exaggerated to aid understanding. [Brief description of the drawings]

[0037] [Figure 1] 1 is a schematic perspective view of an exemplary embodiment of a power semiconductor device as described herein; [Diagram 2] FIG. 2 is a schematic cross-sectional view of the power semiconductor device of FIG. [Diagram 3] FIG. 2 is a schematic cross-sectional view of the power semiconductor device of FIG. [Figure 4] 1 is a schematic cross-sectional view of a modified power semiconductor device; [Diagram 5] 1 is a schematic cross-sectional view of a modified power semiconductor device; [Figure 6] FIG. 6 is a schematic diagram of the switching process of the modified power semiconductor device of FIGS. 4 and 5 . [Figure 7] FIG. 6 is a schematic diagram of the switching process of the modified power semiconductor device of FIGS. 4 and 5 . [Figure 8] FIG. 1 is a diagram of comparative data relating to long term switching stability of exemplary embodiments of power semiconductor devices and modified power semiconductor devices described herein. [Figure 9] FIG. 1 is a diagram of comparative data relating to long term switching stability of exemplary embodiments of power semiconductor devices and modified power semiconductor devices described herein. [Figure 10] 1A-1C are comparative data for exemplary embodiments of the power semiconductor devices and modified power semiconductor devices described herein. [Figure 11] FIG. 1 is a diagram of comparative data for the power semiconductor devices and modified power semiconductor devices described herein. [Figure 12] FIG. 2 is a schematic perspective view of a modified power semiconductor device. [Figure 13] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device as described herein. [Figure 14] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device as described herein. [Figure 15] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device as described herein. [Figure 16] 1 is a schematic top view of an exemplary embodiment of a power semiconductor device described herein; [Figure 17] FIG. 2 is a block diagram of an exemplary embodiment of a method for manufacturing a power semiconductor device as described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0038] 1 to 3 show an exemplary embodiment of a power semiconductor device 1. The power semiconductor device 1 comprises a semiconductor body 2, for example made of Si or SiC. In the semiconductor body 2 there is a drift region 23, which may extend laterally across the entire semiconductor body 2, i.e. for example in a direction parallel to a top surface 20 of the semiconductor body 2. The drift region 23 is of a first conductivity type, for example the drift region is n-doped.

[0039] Furthermore, at the top surface 20, the semiconductor body 2 comprises a source region 21, also of the first conductivity type, but with a maximum doping concentration higher than the maximum doping concentration of the drift region 23. The source region 21 is electrically contacted by a source electrode 32. The source electrode 32 may be applied to the top surface 20 of the semiconductor body 2 or may be partially or completely located in a recess formed into the semiconductor body 2 at the top surface 20.

[0040] The source region 21 can be divided into several partial regions. However, since all partial regions function in the same way and can be at the same potential, in the following, for simplicity, only one source region 21 is explicitly referred to, but there can be separate partial regions or even electrically separate source regions that are not shown. The same applies analogously to all other regions of the semiconductor body 2.

[0041] Furthermore, the semiconductor body 2 comprises a well region 22, for example below the source region 21. The well region 22 is of a second conductivity type, for example the well region 22 is p-doped. The well region 22 is located in a gate electrode 31 contained in a trench. The gate electrode 34 is electrically separated from the semiconductor body 2 by a gate insulating film 4. For simplicity, the gate insulating film 4 is only shown in Figure 1. As an option, the trenches may extend parallel to each other.

[0042] Along the gate electrode 34 a channel region 220 is formed in which charge carrier conduction takes place during operation of the power semiconductor device 1. The gate electrode 34 extends deeper into the semiconductor body 2 than the well region 22. An active cell 5 is formed by the two trenches and the source region 21, for example having two partial areas, as well as the well region 22 located between said two trenches. There can be multiple active cells 5 as shown in FIG. 1 or there can be only one active cell 5.

[0043] Optionally, there is a plug 24 that electrically contacts the well region 22. The plug 24 may be located below the source electrode 32 and may be electrically contacted by the source electrode 32 such that the source region 21 and the plug 24 are at the same potential. Such a plug 24 may also be present in all other exemplary embodiments.

[0044] As a further option, the semiconductor body 2 comprises an enhancement region 26 of the first conductivity type. The enhancement region 26 is on a side remote from the top surface 20 of the well region 22. For example, the enhancement region 26 extends completely between two assigned trenches as seen in cross section A-A' (see FIG. 2). The gate electrode 31 may extend deeper into the semiconductor body 2 than the enhancement region 26. The maximum doping concentration of the enhancement region 26 may exceed the maximum doping concentration of the drift region 23.

[0045] For example, the power semiconductor device 1 is an insulated-gate bipolar transistor, IGBT for short. Therefore, on the side of the drift region 23 remote from the well region 22, there is also a collector region 25 of the second conductivity type. In the collector region 25, a collector electrode 33 is present. Additionally, as a further option, there may be a buffer region of the first conductivity type between the drift region 23 and the collector region 25, which is not shown. The doping concentration of such a buffer region may be higher than the doping concentration of the drift region 23.

[0046] Alternatively, if the power semiconductor device 1 is a field effect transistor, there is a drain region 251 instead of the collector region 25 and the collector electrode 33 is replaced by a drain electrode 331. This is indicated in Figure 1 by brackets around the reference numbers 251, 331. In contrast to the collector region 25, the drain region 251 is of the first conductivity type.

[0047] In other figures, collector region 25 and collector electrode 33, or drain region 251 and drain electrode 331 are not shown, and the respective devices may be either IGBTs or field effect transistors.

[0048] In a top view of the top surface 20, the gate electrode 31 can include a plurality of stripes 51, two of which define one of the active cells 5. Between the two stripes 51 of each active cell 5 is a wiring 53 of the source electrode 32. Optionally, the wiring 53 and the plug 24 can be congruent.

[0049] In the embodiment of Figures 1 to 3, the active cells 5 are arranged as an array of stripes. In other words, the active cells 5 have a main extension direction parallel to the top surface 20 and / or parallel to each other. In another exemplary embodiment not shown, the active cells 5 may also be arranged as a cellular array. That is, the active cells 5 may be arranged in a two-dimensional grid seen in top view of the top surface 20, for example a rectangular or hexagonal grid.

[0050] Furthermore, the power semiconductor device 1 comprises an extraction electrode 34. The extraction electrode 34 may include or consist of a plurality of contacts 52 located between adjacent active cells 5 or on the side of the trench remote from the source electrode 32 if there is only one active cell 5. Furthermore, near the extraction electrode 34, the semiconductor body 2 comprises a barrier region 28 of the first conductivity type. The barrier region 28 may form a well in which the extraction electrode 34 is located. In the intended application of the power semiconductor device 1, any current to and / or from the extraction electrode 34 must therefore pass through the barrier region 28.

[0051] Alternatively, if there are multiple extraction electrodes 34 and / or multiple respective contacts 52, then only one or some of the extraction electrodes 34 and / or contacts 52 need to be provided with a barrier region 28. In other words, there may be a mixture of extraction electrodes 34 and / or respective contacts 52 provided with a barrier region 28 and extraction electrodes 34 and / or contacts 52 not provided with a barrier region. However, preferably, all of the extraction electrodes 34 and / or respective contacts 52 are provided with at least one barrier region 28.

[0052] As an option, the semiconductor body 2 comprises an extraction region 27 of the second conductivity type directly on the extraction electrode 34. The extraction electrode 34 may be in direct contact only with the extraction region 27. On the side of the extraction region 27 facing towards the outside of the extraction electrode 34, the extraction region 27 may be surrounded all around by a barrier region 28, see cross sections A-A' and B-B' shown in figures 2 and 3. The barrier region 28 may thus form a well in which the extraction region 27 is located.

[0053] As yet a further option, the semiconductor body 2 comprises a deep doped region 29 of the second conductivity type. For example, the deep doped region 29 is located along the layout line of the contact 52. The side of the barrier region 28 facing the trench with the gate electrode 31 may therefore be free of the deep doped region 29. Furthermore, the bottom surface of the barrier region 28 remote from the top surface 20 may also be free of the deep doped region 29 (see FIG. 3). In the direction parallel to the trench (see cross section B-B' in FIG. 3), the deep doped region 29 may be directly adjacent to the barrier region 28.

[0054] For example, for the maximum doping concentrations of different regions of the semiconductor body 2 the following apply individually or in any combination:

[0055] The source region 21, plug 24, deep doped region 29, collector region 25 and / or drain region 251: at least 1×1018 cm -3 Or at least 5×10 18 cm -3 Or at least 1×10 19 cm -3 and / or up to 5×10 20 cm -3 or up to 2×10 20 cm -3 or up to 1×10 20 cm -3 , The well region 22, the enhancement region 26, the extraction region 27 and / or the barrier region 28, 16 cm -3 Or at least 1×10 17 cm -3 and / or up to 5×10 19 cm -3 or up to 5×10 18 cm -3 , Depending on the voltage class of the drift region 23, the power semiconductor device 1, at least 1×10 11 cm -3 , or at least 1 × 10 12 cm -3 , or at least 1 × 10 13 cm -3 , and / or up to 1×10 17 cm -3 , or up to 5×10 16 cm -3 , or up to 1×10 16 cm -3 .

[0056] For example, the maximum doping concentration of the deep doping regions 29 is at least two times greater than the maximum doping concentration of the well regions 22. Alternatively or additionally, the maximum doping concentration of the enhancement regions 26 is at least ten times, or at least one hundred times, greater than the maximum doping concentration of the drift regions 23.

[0057] 2, where multiple active cells 5 are shown, in an alternative view, a unit cell 6 can be defined that includes two halves of a nearby active cell 5 as well as a structure that includes regions 27, 28, 29 and an extraction electrode 34. The power semiconductor device 1 may include multiple unit cells 6 arranged in an array of stripes as described above for the active cells 5.

[0058] By means of the barrier region 28, an improved trade-off can be achieved between long-term stability, particularly in terms of robustness against gate dielectric degradation, and static losses. The barrier region can therefore cooperate with the draw-out region 27 and the deep doped region 29. The function of the barrier region 28 is explained in more detail below with respect to the semiconductor device variants 10 and 11.

[0059] In Fig. 4, a first variant 10 of the power semiconductor device 1 of Figs. 1 to 3 is shown. The main difference between the devices 1, 10 is that the variant 10 does not include a barrier region. Furthermore, the first variant device 10 does not include an extraction region and does not include a separate contact for the extraction electrode. In Fig. 5, impact ionization during turn-off of the variant 10 of Fig. 4 is shown.

[0060] As an option, the enhancement region 26 and the well region 22 may be on either side of the trench. In other words, the trench, and therefore the gate electrode 31, may start at the top surface 20 and extend through the enhancement region 26 and the well region 22. A field oxide 42 separates the source electrode 32 from the semiconductor body, the source electrode 32 extending above the top surface 20. These features may also be realized individually or collectively in the power semiconductor device 1 described herein. In other aspects, the same may apply to FIG. 4 as in FIGS. 1-3 and vice versa.

[0061] For example, the long-term performance stability of IGBTs requires robustness against gate dielectric degradation. Gate dielectric degradation can be caused by dynamic avalanche during turn-off switching events at high currents; the charge carriers generated by dynamic avalanche may have enough energy to be injected into the gate dielectric, modifying the switching characteristics of the device, such as gate capacitance and therefore switching speed, and can cause threshold voltage instability. Degradation is a design challenge for trench IGBTs due to the peak P of avalanche generation near the gate dielectric at the bottom of the trench (see Figure 5).

[0062] Figure 6 shows the current-voltage curves during turn-off of the IGBT of Figure 4 configured for a voltage of 3.3 kV, and Figure 7 shows the integral avalanche generation Aint and the maximum avalanche generation Amax during turn-off. It can thus be seen that significant avalanche generation occurs during turn-off.

[0063] A way to improve the robustness of IGBTs against gate oxide degradation is to reduce the anode dose. However, reducing the anode dose also has a detrimental effect on static losses and short circuit safe operating area (SOA) capabilities. Another solution is to implement protective structures such as deep doping regions 29, like deep p-wells, and / or to form dummy trenches, as shown in Figure 4. In this way, dynamic avalanche generation near the active trenches can be reduced, but not in a sufficient manner to guarantee long-term stability for highly demanding applications with harsh switching conditions at high frequencies.

[0064] A more effective approach to reducing degradation is to include an additional electrical contact at a distance from the active cell 5, such as an extraction electrode 34. The additional contact is biased in a way that it can extract a portion of the plasma during turn-off, effectively diverting carriers away from the active trench, thus reducing avalanche generation near the gate oxide. For example, an emitter bias contact connected directly to the p-well diverts a significant amount of current from the backside while starving the plasma during turn-off.

[0065] However, directly connecting the deep doped region 29 with the emitter contact 34 would be an impractical solution since it would significantly increase static losses. This undesirable effect is due to the fact that the additional contact provides an additional extraction point for the charge carriers, reducing the plasma density and therefore the conductivity for the same applied collector-emitter voltage.

[0066] The power semiconductor device 1 described herein allows for an improved trade-off between long-term performance stability, i.e. robustness against gate oxide degradation, and static losses. Unlike other solutions, the additional extraction contact 34 is effectively shielded by the barrier region 28, thereby reducing the detrimental effect of the contact 34 on the on-state, while maintaining the advantages of reduced turn-off losses and improved robustness against gate oxide degradation.

[0067] With the power semiconductor device 1 described herein, e.g. a 3.3 kV trench IGBT, improved robustness against degradation with limited increase in static losses can be achieved compared to alternative solutions. The power semiconductor device 1 can be processed without active engineering development, for example, since the only modification required is a modified layout of the mask used in the photolithography process performed to form the contacts on the top surface.

[0068] 8 and 9 show the results of repeated reverse bias safe operation area (RBSOA) tests to compare the robustness and degradation of the power semiconductor device 1 described herein in relation to FIG. 1 (see FIG. 8 ) and a variant design 10 similar to that described in FIG. 4 without the barrier region (see FIG. 9 ).

[0069] In Figures 8 and 9, the increase in maximum current overshoot during turn-on is measured every 1000 turn-off pulses i up to 100k pulses. In both Figures 8 and 9, the experiments were repeated at increasingly severe turn-off conditions up to 1.39 times the nominal voltage U of 2.5 kV and up to 2.25 times the nominal current C of 337.5 A. The upper and lower limits of the C axis are offset by ±10% from the initial maximum current overshoot.

[0070] The power semiconductor device 1 described herein shows no signs of degradation even under the harshest test conditions, while the device 10 is more susceptible to degradation with increasing turn-off voltage. The results in Figures 8 and 9 demonstrate that the barrier region 28 does not limit the effectiveness of the extraction electrode 34 in terms of robustness against degradation.

[0071] 10 shows a probability plot of the on-state voltage VCEsat at room temperature for three device splits processed in parallel in the same lot. The power semiconductor device 1 described herein has an improvement in VCEsat of about 200 mV compared to a second variant device 11 in which the extraction contact is not completely surrounded by the barrier region. For reference, the first variant device 10 without the extraction contact, which is subject to degradation, is also included in the analysis.

[0072] Thus, the presence of the barrier region 28 completely surrounding the extraction electrode 34 makes it possible to obtain a significant reduction in VCEsat relative to the device 11 in which the extraction layer is directly connected to the deep p-well. The power semiconductor device 1 described herein still has higher static losses than the device 10 without the additional extraction contact, but to a lesser extent.

[0073] In Figure 11, a device 10 without an extraction contact similar to that of Figure 4 is compared with a device 11 in which the extraction contact is not completely surrounded by a barrier region, both devices 10 and 11 being configured as 6.5 kV trench IGBTs. In the presence of the additional extraction electrode 34, a higher voltage VCEsat is required to obtain the plasma density necessary to reach the nominal on-state current. On the other hand, the turn-off losses Eoff are reduced.

[0074] The power semiconductor device 1 described herein has lower switching losses than device 10 without a lead contact, but slightly higher switching losses than device 11. Thus, the power semiconductor device 1 described herein effectively moves within the region of the technology curve optimized for high frequency applications without the need to reduce anode injection efficiency at potentially reduced short circuit capability.

[0075] For comparison, Figure 12 shows the emitter side of the trench IGBT variant 11 referenced above. An emitter bias contact 34 is connected directly to the deep doped regions 29 between the active cells 5. This additional contact 34 can be thought of as a hole extraction contact. This helps to increase robustness against degradation, but has a strong detrimental effect on static losses.

[0076] In figure 13 another example of a power semiconductor device 1 is shown in which there is no trench gate electrode but a gate electrode 31 is applied to the top surface 20. The power semiconductor device 1 of figure 13 is therefore of planar design.

[0077] 13, it can be seen that the optional enhancement region 26 and the barrier region 28 can have the same doping profile. This can be achieved by producing the enhancement region 26 and the barrier region 28 in the same method step. The same is true for the well region 22 and the optional draw-out region 27. Furthermore, as an option, there need not be any deep doping regions.

[0078] In other aspects, what is true for Figures 1-12 may also be true for Figure 13, and vice versa.

[0079] The cross sections of Figures 14 and 15 correspond to the representation of Figure 3. In Figure 14 it is shown that the drift region 23 can extend between the deep doping region 29 and the barrier region 28. According to Figure 15 there is no extraction region and the barrier region 28 is in direct contact with the extraction electrode 34.

[0080] In other aspects, what is true for Figures 1-13 may also be true for Figures 14 and 15, and vice versa.

[0081] In Fig. 16 a top view of an exemplary embodiment of the power semiconductor device 1 is shown. It can be seen that the extraction electrode 34 is formed by a number of contacts 52. The contacts 52 can be relatively small, for example having a size of up to 4 μm x 4 μm or up to 2 μm x 2 μm. The contacts 52 are arranged along a straight line, which is a mirror symmetry axis with respect to adjacent active cells 5, in a top view of the top surface 20. For example, the contacts 52 occupy up to 5% of the straight line.

[0082] In other aspects, what is true for Figures 1-15 may also be true for Figure 16, and vice versa.

[0083] 17 shows a block diagram of a method for producing a power semiconductor device 1. In method step S1 a semiconductor body 2 is provided. For example, in method step S1 the semiconductor body 2 comprises a drift region 23 of a first conductivity type.

[0084] According to a subsequent method step S2, an enhancement region 26 of a first conductivity type and a barrier region 28 are formed. For example, the enhancement region 26 and the barrier region 28 are created simultaneously.

[0085] In method step S3, the well region 22 of the second conductivity type and the leading region 27 are then created. The well region 22 and the leading region 27 may also be created simultaneously.

[0086] Then, in method step S4, a source region 21 of the first conductivity type is formed, followed by method step S5 in which a gate electrode 31 is applied to the well region 22 and an extraction electrode 34 is applied to the extraction region 27 and / or the barrier region 28.

[0087] 17, method step S3 follows method step S2, but alternatively method step S2 could follow method step S3. Furthermore, method step S4 may be performed before method steps S2 and / or S3.

[0088] In other aspects, what is true for Figures 1-16 may also be true for Figure 17, and vice versa.

[0089] Components shown in the figures illustratively follow a designated order of direct overlap, unless otherwise indicated. Components that are not in contact in the figures are illustratively spaced apart from one another. Where lines are drawn parallel to one another, corresponding surfaces may be oriented parallel to one another. Similarly, unless otherwise indicated, the positions of the drawn components relative to one another are accurately reproduced in the figures.

[0090] The term "and / or" describes only a relational relationship for describing related objects and indicates that three relations may exist. For example, A and / or B may describe three cases: only A is present, both A and B are present, and only B is present. The same applies when there are more than three entities.

[0091] The power semiconductor device described herein is not limited to the description based on the exemplary embodiments, but rather includes any novel feature and any combination of features, including any combination of features in the claims, even if this feature or this combination itself is not explicitly specified in the claims or exemplary embodiments.

[0092] This application claims priority to European Patent Application No. 21216358.8, the disclosure of which is incorporated herein by reference. [Explanation of symbols]

[0093] List of References 1. Power Semiconductor Devices 2 Semiconductor body 20 Top side 21 Source Area 22 Well Area 23 Drift Region 24 Plug 25 Collector Region 251 Drain Region 26 Enhancement Area 27 Drawer Area 28 Barrier Region 29 Deep doping region 31 Gate electrode 32 Source electrode 33 Collector electrode 331 Drain electrode 34 Extraction electrode 35 Drain electrode 4 Gate insulating film 42 Field oxide 5 Active Cells 51 Gate electrode stripe 52 Extraction electrode contact 53 Source electrode wiring 6. Unit Cell 10 First Modification of Power Semiconductor Device 11 Second variant of power semiconductor device Aint cm -2 s -1 Unit integral avalanche generation Amax cm -3 s -1 Maximum avalanche generation of units Current in CA Eoff Energy loss during turn-off in J i Pulse count in 1000 units I impact ionization cm -3 s -1 n cm -3 Doping concentration in units P avalanche peak S. Method steps T time in seconds Voltage in UV X,Y abscissa and height coordinate in μm

Claims

1. A power semiconductor device (1) comprising a semiconductor body (2), a gate electrode (31), a source electrode (32) and an extraction electrode (34), the gate electrode (31) being separated from the semiconductor body (2) by an electrically insulating gate insulating film; The semiconductor body (2) a source region (21) of a first conductivity type directly on the source electrode (32) and directly on the gate insulating film; a well region (22) of a second conductivity type different from the first conductivity type, directly on the gate insulating film and directly on the source region (21); a drift region (23) of the first conductivity type electrically connected to the well region (22) on a side remote from the source region (21) and directly on the gate insulating film; an extraction region (27) of the second conductivity type directly on the extraction electrode (34); a barrier region (28) of the first conductivity type assigned to the extraction electrode (34), the barrier region (28) being located directly between the drift region (23) and the extraction electrode (34), such that the extraction region (27) is located between the barrier region (28) and the extraction electrode (34) and is entirely surrounded by the barrier region (28) to form a well in which the extraction region (27) is located, and the barrier region (28) is spaced apart from the gate insulating film; Equipped with A power semiconductor device (1), wherein the well region (22) and the extraction region (27) have the same maximum doping concentration and / or the same doping depth profile.

2. The semiconductor body (2) further comprises a deep doped region (29) of the second conductivity type, the deep doped region (29) being located between the barrier region (28) and at least a portion of the drift region (23); 10. The power semiconductor device (1) according to the preceding claim, wherein a depth of the deep doped region (29) into the semiconductor body (2) exceeds a depth of the well region (22).

3. the deep doped region (29) is directly on at least some sides of the barrier region (28); 10. The power semiconductor device (1) according to the preceding claim, wherein the maximum doping concentration of the deep doped region (29) exceeds the maximum doping concentration of the well region (22) by a factor of at least two.

4. 4. The power semiconductor device (1) according to claim 2 or 3, wherein a bottom surface of the barrier region (28) is at least partially free of the deep doped region (29).

5. The semiconductor body (2) further comprises an enhancement region (26) of the first conductivity type, the enhancement region (26) is located directly on a bottom surface of the well region (22) such that the enhancement region (26) is located between the drift region (23) and the well region (22); 10. The power semiconductor device (1) according to any one of the preceding claims, wherein the maximum doping concentration of the boost region (26) exceeds the maximum doping concentration of the drift region (23) by a factor of at least two.

6. The gate electrode (31) is contained within a trench; 10. The power semiconductor device (1) according to any one of the preceding claims, wherein the gate electrode (31) extends deeper into the semiconductor body (2) than the well region (22).

7. 3. The power semiconductor device (1) according to claim 2 and the preceding claims, wherein the deep doped region (29) extends into the semiconductor body (2) at least as far as the gate electrode (31).

8. In a top view of the semiconductor body (2), the gate electrode (34) includes 2N stripes (51), where N is a natural number equal to or greater than 1; 10. The power semiconductor device (1) according to any one of the preceding claims, wherein the 2N stripes (51) define N active cells (5) of the power semiconductor device (1).

9. The source electrode (32) includes N wirings, 13. The power semiconductor device (1) according to claim 12, wherein, in a top view of the semiconductor body (2), each of the N wirings is assigned to one of the N active cells (5) and is located between two of the stripes (51) of each of the gate electrodes (31).

10. N is a natural number greater than or equal to 2, The extraction electrode (34) has a plurality of contacts (52); 10. The power semiconductor device (1) according to claim 8 or 9, wherein, in a top view of the semiconductor body (2), the contacts (52) are in each case arranged between two adjacent active cells (5).

11. In a top view of the semiconductor body (2), the contacts (52) are arranged along a straight line, The tangent point (52) occupies a maximum of 5% of the straight line; 2. The power semiconductor device (1) according to the preceding claim, wherein the length of each of said linear contacts (52) is at most 50% of the distance between adjacent active cells (5).

12. The semiconductor body (2) further comprises a plug (24) of the second conductivity type, The plug (24) is configured to be in electrical contact with the well region (22); 2. The power semiconductor device (1) according to any one of the preceding claims, wherein the source region (21), the plug (24) and the extraction electrode (31) are configured to have the same potential.

13. The power semiconductor device (1) according to any one of the preceding claims, wherein the power semiconductor device (1) is an insulated-gate bipolar transistor (IGBT), and the IGBT is configured such that a voltage between a drain electrode and an emitter electrode of the IGBT is at least 0.65 kV.

14. A method for producing a power semiconductor device (1) according to at least claim 5, comprising the steps of: providing the semiconductor body (2) having the drift region (23) of the first conductivity type; simultaneously forming the enhancement region (26) and the barrier region (28) of the first conductivity type; Simultaneously forming the well region (22) and the lead-out region (27) of the second conductivity type different from the first conductivity type; creating a source region (21) of said first conductivity type; applying the source electrode (32) to the source region (21), the gate electrode (31) to the well region (22) and an extraction electrode (34) to the extraction region (27), the barrier region (28) being located directly between the drift region (23) and the extraction electrode (34); A method comprising:

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