Semiconductor device having shielding element

Abstract

A semiconductor device is provided. For example, the semiconductor device may include a plurality of transistors arranged in an array in an XY plane. Each of the transistors may include a channel extending in a Z direction. The semiconductor device may further include a plurality of word lines. Each of the word lines may electrically connect adjacent ones of the transistors arranged in a column in the X direction at sidewalls of their channels. The semiconductor device may further include one or more electromagnetic shielding elements. At least one of the electromagnetic shielding elements may be placed between adjacent two of the transistors placed in a row in the Y direction.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to Chinese Patent Application No. 2022101083896, filed on January 28, 2022, which is incorporated herein by reference in its entirety.

[0002] The present disclosure relates to semiconductor memories, and more particularly, to semiconductor devices having shielding elements. [Background technology]

[0003] As the critical dimensions of devices in integrated circuits shrink to the limits of conventional memory cell technology, designers have turned to techniques for stacking multiple planes of memory cells to achieve higher storage capacities and lower cost per bit. 3D NAND memory devices are exemplary devices that stack multiple planes of memory cells to achieve higher storage capacities and lower cost per bit. 3D NAND memory devices may include alternating stacks of insulating layers and word line layers over a substrate and slit structure. Summary of the Invention [Means for solving the problem]

[0004] Aspects of the present disclosure provide a method for manufacturing a semiconductor device. For example, the method may include forming a plurality of transistors arranged in an array in an XY plane. Each of the transistors may include a channel extending in a Z direction. The method may further include forming a plurality of word lines. Each of the word lines may electrically connect adjacent ones of the transistors at sidewalls of their channels. Adjacent ones of the transistors may be arranged in columns in the X direction. The method may further include forming one or more electromagnetic shielding elements. Each of the electromagnetic shielding elements may be placed between adjacent two of the transistors placed in a row in the Y direction.

[0005] In an embodiment, each of the transistors may further include a source located at a first end of the channel and a drain located at a second end of the channel, and the electromagnetic shielding element may have a Y-direction projection onto the channel that does not overlap with the source and drain. In another embodiment, the electromagnetic shielding element may be shorter in the Z direction than the channels of two adjacent transistors. In some embodiments, the electromagnetic shielding element may further be located between adjacent two of the transistors located in the column.

[0006] In an embodiment, each of the transistor channels may be rectangular pillar shaped, and each of the wordlines may be formed on a sidewall of a corresponding one of the rectangular pillar channels, for example, the sidewalls of the rectangular pillar channels of two adjacent transistors on which the wordlines are formed may face in opposite directions.

[0007] In an embodiment, the method may further include forming an electromagnetic shielding contact pad connected to one of the electromagnetic shielding elements and forming a word line contact pad connected to one of the word lines adjacent to the electromagnetic shielding element. The electromagnetic shielding contact pad and the word line contact pad may be located on opposite sides of the array in the X-direction. In an embodiment, the electromagnetic shielding element and the word line may be formed by forming a first trench in which the contact pad is formed on a backside of the semiconductor device in a substrate of the semiconductor device, filling the first trench with an oxide, forming a second trench and a third trench in which the word line and the electromagnetic shielding element are respectively formed in the substrate, the third trench being in contact with the first trench, filling the second trench with a first conductor to form the word line, thinning the backside of the semiconductor device to expose the oxide filled in the first trench, recessing the oxide to expose a sidewall of the third trench, and filling the third trench and the first trench with a second conductor to form the electromagnetic shielding element and the contact pad, respectively.

[0008] Aspects of the present disclosure also provide a semiconductor device. For example, the semiconductor device may include a plurality of transistors arranged in an array in an XY plane. Each of the transistors may include a channel extending in a Z direction. The semiconductor device may further include a plurality of word lines. Each of the word lines may electrically connect adjacent ones of the transistors arranged in a column in the X direction at sidewalls of their channels. The semiconductor device may further include one or more electromagnetic shielding elements. Each of the electromagnetic shielding elements may be placed between adjacent two of the transistors placed in a row in the Y direction.

[0009] In an embodiment, each of the transistors may further include a source located at a first end of the channel and a drain located at a second end of the channel, and the electromagnetic shielding element may have a protrusion in the Y direction onto the channel that does not overlap with the source and drain. In another embodiment, the electromagnetic shielding element may be shorter in the Z direction than the channels of two adjacent transistors. In some embodiments, the electromagnetic shielding element may further be located between adjacent two of the transistors located in the column.

[0010] In an embodiment, each of the transistor channels may be rectangular pillar shaped, and each of the wordlines may be formed on a sidewall of a corresponding one of the rectangular pillar channels, for example, the sidewalls of the rectangular pillar channels of two adjacent transistors on which the wordlines are formed may face in opposite directions.

[0011] In an embodiment, the semiconductor device may further include an electromagnetic shielding contact pad connected to one of the electromagnetic shielding elements and a word line contact pad connected to one of the word lines adjacent to the electromagnetic shielding element. The electromagnetic shielding contact pad and the word line contact pad may be located on opposite sides of the array in the X-direction.

[0012] In an embodiment, at least one of the electromagnetic shielding elements may include a plurality of electromagnetic shielding segments spaced apart from one another, for example, the electromagnetic shielding segments may be arranged along the X-direction, the Y-direction, and / or the Z-direction.

[0013] In embodiments, at least one of the electromagnetic shielding elements may be energized with a first voltage that is lower than a second voltage applied to a corresponding one of the channels. In some embodiments, at least one of the electromagnetic shielding elements may be energized such that a first transistor of two adjacent transistors between which the electromagnetic shielding element is interposed is affected less by a combination of a first electromagnetic field generated by the electromagnetic shielding element and a second electromagnetic field generated by a second transistor of the two adjacent transistors than it is affected by a second electromagnetic field.

[0014] Aspects of the present disclosure further provide a memory system. For example, the memory system may include a semiconductor device and a control circuit coupled to the semiconductor device. The control circuit may be configured to control the operation of the semiconductor device. The semiconductor device may include a plurality of transistors arranged in an array in an XY plane. Each of the transistors may include a channel extending in a Z direction. The semiconductor device may further include a plurality of word lines. Each of the word lines may electrically connect adjacent ones of the transistors arranged in a column in the X direction at sidewalls of their channels. The semiconductor device may further include one or more electromagnetic shielding elements. Each of the electromagnetic shielding elements may be placed between adjacent two of the transistors placed in a row in the Y direction.

[0015] Aspects of the present disclosure can be understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features have not been drawn to scale. In fact, dimensions of various features may be increased or decreased for clarity of discussion. [Brief description of the drawings]

[0016] [Figure 1A] FIG. 1 is a schematic diagram of a planar transistor. [Figure 1B] FIG. 1 is a schematic diagram of a buried channel transistor. [Diagram 2] 1 is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure. [Diagram 3] 1 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. [Figure 4] 1 is a flow diagram of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. [Figure 4A] 1A-1D are top views illustrating the formation of a pillar channel in a semiconductor device according to some embodiments of the present disclosure. [Figure 4B] 1A-1C are schematic diagrams illustrating the formation of a pillar channel in a semiconductor device according to some embodiments of the present disclosure. [Figure 4C] 1A-1D are top views illustrating the formation of an insulating layer of a semiconductor device according to some embodiments of the present disclosure. [Figure 4D] 4A-4C are top views illustrating the formation of second and third grooves in a semiconductor device according to some embodiments of the present disclosure. [Figure 4E] 1A-1D are top views illustrating the formation of a gate oxide layer of a semiconductor device according to some embodiments of the present disclosure. [Figure 4F] 1 is a top view illustrating formation of electromagnetic shielding elements and word lines of a semiconductor device according to some embodiments of the present disclosure. [Diagram 5] 1 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. [Figure 6A] 1A-1D are top views illustrating the formation of a pillar channel in a semiconductor device according to some embodiments of the present disclosure. [Figure 6B] 1A-1D are top views illustrating the formation of an insulating layer of a semiconductor device according to some embodiments of the present disclosure. [Figure 6C] 4A-4C are top views illustrating the formation of second and third grooves in a semiconductor device according to some embodiments of the present disclosure. [Figure 6D] 1A-1D are top views illustrating the formation of a gate oxide layer of a semiconductor device according to some embodiments of the present disclosure. [Figure 6E] 1A-1C are top views illustrating the formation of metal layers and gates of a semiconductor device according to some embodiments of the present disclosure. [Figure 7]1 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. [Figure 8] 1A-1D are top views illustrating the formation of contact pads on a semiconductor device according to some embodiments of the present disclosure. [Figure 9] 4A-4D are top views illustrating the formation of another contact pad on a semiconductor device according to some embodiments of the present disclosure. [Figure 9A] 11A-11C are top views illustrating the formation of yet another contact pad on a semiconductor device according to some embodiments of the present disclosure. [Figure 10A] 1 is a cross-sectional view of a semiconductor device having an electromagnetic shielding element in a configuration according to some embodiments of the present disclosure. [Figure 10B] 1 is a cross-sectional view of a semiconductor device having an electromagnetic shielding element in a configuration according to some embodiments of the present disclosure. [Figure 10C] 1 is a cross-sectional view of a semiconductor device having an electromagnetic shielding element in a configuration according to some embodiments of the present disclosure. [Figure 10D] 1 is a cross-sectional view of a semiconductor device having an electromagnetic shielding element in a configuration according to some embodiments of the present disclosure. [Figure 10E] 1 is a cross-sectional view of a semiconductor device having an electromagnetic shielding element in a configuration according to some embodiments of the present disclosure. [Figure 10F] 1 is a cross-sectional view of a semiconductor device having an electromagnetic shielding element in a configuration according to some embodiments of the present disclosure. [Figure 10G] 1 is a cross-sectional view of a semiconductor device having an electromagnetic shielding element in a configuration according to some embodiments of the present disclosure. [Figure 10H] 1 is a cross-sectional view of a semiconductor device having an electromagnetic shielding element in a configuration according to some embodiments of the present disclosure. [Figure 11A] 1 is a cross-sectional view of a semiconductor device having an electromagnetic shielding element in a configuration according to some embodiments of the present disclosure. [Figure 11B] 1 is a cross-sectional view of a semiconductor device having an electromagnetic shielding element in a configuration according to some embodiments of the present disclosure. [Figure 11C] 1 is a cross-sectional view of a semiconductor device having an electromagnetic shielding element in a configuration according to some embodiments of the present disclosure. [Figure 11D] 1 is a cross-sectional view of a semiconductor device having an electromagnetic shielding element in a configuration according to some embodiments of the present disclosure. [Figure 11E] 1 is a cross-sectional view of a semiconductor device having an electromagnetic shielding element in a configuration according to some embodiments of the present disclosure. [Figure 12A] 1A-1D are cross-sectional views illustrating the fabrication of a semiconductor device according to some embodiments of the present disclosure. [Figure 12B] 1A-1D are cross-sectional views illustrating the fabrication of a semiconductor device according to some embodiments of the present disclosure. [Figure 12C] 1A-1D are cross-sectional views illustrating the fabrication of a semiconductor device according to some embodiments of the present disclosure. [Figure 13] FIG. 1 is a block diagram of a memory system according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first feature and the second feature may be in direct contact, and may also include embodiments in which an additional feature may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Furthermore, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0018] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure can also be employed in a variety of other applications.

[0019] It should be noted that references herein to "one embodiment," "embodiment," "exemplary embodiment," "some embodiments," and the like, indicate that the embodiment being described may include a particular feature, structure, or characteristic, but not every embodiment may necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it will be within the knowledge of one of ordinary skill in the art to affect such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described.

[0020] Generally, terms can be understood at least in part from the usage in the context. For example, the term "one or more" used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense, at least in part depending on the context. Similarly, terms such as "a", "an", or "the" can also be understood to convey a singular usage or a plural usage, at least in part depending on the context. In addition, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, and instead may allow for the existence of additional factors not necessarily explicitly described, also at least in part depending on the context.

[0021] It should be readily understood that the meanings of "on," "above," and "over" in this disclosure should be interpreted in the broadest manner such that "on" not only means "directly on" something, but also includes the meaning "on" something with an intermediate feature or layer between them. Furthermore, "above" or "over" can not only mean "above" or "over" something, but can also include the meaning that it is "above" or "over" something (i.e., directly on top of something) without an intermediate feature or layer between them.

[0022] Additionally, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature shown in the figures for ease of description. The spatially relative terms are intended to encompass different orientations of the device in use or during a process step in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0023] As used herein, the term "substrate" refers to a material onto which subsequent layers of material are added. The substrate includes a "top" and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, and thus, unless otherwise noted, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite the top surface, and thus the bottom side of the substrate is opposite the top side of the substrate. The substrate itself may be patterned. Materials added on top of the substrate may be patterned or may remain unpatterned. Additionally, the substrate may include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of an electrically non-conductive material, such as glass, plastic, or a sapphire wafer.

[0024] As used herein, the term "layer" refers to a portion of a material that includes a region with a thickness. A layer has an upper side and a lower side, the lower side of the layer being relatively close to the substrate and the upper side being relatively far from the substrate. A layer can extend throughout an underlying or overlying structure, or can have an extent that is less than the extent of the underlying or overlying structure. Additionally, a layer can be a region of a homogeneous or non-homogeneous continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be located between the upper and lower surfaces of a continuous structure, or between any set of horizontal surfaces of the upper and lower surfaces. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer and can include one or more layers therein and / or have one or more layers on, above, and / or below it. A layer can include multiple layers. For example, the interconnect layer may include one or more conductive layers and contact layers in which the contacts, interconnect lines, and / or vertical interconnect accesses (VIAs) are formed, and one or more dielectric layers.

[0025] As used herein, the term "nominal / nominally" refers to a desired or target value of a characteristic or parameter of a component or process step, set during the design phase of a product or process, along with a range of values ​​above and / or below the desired value. As used herein, the range of values ​​may be due to slight variations in the manufacturing process or tolerances. As used herein, the term "about" refers to a value of a given quantity that may vary based on a particular technology node associated with the semiconductor device of interest. Based on a particular technology node, the term "about" may refer to a value of a given quantity that varies, for example, within 10-30% of the value (e.g., +-10%, +-20%, or +-30% of the value).

[0026] In this disclosure, the term "horizontal / horizontally / lateral / laterally" means nominally parallel to a side of a substrate, and the term "vertical" or "vertically" means nominally perpendicular to a side of a substrate.

[0027] As used herein, the term "3D memory" refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings", such as NAND strings) on a laterally oriented substrate, such that the memory strings extend perpendicular to the substrate.

[0028] In the related art, the array transistors of mainstream memory include planar array transistors and buried channel array transistors (BCATs). FIG. 1A and FIG. 1B are schematic diagrams showing planar array transistors 100A and BCATs 100B, respectively. As shown in FIG. 1A, the transistor of the planar array transistor 100A includes a gate G and a source S( / D) and a drain D( / S) formed on two substantially horizontal sides of the gate G. As shown in FIG. 1B, the transistor of the BCAT 100B includes a gate G and a source S( / D) and a drain D( / S) also formed on two substantially horizontal sides of the gate G. Since the source S( / D) and the drain D( / S) occupy positions that do not overlap with the gate G, the planar array transistors 100A and BCATs 100B have large areas, respectively.

[0029] In the planar array transistor 100A and BCAT 100B, the source S ( / D) and the drain D ( / S) are placed on two substantially horizontal sides of the gate G, so the bit line (BL) and the capacitor of the memory must be placed on the same side as the gate G. In the subsequent process, the BL, the transistor and the capacitor must be connected to each other, and the transistor must be further connected to the word line (WL). Therefore, the planar array transistor 100A and BCAT 100B respectively have complicated circuit layouts and are difficult to manufacture.

[0030] Only one transistor is shown in the planar array transistor 100A of Figure 1A and the BCAT 100B of Figure 1B. According to this disclosure, the planar array transistor 100A and the BCAT 100B may include any number of transistors.

[0031] Aspects of the present disclosure provide a semiconductor device. See FIG. 2, which is a schematic diagram of a semiconductor device 200 according to some embodiments of the present disclosure. The semiconductor device 200 may include a plurality of transistors 210 arranged in an array in an XY plane. For example, the array may include a plurality of rows arranged along a first direction, e.g., the X direction, and a plurality of columns intersecting the rows and arranged along a second direction, e.g., the Y direction. Each of the transistors 210 may include a channel 211, and the channels 211 of the transistors 210 are arranged along the first direction and the second direction in the array. In an embodiment, each of the channels 211 may be in the shape of a pillar and may extend along a third direction, e.g., the Z direction, perpendicular to the plane defined by the first direction and the second direction. For example, the pillar may have a cross section in the shape of a rectangle, a circle, a diamond, or any other polygon. In an embodiment, each pillar channel 211 in a column of the array may have an oxide layer 215 and a word line 214 formed on its sidewall in sequence, both of which extend along a first direction, e.g., the X-direction, and the pillar channels 211 may thus be connected to each other by the word line 214. In an embodiment, a source 212 and a drain 213 may be formed at two ends of each of the pillar channels 211, respectively. In some embodiments, the source 212 and the drain 213 are interchangeable. Because the sources 212 and drains 213 are formed at the two ends of each of the pillar-shaped channels 211 rather than on the two sides of each of the word lines (i.e., gates) 214, the semiconductor device 200 has a greater transistor density as compared to semiconductor devices including the planar semiconductor device 100A or BCAT 100B, each of which includes transistors having sources and drains, respectively, formed on substantially horizontal sides of a gate, as shown in FIGS. 1A and 1B.

[0032] In a semiconductor device 200 in which each of the word lines 214 is formed on only one sidewall of a corresponding one of the pillar channels 211, any one of the pillar channels 211, e.g., rectangular pillar channel 211', coupled to an unselected word line 214, e.g., word line 214', adjacent to a selected word line, e.g., word line 214'', is affected by the selected word line 214''. For example, activity of the adjacent selected word line 214'' may alter the charge stored in a transistor including a channel 211' connected to the unselected word line 214', and information stored in the transistor may be affected by the so-called Row Hammer effect.

[0033] Please refer to Fig. 3, which is a cross-sectional view of the semiconductor device 200 of Fig. 2 along the cutting line BB'. When a selected word line WL1 connected to the rectangular pillar channel CH1 is activated, another rectangular pillar channel CH2 adjacent to the pillar channel CH1 will be interfered with, and as a result, the performance of the semiconductor device 200 will be affected. Therefore, further improvement of the semiconductor device 200 is needed.

[0034] An aspect of the present disclosure provides a method for manufacturing a semiconductor device. Figure 4 is a flow diagram of a method 400 for manufacturing a semiconductor device, such as the semiconductor device 400A shown in Figures 4A to 4F or the semiconductor device 500 shown in Figure 5, according to some embodiments of the present disclosure. The method 400 may include steps S410 to S440.

[0035] In step S410, a plurality of transistors, e.g., transistors of semiconductor device 400A, are formed on a surface of a wafer, e.g., wafer 409 shown in FIG. 4A. In an embodiment, the transistors can be arranged in an array, and the array can include a plurality of rows arranged along a first direction, e.g., X-direction, parallel to the surface of wafer 409, and a plurality of columns arranged along a second direction, e.g., Y-direction, intersecting the rows and parallel to the surface of wafer 409. For example, the first direction and the second direction can include an included angle of 90 degrees or less. Each of the transistors can include a channel, e.g., channel 401 shown in FIG. 4A, extending in a first direction, a second direction, and a third direction, e.g., Z-direction, perpendicular to the surface of wafer 409. In some embodiments, at least one of the channels 401 can be in the shape of a pillar. In an embodiment, the pillar can have a cross section in the shape of a rectangle, a rhombus, a circle, or any other polygon. For example, the columnar channel 401 can extend in a plane defined by the first direction and the second direction, eg, in a third direction perpendicular to the surface of the wafer 409 .

[0036] In step S420, a plurality of word lines, for example, the word lines 407 shown in FIG. 4F, are formed on the sidewalls of the pillar-shaped channels 401 of the transistors. In an embodiment, each of the word lines 407 may be adjacent to each other and electrically connect one or more of the transistors arranged in a row in a first direction, for example, the X-direction, at their sidewalls. In an embodiment, the word lines 407 each extend along the X-direction, are parallel to the X-direction, and are arranged along the Y-direction.

[0037] In step S430, an electromagnetic shielding element, for example the electromagnetic shielding element 408 shown in FIG. 4F, is formed between at least two adjacent ones of the pillar-shaped channels 401 of the transistors arranged in a row in the Y direction. In an embodiment, the electromagnetic shielding element 408 can extend along the X direction.

[0038] In step S440, a source and a drain, for example, source 504 and drain 503 shown in FIG. 5, are formed at two ends of each of the transistor's pillar-shaped channels 401. In some embodiments, the electromagnetic shielding element 508 has a protrusion in the Y direction onto the channel 211 that does not overlap with the source 212 and drain 213.

[0039] In an embodiment, the wafer 409 can be a single crystal silicon material, such as a single crystal silicon ingot, used in the manufacture of the semiconductor device 400A. For example, a single crystal silicon ingot in the shape of a cylinder can be ground, polished, and diced to form a number of round silicon plates, i.e., wafers. In another embodiment, the wafer 409 can have two opposing round surfaces, one of which is the aforementioned surface of the wafer 409, and the other of which can be referred to as the backside of the wafer 409, according to some embodiments of the present disclosure.

[0040] 4A-4F illustrate the fabrication of an intermediate stage semiconductor device according to some embodiments of the present disclosure, such as semiconductor device 400A, in which wordlines are formed on the sidewalls of any two adjacent transistors (or channels) facing in different directions.

[0041] FIG. 4A is a top view of a semiconductor device 400A illustrating the formation of channels of transistors of the semiconductor device 400A according to some embodiments of the present disclosure. As shown in FIG. 4A, a plurality of channels 401 arranged in an array in, for example, an XY plane are formed on a surface of a wafer 409. For example, the array may include a plurality of rows arranged along a first direction, for example, an X direction, and a plurality of columns intersecting the rows and arranged along a second direction, for example, a Y direction. In an embodiment, each of the channels 401 may be in the shape of a pillar, for example, a rectangular pillar, and each of the rectangular pillar-shaped channels 401 may extend along a third direction, for example, a Z direction, that is perpendicular to the plane defined by the first direction and the second direction, as shown in FIG. 4B, which is a schematic diagram illustrating the formation of the pillar-shaped channels 401 of the semiconductor device 400A according to some embodiments of the present disclosure.

[0042] In some embodiments, the pillared channels 401 may be formed on a surface of the wafer 409 by covering the wafer 409 with a mask (not shown) that covers a particular area of ​​the wafer 409 that will be used to form the pillared channels 401, etching the wafer 409 to a particular depth less than the thickness of the wafer 409 to form the first grooves 402, and removing the mask to form the pillared channels 401 with their sidewalls exposed. In some embodiments, the wafer 409 may be etched by using photolithography (PH) or dry etching (ET), such as electron beam lithography, plasma etching, and reactive ion etching (RIE).

[0043] 4C is a top view illustrating the formation of an insulating layer of the semiconductor device 400A according to some embodiments of the present disclosure. In some embodiments, an insulating material, such as SiO2, may be deposited in the first trench 402 to form an insulating layer 403 that covers the sidewalls of the first trench 402 and the columnar channel 401. In some embodiments, chemical mechanical polishing (CMP) may then be employed to polish and remove the remaining insulating material to expose the top surface of the columnar channel 401.

[0044] FIG. 4D is a top view illustrating the formation of the second and third grooves of the semiconductor device 400A according to some embodiments of the present disclosure. In an embodiment, the insulating layer 403 may be etched to form the second groove 404 exposing one of the sidewalls of each of the pillar-shaped channels 401, e.g., the rectangular pillar-shaped channels 401, and the third groove 405, each of which is located between two adjacent transistors in a row in the Y direction (i.e., two adjacent rectangular pillar-shaped channels 401). In some embodiments, each of the second grooves 404 exposes the sidewalls of the pillar-shaped channels 401 of the transistors adjacent to each other and arranged in a column in the X direction. In an embodiment, the sidewalls of the two adjacent rectangular pillar-shaped channels 401 exposed by corresponding two of the second grooves 404 may face in opposite directions, as depicted in FIG. 4D. In another embodiment, the sidewalls of the two adjacent rectangular pillar-shaped channels 401 exposed by corresponding two of the second grooves 404 may face in the same direction. In some embodiments, the third groove 405 and each of the two second grooves 404 between which the third groove 405 is located are located on opposite sidewalls of the rectangular cylindrical channel 401, as shown in FIG. 4D.

[0045] 4E is a top view illustrating the formation of a gate oxide layer of the semiconductor device 400A according to some embodiments of the present disclosure. In an embodiment, the sidewall of the rectangular pillar channel 401 exposed by the second groove 404 can be oxidized, for example, by direct oxidization, alkaline oxidization, or acidic oxidization, to form a gate oxide layer 406 on the exposed sidewall of the rectangular pillar channel 401. For example, the sidewall of the rectangular pillar channel 401 exposed by the second groove 404 can be heated and directly oxidized, so that the silicon in the sidewall reacts with air containing an oxidizing agent at high temperature to form a silicon dioxide film, i.e., a gate oxide layer 406, on the sidewall of the rectangular pillar channel 401. In some embodiments, the gate oxide layer 406 can include an insulating material such as silicon dioxide (SiO2).

[0046] FIG. 4F is a top view illustrating the formation of electromagnetic shielding elements and word lines of a semiconductor device 400A according to some embodiments of the present disclosure. In an embodiment, the third trench 405 and the second trench 404 can be filled with a metal material to form electromagnetic shielding elements 408 and word lines (or gates) 407, respectively. Thus, the word lines 407 and the electromagnetic shielding elements 408 can be formed in a single deposition step. In an embodiment, the metal material can include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or other suitable metal materials. In an embodiment, the electromagnetic shielding elements 408 can be made of polysilicon. In an embodiment, each of the word lines 407 can electrically connect adjacent ones of the transistors arranged in a column in the X-direction at the sidewalls of their columnar channels 401. In an embodiment, a gate oxide layer 406 is placed between the pillar channel 401 and the word line 407 to separate the word line 407 from the pillar channel 401 and prevent charge leakage. In an embodiment, the sidewalls of two adjacent rectangular pillar channels 401 on which the word lines 407 are placed may face in opposite directions, as shown in FIG. 4F. In another embodiment, the sidewalls of two adjacent rectangular pillar channels 401 on which the word lines 407 are placed may face in the same direction. In some embodiments, the electromagnetic shielding element 408 and each of the two word lines 407 between which the electromagnetic shielding element 408 is placed are placed on opposite sidewalls of the rectangular pillar channel 401, as shown in FIG. 4F. The electromagnetic shielding element 408 can prevent the adjacent pillar channels 410 from interfering with each other and reduce the coupling effect occurring between the word lines 407 and the pillar channel 401. A word line 407 can have a word line voltage applied to it and the transistors connected to the word line 407 can be enabled or disabled.

[0047] In some embodiments, bit lines may be formed to connect the sources or drains of the transistors. Storage capacitors are further formed to store data written to the semiconductor device 400A. Each of the storage capacitors has a first electrode connected to the drain or source of a corresponding one of the transistors and a second electrode connected to a common terminal. In an embodiment, the common terminal may be connected to a low voltage, for example, 0.5V. In another embodiment, the common terminal may be grounded. In an embodiment, the electromagnetic shielding element 408 may be made of a metal material having a high work function so that the electromagnetic shielding element 408 can have an even lower voltage.

[0048] In an embodiment, at least one of the electromagnetic shielding elements 408 may be energized with a first voltage that is lower than a second voltage applied to a corresponding one of the channels 401. In another embodiment, the electromagnetic shielding element 408 may be placed in an intermediate region between two adjacent transistors, and the first voltage may be less than half the second voltage. In some embodiments, at least one of the electromagnetic shielding elements 408 may be energized such that a first one of the two adjacent transistors between which the electromagnetic shielding element 408 is placed is less affected by a combination of a first electromagnetic field generated by the electromagnetic shielding element 408 and a second electromagnetic field generated by a second one of the two adjacent transistors than it is affected by a second electromagnetic field.

[0049] In an embodiment, the electromagnetic shielding element 408 may be connected to a common terminal. In another embodiment, the electromagnetic shielding element 408 may be decoupled from the common terminal and independently supplied with a voltage.

[0050] In some embodiments, the second groove 404 can have a deeper etch depth than the third groove 405. The etch depth of the second groove 404 and the third groove 405 can be controlled by determining various etching parameters, such as etching time, gas flow rate, gas flow proportion, pressure, and temperature. For example, under a certain etching rate, the longer the etching time, the deeper the groove formed in the third direction, e.g., Z direction. In embodiments, the second groove 404 can have a deeper etch depth than the third groove 405 by controlling the etching parameters. The second groove 404 and the third groove 405 can be formed by dry etching, e.g., plasma etching.

[0051] In some embodiments, the first direction and the second direction may include an included angle of less than 90 degrees.

[0052] FIG. 5 is a cross-sectional view of a semiconductor device 500 according to some embodiments of the present disclosure. The semiconductor device 500 may be manufactured by the method 400. In an embodiment, the semiconductor device 500 may include a plurality of transistors arranged in an array in an XY plane, each of the transistors may include a channel, e.g., a columnar channel 501. For example, the array may include a plurality of rows arranged along a first direction, e.g., the X direction, and a plurality of columns intersecting the rows and arranged along a second direction, e.g., the Y direction. Each of the transistors may include a channel 501, the transistor channels 501 being arranged along the first and second directions in the array. In an embodiment, each of the channels 501 may be in the shape of a pillar and may extend along a third direction, e.g., the Z direction, perpendicular to the plane defined by the first and second directions. For example, the pillars may have a cross-section in the shape of a rectangle, a circle, a diamond, or any other polygon. In an embodiment, each columnar channel 501 in a column of the array may have an oxide layer 506 and a word line 507 formed on its sidewall in order, both of which extend along a first direction, e.g., the X-direction, and the columnar channels 501 may thus be connected to each other by the word line 507. In an embodiment, a source 504 and a drain 503 may be formed at two ends of each columnar channel 501, respectively. In some embodiments, the source 504 and the drain 503 are interchangeable. In an embodiment, an electromagnetic shielding element 508 may be placed in a row in the Y-direction and between two adjacent transistors of the transistors extending along the X-direction. For example, the electromagnetic shielding element 508 may be parallel to the word line 507.

[0053] 5, at least one of the electromagnetic shielding elements 508 has a protrusion in the Y direction onto a corresponding one of the pillar channels 501 that does not overlap with the source 504 and the drain 503. For example, the electromagnetic shielding element 508 has a length extending in the Z direction that is less than the length of the pillar channel 501 and is greater than or equal to one-third the length.

[0054] In some embodiments, as shown in FIG. 5 , two adjacent ones of the pillar-shaped channels 501 have their word lines 507 formed on their sidewalls facing in opposite directions, and one of the electromagnetic shielding elements 508 is placed between the two pillar-shaped channels 501 on the sidewall of the pillar-shaped channel 501 opposite the sidewall on which the corresponding word line 507 is formed.

[0055] In one embodiment, the semiconductor device 500 may further include a bit line 510 connected to the drain 503 of the transistor, and a storage capacitor 509 connected at its first terminal to the source 504 via a storage capacitor pad 505 and at its second terminal to a common terminal (not shown) for storing data written to the semiconductor device 500.

[0056] In some embodiments, the electromagnetic shielding element 508 may be connected to a common terminal such that a voltage applied to the common terminal may be provided to the electromagnetic shielding element 508 .

[0057] 6A-6E illustrate the fabrication of a semiconductor device 600 according to some embodiments of the present disclosure, in which wordlines are formed on the sidewalls of any two adjacent transistors (or channels) facing in the same direction.

[0058] 6A is a top view illustrating the formation of columnar channels of a semiconductor device 600 according to some embodiments of the present disclosure. As shown in FIG. 6A, a plurality of channels 601 arranged in an array in, for example, an XY plane are formed on a surface of a wafer (not shown). For example, the array may include a plurality of rows arranged along a first direction, for example, an X direction, and a plurality of columns intersecting the rows and arranged along a second direction, for example, a Y direction. In an embodiment, each of the channels 601 may be in the shape of a pillar, for example, a rectangular pillar, and each of the rectangular columnar channels 601 may extend along a third direction, for example, a Z direction, perpendicular to the plane defined by the first direction and the second direction.

[0059] In some embodiments, the pillar channels 601 may be formed on the surface of the wafer by covering the wafer with a mask (not shown) that covers certain areas of the wafer that will be used to form the pillar channels 601, etching the wafer to a certain depth less than the thickness of the wafer to form first trenches 602 that are interposed between the pillar channels 601, and removing the mask to form the pillar channels 601 with their sidewalls exposed. In some embodiments, the wafer may be etched by using photolithography (PH) or dry etching (ET), such as electron beam lithography, plasma etching, and reactive ion etching (RIE).

[0060] 6B is a top view illustrating the formation of an insulating layer of semiconductor device 600 according to some embodiments of the present disclosure. In some embodiments, an insulating material, for example, SiO2, may be deposited in first trench 602 to form an insulating layer 603 that covers the sidewalls of first trench 602 and columnar channel 601. In some embodiments, chemical mechanical polishing (CMP) may then be employed to polish and remove the residue of the insulating material to expose the top surface of columnar channel 601.

[0061] FIG. 6C is a top view illustrating the formation of the second and third trenches of the semiconductor device 600 according to some embodiments of the present disclosure. In an embodiment, the insulating layer 603 may be etched to form the second trench 604 exposing one of the sidewalls of each of the pillar-shaped channels 601, e.g., the rectangular pillar-shaped channels 601, and the third trench 605, each of which is located between two adjacent transistors in a row in the Y direction (i.e., two adjacent rectangular pillar-shaped channels 601). In some embodiments, each of the second trenches 604 exposes the sidewalls of the pillar-shaped channels 401 of the transistors adjacent to each other and arranged in a column in the X direction. In an embodiment, the sidewalls of the two adjacent rectangular pillar-shaped channels 601 exposed by corresponding two of the second trenches 604 may face the same direction, as shown in FIG. 6C. In another embodiment, the sidewalls of the two adjacent rectangular pillar-shaped channels 601 exposed by corresponding two of the second trenches 604 may face opposite directions. In some embodiments, the third groove 605 and each of the two second grooves 604 between which the third groove 605 is located are located on opposite sidewalls of the rectangular cylindrical channel 601, as shown in FIG. 6C.

[0062] In some embodiments, the second groove 604 can have a deeper etch depth than the third groove 605. The etch depth of the second groove 604 and the third groove 605 can be controlled by determining various etching parameters, such as etching time, gas flow rate, gas flow rate, pressure, and temperature. For example, under a certain etching rate, the longer the etching time, the deeper the groove formed in the third direction, e.g., Z direction. In embodiments, the second groove 604 can have a deeper etch depth than the third groove 605 by controlling the etching parameters. The second groove 604 and the third groove 605 can be formed by dry etching, e.g., plasma etching.

[0063] 6D is a top view illustrating the formation of a gate oxide layer of the semiconductor device 600 according to some embodiments of the present disclosure. In an embodiment, the sidewall of the rectangular pillar channel 601 exposed by the second groove 604 can be oxidized, for example, by direct oxidation, alkaline oxidation, or acidic oxidation, to form a gate oxide layer 606 on the exposed sidewall of the rectangular pillar channel 601. For example, the sidewall of the rectangular pillar channel 601 exposed by the second groove 604 can be heated and directly oxidized, so that the silicon in the sidewall reacts with the air containing the oxidizing material at high temperature to form a silicon dioxide film, i.e., a gate oxide layer 606, on the sidewall of the rectangular pillar channel 601. In some embodiments, the gate oxide layer 606 can include an insulating material such as silicon dioxide (SiO2).

[0064] FIG. 6E is a top view illustrating the formation of electromagnetic shielding elements and word lines of a semiconductor device 600 according to some embodiments of the present disclosure. In an embodiment, the third trench 605 and the second trench 604 can be filled with a metal material to form electromagnetic shielding elements 608 and word lines (or gates) 607, respectively. Thus, the word lines 607 and the electromagnetic shielding elements 608 can be formed in a single deposition step. In another embodiment, the word lines 607 and the electromagnetic shielding elements 608 can be formed sequentially in two process steps. In an embodiment, the metal material can include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or other suitable metal materials. In an embodiment, each of the word lines 607 can electrically connect adjacent ones of the transistors arranged in a column in the X direction at the sidewalls of their columnar channels 601. In an embodiment, a gate oxide layer 606 is placed between the pillar channel 601 and the word line 607 to separate the word line 607 from the pillar channel 601 and prevent charge leakage. In an embodiment, the sidewalls of two adjacent rectangular pillar channels 601 on which the word lines 607 are placed may face the same direction, as shown in FIG. 6E. In another embodiment, the sidewalls of two adjacent rectangular pillar channels 601 on which the word lines 607 are placed may face opposite directions. In some embodiments, the electromagnetic shielding element 608 and each of the two word lines 607 between which the electromagnetic shielding element 608 is placed are placed on opposite sidewalls of the rectangular pillar channel 601, as shown in FIG. 6E. The electromagnetic shielding element 608 can prevent the adjacent pillar channels 601 from interfering with each other and reduce the coupling effect occurring between the word lines 607 and the pillar channel 601. Word line 607 can have a word line voltage applied to it and the transistor connected to word line 407 can be enabled or disabled.

[0065] In some embodiments, bit lines may be formed to connect the drains of the transistors. Storage capacitors are further formed to store data written to the semiconductor device 600. Each of the storage capacitors has a first electrode connected to a source of a corresponding one of the transistors and a second electrode connected to a common terminal. In an embodiment, the common terminal may be connected to a low voltage, for example, 0.5V. In another embodiment, the common terminal may be grounded.

[0066] In an embodiment, the electromagnetic shielding element 608 may be connected to a common terminal. In another embodiment, the electromagnetic shielding element 608 may be decoupled from the common terminal and independently supplied with a voltage. In some embodiments, the electromagnetic shielding element 608 may be grounded.

[0067] FIG. 7 is a cross-sectional view of a semiconductor device 700 according to some embodiments of the present disclosure. The semiconductor device 700 may be manufactured by the method 400. The semiconductor device 700 may include a plurality of transistors arranged in an array in an XY plane defined by a first direction, e.g., an X direction, and a second direction, e.g., a Y direction, each of the transistors including a channel 701, e.g., a rectangular pillar channel, extending in a third direction, e.g., a Z direction, perpendicular to the XY plane. A gate oxide layer 706 and a word line 707 are formed in turn on one of the sidewalls of each of the rectangular pillar channels 701. Thus, the gate oxide layer 706 separates the word line 707 from the rectangular pillar channel 701 and is interposed between the rectangular pillar channel 701 and the word line 707 to prevent charge leakage. Each of the word lines 707 may extend along a first direction, e.g., an X direction, and connect at least a portion of the transistors arranged in a row in the X direction. An electromagnetic shielding element 708 is interposed between at least two adjacent transistors arranged in a row in the Y direction. In an embodiment, the electromagnetic shielding element 708 can extend in the X direction. In an embodiment, the word lines 707 and the electromagnetic shielding element 708 are parallel. A source 704 and a drain 703 are formed at two ends of each of the pillar-shaped channels 701, respectively.

[0068] In an embodiment, as shown in FIG. 7, the electromagnetic shielding element 708 has a length longer than the word line 707 along the direction in which the columnar channel 701 extends, e.g., the Z direction. The length of the electromagnetic shielding element 708 and the length of the word line 707 can be determined by controlling the etching depth of the third groove, e.g., the third groove 605, and the second groove, e.g., the second groove 604, respectively. The etching depth of the second groove 604 and the third groove 605 can be controlled by determining various etching parameters such as etching time, gas flow rate, gas flow rate, pressure, and temperature. In an embodiment, the length of the electromagnetic shielding element 708 along the direction in which the columnar channel 701 extends, e.g., the Z direction, is longer than one-third of the length of the word line 707 in the Z direction.

[0069] In one embodiment, the semiconductor device 700 may further include a bit line 710 connected to the drain 703 of the transistor, and a storage capacitor 709 connected at its first terminal to the source 704 via a storage capacitor pad 705 and at its second terminal to a common terminal (not shown) for storing data written to the semiconductor device 700.

[0070] In an embodiment, the electromagnetic shielding element 708 may be connected to a common terminal, such that a voltage applied to the common terminal may be provided to the electromagnetic shielding element 708. In another embodiment, the electromagnetic shielding element 708 may be decoupled from the common terminal and independently supplied with a voltage.

[0071] FIG. 8 is a top view illustrating the formation of contact pads of a semiconductor device 800 according to some embodiments of the present disclosure. A bit line 810 is connected to the drains of a plurality of transistors arranged in an array in an XY plane, for example. Each of the transistors has a channel 809, for example, a rectangular columnar channel, extending in a direction perpendicular to the XY plane, for example, in the Z direction. The semiconductor device 800 may include a plurality of word lines 807 and one or more electromagnetic shielding elements 808. Each of the word lines 807 may electrically connect adjacent ones of the transistors arranged in a column in the X direction at their sidewalls. Each of the electromagnetic shielding elements 808 may be placed between adjacent two of the transistors placed in a row in the Y direction. In an embodiment, the sidewalls of the rectangular columnar channels 809 of two adjacent transistors in which the word line 807 is formed face in opposite directions. The semiconductor device 800 may further include a word line contact pad 801 connected to the word line 807 and an electromagnetic shielding contact pad 802 connected to the electromagnetic shielding element 808. In an embodiment, the word line contact pads 801 and the electromagnetic shielding contact pads 802 may be larger in size than the word lines 807 and the electromagnetic shielding elements 808, respectively, so that any adjacent two of the word line contact pads 801 may be located on two opposite sides of the array in the X direction, and any adjacent ones of the electromagnetic shielding contact pads 802 and the word line contact pads 801 may be offset relative to each other to prevent the word lines 807 and the electromagnetic shielding elements 808 from contacting each other.

[0072] FIG. 9 is a top view illustrating the formation of contact pads of a semiconductor device 900 according to some embodiments of the present disclosure. A bit line 910 is connected to the source or drain of a plurality of transistors arranged in an array in an XY plane, for example. Each of the transistors has a channel 909, for example, a rectangular columnar channel, extending in a direction perpendicular to the XY plane, for example, in the Z direction. The semiconductor device 900 may include a plurality of word lines 907 and one or more electromagnetic shielding elements 908. Each of the word lines 907 may electrically connect adjacent ones of the transistors arranged in a column in the X direction at their sidewalls. Each of the electromagnetic shielding elements 908 may be placed between adjacent two of the transistors placed in a row in the Y direction. In an embodiment, the sidewalls of the rectangular columnar channels 909 of two adjacent transistors in which the word line 907 is formed face in the same direction. The semiconductor device 900 may further include a word line contact pad 901 connected to the word line 907 and an electromagnetic shielding contact pad 902 connected to the electromagnetic shielding element 908. In some embodiments, the word line contact pads 901 and the electromagnetic shielding contact pads 902 are located on the same side of the array in the X direction, and any one of the electromagnetic shielding contact pads 902 and any adjacent one of the word line contact pads 901 are offset with respect to each other.

[0073] FIG. 9A is a top view illustrating the formation of contact pads of a semiconductor device 900A according to some embodiments of the present disclosure. A bit line 910A is connected to the source or drain of a plurality of transistors arranged in an array in the XY plane, for example. Each of the transistors has a channel 909A, for example, a rectangular columnar channel, extending in a direction perpendicular to the XY plane, for example, in the Z direction. The semiconductor device 900A may include a plurality of word lines 907A and one or more electromagnetic shielding elements 908A. Each of the word lines 907A may electrically connect adjacent ones of the transistors arranged in a column in the X direction at their sidewalls. Each of the electromagnetic shielding elements 908A may be placed between adjacent two of the transistors placed in a row in the Y direction. In an embodiment, the sidewalls of the rectangular columnar channels 909A of two adjacent transistors in which the word lines 907A are formed face the same direction. The semiconductor device 900A may further include a word line contact pad 901A connected to a word line 907A and an electromagnetic shielding contact pad 902A connected to an electromagnetic shielding element 908A. In some embodiments, to prevent the word line 907A and the electromagnetic shielding element 908 from contacting each other, any two adjacent word line contact pads 901A and electromagnetic shielding contact pads 902A are located on opposite sides of the array in the X direction. For example, as shown in FIG. 9A, the electromagnetic shielding contact pad 902A is located on the back side of the array in the X direction, while the word line contact pad 901A adjacent to the electromagnetic shielding contact pad 902A is located on the front side of the array in the X direction.

[0074] 10A through 10H are cross-sectional views of semiconductor devices 1000A through 1000H having electromagnetic shielding elements 1008A through 1008H in various configurations according to some embodiments of the present disclosure. The semiconductor device 1000A / 1000B / 1000C / 1000D / 1000E / 1000F / 1000G / 1000H includes, for example, a plurality of transistors arranged in an XY plane, each of which has a channel 1001A / 1001B / 1001C / 1001D / 1001E / 1001F / 1001G / 1001H extending in the Z direction, for example a rectangular columnar channel, and a source 1004A / 1004B / 1004C / 1004D / 1004E / 1004F / 1004G / 1004H and a drain 1004H formed at two ends of the columnar channel 1001A / 1001B / 1001C / 1001D / 1001E / 1001F / 1001G / 1001H, respectively. 3A / 1003B / 1003C / 1003D / 1003E / 1003F / 1003G / 1003H, a plurality of word lines 1007A / 1007B / 1007C / 1007D / 1007E / 1007F / 1007G / 1007H each electrically connecting adjacent ones of the transistors arranged in a column in the X-direction at the sidewalls of the pillar-shaped channels 1001A / 1001B / 1001C / 1001D / 1001E / 1001F / 1001G / 1001H, and one or more electromagnetic shielding elements 1008A / 1008B / 1008C / 1008D / 1008E / 1008F / 1008G / 1008H each interposed between adjacent two of the transistors in a row in the Y-direction. The electromagnetic shielding elements may have a Y-direction protrusion onto the columnar channel and may be equal in length to the columnar channel (e.g., electromagnetic shielding element 1008A) or shorter in length than the columnar channel (e.g., electromagnetic shielding elements 1008B, 1008C, and 1008D, which may be located in the middle, upper, and lower regions for columnar channels 1001B, 1001C, and 1001D, respectively). The electromagnetic shielding elements may have a rectangular shaped cross-section (e.g., electromagnetic shielding elements 1008A through 1008E, 1008G, and 1008H) or an elliptical shaped cross-section (e.g., electromagnetic shielding element 1008F).The electromagnetic shielding elements may each include multiple electromagnetic shielding segments that are spaced apart from one another and arranged along the Z direction (e.g., electromagnetic shielding element 1008G) and / or along the Y direction (e.g., electromagnetic shielding element 1008H).

[0075] 11A-11E are cross-sectional views of semiconductor devices 1100A-1100E having electromagnetic shielding elements 1108A-1108E of various configurations according to some embodiments of the present disclosure. The semiconductor devices 1100A / 1100B / 1100C / 1100D / 1100E include, for example, a plurality of transistors arranged in an XY plane, each of the transistors having a channel 1101A / 1101B / 1101C / 1101D / 1101E extending in the Z direction, for example, a rectangular cylindrical channel and a source and a drain (not shown) formed at two ends of the cylindrical channel 1101A / 1101B / 1101C / 1101D / 1101E, respectively. 11C and 11D, and one or more electromagnetic shielding elements 1108A / 1108B / 1108C / 1108D / 1108E, each of which is interposed between adjacent two of the transistors in a row in the Y direction. The electromagnetic shielding elements may each include a plurality of electromagnetic shielding segments that are spaced apart from one another and disposed along the Y direction (e.g., electromagnetic shielding element 1108E) or disposed along the X direction (e.g., electromagnetic shielding elements 1108C and 1108D, whose electromagnetic shielding segments may extend in the X direction and / or the Y direction as shown in FIG. 11C and FIG. 11D, respectively). An electromagnetic shielding element may further be placed between adjacent two of the transistors placed in a column in the X direction (eg, electromagnetic shielding elements 1108B and 1108E).

[0076] 12A to 12C are cross-sectional views illustrating the fabrication of a semiconductor device according to some embodiments of the present disclosure. In an embodiment, the electromagnetic shielding element and the word line can be formed simultaneously in a single process. For example, as shown in FIG. 12A, a vertical gate groove (or trench) VG (e.g., the second groove 404) and an isolation groove (or trench) ISO (e.g., the third groove 405) narrower than the vertical gate groove VG can be formed in a substrate, an oxide layer, e.g., a gate oxide layer 406, can be formed on the exposed sidewalls of the vertical gate groove VG and the isolation groove ISO, and a conductor, e.g., a metal material or polysilicon can be simultaneously deposited in the vertical gate groove VG and the isolation groove ISO to form the word line WL (e.g., the word line 407) and the electromagnetic shielding element ESE (e.g., the electromagnetic shielding element 408) of the semiconductor device 1200A, respectively.

[0077] In another embodiment, the word lines WL and the electromagnetic shielding elements ESE of the semiconductor device 1200B may be formed in sequence, as shown in Fig. 12B. For example, to form the word lines WL, vertical gate grooves VG may be formed in a substrate, an oxide layer may be formed on exposed sidewalls of the vertical gate grooves VG, and a first conductor may be deposited in the vertical gate grooves VG, and to form the electromagnetic shielding elements ESE, isolation grooves ISO may be etched and formed in the substrate, an oxide liner may be deposited on exposed sidewalls of the isolation grooves ISO, and a second conductor may be deposited to fill the isolation grooves ISO.

[0078] In some embodiments, the word lines WL and the electromagnetic shielding elements ESE of the semiconductor device 1200C can be formed individually, as shown in FIG. 12C. For example, a trench in which a contact pad, e.g., the electromagnetic shielding contact pad 902A shown in FIG. 9A, is formed can be formed and filled with oxide, and then the vertical gate trench VG and the isolation trench ISO can be etched, e.g., by self-aligned double patterning (SADP). Thus, the portion of the isolation trench ISO in which the electromagnetic shielding contact pad on the backside of the semiconductor device 1200C is to be formed can be deeper than the vertical gate trench VG, and the remainder of the isolation trench ISO can be as deep as the vertical gate trench VG. Thereafter, an oxide layer and a first conductor may be sequentially formed in the vertical gate trench VG to form the word line WL, and the backside of the semiconductor device 1200C may be thinned to expose the oxide filled in the isolation trench ISO to form the electromagnetic shielding element ESE and the electromagnetic shielding contact pad, respectively, and then the oxide may be recessed and an oxide lining may be deposited on the exposed sidewalls of the isolation trench ISO, and a second conductor may fill the isolation trench ISO and the space formed after the oxide is recessed.

[0079] 13 illustrates a block diagram of a memory system 1300 according to some embodiments of the present disclosure. Memory system 1300 may include one or more semiconductor devices 1301-1304, such as semiconductor devices 400A, 500, 600, 700, 800, 900A, 1000A-1000H, 1100A-1100E, and 1200A-1200C. In some embodiments, memory system 1300 may be a solid-state drive (SSD) or a memory module.

[0080] Memory system 1300 may include other suitable components. For example, memory system 1300 may include an interface (or master interface circuit) 1310 and a master controller (or control circuit) 1320 coupled to each other. Memory system 1300 may also include a bus 1330 coupling master controller 1320 to semiconductor devices 1301 through 1304. Additionally, master controller 1320 is connected to semiconductor devices 1301 through 1304, as indicated by respective control lines 1340-1370, respectively.

[0081] The interface 1310 is suitably configured mechanically and electrically to connect between the memory system 1300 and a host device, and can be used to transfer data between the memory system 1300 and the host device.

[0082] The master controller 1320 is configured to connect each semiconductor device 1301 to 1304 to the interface 1310 for data transfer. For example, the master controller 1320 may be configured to provide enable / disable signals to the semiconductor devices 1301 to 1304, respectively, to activate one or more of the semiconductor devices 1301 to 1304 for data transfer.

[0083] The master controller 1320 is responsible for the completion of various instructions within the memory system 1300. For example, the master controller 1320 may perform bad block management, error checking and correction, garbage collection, etc. In some embodiments, the master controller 1320 may be implemented using a processor chip. In some examples, the master controller 1320 may be implemented using multiple master control units (MCUs).

[0084] The above outlines the features of some embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should understand that they may easily use the present disclosure as a basis for designing or modifying other processes and structures to accomplish the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that those skilled in the art may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. [Explanation of symbols]

[0085] 100A Planar Array Transistor, Planar Semiconductor Device 100B BCAT 200 Semiconductor Devices 210 Transistor 211 Channel, Columnar Channel 212 Source 213 Drain 400A Semiconductor Device 401 Channel, Columnar Channel, Rectangular Columnar Channel 402 First Groove 403 Insulating layer 404 Second Groove 405 The Third Groove 406 Gate oxide layer 407 Word Line 408 Electromagnetic Shielding Elements 409 Wafer 500 Semiconductor Devices 501 Columnar Channel 503 Drain 504 Source 505 Memory Capacitor Pad 506 Oxide layer 507 Word Line 508 Electromagnetic Shielding Elements 509 Storage Capacitor 510 bit lines 600 Semiconductor Devices 601 Channel, Rectangular Column Channel, Column Channel 602 First Groove 603 Insulation Layer 604 Second Groove 605 The Third Groove 606 Gate oxide layer 607 Word Line 608 Electromagnetic Shielding Elements 700 Semiconductor Devices 701 Channel, Rectangular Column Channel, Column Channel 703 Drain 704 Source 706 Gate oxide layer 707 Word Line 708 Electromagnetic Shielding Elements 709 Memory Capacitor 710 bit lines 800 Semiconductor Devices 801 Word Line Contact Pad 802 Electromagnetic Shielding Contact Pads 807 Word Line 808 Electromagnetic Shielding Elements 809 Channel, Rectangular Column Channel 810 bit lines 900 Semiconductor Devices 900A Semiconductor Device 901 Word Line Contact Pad 901A Word Line Contact Pad 902 Electromagnetic Shielding Contact Pads 902A Electromagnetic Shielding Contact Pads 907 Word Line 907A Word Line 908 Electromagnetic Shielding Elements 908A Electromagnetic Shielding Element 909 Channel, Rectangular Column Channel 909A Channel, Rectangular Cylindrical Channel 910 bit lines 910A Bit Line 1000A Semiconductor Device 1000B Semiconductor Device 1000C Semiconductor Device 1000D Semiconductor Device 1000E Semiconductor Device 1000F Semiconductor Device 1000G Semiconductor Device 1000H Semiconductor Device 1001A Channel, Columnar Channel 1001B Channel, Columnar Channel 1001C Channel, Columnar Channel 1001D Channel, Columnar Channel 1001E Channel, Columnar Channel 1001F Channel, Columnar Channel 1001G Channel, Columnar Channel 1001H Channel, Columnar Channel 1003A Drain 1003B Drain 1003C Drain 1003D Drain 1003E Drain 1003F Drain 1003G Drain 1003H Drain 1004A Source 1004B Source 1004C Source 1004D Source 1004E Source 1004F Source 1004G Source 1004H Source 1007A Word Line 1007B Word Line 1007C Word Line 1007D Word Line 1007E Word Line 1007F Word Line 1007G Word Line 1007H Word Line 1008A Electromagnetic Shielding Element 1008B Electromagnetic shielding element 1008C Electromagnetic Shielding Element 1008D Electromagnetic Shielding Elements 1008E Electromagnetic shielding element 1008F Electromagnetic shielding element 1008G electromagnetic shielding element 1008H Electromagnetic shielding element 1100A Semiconductor Device 1100B Semiconductor Devices 1100C Semiconductor Devices 1100D Semiconductor Devices 1100E Semiconductor Device 1101A Channel, Columnar Channel 1101B Channel, Pillar Channel 1101C Channel, Columnar Channel 1101D Channel, Columnar Channel 1101E Channel, Columnar Channel 1107A Word Line 1107B Word Line 1107C Word Line 1107D Word Line 1107E Word Line 1108A Electromagnetic Shielding Element 1108B Electromagnetic Shielding Element 1108C Electromagnetic Shielding Element 1108D Electromagnetic Shielding Element 1108E Electromagnetic Shielding Element 1200A Semiconductor Device 1200B Semiconductor Device 1200C Semiconductor Device 1300 Memory System 1301 Semiconductor devices 1304 Semiconductor devices 1310 Interface 1320 Master Controller 1330 Bus 1340 Control Line 1370 Control Line WL1 Word Line CH1 Rectangular columnar channel CH2 Rectangular columnar channel

Claims

1. 1. A method for manufacturing a semiconductor device, comprising: forming a plurality of transistors arranged in an array in an XY plane, each of the transistors including a channel extending in a Z direction; forming a plurality of word lines, each of the word lines electrically connecting adjacent ones of the transistors at sidewalls of the channels of the adjacent ones of the transistors, the adjacent ones of the transistors being arranged in columns in an X-direction; forming one or more electromagnetic shielding elements, at least one of the one or more electromagnetic shielding elements being disposed between adjacent two of the transistors disposed in a row in a Y direction; A method comprising:

2. 2. The method of claim 1 , wherein each of the transistors further includes a source located at a first end of the channel and a drain located at a second end of the channel, and the electromagnetic shielding element has a Y-direction protrusion onto the channel that does not overlap the source and the drain.

3. The method of claim 1 , wherein the electromagnetic shielding element is shorter in a Z direction than the channels of the two adjacent transistors.

4. The method of claim 1 , wherein the electromagnetic shielding element is further disposed between adjacent two of the transistors disposed in the column.

5. 2. The method of claim 1, wherein each of the channels of the transistors is a rectangular pillar, and each of the wordlines is formed on a sidewall of a corresponding one of the rectangular pillar channels.

6. The method of claim 5 , wherein the sidewalls of the rectangular pillar channels of the two adjacent transistors between which the word line is formed face in opposite directions.

7. forming an electromagnetic shielding contact pad connected to one of the electromagnetic shielding elements; forming a word line contact pad connected to one of the word lines adjacent the electromagnetic shielding element; Further comprising:

2. The method of claim 1, wherein the electromagnetic shielding contact pads and the word line contact pads are located on opposite sides of the array in an X-direction.

8. the electromagnetic shielding element and the word line; forming a first trench in a substrate of the semiconductor device on a backside of the semiconductor device, the first trench having a contact pad formed therein, and filling the first trench with an oxide; forming second and third grooves in the substrate into which the word lines and the electromagnetic shielding elements are respectively formed, the third groove contacting the first groove; filling the second trench with a first conductor to form the word line; thinning the backside of the semiconductor device to expose the oxide filled in the first trench; recessing the oxide to expose sidewalls of the third trench; filling the third groove and the first groove with a second conductor to form the electromagnetic shielding element and the contact pad, respectively; The method of claim 7 , wherein the compound is formed by

9. a plurality of transistors arranged in an array in the XY plane, each of the transistors including a channel extending in the Z direction; a plurality of word lines, each of the plurality of word lines electrically connecting adjacent ones of the transistors arranged in a column in an X direction at sidewalls of the channels of the adjacent ones of the transistors; one or more electromagnetic shielding elements, at least one of the one or more electromagnetic shielding elements being disposed between adjacent two of the transistors disposed in a row in the Y direction; 13. A semiconductor device comprising:

10. 10. The semiconductor device of claim 9, wherein each of the transistors further includes a source located at a first end of the channel and a drain located at a second end of the channel, and the electromagnetic shielding element has a Y-direction protrusion onto the channel that does not overlap the source and the drain.

11. The semiconductor device of claim 9 , wherein the electromagnetic shielding element is shorter in a Z direction than the channels of the two adjacent transistors.

12. The semiconductor device of claim 9 , wherein the electromagnetic shielding element is further disposed between adjacent two of the transistors disposed in the column.

13. 10. The semiconductor device of claim 9, wherein each of the channels of the transistors is a rectangular pillar, and each of the wordlines is formed on a sidewall of a corresponding one of the rectangular pillar channels.

14. 14. The semiconductor device of claim 13, wherein the sidewalls of the rectangular pillar channels of the two adjacent transistors between which the word lines are formed face in opposite directions.

15. an electromagnetic shielding contact pad connected to one of the electromagnetic shielding elements; a word line contact pad connected to one of the word lines adjacent the electromagnetic shielding element; Further comprising:

10. The semiconductor device of claim 9, wherein the electromagnetic shielding contact pads and the word line contact pads are located on opposite sides of the array in an X-direction.

16. The semiconductor device of claim 9 , wherein at least one of the electromagnetic shielding elements includes a plurality of electromagnetic shielding segments that are spaced apart from one another.

17. The semiconductor device of claim 16 , wherein the electromagnetic shielding segments are arranged along an X-direction, a Y-direction, and / or a Z-direction.

18. 10. The semiconductor device of claim 9, wherein at least one of the electromagnetic shielding elements is applied with a first voltage that is lower than a second voltage applied to a corresponding one of the channels.

19. 10. The semiconductor device of claim 9, wherein at least one of the electromagnetic shielding elements is voltaged such that a first transistor of the two adjacent transistors between which the electromagnetic shielding element is interposed is affected less by a combination of a first electromagnetic field generated by the electromagnetic shielding element and a second electromagnetic field generated by a second transistor of the two adjacent transistors than by the second electromagnetic field.

20. 1. A memory system comprising: a plurality of transistors arranged in an array in the XY plane, each of the transistors including a channel extending in the Z direction; a plurality of word lines, each of the plurality of word lines electrically connecting adjacent ones of the transistors arranged in a column in the X direction at sidewalls of the channels of the adjacent ones of the transistors; and one or more electromagnetic shielding elements, at least one of which is located between adjacent two of the transistors located in a row in the Y direction; A semiconductor device comprising: a control circuit coupled to the semiconductor device and configured to control an operation of the semiconductor device; A memory system including:

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