Interconnects in diffusion breaks in integrated circuits

Abstract

The semiconductor device includes a first three-dimensional (3D) transistor disposed in a substrate and a second 3D transistor oriented parallel to the first 3D transistor, the first 3D transistor and the second 3D transistor being a subset of a plurality of transistors. The device includes a diffusion break trench disposed in a region laterally separating the second 3D transistor from the first 3D transistor, the diffusion break trench having a length extending along the lateral direction. The device includes a diffusion break wire filling the diffusion break trench, the diffusion break wire having a height along a vertical direction, and gates of the plurality of transistors are fabricated from a different conductive material than the diffusion break wire.

Description

[Technical field]

[0001] Related Applications This application claims priority to U.S. Non-Provisional Patent Application No. 17 / 647,938, entitled "WIRING IN DIFFUSION BREAKS IN AN INTEGRATED CIRCUIT," filed January 13, 2022, the disclosure of which is expressly incorporated herein by reference in its entirety.

[0002] Technical Field The present invention relates generally to integrated circuits, and in a particular embodiment, to interconnects in diffusion breaks within integrated circuits. [Background technology]

[0003] Typically, integrated circuits (ICs) are fabricated by sequentially depositing and patterning dielectric, metal, and semiconductor layers above a substrate to form a network of electronic components connected by metal lines and vias in a monolithic structure. Traditionally, innovations in photolithography, such as multi-patterning and extreme ultraviolet (EUV) lithography, have enabled feature sizes to shrink with each new technology node, nearly doubling packing density to reduce IC cost and increase functionality. The increase in electric field that accompanies dimensional scaling makes it difficult to miniaturize field-effect transistors (FETs) within the constraints of switching speed, leakage power, and reliability. Recently, achieving worthwhile power-performance-area-cost (PPAC) improvements has involved the use of three-dimensional (3D) FET structures. 3D FET structures have evolved from FinFETs, to gate-all-around FETs (GAAFETs), to complementary FETs (CFETs), which are a pair of FETs stacked vertically, for example, a p-type FET on top of an n-type FET. FinFETs have layered high-k metal gates (HKMG) surrounding a vertically protruding thin fin-shaped semiconductor channel, while GAAFET structures are vertical stacks of thin semiconductor nanosheets or nanowires with a shared HKMG gate surrounding and connecting along the two vertical sides of the stack, filling the space between vertically adjacent nanosheets. The 3D architecture of CFETs further reduces the device footprint by stacking two transistors vertically. However, innovations are needed to efficiently wire 3D devices to fully realize their potential. Summary of the Invention

[0004] The semiconductor device includes a first three-dimensional (3D) transistor disposed in a substrate and a second 3D transistor oriented parallel to the first 3D transistor, the first 3D transistor and the second 3D transistor being a subset of a plurality of transistors. The device includes a diffusion break trench disposed in a region laterally separating the second 3D transistor from the first 3D transistor, the diffusion break trench having a length extending along the lateral direction. The device includes a diffusion break wire filling the diffusion break trench, the diffusion break wire having a height along a vertical direction, and gates of the plurality of transistors are fabricated from a different conductive material than the diffusion break wire.

[0005] A method of forming a semiconductor device includes forming a first three-dimensional (3D) transistor in a first region and forming a second 3D transistor in a second region oriented parallel to the first 3D transistor. The method includes forming a diffusion break trench between the second 3D transistor and the first 3D transistor, the diffusion break trench extending along a first lateral direction. The method includes forming a diffusion break wire by filling the diffusion break trench, the diffusion break wire having a height along a vertical direction, and filling the diffusion break trench includes forming a conductive core, and the gates of the first and second transistors are made of a different conductive material than the diffusion break wire.

[0006] The semiconductor device includes a first three-dimensional (3D) transistor disposed in a substrate, a first circuit component disposed in the substrate, a diffusion break trench having a length extending along a first lateral direction, and a diffusion break wire disposed in the diffusion break trench, the diffusion break wire including an insulating outer liner and a first conductive core, the first conductive core electrically coupled to an electrode of the first 3D transistor and an electrode of the first circuit component. [Brief description of the drawings]

[0007] For a more complete understanding of the present invention, and the advantages thereof, reference should be made to the following descriptions taken in conjunction with the accompanying drawings, in which:

[0008] [Figure 1] 1A-1C are schematic diagrams of two layouts of a simplified standard cell according to some embodiments. [Figure 2A] FIG. 2 is a perspective view of a CFET and a diffusion break wire according to some embodiments. [Figure 2B] FIG. 2 is a perspective view of a CFET and a diffusion break wire according to some embodiments. [Figure 3A] 2A-2C are cross-sectional views of the simplified standard cell shown in FIG. 1 at various intermediate stages of manufacture, according to some embodiments. [Figure 3B] 2A-2C are cross-sectional views of the simplified standard cell shown in FIG. 1 at various intermediate stages of manufacture, according to some embodiments. [Figure 3C] 2A-2C are cross-sectional views of the simplified standard cell shown in FIG. 1 at various intermediate stages of manufacture, according to some embodiments. [Figure 3D] 2A-2C are cross-sectional views of the simplified standard cell shown in FIG. 1 at various intermediate stages of manufacture, according to some embodiments. [Figure 3E] FIG. 3E is a cross-sectional view of the simplified standard cell shown in FIG. 3D according to another embodiment. [Figure 4A] 1A-1D are plan and respective cross-sectional views of a simplified standard cell, according to one embodiment; [Figure 4B] 1A-1D are plan and respective cross-sectional views of a simplified standard cell, according to one embodiment; [Figure 5A] FIG. 2 illustrates a standard cell layout, according to one embodiment. [Figure 5B] FIG. 2 illustrates a standard cell layout, according to one embodiment. [Figure 5C] FIG. 5C is a cross-sectional view of a diffusion break wire in the standard cell layout shown in FIGS. 5A to 5B. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] This disclosure describes embodiments of structures and methods for forming wires, referred to as diffusion break wires, that run along the lines of diffusion breaks formed between adjacent diffusion areas that comprise three-dimensional (3D) transistors. Certain exemplary embodiments described in this disclosure illustrate the inventive concept of using nanosheet transistors (NTs) in complementary metal oxide semiconductor (CMOS) field effect transistor (FET) integrated circuit (IC) technology. In NTs, the channel is part of a stack of semiconductor nanosheets with a gate structure surrounding the nanosheets. Self-aligned semiconductor source / drain (S / D) regions on either side of the gate are formed from the same stack of nanosheets. The diffusion area refers to the continuous active area of ​​the NT channel and S / D regions that are physically connected by an unbroken nanosheet stack. After forming the diffusion areas, in various embodiments, a diffusion break is formed to divide the long diffusion area into a row of separate diffusion areas by removing the nanosheet stack from the region between adjacent diffusion areas, as described in more detail below. In the present disclosure, an NT transistor may be a gate-all-around FET (GAAFET) or a complementary FET (CFET) comprising a vertical stack of a lower GAAFET and an upper GAAFET. The GAAFET channel may comprise a nanowire or a nanosheet, as discussed in the Background section. GAAFETs and CFETs with a nanowire instead of a nanosheet as the channel region are similar to NTs and may be referred to as nanowire transistors (NWTs).

[0010] The concept of a CFET is to increase the packing density of transistors by stacking several transistors vertically. An exemplary embodiment of the diffusion break wire is described in the context of a CFET structure including a vertical stack of n-type and p-type GAAFETs. Although the diffusion break wire has been described for a complementary metal oxide semiconductor (CMOS) digital logic IC technology using a CFET structure with a stack of two GAAFETs, aspects of the invention may be applied to technologies using active elements with other types of 3D architectures, such as FinFETs, GAAFETs, or CFETs with larger stacks of transistors. In this disclosure, the CFET comprises a vertical stack of a first transistor and a second transistor, so that each CFET channel, S / D, and gate structure comprises respective first and second channel, S / D, and gate structures.

[0011] Standard cells in a standard cell library provide combinational and sequential logic functions in microelectronic designs. A layout of standard cells from a standard cell library for implementing a logic function in a digital IC often comprises rows of diffusion areas, columns of diffusion breaks, and gate structures intersecting and crossing the rows.

[0012] As described in more detail below, the embodiments described herein enable the scaling of logic standard cells. More specifically, various embodiments increase transistor density in digital logic designs by reducing cell height. Cell height in standard cell logic designs is expressed as the number of wiring tracks, i.e., the number of minimum pitch wiring tracks available for routing transistors to each other and to input and output pins. For example, reducing cell height from 7T to 3.5T while maintaining the same cell width corresponds to approximately 50% area scaling or doubling of density. The reduced space for wiring tracks increases the difficulty in routing power lines and signals between transistors. The embodiments achieve the reduced cell height along with novel connectivity that helps overcome wiring congestion in aggressively scaled low track height logic cells. This novel connectivity is achieved in part by utilizing wasted space in the diffusion breaks as an additional wiring layer. Thus, the embodiments enable further scaling of wiring limited standard cells.

[0013] First, one embodiment of a diffusion break wire is described using the standard cell layout of Figure 1. A structural embodiment of a CFET with a diffusion break wire used as a metal interconnect is described using Figures 2A-2B, 3D, 3E, and 4-5. An embodiment method of forming the device is described using Figures 3A-3E.

[0014] FIG. 1 shows a schematic diagram of two layouts of a simplified standard cell. The first layout 101A is for CFET technology with a two-transistor footprint, and the second layout 101B is for GAAFET technology with a one-transistor footprint. The boundaries of the standard cells are shown by dashed rectangles. Reference numbers with the same number refer to similar entities, those ending with A refer to the first layout 101A and those ending with B refer to the second layout 101B.

[0015] Each of the simplified standard cell layouts 101A and 101B in FIG. 1 shows six columnar tracks with three rows of gate structures 103A / 103B and three rows of diffusion breaks, and two types of diffusion break lines: non-conductive diffusion break lines 105A / 105B and diffusion break wires 112A / 112B. As will be explained in more detail below, the diffusion break wires comprise a conductive material to which an electrical contact is made to connect the diffusion break wire to an electrode of an electronic component or to another wire. In contrast, the non-conductive diffusion break lines are all made of insulating material. The first layout 101A shows a row of CFETs, each of which is a stack of n-type and p-type GAAFETs. In contrast, the second layout 101B for one-transistor footprint GAAFET technology has two rows for the same number of transistors, e.g., one row for n-type and one row for p-type GAAFETs, marked n-GAAFET and p-GAAFET, respectively, in FIG. 1. As shown in FIG. 1, each row is divided into segments by diffusion breaks 105A / 105B, and each segment is one diffusion area 111A / 111B in the respective row. The standard cell shown in the first layout 101A and the second layout 101B has two diffusion areas 111A / 111B in each row of diffusion areas 111A / 111B. At each intersection between a gate structure 103A / 103B and a diffusion area 111A / 111B, a portion of the diffusion area 111A / 111B common to the gate structures 103A / 103B is a transistor channel area 107A / 107B (shown by a dotted X in FIG. 1). The remaining portion of the diffusion area 111A / 111B comprises S / Ds 109A / 109B. Each diffusion area 111A / 111B has at least one transistor channel 107A / 107B and two S / Ds 109A / 109B.However, the diffusion area 111A / 111B may have multiple intersecting gate structures 103A / 103B creating multiple channel areas 107A / 107B with S / Ds 109A / 109B between adjacent channel areas 107A / 107B.

[0016] The diffusion break lines may be created by forming diffusion break trenches along the column direction using a diffusion cut etch, with each trench often passing through several rows of diffusion areas, as described in more detail below. Some of the diffusion break trenches are then selectively filled with an insulating material to form the non-conductive diffusion break lines 105A / 105B, while other diffusion break trenches are selectively filled to form the diffusion break wires 112A / 112B. The diffusion break wires 112A / 112B include a conductive core that is insulated from adjacent diffusion areas by an insulating outer liner formed along the sidewalls and bottom wall of each diffusion break trench, as described in more detail below. In some embodiments, the diffusion break wires 112A / 112B may include a vertical stack including a first conductive core, a second conductive core below the first conductive core, and an insulating layer that insulates the second conductive core from the first conductive core. Electrical connections may be made to the conductive cores of the diffusion break wires 112A / 112B using vertical and lateral connectors. Through these connectors, the conductive cores may be coupled to transistor electrodes and also to the multilevel interconnect system of the IC. Thus, the diffusion break wires 112A / 112B may be utilized as additional routing tracks, providing the advantage of easing wiring congestion in aggressively scaled standard cells designed for advanced digital CMOS ICs.

[0017] The evolution of three-dimensional (3D) transistor architectures from single transistor footprints (e.g., FinFET and GAAFET) to the stacked transistor concept of CFET has increased the packing density of transistors, but it exacerbates the wiring congestion in standard cells. Typically, in standard cells, back-end-of-line (BEOL) metal interconnect lines at the lowest wiring level above the transistors run perpendicular to the gates and are used to route signals and power supplies between transistors in different columns. One measure of area efficiency and packing density of CMOS digital logic technology is the cell height of a standard cell layout. The cell height is the cell dimension parallel to the transistor gate, e.g., cell heights HA and HB of the first layout 101A and the second layout 101B in FIG. 1, respectively. As mentioned above, the cell height is expressed as a multiple of the minimum pitch of the wiring tracks of metal interconnects available for routing signals, power supplies, and grounds. Thus, efforts to reduce the cell height to reduce the cost per function of digital ICs by increasing cell density constrain the number of wiring tracks for routing.

[0018] Logic IC designs with FinFETs (the most widely used 3D transistor architecture) may use fewer fins per transistor to reduce cell height, which pushes the technology towards taller fins to help restore the total drive current of the transistor. GAAFET structures use parallel channels in vertical stacks of nanosheets, so cell height in CMOS GAAFET technology may be reduced by scaling down the stack width parallel to the gate. Loss of transistor drive with scaling down stack width forces GAAFET technology to increase the number of nanosheets in the stack to recover the total drive current, as well as increasing fin height. However, limited scaling of cell height may be achieved with FinFETs with taller fins or GAAFETs due to the processing complexity and increased parasitic S / D resistance associated with high aspect ratio fin spacing and GAAFET gate structures that encompass multiple tall stacks.

[0019] The CFET concept of stacking transistors provides an opportunity to significantly reduce the cell height by reducing the number of rows of diffusion area within the cell, as can be seen from a comparison of the first layout 101A and the second layout 101B in FIG. 1. As explained above, the significantly reduced cell height of the aggressively scaled standard cell also means a similarly significant reduction in the number of wiring tracks parallel to the rows of diffusion area available to connect the transistors to the circuit network. While some IC technologies provide additional interconnect levels in the portion of the substrate below the transistors for buried power lines, further relief to wiring congestion may be obtained by using embodiments of the diffusion break wires 112A / 112B as routing tracks parallel to the columns of gate structures, as described in this disclosure.

[0020] Figures 2A and 2B show perspective views of a CFET 200 and a diffusion break wire 210. In Figure 2A, the location of the diffusion break wire is indicated by a dashed rectangular block to more clearly see the CFET 200, and in Figure 2B, the diffusion break wire 210 is shown as a solid rectangular block, with a first conductive pillar 230 and a lateral second wire bridge 232 (the first and second wire bridges are described in more detail below) as vertical and lateral connectors that make electrical connections to the conductive core of the diffusion break wire 210.

[0021] The CFET 200 shown in FIG. 2A is a stack of a first transistor 200A and a second transistor 200B. In this example, the first transistor 200A and the second transistor 200B are GAAFETs, each of which comprises two nanosheets of a stack of four nanosheets. In general, the transistors may be of any type, but specifically, in this embodiment, the first transistor 200A may be a p-type GAAFET and the second transistor 200B may be an n-type GAAFET with two nanosheets at the bottom. In some other embodiments, the number of nanosheets for each transistor may not be equal and may be some number other than two.

[0022] The gate structure 202 forms a CFET channel that surrounds the four nanosheets and extends beyond the stack. The CFET channel, which is the portion of the nanosheets that is covered by the gate structure 202, is not visible in FIGS. 2A and 2B. The first channel of the first transistor 200A comprises portions of the top two nanosheets that are buried in the gate structure 202, and the second channel comprises similar portions of the bottom two nanosheets. The lateral dimension of the nanosheet stack parallel to the gate structure 202 is the width W of the diffusion area. D(indicated by a double-headed arrow in FIG. 2A). In this embodiment, the gate structure 202 is shared between a pair of stacked transistors. However, it will be appreciated that a split-gate CFET structure may also be used. In a split-gate CFET structure, the gate electrodes of each of the stacked transistors of the split-gate CFET may be independently energized.

[0023] The portion of the nanosheet extending from under the gate outside the CFET channel is the CFET S / D 208 shown in Figure 2A. The CFET S / D 208 has a pair of S / D regions along two opposing sides of the gate structure 202, for a total of four S / D regions. In Figure 2A, a first (top) S / D region 204 comprising the nanosheet of the first transistor 200A and a second (bottom) S / D region 206 comprising the nanosheet of the second transistor 200B are visible on one side of the gate structure 202.

[0024] CFET S / D 208 may be configured to construct four S / D interconnect lines, each line connecting to a respective S / D region. In Figures 2A and 2B, a first (top) S / D interconnect line 224 (connected to first S / D region 204) and a second (bottom) S / D interconnect line 226 (connected to second (bottom) S / D region 206) run in parallel along one side of gate structure 202. S / D interconnect lines such as first (top) S / D interconnect line 224 and second (bottom) S / D interconnect line 226 may be used as local interconnect tracks to directly couple adjacent CFET S / D regions along a column of CFETs.

[0025] The S / D interconnect lines may also be coupled to a BEOL metal interconnect system using vertical conductive connectors, and thereby to electrodes of various other circuit components. For example, the perspective view of CFET 200 in FIG. 2A shows a second conductive pillar 222 that provides a connection between a first (top) S / D interconnect line 224 and a metal interconnect line 220 in the wiring level above the first (top) S / D interconnect line 224. A third conductive pillar 214 in FIG. 2A, which is higher than the second conductive pillar 222, connects a second (bottom) S / D interconnect line 226 to the metal interconnect line 220. Because the S / D interconnect lines (e.g., first (upper) S / D interconnect line 224 and second (lower) S / D interconnect line 226) are connected to their respective S / D regions (e.g., first (upper) S / D region 204 and second (lower) S / D region 206), the conductive pillars connecting the S / D interconnect lines to the metal interconnect lines (e.g., metal interconnect line 220) may be considered S / D contacts.

[0026] In this embodiment, metal interconnect line 220 is a wire in the lowest interconnect level above CFET 200. Metal interconnect line 220 in the lowest interconnect level above CFET 200 is typically oriented perpendicular to the transistor gates to facilitate routing of signals and power supplies between transistors in different columns of the standard cell. Much of the routing of signals between transistors in different rows of the standard cell may be accomplished by metal gate electrodes of gate structure 202 and first (top) and second (bottom) S / D interconnect lines 224 and 226. Diffusion break wire 210 provides yet another routing track along the same direction as gate structure 202 and first (top) and second (bottom) S / D interconnect lines 224 and 226.

[0027] 2B shows a diffusion break wire 210 and a connector that makes the connection to the gate structure 202. The diffusion break wire 210 is disposed in a diffusion break line that is formed parallel to the gate structure 202 of the CFET 200. As shown in FIG. 2B, a first conductive pillar 230 provides an electrical connection between the conductive core of the diffusion break wire 210 and a metal interconnect line 220 above the diffusion break wire 210. The gate structure 202 is connected to another metal interconnect line 220 above the gate structure 202 through another vertical conductive pillar referred to as a gate contact 236.

[0028] In addition to the vertical connectors, such as the first conductive pillar 230, which make an electrical connection through the top surface of the diffusion break wire 210, a lateral electrical connection may be made to the conductive core of the diffusion break wire 210 through the sidewalls of the diffusion break wire 210. The lateral connectors may be lateral conductive wire bridges between the conductive core of the diffusion break wire 210 and adjacent S / D interconnect lines. There may be respective first and second wire bridges connecting through one sidewall of the diffusion break wire 210 to provide a first (top) S / D interconnect line 224 and a second (bottom) S / D interconnect line 226 at two different vertical locations in a CFET structure, such as the CFET 200. A second wire bridge 232 is shown in FIG. 2B connecting the conductive core of the diffusion break wire 210 to the second (bottom) S / D interconnect line 226.

[0029] A second wire bridge, such as the second wire bridge 232 shown in FIG. 2B, is particularly useful in embodiments in which the conductive cores of the diffusion break wire are a vertical stack with a second conductive core formed below the first conductive core and an insulating layer electrically insulating the two conductive cores from each other. The second conductive core of the two-tier diffusion break wire may also be coupled to an electrode of a circuit component using a conductive pillar (referred to as a fourth conductive pillar) that provides a connection to the lower portion of the two-tier diffusion break wire. The fourth conductive pillar may be formed in a deep hole extending below the upper portion of the two-tier diffusion break wire to expose the top surface of the second (lower) conductive core of the two-tier diffusion break wire. The deep hole may be filled to form a fourth conductive pillar, where the filling includes an inner conductor. The inner conductor may be insulated from any adjacent portion of the first (upper) conductive core of the two-tier diffusion break wire by an outer insulating jacket.

[0030] In some embodiments, if the IC technology provides an interconnect level (e.g., for buried power lines) in a portion of the substrate below the transistors, it may be possible to fabricate a conductive pillar that makes an electrical connection through the bottom wall of the diffusion break wire (e.g., diffusion break wire 210).

[0031] A method for forming a diffusion break wire in a standard cell for digital CMOS technology using CFET, for example the diffusion break wire 112A in the simplified standard cell layout (first layout 101A) shown in FIG. 1, is described with reference to FIGS. 3A-3D. FIG. 3E shows an alternative cross-sectional view of the simplified standard cell shown in FIG. 3D. The vertical cross-sections in FIGS. 3A-3E are of a simplified standard cell 300 having the first layout 101A along the cut lines 3A-3E shown by the dashed and dotted lines in FIG. 1.

[0032] As described above with reference to FIGS. 2A and 2B, the example CFET is a vertical stack of a p-type GAAFET on top of an n-type GAAFET. The CFET channel comprises a nanosheet stack of four nanosheets, the top two nanosheets being used to form the p-type GAAFET and the bottom two nanosheets being used for the n-type GAAFET. The CFET is fabricated using a replacement metal gate (RMG) method. In the RMG method, a CFET dummy structure comprising the CFET channel, CFET S / D, and CFET S / D interconnect structure (described above with reference to FIGS. 2A and 2B) is first formed along with a sacrificial (or dummy) CFET gate structure. The dummy CFET structure is embedded in an insulating layer, referred to as a pre-metal dielectric (PMD) layer. The sacrificial CFET gate structure is then removed and replaced with a gate stack comprising a high-k gate dielectric layer and a metal gate electrode, referred to as a HKMG gate stack, to form the CFET gate structure.

[0033] The CFET dummy structure with the sacrificial gate structure is formed not only to later form the active transistor, but also to form a diffusion break trench that may later be filled to form a diffusion break wire, as described further below.

[0034] Figure 3A shows a cross-sectional view of the simplified standard cell 300 shown in the first layout 101A shown in Figure 1. The cross-sectional view shown in Figure 3A shows the vertical structure of the cell at a stage of fabrication after the CFET dummy structures have been formed and embedded in the PMD layer 308. The CFET S / D interconnect structures (described with reference to Figures 2A and 2B) are not shown for clarity.

[0035] As shown in FIG. 3A, the CFET nanosheet stack has four nanosheets that also extend in a direction perpendicular to the plane of the cross section. The nanosheet stack is patterned to form a line of nanosheet stacks 305. Nanosheets 304 of the line of nanosheet stacks 305 are the two top nanosheets that may be used to form a p-type GAAFET (first transistor of the CFET) and the two bottom nanosheets may be used to form an n-type GAAFET (second transistor of the CFET). The sacrificial gate structure 302 is depicted in FIG. 3A as a semi-transparent feature to show that the nanosheets 304 and 305 of the nanosheet stack 305 are embedded within the sacrificial gate structure 302. The sacrificial gate structure 302 may comprise, for example, a thin silicon oxide layer and a polycrystalline or amorphous silicon layer formed on the silicon oxide layer.

[0036] 3B, the sacrificial gate structure 302 has been removed and trenches 310 having depth dimensions similar to the height dimensions of the sacrificial gate structure 302 are formed in the PMD layer 308. The sacrificial gate structure 302 has been removed using a selective etching chemistry to expose the nanosheets 304 and 306 within the trenches 310. After the sacrificial gate structure 302 has been removed, a patterned diffusion cut etch may be performed on selected trenches 310.

[0037] FIG. 3C shows the vertical structure of the simplified standard cell 300 after a diffusion cut etch is performed using a patterned etch mask to remove exposed nanosheets 304 and 306 from selected trenches to form diffusion break trenches 320. The diffusion break trenches 320 divide the lines of the nanosheet stacks 305 into line segments that are diffusion areas for the CFETs, as described above. As will be further described below, a portion of the diffusion break trenches 320 may then be filled with an insulating material to form a non-conductive diffusion break line. The remaining diffusion break trenches 320 are used to form conductive diffusion break wires. It should be noted that the conductive cores of the diffusion break wires are formed in the areas vacated by removing the sacrificial gate structures 302, so that the dimensions of the diffusion break wires match the shapes of the respective sacrificial gate structures.

[0038] In Fig. 3D, the trench 310 in the diffusion area and the diffusion break trench 320 between adjacent diffusion areas are filled and etched back. The trench 310 in the diffusion area is selectively filled with an HKMG gate stack and etched back to form a CFET gate structure 350, as shown in Fig. 3D. The two diffusion break trenches 320 located at the two ends of the simplified standard cell 300 are selectively filled with an insulating material (e.g., silicon oxide) and planarized using an etch-back process to form two non-conductive diffusion break lines 330.

[0039] The remaining diffusion break trench 320 in the simplified standard cell 300 is used to form a diffusion break wire 340. As shown in FIG. 3D, an insulating outer liner 342 is formed along the sidewalls and bottom wall of the diffusion break trench 320. The remainder of the diffusion break trench 320 is filled with a conductive material to form a conductive core 344. The insulating outer liner 342 may comprise a dielectric material such as silicon oxide or silicon nitride, and the conductive material of the conductive core 344 may comprise a metallic material, such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, aluminum, a metal alloy, and a metal silicide.

[0040] After the diffusion break wire 340 is formed, vertical and lateral connectors may be formed to connect the diffusion break wire to electrodes of transistors and other circuit components, as described above with reference to Figures 2A and 2B. The other circuit components may include active elements including diodes and transistors, and passive elements including capacitors, inductors, and resistors. Note that both the transistor gate and the diffusion break wire are formed in a trench vacated by a sacrificial gate structure. Thus, the height H of the diffusion break wire 210 in Figure 2B (as well as the diffusion break wires 340 and 360 in Figures 3D and 3E) is 1 / 100. DBW (indicated by a double-headed arrow) indicates the height H of the gate structure 202 in FIG. 2B (as well as the gate structure 350 in FIGS. 3D and 3E). G (indicated by another double-headed arrow in FIG. 2B). The similarity in height may provide an advantage in using the same process to form the first conductive pillar 230 and the gate contact 236.

[0041] FIG. 3E illustrates another embodiment of a diffusion break wire 340 having a two-tier conductive structure that differs from the one-tier conductive structure of the diffusion break wire 360 ​​in FIG. 3D. As shown in FIG. 3E, the insulating outer liner 362 of the diffusion break wire 360 ​​is similar to the insulating outer liner 342 of the diffusion break wire 340 in FIG. 3D. However, unlike the diffusion break wire 340 (shown in FIG. 3D), the diffusion break wire 360 ​​has, in addition to the insulating outer liner 362, a first conductive core 364, a second conductive core 366, and an insulating layer 368 between the first conductive core 364 and the second conductive core 366. The use of vertical conductive pillars and lateral conductive wire bridges to connect the two-tier conductive cores of the diffusion break wire 360 ​​was described above with reference to FIG. 2B. The processes performed to form the trench 310 and diffusion break trench 320 in the PMD layer 308 for the two-level conductive structure of the diffusion break wire 340 may be similar to those used to form the diffusion break wire 360, as described above with reference to Figures 3A-3C. As shown in Figure 3E, the top conductor of the two-level conductive structure is a first conductive core 364 and the bottom conductor is a second conductive core 366. The diffusion break trench 320 may be filled using a multi-step process to sequentially form a lower level comprising the second conductive core 366 before forming an upper level comprising the first conductive core 364.

[0042] 4A-4B illustrate vertical and lateral connections to diffusion break wires with reference to a plan view and respective cross-sectional views of a simplified standard cell 370. Standard cell 370 is similar to the simplified standard cell described with reference to first layout 101A in FIG 1 and the cross-sectional views of standard cell 300 in FIGS 3A-3E.

[0043] As described above with reference to FIG. 2B, vertically conducting conductive pillars and laterally conducting wire bridges may be formed to provide electrical connections to the top surface and sidewalls of the conductive core of the diffusion break wire, respectively. A first wire bridge contacts the top portion of the diffusion break wire, and a second wire bridge contacts the bottom portion of the diffusion break wire. The first conductive pillar contacts the top surface of the first conductive core, which is the conductor in a one-tier diffusion break wire or the top conductor in a two-tier diffusion break wire. As described above, a fourth, higher conductive pillar contacts the top surface of the second conductive core, which is the bottom conductor in a two-tier diffusion break wire.

[0044] The cross-sectional views of standard cell 370 in Figures 4A and 4B begin with the cross-sectional views of standard cell 300 shown in Figures 3D and 3E. Similar to Figures 3D and 3E, Figures 4A and 4B also show a simplified standard cell 370 having one row of nanosheet stacks 305 and six columns with two non-conductive diffusion break lines 330, three CFET gate structures 350, and one diffusion break wire.

[0045] Figure 4A shows a one layer diffusion break wire 340 having a first conductive core 344 insulated by an insulating outer liner 342. A first conductive pillar 374 in Figure 4A is shown contacting the top surface of the first conductive core 344.

[0046] 4B illustrates a two tier diffusion break wire 360 ​​having a second conductive core 366 insulated by an insulating outer liner 362 and a fourth conductive pillar 380. The fourth conductive pillar 380 includes an inner conductor 384 and an outer insulating jacket 382. The inner conductor 384 of the fourth conductive pillar 380 in FIG. 4B is shown contacting the top surface of the second conductive core 366.

[0047] Also, similar to Figures 3D and 3E, the complete CFET S / D interconnect structure (described with reference to Figures 2A and 2B), including the first (top) and second (bottom) S / D interconnect lines, is not shown in Figures 4A and 4B for clarity, as the S / D interconnect lines are further illustrated below in a more complex standard cell layout 400 shown in Figures 5A-5C.

[0048] In addition to the structure of the standard cell 300 shown in Fig. 3D, Figs. 4A and 4B show a metal interconnect line 372, a first conductive pillar 374, a fourth conductive pillar 380, a gate contact 376 buried in an interlayer dielectric (ILD) layer 390, and a second wire bridge 378 in the standard cell 370. Similar to the second (lower) S / D interconnect line 226 and the second wire bridge 232 in Fig. 2B, the second wire bridge 378 is physically connected at one end to the lower portion of the first conductive core 344 of the one-level diffusion break wire 340 in Fig. 4A and to the second (lower) conductive core of the two-level diffusion break wire 360 ​​in Fig. 4B. The opposite end is connected to a respective second (lower) S / D interconnect line (not shown) originating from the nanosheet 306 of the first CFET (shown as CFET1 in Figs. 4A and 4B) brought out to the left of the diffusion break wire 340. The lower ends of the first conductive pillar 374 and the fourth conductive pillar 380 are physically connected to the upper surface of the first conductive core 344 of the one-tier diffusion break wire 340 and the upper surface of the second conductive core 366 of the two-tier diffusion break wire 360, respectively. The upper ends of the first conductive pillar 374 and the fourth conductive pillar 380 make a physical connection to the bottom surface of the metal interconnect line 372. The fourth conductive pillar 380 may be surrounded by an outer insulating jacket 382 to prevent unintentional electrical shorting between the fourth conductive pillar 380 and the adjacent first (upper) conductive core of the two-tier diffusion break wire 360. (The first conductive core 364 is shown in FIG. 3E but is not visible in FIG. 4B.) The metal interconnect line 372 is connected to the upper end of the gate contact 376. The bottom end of gate contact 376 is physically connected to the common gate of CFET gate structure 350 of a second CFET (shown as CFET2 in FIGS. 4A and 4B). A conductive signal path established between the second S / D region of CFET1 (the lower S / D region comprising nanosheet 306) and CFET gate structure 350 of CFET2 via diffusion break wire 340 is shown by a dashed line in FIGS. 4A and 4B.

[0049] 5A-5C show an example standard cell layout 400 demonstrating the improved routability achieved by the connection to an example two-tier diffusion break wire 430. Note that for clarity, the power supply lines have been removed from the layout views in FIGS. 5A and 5B. The same standard cell layout 400 is shown in FIGS. 5A-5C. FIG. 5A shows the connection made by the first (top) conductive core of the two-tier diffusion break wire 430, and FIG. 5B shows the connection made by the second (bottom) conductive core of the two-tier diffusion break wire 430. FIG. 5C shows a cross-sectional view of the two-tier diffusion break wire 430 showing the first conductive pillar 424 connecting the first conductive core 564 of the two-tier diffusion break wire 430 and the fourth conductive pillar 427 connecting the second conductive core 566 of the two-tier diffusion break wire 430 to the metal interconnect line 420 of the lowest interconnect level above the diffusion break wire 430.

[0050] The various depicted layers shown in Figures 5A and 5B include a gate structure 412 and a diffusion area 410 depicted perpendicular to each other. A transistor channel 414 is formed at the intersection of the gate structure 412 and the diffusion area 410. Two non-conductive diffusion break lines 402 are drawn at two ends of the standard cell layout 400 to isolate the standard cell from adjacent standard cells that may be located along the same row. First (top) and second (bottom) S / D interconnect lines 404 and 408 are drawn parallel to the gate structure 412. As explained above, the S / D interconnect lines 404 and 408 are physically connected to their respective diffusion areas 410. A metal interconnect line 420 is drawn perpendicular to the S / D interconnect lines 404 and 408. Vertical connections to the metal interconnect lines 420 are made by conductive pillars. The various conductive pillars in the standard cell layout 400 include a gate contact 421 that connects to the gate structure 412, and first and fourth conductive pillars 424 and 427 that connect to first (top) and second (bottom) conductive cores, respectively, of a two-tier diffusion break wire 430. In some embodiments, the gate contact 421 and the first conductive pillar 424 may be formed simultaneously. The second and third conductive pillars 406 and 426 connect the metal interconnect line 420 to the first (top) and second (bottom) S / D interconnect lines 404 and 408, respectively. The standard cell layout 400 does not use a first lateral bridge to connect the first (top) S / D interconnect line 404 to a first conductive core of the two-level diffusion break wire 430, but a second lateral bridge 428 is drawn connecting the second (bottom) S / D interconnect line 408 to a second (bottom) conductive core of the two-level diffusion break wire 430.

[0051] The connection paths are shown by solid lines for row-parallel lateral segments comprising metal interconnect lines 420 and column-parallel lateral segments comprising first (top) and second (bottom) S / D interconnect lines 404 and 408. Dashed lines are used to indicate column-parallel lateral segments comprising diffusion break wires 430 or row-parallel lateral segments comprising second (bottom) lateral bridge 428. Solid circles indicate vertical segments comprising the first 424, second 406, third 426, or fourth 427 conductive pillars or gate contacts 421.

[0052] 5A shows that the first (top) S / D interconnect line 404 (connected to the respective S / D regions of the first CFET T1) is routed to couple to the first (top) S / D interconnect lines 404 of the second and third CFETs T2 and T3 and to the bottom S / D interconnect line 408 of the fourth CFET T4. Starting from the first (top) S / D interconnect line 404 of the CFET T1, the signal may be connected to a metal interconnect line 420 using a second conductive pillar 406. A first conductive pillar 424 connects the signal from the metal interconnect line 420 to a first (top) conductive core of a two-level diffusion break wire 430. Another first conductive pillar 424 connects the signal from the first conductive core of the diffusion break wire 430 to another metal interconnect line 420. This metal interconnect line 420 distributes the signal to the first (top) S / D interconnect line 404 of the second and third CFETs T2 and T3 using the second conductive pillar 406, and to the second (bottom) S / D interconnect line 408 of the fourth CFET T4 using the third conductive pillar 426.

[0053] 5B shows the bottom S / D interconnect line of the third CFET T3 connected to the second conductive core of the diffusion break wire 430. A signal may be connected from the second conductive core of the diffusion break wire 430 to the metal interconnect line 420 using a fourth conductive pillar 427. A signal may be coupled from the metal interconnect line 420 to the second (bottom) S / D interconnect line 408 of the fifth CFET T5.

[0054] A cross-sectional view of a two-tier diffusion break wire 430 in a standard cell layout 400 is shown in Figure 5C. A portion of the respective layout 400 is copied from Figure 5B and displayed on the right side of Figure 5C for reference. The cross-sectional view on the left shows a two-tier diffusion break wire 430 with first (top) and second (bottom) conductive cores 564 and 568 insulated from each other by an insulating layer 568. The diffusion break wire 430 can be seen to be embedded in a PMD layer 508.

[0055] As shown in FIG. 5C, two first conductive pillars 424 connect the first conductive core 564 of the two-level diffusion break wire 430 to the metal interconnect line 420 of the lowest interconnect level above the diffusion break wire 430. The conductive pillars are embedded in the ILD layer 590. The cross-sectional view of FIG. 5C further includes one fourth conductive pillar 427 (as seen in the layout 400) that connects the second conductive core 566 of the two-level diffusion break wire 430 to the metal interconnect line 420 near the edge of the standard cell boundary. As described above, the fourth conductive pillar 427 includes an inner conductor 584 and an outer insulating jacket 584. The inner conductor 584 forms a vertical connection between the interconnect line 420 and the second conductive core 566 above. The outer insulating jacket 584 insulates the inner conductor 584 from the adjacent first conductive core 564.

[0056] The example illustrated by FIGS. 5A-5C illustrates how the embodiments described in this disclosure may be applied to alleviate some of the wiring congestion in aggressively scaled standard logic cells.

[0057]

[0023] Exemplary embodiments of the present invention are summarized herein. Other embodiments can be seen throughout the specification and claims appended hereto.

[0058] Example 1. A semiconductor device comprising: a first three-dimensional (3D) transistor and a second 3D transistor oriented parallel to the first 3D transistor disposed in a substrate, the first 3D transistor and the second 3D transistor being a subset of a plurality of transistors; a diffusion break trench disposed in a region laterally separating the second 3D transistor from the first 3D transistor, the diffusion break trench having a length extending along a lateral direction; and a diffusion break wire filling the diffusion break trench, the diffusion break wire having a height along a vertical direction, and gates of the plurality of transistors being made from a different conductive material than the diffusion break wire.

[0059] Example 2. The device of Example 1, wherein the first 3D transistor includes a first nanowire transistor (NWT), the second 3D transistor includes a second NWT oriented parallel to the first NWT disposed within a substrate, and the first NWT and the second NWT include multiple nanowires stacked along a vertical direction.

[0060] Example 3. The device of one of Examples 1 or 2, wherein the first 3D transistor comprises a first nanosheet transistor (NT), the second 3D transistor comprises a second NT oriented parallel to the first NT disposed in the substrate, and the first NT and the second NT comprise a plurality of nanosheets stacked along a vertical direction.

[0061] Example 4. The device of any one of Examples 1-3, wherein the first 3D transistor includes a first complementary field effect transistor (CFET), the second 3D transistor includes a second CFET oriented parallel to the first CFET disposed in the substrate, the first CFET includes a first NT, and the second CFET includes a second NT.

[0062] Example 5. The semiconductor device of any one of Examples 1-4, wherein the diffusion break wire includes an insulating outer liner and a conductive core that is electrically insulated from the first 3D transistor and the second 3D transistor by the outer liner.

[0063] Example 6. The semiconductor device of one of Examples 1-5, wherein the diffusion break wire includes an insulating outer liner, a first conductive core electrically insulated from the first 3D transistor and the second 3D transistor by the outer liner, a second conductive core electrically insulated from the first 3D transistor by the outer liner, and an insulating layer between the first conductive core and the second conductive core, electrically insulating the first conductive core from the second conductive core.

[0064] Example 7. A method of forming a semiconductor device, the method comprising: forming a first three-dimensional (3D) transistor in a first region and forming a second 3D transistor in a second region, the second 3D transistor being oriented parallel to the first 3D transistor; forming a diffusion break trench between the second 3D transistor and the first 3D transistor, the diffusion break trench extending along a first lateral direction; and forming a diffusion break wire by filling the diffusion break trench, the diffusion break wire having a height along a vertical direction, and filling the diffusion break trench comprises forming a conductive core, and gates of the first and second transistors are made from a different conductive material than the diffusion break wire.

[0065] Example 8. The method of Example 7, wherein the first 3D transistor includes a first nanowire transistor (NWT), the second 3D transistor includes a second NWT oriented parallel to the first NWT disposed within a substrate, and the first NWT and the second NWT include a plurality of nanowires stacked along a vertical direction.

[0066] Example 9. The method of any one of Examples 7 or 8, wherein filling the diffusion break trench further comprises forming a further conductive core separated from the conductive core by an insulating layer.

[0067] Example 10. The method of any one of Examples 7-9, wherein the first 3D transistor comprises a first nanosheet transistor (NT), the second 3D transistor comprises a second NT oriented parallel to the first NT disposed within the substrate, and the first NT and the second NT comprise a stack of nanosheets stacked along a vertical direction.

[0068] Example 11. The method of any one of examples 7-10, wherein the first 3D transistor includes a first complementary field effect transistor (CFET), the second 3D transistor includes a second CFET oriented parallel to the first CFET disposed in the substrate, the first CFET includes a first NT, and the second CFET includes a second NT.

[0069] Example 12. The method of any one of Examples 7-11, wherein forming the diffusion break trench includes forming an NT dummy structure on the substrate, the NT dummy structure including a sacrificial NT gate structure surrounding a portion of the stack of nanosheets, etching the sacrificial NT gate structure to expose the portion of the stack of nanosheets, and etching the exposed portion of the stack of nanosheets.

[0070] Example 13. The method of any one of Examples 7-12, further comprising forming a vertical pillar physically connected to the conductive core and coupling the pillar to a wiring level above the diffusion break wire.

[0071] Example 14. The method of any one of Examples 7-13, further comprising forming a wire bridge physically connecting the conductive core to an S / D interconnect line that is connected to the S / D region of the first NT.

[0072] Example 15. The method of any one of Examples 7-14, wherein forming the diffusion break trench includes performing a sequential process flow including: forming a plurality of NT dummy structures oriented parallel to one another, each of the plurality of NT dummy structures including a sacrificial NT gate structure, an NT channel including a stack of nanosheets, an NT source / drain (S / D), and an NT S / D interconnect structure, the sacrificial NT gate structure surrounding each nanosheet of the NT channel; embedding the plurality of NT dummy structures in a pre-metal dielectric (PMD) layer, the embedding including exposed surfaces of the sacrificial NT gate structures; selectively removing the sacrificial NT gate structures, the selective removal forming a plurality of trenches and exposing the plurality of NT channels inside the trenches; and removing the exposed NT channels from a selected subset of the plurality of trenches using a patterned etch mask, the removing the exposed NT channels from each selected trench forming a respective diffusion break trench along a first lateral direction.

[0073] Example 16. The method of any one of Examples 7-15, wherein forming the plurality of NT dummy structures includes: patterning a stack of nanosheets to form a plurality of parallel lines of nanosheet stacks extending along a second lateral direction perpendicular to the first lateral direction; forming a plurality of parallel sacrificial gate structures embedding portions of the lines of nanosheet stacks, each sacrificial gate structure of the plurality of sacrificial gate structures having a length extending along the first lateral direction; forming a plurality of NT S / Ds including portions of the lines of nanosheet stacks extending outside the sacrificial gate structures; and forming a plurality of NT S / D interconnect structures by configuring regions of the S / Ds to form respective S / D interconnect lines.

[0074] Example 17. A semiconductor device comprising: a first three-dimensional (3D) transistor disposed in a substrate; a first circuit component disposed in the substrate; a diffusion break trench having a length extending along a first lateral direction; and a diffusion break wire disposed in the diffusion break trench, the diffusion break wire including an insulating outer liner and a first conductive core electrically coupled to an electrode of the first 3D transistor and an electrode of the first circuit component.

[0075] Example 18. The device of Example 17, wherein the first 3D transistor includes a first nanowire transistor (NWT), the second 3D transistor includes a second NWT oriented parallel to the first NWT disposed within a substrate, and the first NWT and the second NWT include multiple nanowires stacked along a vertical direction.

[0076] Example 19. The semiconductor device of any one of Examples 17 or 18, wherein the first circuit component is a second 3D transistor.

[0077] Example 20. The semiconductor device of any one of Examples 17-19, wherein the first conductive core is physically connected to a vertically conductive first pillar, the first pillar being connected to a wiring level above the diffusion break wire.

[0078] Example 21. The device of any one of Examples 17-20, wherein the first 3D transistor comprises a first nanosheet transistor (NT), the second 3D transistor comprises a second NT oriented parallel to the first NT disposed within a substrate, and the first NT and second NT comprise multiple nanosheets stacked along a vertical direction.

[0079] Example 22. The device of any one of Examples 17-21, wherein the first 3D transistor includes a first complementary field effect transistor (CFET), the second 3D transistor includes a second CFET oriented parallel to the first CFET disposed in the substrate, the first CFET includes a first NT, and the second CFET includes a second NT.

[0080] Example 23. The semiconductor device of any one of Examples 17-22, wherein the first CFET includes a vertical stack of a first gate-all-around field effect transistor (GAAFET) including a first S / D region connected to a first S / D interconnect line, and a second GAAFET including a second S / D region connected to a second S / D interconnect line.

[0081] Example 24. The semiconductor device of any one of Examples 17-23, further comprising a first wire bridge, the first wire bridge physically connecting the first conductive core to the first S / D interconnect line, and the first CFET being laterally adjacent to the diffusion break wire.

[0082] Example 25. The semiconductor device of any one of Examples 17-24, wherein the first S / D interconnect line is physically connected to the S / D region of the third CFET.

[0083] Example 26. A semiconductor device of any one of Examples 17-25, wherein the first S / D interconnect line is physically connected to a vertically conductive second pillar, the second pillar being connected to a wiring level above the first S / D interconnect line.

[0084] Example 27. The semiconductor device of one of Examples 17 to 26, wherein the diffusion break wire further includes a second conductive core disposed in the diffusion break trench below the first conductive core, the second conductive core being electrically insulated from the first conductive core by an insulating layer, and the second conductive core being electrically coupled to an electrode of the second CFET and an electrode of the second circuit component.

[0085] Example 28. The semiconductor device of any one of Examples 17-27, further including a second wire bridge, the second wire bridge physically connecting the second conductive core to a second S / D interconnect line that is connected to a second S / D region of the second CFET, the second CFET being laterally adjacent to the diffusion break wire.

[0086] Example 29. The semiconductor device of any one of Examples 17-28, wherein the second S / D interconnect line connected to the second S / D region of the second CFET is physically connected to the S / D region of the third CFET.

[0087] Example 30. The semiconductor device of any one of Examples 17-29, wherein a second S / D interconnect line connected to the second S / D region of the second CFET is physically connected to a vertically conductive third pillar, the third pillar being connected to an interconnect level above the second S / D interconnect line.

[0088] Example 31. The semiconductor device of any one of Examples 17-30, wherein the second conductive core is physically connected to a vertically conducting fourth pillar, the fourth pillar being insulated from the first conductive core, and the fourth pillar being connected to a wiring level above the diffusion break wire.

[0089] While the present invention has been described with reference to exemplary embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the exemplary embodiments, as well as other embodiments of the invention, will become apparent to those skilled in the art upon reference to the description. It is therefore intended that the appended claims cover such modifications or embodiments.

Claims

1. 1. A semiconductor device comprising: a first three-dimensional (3D) transistor disposed in a substrate and a second 3D transistor oriented parallel to the first 3D transistor, the first 3D transistor and the second 3D transistor being a subset of a plurality of transistors; a diffusion break trench disposed in a region laterally separating the second 3D transistor from the first 3D transistor, the diffusion break trench having a length extending along a lateral direction; a diffusion break wire filling the diffusion break trench, the diffusion break wire having a height along a vertical direction, and gates of the plurality of transistors being made from a different conductive material than the diffusion break wire.

2. 2. The semiconductor device of claim 1, wherein the first 3D transistor comprises a first nanowire transistor (NWT), the second 3D transistor comprises a second NWT oriented parallel to the first NWT disposed in a substrate, and the first NWT and the second NWT comprise multiple nanowires stacked along a vertical direction.

3. 2. The semiconductor device of claim 1, wherein the first 3D transistor comprises a first nanosheet transistor (NT), and the second 3D transistor comprises a second NT oriented parallel to the first NT disposed in a substrate, the first NT and the second NT comprising multiple nanosheets stacked along a vertical direction.

4. 4. The semiconductor device of claim 3, wherein the first 3D transistor comprises a first complementary field effect transistor (CFET), the second 3D transistor comprises a second CFET oriented parallel to the first CFET disposed in a substrate, the first CFET comprising the first NT, and the second CFET comprising the second NT.

5. The diffusion break wire is an insulating outer liner; 2. The semiconductor device of claim 1 , further comprising: a conductive core electrically isolated from the first 3D transistor and the second 3D transistor by the insulating outer liner.

6. The diffusion break wire is an insulating outer liner; a first conductive core electrically isolated from the first 3D transistor and the second 3D transistor by the insulating outer liner; a second conductive core electrically isolated from the first 3D transistor by the insulating outer liner; 10. The semiconductor device of claim 1 , further comprising: an insulating layer between the first conductive core and the second conductive core, the insulating layer electrically insulating the first conductive core from the second conductive core.

7. 1. A method of forming a semiconductor device, comprising: forming a first three-dimensional (3D) transistor in a first region and a second 3D transistor in a second region oriented parallel to the first 3D transistor; forming a diffusion break trench between the second 3D transistor and the first 3D transistor, the diffusion break trench extending along a first lateral direction; forming a diffusion break wire by filling the diffusion break trench, the diffusion break wire having a height along a vertical direction, and filling the diffusion break trench includes forming a conductive core, and gates of the first and second 3D transistors are made from a different conductive material than the diffusion break wire.

8. 8. The method of claim 7, wherein the first 3D transistor comprises a first nanowire transistor (NWT), the second 3D transistor comprises a second NWT oriented parallel to the first NWT disposed in a substrate, and the first NWT and the second NWT comprise multiple nanowires stacked along a vertical direction.

9. 8. The method of claim 7, wherein filling the diffusion break trench further comprises forming a further conductive core separated from the conductive core by an insulating layer.

10. 8. The method of claim 7, wherein the first 3D transistor comprises a first nanosheet transistor (NT), and the second 3D transistor comprises a second NT oriented parallel to the first NT disposed in a substrate, the first NT and the second NT comprising a stack of nanosheets stacked along a vertical direction.

11. 11. The method of claim 10, wherein the first 3D transistor comprises a first complementary field effect transistor (CFET), the second 3D transistor comprises a second CFET oriented parallel to the first CFET disposed in a substrate, the first CFET comprising the first NT, and the second CFET comprising the second NT.

12. Forming the diffusion break trench includes: forming an NT dummy structure on the substrate, the NT dummy structure comprising a sacrificial NT gate structure surrounding a portion of the stack of nanosheets; Etching the sacrificial NT-gate structure to expose a portion of the stack of nanosheets; and etching the exposed portions of the stack of nanosheets.

13. The method of claim 10 , further comprising forming a vertical pillar physically connected to the conductive core, and coupling the vertical pillar to a wiring level above the diffusion break wire.

14. 11. The method of claim 10, further comprising forming a wire bridge that physically connects the conductive core to an S / D interconnect line that is connected to an S / D region of the first NT.

15. 1. A semiconductor device comprising: a first three dimensional (3D) transistor disposed in a substrate; a first circuit component disposed within the substrate; a diffusion break trench having a length extending along a first lateral direction; A diffusion break wire disposed in the diffusion break trench, an insulating outer liner; a diffusion break wire comprising a first conductive core electrically coupled to an electrode of the first 3D transistor and an electrode of the first circuit component.

16. 16. The semiconductor device of claim 15, wherein the first 3D transistor comprises a first nanowire transistor (NWT), and the second 3D transistor comprises a second NWT oriented parallel to the first NWT disposed in a substrate, the first NWT and the second NWT comprising a plurality of nanowires stacked along a vertical direction.

17. 16. The semiconductor device of claim 15, wherein the first conductive core is physically connected to a vertically conducting first pillar, the first pillar being connected to a wiring level above the diffusion break wire.

18. 16. The semiconductor device of claim 15, wherein the first 3D transistor comprises a first nanosheet transistor (NT), and the second 3D transistor comprises a second NT oriented parallel to the first NT disposed in a substrate, the first NT and the second NT comprising multiple nanosheets stacked along a vertical direction.

19. 20. The semiconductor device of claim 18, wherein the first 3D transistor comprises a first complementary field effect transistor (CFET), the second 3D transistor comprises a second CFET oriented parallel to the first CFET disposed in a substrate, the first CFET comprising the first NT, and the second CFET comprising the second NT.

20. 20. The semiconductor device of claim 19, wherein the first CFET comprises a vertical stack of a first gate-all-around field effect transistor (GAAFET) having a first S / D region connected to a first S / D interconnect line and a second GAAFET having a second S / D region connected to a second S / D interconnect line.

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