Iterative Hybrid Matrix Multiplier

Abstract

The hybrid time multiplexing iterative multiply-accumulate circuit comprises a product storage circuit, a multiplication circuit operable to receive a first input value, receive a second input value, generate a product of the first input value and the second input value, and store the product in the product storage circuit, an integration value storage circuit for storing an integration value, and an integration switch connecting the product storage circuit and the integration value storage circuit, operable to electrically connect the product storage circuit and the integration value storage circuit in parallel or to electrically disconnect the product storage circuit and the integration value storage circuit.

Description

[Technical field]

[0001] The present disclosure relates generally to processing architectures, devices, and methods for matrix multiplication, and more particularly to hybrid multiply-accumulate circuits. [Background technology]

[0002] Matrix multiplication is an important operation in many mathematical computations. For example, in linear algebra, matrix multiplication can be used to solve simultaneous linear equations, such as differential equations. Such mathematical computations have applications in, for example, pattern matching, artificial intelligence, analytic geometry, engineering, physics, natural sciences, computer science, computer animation, and economics. Summary of the Invention [Problem to be solved by the invention]

[0003] Matrix multiplication is typically performed on digital computers running stored programs. The programs describe the operations to be performed, and hardware within the computer, such as digital multipliers and adders, performs the operations. In some computing systems, specially designed hardware can accelerate the speed of calculations. Some applications, especially safety-critical tasks, require real-time processing to provide useful output in a useful time. Furthermore, applications on portable devices have limited power available. Despite these high-speed computing systems, solving problems with large matrices and high data rates can take time and consume more power than necessary. Therefore, there is a need for computing hardware accelerators that can perform matrix multiplication at higher speeds and with lower power consumption. [Means for solving the problem]

[0004] In particular, embodiments of the present disclosure may provide a hybrid computing hardware accelerator for performing matrix multiplication using multiply accumulate operations. The computing hardware accelerator of the present disclosure is comprised of a digital binary single-bit multiplier with an analog accumulate value. The data values ​​of the single-bit multipliers are each stored in a digital memory, and the single-bit multiplication results are stored as charges on capacitors. The charges on the capacitors are combined to sum the values, providing the multiply-accumulate operation. By combining the charges on the capacitors, the sum operation is nearly instantaneous, dependent on the speed at which the charges flow in the conductors, and does not require external power. Thus, embodiments of the present disclosure may provide a very fast and low power multiply-accumulate circuit. Charge is denoted as Q in electronic systems, so each single-bit multiply-accumulate circuit is referred to herein as a qmac. This is a hybrid circuit using digital multiplication and analog accumulation.

[0005] According to an embodiment of the present disclosure, a hybrid multiply-accumulate circuit comprises an array of single-bit multiply-accumulate circuits, each single-bit multiply-accumulate circuit comprising (i) a first storage element for storing a first single-bit value, (ii) a second storage element for storing a second single-bit value, (iii) a bit-multiply circuit for multiplying the first single-bit value by the second single-bit value to compute a product, and (iv) an analog storage circuit, the bit-multiply circuit operable to accumulate a charge in the analog storage circuit representative of the product. The array of single-bit multiply-accumulate circuits is operable to combine the charges accumulated in each analog storage circuit to provide an accumulated charge representative of a sum of the products. The analog storage circuit may be a capacitor.

[0006] According to an embodiment, the hybrid multiply-accumulate circuit comprises a switch circuit coupled to the bit multiplier circuit and the analog storage circuit operable in a first mode to transfer charge from the bit multiplier circuit to the analog storage circuit and in a second mode to isolate the bit multiplier circuit from the analog storage circuit and connect the analog storage circuits of the array together to provide the stored charge. It may also comprise a clear circuit coupled to the analog storage circuits of the array operable to remove charge from the analog storage circuits of the array. The bit multiplier circuit may be a functional AND gate or perform the function of an AND gate.

[0007] In an embodiment of the present disclosure, the hybrid multiply-accumulate circuit includes an analog-to-digital converter that converts accumulated charges connected to analog storage circuits in the array into digital accumulated values. It may include a shift circuit or shift electrical connection that multiplies the digital accumulated values ​​by a power of two. It may include a digital adder operable to add the digital accumulated values ​​to generate a digital matrix value. The digital adder may be pipelined.

[0008] In embodiments, there is no analog-to-digital converter converting the output of the analog storage circuits 16 of the parallel-connected qmacs10, and summing of the outputs of the array of hybrid multiplication storage circuits may be performed by an analog summer operable to sum the accumulated charges to generate analog matrix values. In embodiments, it may consist of voltage multipliers connected to the analog storage circuits in the array to multiply the accumulated charges by powers of two. Such summing and multiplication may be performed by an op-amp configured as a summer having an op-amp input connected to the analog storage circuits operable to provide analog matrix values. The op-amp input of the op-amp may be configured to multiply or divide the op-amp input by a power of two. Some embodiments include an analog-to-digital converter that converts the analog matrix values ​​to generate digital matrix values, and the output of the op-amp is digitized.

[0009] In an embodiment, the bit multiplication circuit may be comprised of a series connected switch, e.g., a series switch circuit including a pair of MOS transistors, a first MOS transistor controlled by a positive control signal and a second MOS transistor controlled by an inverted (negative) version of the same control signal, one of the series connected switches being controlled by a weight value and the other being controlled by an input value representing a matrix multiplication of the weight value and the input value.

[0010] According to an embodiment of the present disclosure, a hybrid matrix multiplier comprises digital storage elements, each of the digital storage elements operable to store a digital value, a multiplication circuit for multiplying the stored digital values ​​to generate a product, and an analog storage circuit operable to store the product. The voltage connection may provide power for operating the digital storage elements, the multiplication circuit, and the analog storage circuit. The power supply connection provides power for operating the digital storage elements, the multiplication circuit, and the analog storage circuit, and may have a voltage of 1V or less (e.g., 500mV or less, 100mV or less, 50mV or less, or 10mV or less). The multiplication circuit may be comprised of a series-connected switch including a pair of MOS transistors.

[0011] According to an embodiment of the present disclosure, a hybrid time-multiplexed product-sum operation circuit includes a product storage circuit, a multiplication circuit operable to receive a first input value, receive a second input value, generate a product of the first input value and the second input value, and store the product in the product storage circuit, an accumulator storage circuit that stores an accumulation value, and an accumulation switch connecting the product value storage circuit to the product value storage circuit, operable to electrically connect the product value storage circuit to the product value storage circuit in parallel or to electrically disconnect the product value storage circuit from the product value storage circuit.

[0012] An embodiment of the time-multiplexed multiply-accumulate circuit may comprise a first multiplexer operable to select one of a plurality of first input values ​​input to the first multiplexer, and the multiplication circuit may be operable to receive the selected one of the plurality of first input values ​​from the first multiplexer, receive a second input value, and generate a product of the selected one of the plurality of first input values ​​and the second input value. In an embodiment, the embodiment may comprise a second multiplexer operable to select one of the plurality of second input values ​​input to the second multiplexer, and the multiplication circuit may be operable to receive the selected one of the second input values ​​from the second multiplexer, and generate a product of the selected one of the plurality of first input values ​​and the selected one of the second input values.

[0013] According to an embodiment of the present disclosure, the product storage circuit and the integrated value storage circuit are analog storage circuits that store electric charge. The product storage circuit and the integrated value storage circuit may be a capacitor.

[0014] According to an embodiment of the present disclosure, the multiplication circuit is a single-bit multiplication circuit for multiplying two binary bits. The multiplication circuit may be composed of serially connected serial switch circuits. The accumulation switch may be a serial switch circuit connected in series with the serial switch circuit of the multiplication circuit. The multiplication circuit is composed of serially connected serial switch circuits, and one or more of the serial switch circuit of the multiplication circuit and the serial switch circuit of the accumulation switch may be a differential switch.

[0015] According to an embodiment of the present disclosure, when the accumulation switch is operated to connect the integral memory circuit and the integral value memory circuit in parallel, the integral value of the integral value memory circuit and the product of the integral memory circuit are combined, and a combined value stored in the integral memory circuit and the integral value memory circuit is obtained.

[0016] An embodiment of the hybrid time multiplexing matrix multiplier comprises a control circuit sequentially operable to (i) provide a first input value and a second input value to the multiplier and switch an accumulation switch to store the product in a product storage circuit; and (ii) switch the accumulation switch to electrically connect the product storage circuit and the accumulation value storage circuit in parallel and combine the product and the accumulation value in the product storage circuit to provide a combined value stored in the product storage circuit and the accumulation value storage circuit.

[0017] According to an embodiment of the present disclosure, the hybrid matrix multiplier includes a plurality of time-multiplexed multiply-accumulate circuits and an adder for adding the multiplied values ​​of the plurality of time-multiplexed multiply-accumulate circuits. The multiplied values ​​may be analog values, and in some embodiments, the adder may include an analog-to-digital converter for converting the multiplied values ​​to digital values, and a digital adder. In some embodiments, the multiplied values ​​are analog values ​​and the adder is an analog adder.

[0018] According to an embodiment of the present disclosure, a hybrid method of matrix multiplication includes: a) providing a multi-bit value having N bits; b) providing a hybrid time-multiplexed iterative multiply-accumulate circuit; c) providing an input bit of the multi-bit value, providing a second input bit to the multiplier, and setting an accumulation switch to connect the accumulation value storage circuit to the time-shared multiplication value storage circuit and to disconnect the accumulation value storage circuit from the accumulation value storage circuit. d) multiplying the input bit of the multi-bit value by a second input bit to form a bit product that is stored in the product storage circuit. e) switching an accumulation switch to disconnect the product storage circuit from the time-division multiply-and-accumulate circuit, connect the product storage circuit to the integrated value storage circuit, and combine the product in the product storage circuit with the accumulated value to generate a combined value in the integrated value storage circuit; f) repeating steps c) to e) N times until all bits of the multi-bit value have been supplied in bit order and the product of the multi-bit value and the second input bit has been generated.

[0019] According to an embodiment of the present disclosure, a hybrid method of matrix multiplication includes: a) providing a first multi-bit value having N bits and a second multi-bit value having M bits; b) providing the M time-division multiply-accumulate circuits; c) providing input bits of a first multi-bit value and different second input bits of a second multi-bit value to a multiplier of each of the M time-multiplexed multiply-accumulate circuits, and setting an accumulation switch to connect an accumulator circuit to the time-multiplexed multiply-accumulate circuit and to disconnect the accumulator circuit from an accumulation value storage circuit of each of the M time-multiplexed multiply-accumulate circuits. d) multiplying the input bit of the multi-bit value by a second input bit to form bit products stored in each of the M time-multiplexed multiply-accumulate circuits and the multiply-accumulate circuits. e) switching the accumulation switch to disconnect the integrated value storage circuit from the time-division product-sum operation circuit and connect it to the integrated value storage circuit, and synthesize the integrated value of the integrated value storage circuit to generate a synthesized value in each integrated value storage circuit of the M time-division product-sum operation circuits; f) repeating steps c) to e) for each of the N bits of the first multi-bit value until all bits of the first multi-bit value have been provided in bit order. g) scaling the integrated values ​​of the M time-division multiply-and-accumulate circuits h) adding the respective integrated values ​​of the M time-division multiply-and-accumulate circuits to generate a product.

[0020] According to an embodiment of the present disclosure, a hybrid method of matrix multiplication includes: a) providing a first multi-bit value having N bits and a second multi-bit value having M bits; b) providing the time-division multiply-accumulate circuit; c) providing input bits of the first multi-bit value and providing second input bits of the second multi-bit value to the multiplier, and setting an accumulation switch to connect the accumulation value storage circuit to the time-multiplexed multiply-accumulate circuit and to disconnect the accumulation value storage circuit from the accumulation value storage circuit of the time-multiplexed multiply-accumulate circuit. d) multiplying the input bit of the first multi-bit value by the second input bit of the second multi-bit value to form a bit product that is stored in the product storage circuit. e) switching the accumulation switch to disconnect the integrated value storage circuit from the time-division product-sum operation circuit and connect it to the integrated value storage circuit, and synthesize the integrated value of the integrated value storage circuit to generate a synthesized value in each integrated value storage circuit of the M time-division product-sum operation circuits; f) repeating steps c) to e) for each of the N bits of the first multi-bit value until all bits of the first multi-bit value have been provided in bit order. g) scaling the integrated value of the time-multiplexed multiply-accumulate circuit to generate a scaled value. h) adding the scaled value to the multi-bit product. i) repeating steps c) through h) to generate a multi-bit product.

[0021] According to an embodiment of the present disclosure, a hybrid matrix multiplier includes a hybrid time-division iterative multiply-accumulate circuit, a memory circuit for storing an accumulated value, and a control circuit for repeatedly executing the following steps in sequence and storing the accumulated value in the memory circuit: (i) providing a first input value to the multiplier, providing a second input value, and setting an accumulation switch to connect an accumulation value storage circuit to the multiplier and to disconnect the accumulation value storage circuit from the accumulation value storage circuit; (ii) switching an accumulation switch to electrically disconnect the integration value storage circuit from the time-multiplexed product-sum operation circuit and electrically connect the integration value storage circuit to the integration value storage circuit to combine the product of the integration value storage circuit with the integration value and provide a combined value stored in the integration value storage circuit and the integration value storage circuit;

[0022] Some embodiments of the present disclosure include memory circuits, each memory circuit for storing an integrated value, and an adder for adding the integrated values ​​in the memory circuits, and a control circuit operable to provide different first input values, provide different second input values, and store the integrated value in each memory circuit.

[0023] According to some embodiments of the present disclosure, a time-multiplexed multiply-accumulate circuit includes a multiplier circuit operable to receive a first input value, receive a second input value, and generate a product of the first input value and the second input value, an accumulation digital storage circuit operable to store an accumulation digital value, and a digital bit accumulator operable to receive the product, combine the product with the accumulation digital value stored in the accumulation digital storage circuit, and output the accumulation digital value. Combining the product with the accumulation digital value may include (i) storing a value in the accumulation digital storage circuit if the product is one and the accumulation digital value is zero, (ii) keeping the same accumulation digital value if the product is one and the accumulation digital value is not zero, or (iii) doubling the accumulation digital value if the product is zero. Some embodiments of the present disclosure include a product storage circuit operable to receive the product, and a 1-bit analog-to-digital converter connected to the product storage circuit and the digital bit accumulator. The product storage circuit is operable to provide the product to a 1-bit analog-to-digital converter, and the 1-bit digital-to-digital converter is operable to receive the product, convert the product to a digital bit product, and provide the digital bit product to a digital bit accumulator.

[0024] DETAILED DESCRIPTION OF THE DRAWINGS Embodiments of the present disclosure provide a high-speed, efficient, low-power, compact hybrid hardware accelerator that performs matrix multiplication using multiply-add operations. [Brief description of the drawings]

[0025] [Figure 1A] FIG. 2 is a mathematical illustration of a matrix multiplication operation useful in understanding embodiments of the present disclosure. [Figure 1B] FIG. 2 is a mathematical illustration of a matrix multiplication operation useful in understanding embodiments of the present disclosure. [Figure 1C] FIG. 1 illustrates a simplified computer program illustrating a matrix multiplication operation that is useful in understanding embodiments of the present disclosure. [Figure 1D]FIG. 1 illustrates a simplified computer program illustrating a matrix multiplication operation that is useful in understanding embodiments of the present disclosure. [Diagram 2] FIG. 2 is a functional circuit diagram of a single-bit multiply-accumulate circuit according to an exemplary embodiment of the present disclosure. [Diagram 3] 3 is a schematic diagram of a one-dimensional array of single-bit multiply-accumulate circuits shown in FIG. 2 according to an exemplary embodiment of the present disclosure. [Figure 4A] FIG. 2 is a functional circuit diagram of a single-bit multiply-accumulate circuit with a switch circuit and a clear circuit, in accordance with an exemplary embodiment of the present disclosure. [Figure 4B] FIG. 4B is an abstract diagram of the functional schematic diagram of FIG. 4A in accordance with an exemplary embodiment of the present disclosure. [Figure 4C] FIG. 4B is a timing diagram for operating the single-bit multiply-accumulate circuit of FIG. 4A according to an exemplary embodiment of the present disclosure. [Diagram 5] FIG. 4B is a schematic diagram of a one-dimensional array of single-bit multiply-accumulate circuits shown in FIG. 4A according to an exemplary embodiment of the present disclosure. [Figure 6] 1 is a graph illustrating a multiplication operation by a multiply-accumulate operation value that is useful for understanding an embodiment of the present disclosure. [Figure 7] FIG. 2 is a schematic diagram of a two-dimensional array of single-bit multiply-accumulate circuits with digital summation circuits in accordance with an exemplary embodiment of the present disclosure. [Figure 8] FIG. 2 is a schematic diagram of a two-dimensional array of single-bit multiply-accumulate circuits with analog summing circuits, in accordance with an exemplary embodiment of the present disclosure. [Figure 9] FIG. 2 is a circuit diagram of an analog summing circuit according to an exemplary embodiment of the present disclosure. [Figure 10] FIG. 2 is a circuit diagram of an analog summing circuit according to an exemplary embodiment of the present disclosure. [Figure 11A] FIG. 1 is a schematic diagram of a vector-matrix hybrid multiply-accumulate circuit. [Figure 11B] FIG. 11B is a diagram illustrating matrix values ​​in the vector-matrix hybrid multiply-accumulate circuit of FIG. 11A in accordance with an exemplary embodiment of the present disclosure. [Figure 12]FIG. 9 is a circuit diagram of a vector-matrix hybrid multiply-accumulate circuit including a two-dimensional array of single-bit multiplier circuits with analog sum circuits as shown in FIG. 8 in accordance with an exemplary embodiment of the present disclosure. [Figure 13] FIG. 1 is an abstract circuit diagram of analog voltage controlled cascaded switches illustrating low power single-bit multiplication in accordance with an exemplary embodiment of the present disclosure. [Figure 14] FIG. 2 is a schematic diagram of a low power analog voltage controlled switch according to an exemplary embodiment of the present disclosure. [Figure 15A] FIG. 2 is a schematic diagram of a time-multiplexed iterative multiply-accumulate switch with a storage capacitor, according to an exemplary embodiment of the present disclosure. [Figure 15B] FIG. 2 is a schematic diagram of a time-multiplexed iterative multiply-accumulate switch with a product storage capacitor and a digital integration value, according to an exemplary embodiment of the present disclosure. [Figure 15C] FIG. 2 is a schematic diagram of a time-multiplexed iterative multiply-accumulate switch with digital integration values, according to an exemplary embodiment of the present disclosure. [Figure 16] FIG. 2 is a schematic diagram of a time-multiplexed iterative multiply-accumulate switch with a controller and an input multiplexer according to an exemplary embodiment of the present disclosure. [Figure 17] 1 is a flowchart of a method according to an exemplary embodiment of the present disclosure. [Figure 18] FIG. 2 is a schematic diagram of multiple time-multiplexed multiply-accumulate switches with analog summers according to an exemplary embodiment of the present disclosure. [Figure 19] FIG. 2 is a schematic diagram of multiple time-multiplexed multiply-accumulate switches with digital adders according to an exemplary embodiment of the present disclosure. [Figure 20] FIG. 2 is a schematic diagram of a time-multiplexed iterative multiply-accumulate switch with a controller and two input multiplexers, according to an exemplary embodiment of the present disclosure. [Figure 21] 1 is a flowchart of a method according to an exemplary embodiment of the present disclosure. [Figure 22] FIG. 1 is a schematic diagram of a time-multiplexed iterative single-bit multiply-accumulate switch and digital shift accumulator for multi-bit multiplication, in accordance with an exemplary embodiment of the present disclosure. [Figure 23] FIG. 2 is a schematic diagram of a time-multiplexed single-bit iterative multiply-accumulate switch for multi-bit multiplication with an analog storage device and an analog adder, according to an exemplary embodiment of the present disclosure. [Figure 24] FIG. 2 is a schematic diagram of a time-multiplexed single-bit multiply-accumulate switch for multi-bit multiplication with a digital storage device and a digital adder, according to an exemplary embodiment of the present disclosure. [Diagram 25] 11 is a table illustrating a time-multiplexed multiply-accumulate operation on a 2-bit value according to an exemplary embodiment of the present disclosure. [Figure 26A] 11 is a table illustrating a time-multiplexed multiply-accumulate operation on a 4-bit value according to an exemplary embodiment of the present disclosure. [Figure 26B] 11 is a table illustrating a time-multiplexed multiply-accumulate operation on a 4-bit value according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] The features and advantages of the present disclosure will become more apparent from the detailed description set forth below when considered in conjunction with the drawings, in which like reference characters identify corresponding elements throughout, in which like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. The figures are not necessarily drawn to scale.

[0027] A particular embodiment of the present disclosure relates to a single-bit hybrid multiply-accumulate circuit (each referred to as a qmac, and plural referred to as qmacs) that includes two digital single-bit binary storage elements, each storing a single-bit value, a multiplier that multiplies the two single-bit values ​​to calculate a product, and an analog charge storage element, such as a capacitor, to store the product as a charge (or voltage). A one-dimensional array of qmacs can calculate and sum one-dimensional arrays (vectors) of single-bit products. A two-dimensional array of qmacs can calculate the product of two multi-bit digital multipliers (a multiplier is a value that is multiplied with another value to calculate the multiplied product). The size of a two-dimensional array of qmacs for calculating multi-bit multipliers can be N+M-1, where N is the number of bits in one of the two digital multipliers and M is the number of bits in the other of the two digital multipliers. Vector matrix multiplication and accumulation of two linear vectors (one-dimensional arrays of numbers) with M values ​​can be calculated with M two-dimensional arrays and accumulated to one value.

[0028] As shown in Figure 1A, the calculation C=AxB where A, B, and C are matrices is matrix multiplication. If A is an m×n matrix and B is an n×p matrix, then C is an m×p matrix. Here, C ij =ΣA ik B kj (k=1 to n, i=1 to m, j=1 to p). For k=1 to N, the sum operation of the products of A and B is a multiplication (mac) operation. Thus, matrix multiplication is a series of (i×j) multiplication and product operations of size k, each of which provides one value of matrix C. FIG. 1B illustrates the calculation C=A×B for p=1, where C and B are linear (e.g., one-dimensional or vector) matrices. FIG. 1C is a simplified software program illustrating the calculation of the matrix calculation of FIG. 1A, and FIG. 1D is a simplified software program illustrating the calculation of the matrix calculation of FIG. 1B. The k=0 to (n-1) loop is a multiplication and product operation requiring n multiplications and n additions.

[0029] According to an embodiment of the present disclosure, as shown in Figures 2 and 3, a hybrid multiply-and-accumulate operation can be performed by an array of qmacs 10, which includes a first digital single-bit binary storage element 12 for storing a first bit A, a second digital single-bit binary storage element 12 for storing a second bit B, and a bit multiplier 14 (bit multiplier circuit 14) for multiplying the multipliers A and B and generating a product that is stored as a charge on a bit capacitor 16 (analog storage circuit 16). The storage element 12 may be an SRAM cell, a DRAM cell, a flip-flop (e.g., a D flip-flop), or a pair of inverters with their inputs and outputs connected together, as shown in the expanded view of Figure 2. The bit multiplier 14 may be an AND gate that provides a positive value (e.g., 1) only if both A and B are positive (e.g., 1), thus providing multiplication. The AND gate can be implemented as a transistor with its source connected to the storage element 12 for A and its gate connected to the storage element 12 for B (or vice versa), as shown in FIG. 2, providing a charge Q stored in the bit capacitor 16 when the product of the multipliers A and B has a value of 1. If the values ​​of A or B are the same for different qmacs 10, the storage element 12 for the constant can be shared by multiple qmacs 10 (e.g., a single storage element 12 can provide input values ​​to multiple qmacs 10, as shown in FIG. 7, described below). As will be appreciated by those with knowledge of analog and digital circuit design, FIGS. 2 and 3 are simplified designs, and much more complex designs, such as those shown in FIGS. 13 and 14, described below, that can operate at very low voltages and power, are included as embodiments of the present disclosure. For example, the amount of current stored in the bit capacitor 16 can be made very small to reduce the power used by the qmac 10 and increase the circuit speed. The bit capacitor 16 can be made very small to reduce the area of ​​the bit capacitor 16 in integrated circuit embodiments. Thus, in some embodiments, bit multiplier 14 provides very precise control over the current that accumulates charge on bit capacitors 16 over time to maintain accuracy and precision of the multiply-accumulate operation.Thus, bit multiplier 14 can be designed to very precisely control the amount of charge stored on bit capacitor 16, for example, in response to carefully calibrated timing signals and voltages.

[0030] FIG. 3 shows four qmacs 10 with bit capacitors 16 (analog storage circuits 16) connected in parallel to sum four products in a hybrid multiply-accumulate circuit 20. The four parallel arranged qmacs 10 provide a multiply-accumulate operation in which four single-bit A values ​​are multiplied by single-bit B values, respectively. The single-bit B values ​​may be the same or different. Thus, FIG. 3 shows a circuit for performing a multiply-accumulate operation on four single-bit binary values ​​(e.g., k=4 in the mathematical illustrations of FIGS. 1A-1D). In this manner, the array of single-bit multiply-accumulate circuits 10 is operable together to combine the charges stored in each analog storage circuit 16 to provide a stored charge representing the sum of the products of the qmacs 10.

[0031] The sum of the charges on the parallel connected bit capacitors 16 provides an analog integrated value output O that is converted to a digital value in an analog-to-digital converter (ADC) 30 or used as an analog value for further calculations. Since a parallel capacitor has a capacitance equal to the sum of the capacitances of the parallel connected capacitors, the absolute value of the voltage or charge (output O) must be scaled by the number of capacitors n. Since the charge of a capacitor is equal to voltage times capacitance (Q=CV), if the capacitance increases for a constant charge, the voltage decreases accordingly. For example, if all capacitors store a charge Q equivalent to a value of one, the sum of the values ​​would be four (example of FIG. 3), but since the four capacitors are electrically connected in parallel, the voltage remains one. Therefore, the voltage output must be scaled by the number of capacitors (e.g., by a factor of four in the diagram of FIG. 3).

[0032] The hybrid multiply-accumulate circuit can operate with less power than a digital equivalent circuit using, for example, a digital adder. The net current or charge leakage from the small bit capacitor 16 can be very small, and the analog storage circuit 16 and other analog operations can operate at very low voltages, for example, 1 volt or less (e.g., 500 mV or less, 100 mV or less, 50 mV or less, or 10 mV or less), lower than the voltages used for conventional digital logic (e.g., 5 V, 3.6 V, 3.3 V, or 1.65 V). Some embodiments of the present disclosure can operate at substantially 10 mV.

[0033] The circuits in Figures 2 and 3 are simplified representations of qmacs 10 and their implementation in a multiply-accumulate array. As mentioned above, precise control of charge storage on bit capacitors 16 helps maintain precision and accuracy of the multiply-accumulate operations. As shown in Figure 4A, a more complex circuit for qmacs 10 controls the electrical connections between qmacs 10 in an array of qmacs 10 using a switch circuit 18 (also designated S in the figure) connected to the output of bit multiplier 14 and to bit capacitors 16. When switch circuit 18 is on, charge Q, representing the product of bits A and B, is stored on bit capacitor 16 via the left transistor of switch circuit 18. When switch circuit 18 is off, the left transistor is off and an inverter including the center transistor of switch circuit 18 applies a positive signal to a connecting switch including the right transistor of switch circuit 18, connecting bit capacitors 16 in parallel.

[0034] The switch circuit 18 of FIG. 4A is a simplified circuit, and more complex circuits can be implemented to provide the switch function, and such switch circuits are also included in this disclosure. Thus, in a first mode, the switch circuit 18 is on, and the products of the multiplications by the bit multipliers 14 are applied separately and individually to transfer charge to the bit capacitors 16 in each qmac 10. In a second mode, the switch circuit 18 is off, the bit capacitors 16 are connected in parallel, and the charge Q on the bit capacitors 16 of each qmac 10 is isolated from the bit multipliers 14 and summed to provide an integrated value output O. FIG. 4B is an abstraction of the single-bit multiply-accumulate circuit 10 of FIG. 4A, where A and B are single-bit digital storage elements 12, M is the bit multiplier 14, S is the switch circuit 18, and C is the clear circuit 19.

[0035] FIG. 4C illustrates a multiply-accumulate cycle of qmac 10. Load signals A and B are set to store corresponding values ​​in storage elements 12, provided by, for example, a computer or other state machine controller, and are multiplied by bit multipliers 14. At the same time, the clear signal goes high and the switch signal goes low, isolating and clearing bit capacitors 16. Once bit capacitors 16 are cleared, the clear signal is set low and the switch signal is set high to allow a charge Q, representing the product of A and B, to be deposited on bit capacitors 16. Once charge Q is loaded onto bit capacitors 16, the switch signal is set low, isolating bit multipliers 14 from bit capacitors 16 and connecting all bit capacitors 16 in parallel, thereby summing the charges Q on bit capacitors 16 to provide an integrated value output O. The summed charge Q, which is equal to output O, is appropriately scaled and converted to a digital value in analog-to-digital converter 30 or used as an analog value for further calculations. When switch circuit 18 switches from the first mode to the second mode, the entire operation can be performed in two cycles.

[0036] Figure 5 shows an array of qmacs 10 forming a hybrid multiply-accumulate circuit 20 using the abstract representation of Figure 4B. In some embodiments, a single clear circuit 19 can be used to clear charge from all of the connected bit capacitors 16 when the switch circuits 18 are off, but switch circuits 18 connected between the bit capacitors 16 can prevent charge removal for all of the bit capacitors 16. In some embodiments, a clear circuit 19 is provided for each qmac 10, and the clear circuits 19, like the switch circuits 18, are commonly controlled in the hybrid multiply-accumulate circuit 20.

[0037] Figure 6 illustrates a complete multiplication for binary multi-digit multi-bit values. While Figure 6 illustrates the case of values ​​having 4 bits, any number of bits can be used with hybrid multiply-add circuits 20 having a number of qmacs 10 corresponding to the number of bits being multiplied. The number of qmacs 10 in each hybrid multiply-add circuit 20 corresponds to the number of bits in A, and the number of hybrid multiply-add circuits 20 corresponds to the number of simultaneous multiply-add operations. If the number of qmacs 10 is less than the number of bits in A, or the number of simultaneous multiply-add operations is less than the number of bits in B, partial calculations can be performed and the products stored and combined under the control of an external computer or controller, such as a state machine.

[0038] As shown in the four-bit example of FIG. 6, each column of products shown is one bit of value B multiplied by a bit of value A. In FIG. 6, the columns are spatially shifted relative to each other to show the relative magnitude (location) of the products of each column, as is conventional for multiplication written by hand on paper. The products (multiplication values) of each column 21 are summed in each hybrid multiply-accumulate circuit 20 to form an accumulation result (sum output value O) as shown in FIG. 5. Each column 21 of products may be calculated and summed in a different hybrid multiply-accumulate circuit 20. The accumulation results (accumulation output value O) of the hybrid multiply-accumulate circuits 20 are then summed (added) to obtain the final value of the multi-bit multiplication.

[0039] The multiplication and accumulation of each column 21 of products can be performed by a one-dimensional array of qmacs 10. As shown in FIG. 7, each column of qmacs 10 forms a hybrid multiply-accumulate circuit 20 that shares a common B storage element 12. The array of qmacs 10 of each hybrid multiply-accumulate circuit 20 (which in this example corresponds to the multiplication illustrated in FIG. 6) calculates and sums the column 21 of products as an output value O. The output values ​​O of each hybrid multiply-accumulate circuit 20 can be added. Since each column 21 of products has a different scale value (relative magnitude), the values ​​of each column 21 of products must be scaled to multiply by their scale value, e.g., 1 to 6, before being added. Multiple multiplication operations can be performed without reloading the bit value (B storage element 12) whose bit does not change, for example, if the bit value represents a weight common to the multiplication of multiple input values.

[0040] The array of hybrid multiply-accumulate circuits 20 forming hybrid multi-bit multiplier 22 provides extremely fast operation having many fewer cycles than conventional digital circuits. Furthermore, the addition step to sum the output value O (if performed digitally) can be split into stages (e.g., adding a pair of values ​​at a time) and pipelined, making the operation even faster, and multiply-accumulate operations on different values ​​can be overlapped in time, e.g., under the control of a computer or state machine controller.

[0041] In some embodiments of the present disclosure, the sum of the output values ​​O from the hybrid multiply-accumulate circuit 20 is calculated digitally. In some embodiments, the sum of the output values ​​O from the hybrid multiply-accumulate circuit 20 is calculated using analog circuitry. As shown in Figure 7, the output values ​​are converted with an analog-to-digital converter 30 to provide digital bit values ​​that are stored, for example, in a register or other memory, the digital bit values ​​are scaled, for example, by shifting them relative to each other (each shift corresponds to a power of two), and the scaled bit values ​​are summed using a digital adder.

[0042] As shown in FIG. 8, the analog integration result of each hybrid multiply-accumulate operation (columns of qmacs10) is a voltage (or charge) that is multiplied (e.g., by a voltage multiplier VM) by an amount corresponding to the location of the analog integration, the multiplied analog integrations are added, e.g., using an analog adder, and the final integration is converted to a digital value in an analog-to-digital converter 30. In such an embodiment, the entire calculation can be done in two switch cycles (excluding clear or load cycles), resulting in a very fast operation compared to conventional embodiments. FIG. 8 shows an embodiment in which every qmac 10 has a separate storage element 12.

[0043] Multiplication and summation of analog voltages can be implemented in some embodiments using an opamp 40 configured in summing mode. Figure 9 shows an inverting summing opamp 40. The output Vo of the opamp 40 is a sum of each voltage V 1 ~V N The sum of R' / R n where n is the particular column and N is the number of columns 21 whose products are being added (e.g., 7 in the example of Figure 7). Each voltage corresponds to the output O of a column of qmacs 10. For example, R1 is R' / R 1 = 1 / 64, R' / R 2 = 1 / 32, R' / R 3 = 1 / 16, R' / R 4 = 1 / 8, R' / R 5 =1 / 4, R' / R 6 =1 / 1, R' / R 7 = 1. The inverting output of the operational amplifier 40 can be converted to a digital value using the analog to digital converter 30 and scaled appropriately.

[0044] FIG. 10 shows a non-inverting summing operational amplifier 40. The output Vo of the operational amplifier 40 is 1 ~V N is equal to the sum of R' / R multiplied by the ratio R 1 ~R N are equal. Voltage value V 1~V N can be scaled with a resistor implemented voltage divider. For example, V 1 The resistors connected to V can have a ratio of 63:1. 2 The resistors connected to V can have a ratio of 31:1. 3 The voltage can be top-scaled to correspond to the location of the added value, such as a resistor connected to R could have a ratio of 15:1. The output of the op-amp 40 is scaled by a ratio of (R+R') / R (e.g., 64) and can be converted to a digital value using the analog-to-digital converter 30.

[0045] The embodiments of Figures 7 and 8 with analog summing can provide faster operation, and the embodiment of Figure 6 with digital summing can provide higher accuracy. The embodiments of the present disclosure are not limited by the number of bits shown. For example, the hybrid multiply-accumulate circuit 20 can have 64, 128, 256, 512, 1024, 2048, 4096, 8192, or 16384 or more qmacs10s, and the same number of hybrid multiply-accumulate circuits 20 can be employed in an array to provide fast multiplication by many bits. The embodiments of the present disclosure can be provided as a hardware accelerator for a conventional computer or graphics processor. Data can be fed to the hardware accelerator in a pipelined manner with two or more shift registers at the input and output. The hardware implementation of the array of hybrid multiply-accumulate circuits 20 must be sized to efficiently correspond to the size of the input vector. If the array of hybrid multiply-accumulate circuits 20 is too large for the task, much of the circuitry will not be used (e.g., the number of qmacs10s is too large). If the array of hybrid multiply-accumulate circuit 20 is too small, vector multiplications must be decomposed into smaller vectors. Having too many small vectors also leads to inefficiencies.

[0046] As shown in FIG. 6, a two-dimensional multiplication array of single-bit multiply-accumulate circuit 10 can perform multi-bit multiplication (e.g., FIGS. 7 and 8). A hybrid multi-bit multiplier 22 including multiple arrays such as those in FIGS. 8 and 9 forming a hybrid matrix multiply-accumulate circuit 24 can compute the entire vector multiplication. Each multi-bit multiplication of the vector multiply-accumulate operation (e.g., as shown in FIG. 1B) can generate a digital product (as shown in FIG. 7 or after analog-to-digital conversion of the analog sum output value O), and the digital products can be digitally added using a digital adder. In some embodiments, each multi-bit multiplication of the vector multiply-accumulate operation (e.g., as shown in FIG. 1B) can generate an analog product (output value O as shown in FIG. 8), and the analog products can be added using similar circuits as shown in FIGS. 1-6. The analog product P (shown in FIG. 8) can be stored in a capacitor (e.g., similar to the bit capacitor 16 but with a larger storage capacity for a larger charge) using a storage circuit similar to that of the bit multiplier 14. As shown in Figure 12, switch and clear circuits 18, 19 similar to those in Figure 5 can allow charge Q to accumulate on the capacitors, which can be summed by connecting the capacitors in parallel and converted by an analog-to-digital converter 30 to provide the entire vector matrix multiplication in one cycle. Figure 11A shows a hybrid matrix multiply-accumulate circuit 24, and Figure 11B associates the hybrid multi-bit multiplier 22 with the multiplicands in a vector multiply-accumulate calculation.

[0047] The embodiments of the present disclosure can provide a very low-voltage sum-of-products circuit 10 using, for example, a voltage of 10 mV to 1 V. A bit multiplier 14 using a conventional AND gate may require, for example, six relatively large transistors operating at a relatively high voltage to implement a bit multiplication circuit that can adequately control the charge Q stored in the analog storage circuit 16 (for example, 1.65 to 5 V). In contrast, as shown in FIG. 13, the bit multiplier 14 of the present disclosure can operate at a relatively low voltage (for example, not exceeding 1 V, and as low as 10 mV) and low power, and can configure a series-connected series switch circuit 15 that can adequately control the charge Q stored in the analog storage circuit 16 with, for example, only four relatively small transistors.

[0048] As shown in Figure 13, a series of three series switch circuits 15 and an analog storage circuit 16 can provide a qmac 10 similar in function to the circuit shown in Figures 4A and 4B. Each serial switch circuit 15 has two differential voltage inputs (V and V with a bar, where Vbar is the inverted value of V), two voltage inputs In and In with a bar, where Inbar is the inverted value of In), and an output O. Thus, each of the signals A, B, and switches (described in more detail below) in Figures 13 and 14 are differential signals. The first series switch circuit 15 has a reference voltage V REFP (For example, V REF , a high or positive value such as 10 mV) and its inverse value V REFN (e.g., a low or negative value such as 0 mV) and has two inputs, a value A (e.g., a weight value) and its inverse, Abar. As shown in the inset of FIG. 13 for serial switch circuit 15A, when A is high (e.g., positive or 10 mV) and Abar is consequently low (e.g., 0 mV), the output O is V, as shown by the undashed connection. REF As shown in the inset of FIG. 13 for series switch circuit 15B, when A is low (e.g., negative or 0 mV) and Abar is consequently high (e.g., 10 mV), the output O is V REFNThus, if A is positive, O is positive, and if A is negative, O is negative. The second series switch 15 in series has an input value B and its inverse value Bbar, and transfers the value O from the first series switch 15 to V REFP , and V REFN is an inverted voltage value (e.g., 0 volts). Thus, if O is low (negative), then the output P from the second serial switch circuit 15 will be low (negative) regardless of what value B is. If O is high (positive) and B is high (positive), then the output O from the second serial switch circuit 15 will be high (positive), and if B is low, then the output P from the second serial switch circuit 15 will be low (negative). In this way, the first two serial switch circuits 15 perform an AND function with less circuitry and power.

[0049] The third serial switch circuit 15 can be used to implement the switch circuit 18 and has an input switch value and its inverse (corresponding to the switch values ​​in FIGS. 4A and 4B) and converts the value O from the second serial switch 15 to V REF value and common V SUM The connection is captured as an inverted voltage value. Thus, when the switch is high, the output O charges the analog storage circuit 16. When the switch is low, the charge Q on the analog storage circuit 16 is connected in common to any other analog storage circuits 16 in the array of qmacs10 (e.g., as shown as the analog qmac10 array output in FIG. 3) to provide a summation operation.

[0050] FIG. 14 shows some embodiments of a low-voltage qmac 10 including three series-connected series switch circuits 15. Each switch circuit 15 is composed of a pair of simple MOS (metal oxide semiconductor) transistors with separate differential inputs and a common output. One of the pair of simple MOS transistors is controlled by a positive control signal, and the other is controlled by an inverted (negative) version of the same control signal, e.g., the positive and negative outputs of any single-bit storage element 12 (e.g., a pair of D flip-flops or inverters as shown and described with respect to FIG. 2). The function of the circuit is as described above with respect to FIG. 13. Such a series of series switch circuits 15 can require fewer, simpler transistors that operate at much lower voltages (e.g., 1 percent or less, e.g., 10 mV instead of 0.624 percent, or 1.65 volts) and therefore require much less power. The combined (added) voltage of the analog storage circuit 16 can be: V SUM = ((n * V REFP ) + (Nn)*V REFN )) / N. where V REFN =0 Volts: V SUM = (n * V REFP ) / N Here, n is the number of capacitors, and N is the number of qmacs10s connected in a row. SUM is scaled or transformed as described above (not shown in FIG. 14 with explicit circuit 19).

[0051] Thus, in accordance with some embodiments of the present disclosure, a hybrid matrix multiplier includes digital storage elements 12, each of the digital storage elements 12 operable to store a digital value, a multiplication circuit 14 for multiplying the stored digital values ​​to generate a product, an analog storage circuit 16 operable to store the product, and a power connection (e.g., V REFP , VREFN ). The power supply connections may have a voltage of 1V or less, 500mV or less, 100mV or less, 50mV or less, or 10mV or less. The bit multiplication circuit 14 may be comprised of switches 15 connected in series.

[0052] In some embodiments, the hardware implementation of the hybrid matrix multiply-accumulate circuit 24, the hybrid multi-bit multiplier 22, or the hybrid multiply-accumulate circuit 20 may not exactly match the computation desired for a particular application. In such applications, the computation may be divided into subproblems that better fit the available hardware, and the results may be combined to provide the desired computation. The subproblems may be executed sequentially in time, such that the hardware is time-shared or time-multiplexed. A portion of the value (e.g., bits of the multiplier B) may be stored in the storage element 12 for multiple hardware operations, thereby reducing the power and time used by the hardware.

[0053] The embodiments of the present disclosure enable vector multiply-add operations that use very little energy at very high rates. Instead of requiring n loops of a program (e.g., as shown in Figures 1C and 1D, each of which requires multiple machine code cycles to run the program), the entire calculation is performed in one cycle. Many large matrix operations, for example in machine learning applications, have many zero values ​​in the matrix and require relatively low bit precision to iterate the solution of the matching problem. Thus, the embodiments of the present disclosure provide an efficient circuit for such applications.

[0054] In some embodiments of the present disclosure, multi-bit digital multiplication is performed in a single step using multiple single-bit multiply-accumulate circuits 10 in a hybrid multiply-accumulate circuit 20, for example, as shown in Figures 2 and 3. An array of hybrid multiply-accumulate circuits 20 can be used to multiply two multi-bit digital values ​​in a single step, as shown in Figures 6-8. In such hybrid multi-bit multipliers, accuracy is improved by carefully matching the operational performance of the bit multiplying circuits 14 (e.g., including the series switch circuits 15) so that the charges stored by each bit multiplying circuit 14 are the same and the analog sum from the parallel-connected analog storage circuits 16 is correct, at least within the error of any analog-to-digital converter 30.

[0055] In some embodiments of the present disclosure, rather than matching the operational performance of the bit multiplier circuits 14, a single bit multiplier circuit 14 is used repeatedly (e.g., repeatedly over time such that the single bit multiplier circuit 14 is shared over time) to store bit products in the accumulation value storage circuit 17, without requiring circuit matching. Although the repetition requires time, the single bit multiplier circuit 14 and accumulation value storage circuit 17 can be made very small, e.g., consisting of three transistors and an additional accumulation value capacitor (as shown in FIG. 14). Thus, millions or even billions of such circuits can be built in an integrated circuit to provide very fast matrix multiplication with relatively little energy usage compared to existing digital multipliers.

[0056] FIG. 15A shows a simple hybrid iterative single-bit multiply-accumulate circuit 11 (iqmac11) comprising a single-bit multiply-accumulate circuit 10 having a product storage circuit 16 (capacitor 16) electrically connected in parallel with an accumulation value storage circuit 17 (e.g., capacitor 17 having the same capacitance as the product storage circuit 16 of the single-bit multiply-accumulate circuit 10) by a switch 18 functioning as an accumulation switch 60. The accumulation switch 60 can be the same, substantially similar, or the same as the differential switch 18 of the single-bit multiply-accumulate circuit 10, as shown in more detail in FIG. 16. FIG. 16 shows the single-bit multiplier circuit 14 of FIG. 14 with the addition of an accumulation value storage circuit 17 forming the iterative single-bit multiply-accumulate circuit 11. Optionally, the output of the accumulation value storage circuit 17 can be connected to an analog-to-digital converter 30 via an optional switch 18.

[0057] FIG. 15A illustrates the multiplication of two single-bit values ​​stored in two corresponding single-bit storage elements 12. When the switch 18 is set to a multiplication mode (first mode), the product P is stored in the product storage circuit 16 (capacitor 16) as described above with respect to FIG. 2 and FIG. 14. When the switch 18 is set to an accumulation mode (second mode), the charge stored in the product storage circuit 16 is shared (combined) with the charge stored in the accumulation value storage circuit 17, similar to the product sum shown in FIG. 3, except that there are only two capacitors 16, 17 in the product sum storage circuit 11. Multiple bit products can be stored in the two capacitors by repeatedly supplying bits to the storage element 12, setting the switch 18 to the multiplication mode, storing the charge representing the bit product of the storage element 12 in the product sum storage circuit 16, and setting the switch 18 to the accumulation mode to combine the charges of the capacitors 16 and 17.

[0058] FIG. 15B shows a simple hybrid iterative single-bit multiply-accumulate circuit 11 (iqmac11) that includes a single-bit multiply-accumulate circuit 10 that provides bit products stored in a product storage circuit 16 (capacitor 16) whose values ​​are digitized (to digital bit products of one or zero) by an analog-to-digital converter 30. In some embodiments, and as shown in FIG. 15C, the single-bit multiply-accumulate circuit 10 generates a voltage that is actually a digital voltage, in which case the product storage circuit 16 and separate analog-to-digital converter 30 are not required. A digital bit accumulator 32 receives each digital bit product and combines it with a multi-bit accumulated digital value in an accumulated digital storage circuit 34 (e.g., a memory or register). Each combination involves scaling the accumulated digital value in the accumulated digital storage circuit 34. Combining the digital bit product with the accumulated digital value may include storing a value in the accumulated digital storage circuit when the digital bit product is one and the accumulated digital value is zero, maintaining the same accumulated digital value when the digital bit product is one and the accumulated digital value is not zero, or scaling the accumulated digital value by a factor of two when the product is zero, as described further below. This combination can be implemented with a simple digital circuit, for example, a state machine with a digital shift circuit 36 ​​(e.g., a divide-by-two circuit). Such a hybrid iterative single-bit multiply-accumulate circuit 11 does not require matching capacitors 16 and 17. The size of a suitable state machine having a digital bit, digital bit, and accumulated digital bit can be relatively small, for example, compared to the capacitors 16, 17 and multi-bit ADC 30 of FIG. 15A. In particular, in embodiments such as those of FIG. 15B and FIG. 15C, the multi-bit ADC 30 is not required, which can reduce the circuit size of the iqmac 11 and reduce the time and power required for operation.

[0059] As shown in FIG. 16, a single bit B is applied to one input of the bit multiplier circuit 14, and a bit of a multi-bit value A (in this example A 0 ~A 3A single bit can be multi-bit multiplied by a multi-bit value by successively applying multiple bits A to multiplexer 50. Successive bit application can be done in low to high bit order by storing the multi-bit value in register (memory) 56, successively multiplexing successive bits from register 56 under the control of control circuit 70 which can provide the bit selection values ​​for multiplexer 50 and the multi-bit value A in register 56, and applying the multiplexed bits to bit multiplier circuit 14.

[0060] As shown in FIG. 17, a single bit B can be multiplied by a multi-bit value A by first providing iqmac 11 in step 100 and clearing product storage circuit 16 and integrated value storage circuit 17 in step 110 (e.g., setting their values ​​to zero by connecting them to ground with clear circuit C as shown in FIGS. 4A-4C). Control circuit 70 provides single bit value B to storage element 12 and multi-bit value A to register 56 in step 102 and sets bit count value N to zero in step 115. Steps 102 and 110 can be performed in any order. Bit N of multi-bit value A is selected by multiplexer 50 in step 120, and switch 18 is set to multiplication (first) mode under the control of control circuit 70 in step 125. Bit multiplier 14 multiplies bit N of multi-bit value A by bit B in step 130 and stores the product in product storage circuit 16. The switch 18 is then set to an accumulation (second) mode in step 135, and in step 140, the charges of the product storage circuit 16 and the accumulation value storage circuit 17 are combined and shared between the product storage circuit 16 and the accumulation value storage circuit 17 by connecting the product storage circuit 16 and the accumulation value storage circuit 17 in parallel. In step 145, the bit count N is tested to see if all bits of the multi-bit value A have been multiplied by bit B. If not, N is incremented (e.g., by the control circuit 70) in step 150. If all bits of the multi-bit value A have been multiplied by bit B (test step 145), the process is complete and a value corresponding to the product is stored in the accumulation value storage circuit 17. Optionally under the control of the switch 18, the analog-to-digital converter 30 converts the accumulated products to a digital value in step 155. For example, the output (V ACC) may itself be switched, for example using serial switch circuit 15, and applied to analog-to-digital circuit 30. If all of the A bits have not been multiplied with the B bits, then bit count N is incremented and steps 120 to 145 are repeated until all of the A bits have been multiplied. New multiplications can then proceed.

[0061] In some embodiments, an iterative single-bit multiply-accumulate circuit 11 may be provided for each bit of the second multi-bit value B, multiplying each bit of the second multi-bit value B simultaneously. Each iterative single-bit multiply-accumulate circuit 11 then accumulates a sum corresponding to each row or product of FIG. 6. Thus, in this example, four iterative single-bit multiply-accumulate circuits 11 accumulate values ​​corresponding to rows of the calculation shown in FIG. 6. FIG. 18 illustrates an analog sum of products. Each product (corresponding to a row in FIG. 6) is scaled (multiplied by a power of 2 corresponding to the row), for example using a voltage multiplier, and then summed, for example, as shown in FIGS. 7-9. As shown in FIG. 19, each product can be digitized by an analog-to-digital converter 30, scaled by a shift circuit, and digitally summed by a digital adder 54. The top row is multiplied by a power of 2, for example using a voltage multiplier. 0 = 1, i.e. it is scaled (multiplied) by a zero-place shift, and the next row is 2 1 =2, i.e. it is scaled (multiplied) by a shift of 1, and the next row is 2 2 = 4, i.e. scaled (multiplied) by a shift of 2, so the last row is 2 3 =8, i.e. it is scaled (multiplied) by a shift of 3.

[0062] According to some embodiments of the present disclosure, a multi-bit value B may be multiplied by a multi-bit value A by iteratively applying iqmac11 to each bit of the multi-bit value B, with only one iterative single-bit multiply-accumulate circuit 11 being used to calculate the total product. FIG. 20 shows a useful circuit in which the storage element 12 of bit B of FIG. 16 is replaced with a multiplexer 50 under the control of a control circuit 70. The control circuit 70 may store the multi-bit value B in a register 56, select a bit M of the multi-bit value B with the multiplexer 50, and apply the selected bit to iqmac11. Each single-bit multiplication of bit M of the multi-bit value B with the multi-bit value A proceeds iteratively as described with respect to the flow diagram of FIG. 17 (e.g., step 200).

[0063] As shown in FIG. 21, multi-bit value B may be multiplied with multi-bit value A by first providing iqmac11 in step 100 and then setting bit counter M to zero in step 105. The method of step 200 (FIG. 17) then proceeds for multi-bit value A and selected bit M of multi-bit value B. If not all bits of multi-bit value B have been multiplied with multi-bit value A (determined in step 160), the accumulated bit products are stored in step 165, e.g., in a capacitor if the value is a charge, or in a register if the value is digital (e.g., converted by analog-to-digital converter 30 in step 155), and the bit count value M is incremented in step 170. The products of each bit of multi-bit value B with multi-bit value A correspond to the rows of multi-bit product values ​​shown in FIG. 6. Once all bits of multi-bit value B have been multiplied with multi-bit value A, the sum of the products of each bit of multi-bit value B with multi-bit value A is calculated in step 175, as described in FIGS. 7 and 8. For example, analog or digital summation may be performed, with appropriate care taken to scale the product of each bit of the multi-bit value B before summing the results.

[0064] FIG. 22 shows a hybrid circuit for iteratively multiplying two 8-bit digital values ​​using iterative single-bit multiply-accumulate circuit 11. As shown in FIG. 22, control circuit 70 controls switch 18 and multiplexer 50 to cycle through the bits of multi-bit value A and multi-bit value B as described in FIG. 20 and FIG. 21. The product of each bit of multi-bit value B and multi-bit value A is converted to a digital value, scaled, and then accumulated (added to an existing value) in digital shift accumulator 52. As shown in FIG. 23, digital shift accumulator 52 can be composed of a demultiplexer 51 responsive to control circuit 70 for shifting each bit of the digitized product (scaling the digitized product corresponding to the rows of FIG. 6), a multi-bit register or memory 13 for storing the accumulated product, and an adder 54 for adding the scaled product to the accumulated product and storing the sum in a register. The shift (scale) can correspond to the bit of multi-bit value B selected for multiplication with multi-bit value A. After all bits of the multi-bit product have been multiplied with multi-bit value A and the products have been accumulated, the accumulated value of digital shift accumulator 52 comprises the product of multi-bit values ​​A and B.

[0065] FIG. 24 performs the same function as FIG. 23, except that the summations are performed in analog circuitry. As shown in FIG. 24, control circuit 70 controls switches 18 and multiplexer 50 to cycle through the bits of multi-bit value A and multi-bit value B as described in FIG. 20 and FIG. 21. Each product of a bit of multi-bit value B and multi-bit value A is scaled (e.g., with a voltage multiplier) and stored in a separate analog storage circuit 16 (e.g., a capacitor) selected by analog demultiplexer 53. Once all the products corresponding to the rows of FIG. 6 have been stored, they can be summed in one step using circuitry similar to that of FIGS. 2-5.

[0066] According to an embodiment of the present disclosure, array multiplication can be implemented using a hybrid iterative single-bit multiply-accumulate circuit 11 as shown in Figure 22 for each multi-bit product, whereby all of the product values ​​are calculated simultaneously, but each product value is calculated iteratively. According to an embodiment of the present disclosure, such an array multiplier is fast and low power.

[0067] The iterative single-bit multiply-accumulate calculator 11 sequentially calculates the product of a single bit B and a 1-bit of a multi-bit value A, sequentially stores the product of each pair of bits in a product storage circuit 16, sequentially accumulates the products, and stores them in an accumulated value storage circuit 17. Because the multi-bit values ​​are binary values, the product of each successive bit has twice the value of the previous product. For example, the product of a single-bit value 1 and a multi-bit value 111 has three successive 1-bits. The value of the first bit is 1, the value of the second bit is 2, and the value of the third bit is 4, which correspond to the bit positions of the numeric value. Therefore, the sequential accumulation of bit products must provide for proper scaling of the bits corresponding to the bit positions.

[0068] Whenever an integral storage circuit 16 is electrically connected in parallel with an integrated value storage circuit 17, the charges of the two circuits are equalized as a combined shared charge. Figure 25 shows the charge combination and equalization when a single-bit value B is multiplied by a two-bit value A. If the value of B is zero, then the products are all zero and the accumulated charges are zero as well (not shown in Figure 25). Numbers are written in binary notation.

[0069] If B is equal to 1 and A is equal to 00, the top left column shows the process. Voltage C M is the charge stored in the integration memory circuit 16, and the voltage C Ais the accumulated charge for the charge corresponding to one integrated value accumulated in the integrated value storage circuit 17. In clear cycle 0, the integrated value storage circuit 16 and the integrated value storage circuit 17 are cleared. In cycle 1, bit 0 (0) of A is multiplied by B (1) to become a zero product, which is stored in the integrated value storage circuit 16 and then stored in the integrated value storage circuit 17, and both accumulate a charge of zero product. In cycle 2, bit 1 (zero) of A is multiplied by B (1) to become a zero product, which is stored in the integrated value storage circuit 16 and then stored in the integrated value storage circuit 17, and again becomes a zero charge. In cycle 3, the analog-to-digital converter 30 converts the charge (zero charge) accumulated in the integrated value storage circuit 17 to zero.

[0070] The top right column shows the process when B is 1 and A is 01. In clear cycle 0, product storage circuit 16 and accumulated value storage circuit 17 are cleared. In cycle 1, bit 0 (1) of A is multiplied with B(1) in multiplication mode, resulting in a product of 1, which is stored as one charge in product storage circuit 16. Since product storage circuit 16 is a capacitor with equal capacitance to the capacitor of accumulated value storage circuit 17, the parallel connection between the two (enabled by switch 18 in accumulate mode) doubles the capacitance, thus halving the charge on each capacitor and the voltage on the capacitor, so that accumulated value storage circuit 17 stores one-half the relative charge. In cycle 2, bit 1 (zero) of A is multiplied with B(1), resulting in a zero product, which is stored in product storage circuit 16 in multiplication mode and then in accumulated value storage circuit 17 in accumulation mode. This combination combines the half charge in accumulation storage circuit 17 with the zero charge in accumulation storage circuit 16, reducing the charge and voltage in each circuit by a factor of two, and reducing the relative charge and voltage in accumulation storage circuit 17 by a factor of four. In cycle 3, the charge is scaled by a factor of four (equal to the number of values ​​a 2-bit binary digital value can store) and analog-to-digital converter 30 converts the stored charge in accumulation storage circuit 17 to one (four times one-quarter), resulting in B=1 multiplied by A=01 (1 in decimal notation).

[0071] When B is 1 and A is 10, the bottom left column shows the process. In clear cycle 0, the product storage circuit 16 and the accumulated value storage circuit 17 are cleared. In cycle 1, bit 0 (zero) of A is multiplied by B (1) to produce a zero product, which is stored in the product storage circuit 16 as a zero charge. In cycle 2, bit 1 (1) of A is multiplied by B (1) to produce a one product, which is stored in the multiply-accumulate circuit 16 in multiplication mode and accumulated in the accumulated value storage circuit 17 in accumulation mode. This combination combines the zero charge in the accumulated value storage circuit 17 with the one charge in the product storage circuit 16, and the relative charge and voltage in the accumulated value storage circuit 17 are halved. In the 3rd cycle, the charge is scaled by a factor of 4, and the analog-to-digital converter 30 converts the accumulated charge in the accumulated value storage circuit 17 to 2 (4 times 1 / 2), which is the product of B=1 and A=10 (2 in decimal notation).

[0072] When B is 1 and A is 11, the bottom right column shows the process. In clear cycle 0, the product storage circuit 16 and the integrated value storage circuit 17 are cleared. In cycle 1, bit 0 of A(1) is multiplied with B(1) to become 1 product, which is stored in the product-sum operation circuit 16 as 1 charge in the multiplication mode and stored in the integrated value storage circuit 17 as 1 / 2 charge voltage in the integrated value mode. In the second cycle, bit 1 (1) of A is multiplied with B(1) to become 1 product, which is stored in the product-sum operation circuit 16 and stored in the integrated value storage circuit 17. This combination combines the 1 / 2 charge in the integrated value storage circuit 17 with the 1 charge in the integrated value storage circuit 16, and the relative charge and voltage in the integrated value storage circuit 17 become 3 / 4. In the th cycle, the charge is scaled by a factor of 4, and the analog-to-digital converter 30 converts the charge stored in the integrated value memory circuit 17 to 3 (4 times 3 / 4), which is the product of B=1 and A=11 (3 in decimal notation).

[0073] Figures 26A and 26B show the same process for a 4-bit binary value A. The product voltage (charge) of product storage circuit 16 is shown to the left of each column pair corresponding to the value of A, and the integrated voltage (charge) of integrated value storage circuit 17 is shown to the right of each column pair corresponding to the value of A for the cycle shown. For A=0000, the products and integrated charges are all zero, resulting in an integrated value of zero.

[0074] When A=0001, B is 1 and bit 0 of A is 1, so the first product stored in product storage circuit 16 is 1. Since the first product is shared equally between product storage circuit 16 and integrated value storage circuit 17, integrated value storage circuit 17 stores a value of 1 / 2 relatively. After that, the product becomes 0, and the charge in integrated value storage circuit 17 decreases by 1 / 2 each time it is shared with the charge in product storage circuit 16, decreasing to 1 / 4 in the second cycle, 1 / 8 in the third cycle, and 1 / 16 in the fourth cycle. Since A is 4 bits, the accumulated charge is multiplied by 16, and as a result, the product becomes 16 times 1 / 16, or equal to 0001 (1 in decimal).

[0075] For A=0010, bit 0 of A is 0, so the first product is 0 and the first accumulated value is 0. The second product (bit 1 of A) is 1 and the accumulated charge is shared equally between product storage circuit 16 and accumulated value storage circuit 17, so the corresponding accumulated relative charge is 1 / 2. Thereafter, the product is zero because the bit of A is zero, and the charge in accumulated value storage circuit 17 decreases by 1 / 2 each time it is shared with the charge in product storage circuit 16, so the charge decreases by 1 / 4 in cycle 3 and 1 / 8 in cycle 4. The accumulated charge is multiplied by 16, so that the product is equal to 1 / 8 times 16, or 0010 (decimal value 2).

[0076] For A=0011, the first product is 1 and the first accumulated value is 1 / 2 because the charge is shared equally between product storage circuit 16 and accumulated value storage circuit 17. The second product (bit 1 of A) is 1 and the corresponding accumulated relative charge is 3 / 4 because the charge of 1 in product storage circuit 16 is shared equally with the charge of 1 / 2 in accumulated value storage circuit 17. The product then becomes 0 and the charge in accumulated value storage circuit 17 is reduced by 1 / 2 each time it is shared with the charge in product storage circuit 16, so that the charge is reduced to 3 / 8 in the third cycle and 3 / 16 in the fourth cycle. The accumulated charge is scaled by a factor of 16, resulting in a product equal to 3 / 16 times 16 or 0011 (decimal value 3).

[0077] If A=0100, the first product is zero and the first accumulated value is zero. If A=0100, the first product is zero and the first accumulated value is zero. Since bit 1 of A is 0, the second accumulated value is also 0. The third product (bit 2 of A in the third cycle) is 1 and the corresponding accumulated relative charge is halved because the charge is shared equally between the product storage circuit 16, which stores a 1, and the accumulated value storage circuit 17, which stores a 0. The product then becomes 0 and the charge in the product storage circuit 17 is reduced by 1 / 2 each time it is shared with the charge in the product storage circuit 16, until it is reduced to 1 / 4 in the fourth cycle. The accumulated charge is scaled by a factor of 16, resulting in a product equal to 16 times 1 / 4 or 0100 (decimal value 4).

[0078] For A=0101, the first product is 1 and the first integrated value is 1 / 2. This is because the charge is shared equally between the integrated value storage circuit 16 and the integrated value storage circuit 17, and the relative value is 1 / 2. The second product (cycle 2) is 0 because bit 1 of A is 0, and the integrated value is the average of 0 and 1 / 2, which is 1 / 4. The third product (cycle 3) is 1 because bit 2 of A is 1, and the integrated value is the average of 1 / 4 and 1, which is equal to 5 / 8. The fourth product (cycle 4) is 0 because bit 3 of A is 0, and the integrated value is the average of 0 and 5 / 8, which is equal to 5 / 16. As a result of scaling by a factor of 16, the resulting product is 16 times 5 / 16, or 0101 (decimal 5).

[0079] For A=0110, the first product is 0 and the first accumulated value is 0. The second product (cycle 2) is 1 because bit 1 of A is 1, and the accumulated value is the average of 0 and 1, which equals 1 / 2. The third product (cycle 3) is 1 because bit 2 of A is 1, and the accumulated value is the average of 1 and 1 / 2, which equals 3 / 4. The fourth product (cycle 4) is 0 because bit 3 of A is 0, and the accumulated value is the average of 0 and 3 / 4, which equals 3 / 8. After scaling by a factor of 16, the product equals 3 / 8 × 16, or 0110 (decimal 6).

[0080] For A=0111, the first product is 1 and the first accumulation is 1 / 2. The second product (cycle 2) is 1 because bit 1 of A is 1, so the accumulation is the average of 1 and 1 / 2, or 3 / 4. The third product (cycle 3) is 1 because bit 2 of A is 1, so the accumulation is the average of 1 and 3 / 4, or 7 / 8. The fourth product (cycle 4) is 0 because bit 3 of A is 0, so the accumulation is the average of 0 and 7 / 8, or 7 / 16. After scaling by a factor of 16, the product is 7 / 16 times 16, or equal to 0111 (decimal 7).

[0081] Figure 26B shows the result of accumulating the value 1000 to the value 1111. As shown in Figure 26B, the product is the same as that shown in Figure 26A, except that the accumulated value in cycle 3 is averaged with 1 to produce the final result, since the final bitwise product is 1.

[0082] Figures 25-26B mathematically illustrate the repeated accumulation of charge in bit multiplication, as illustrated in Figures 16-19, of a single bit B multiplied by a multi-bit value A. By repeating this process for each bit of the multi-bit value B (as described in Figures 20 and 21), two multi-bit values ​​can be calculated with high speed and low power consumption.

[0083] The calculation can be summarized mathematically: Given a bit B and an N-bit multi-bit value A, where A(i) is bit i of multi-bit value A, the first bit (least significant bit or LSB) is A(0) for i=0, and the last bit (most significant bit or MSB) is A(N-1), the accumulated product is:

number

[0084] In an embodiment in which a multi-bit value B having M bits, with its first bit (least significant bit) being B(0) and its last bit (most significant bit or MSB) being B(M-1), is multiplied by a multi-bit value A having N bits, with its first bit (least significant bit) being A(0) for i=0 and its last bit (most significant bit or MSB) being A(N-1), the product A×B is multiplied.

number

[0085] If B(j) is equal to zero, there is no need to compute the sum over i, saving computation time and energy.

[0086] The embodiments of the present disclosure are not limited to the specific examples shown in the figures and described herein, and a skilled designer will readily appreciate that various implementations of analog and digital circuits can be employed to perform the described operations and that such implementations are included in the embodiments of the present disclosure.

[0087] Embodiments of the present disclosure may be used in neural networks, pattern matching computers, or machine learning computers to provide efficient and timely processing with reduced power and hardware requirements. Such embodiments may constitute computing accelerators, such as neural network accelerators, pattern matching accelerators, machine learning accelerators, or artificial intelligence computing accelerators designed for static or dynamic processing workloads.

[0088] Having described specific implementations of the embodiments, it will now be apparent to those of ordinary skill in the art that other implementations incorporating the concepts of the present disclosure may be used. Accordingly, the present disclosure should not be limited to specific implementations, but rather should be limited only by the spirit and scope of the following claims.

[0089] Throughout this specification, where devices and systems are described as having, including, or consisting of certain elements, or processes and methods are described as having, including, or consisting of certain steps, it is further contemplated that there are devices and systems of the disclosed technology that consist essentially of, or consist of, the disclosed elements, and that there are processes and methods according to the disclosed technology that consist essentially of, or consist of, the disclosed processing steps.

[0090] It should be understood that the order of steps or order for performing certain actions is immaterial so long as the disclosed technology remains operable. Moreover, in some circumstances, two or more steps or actions may be performed simultaneously. Although the disclosure has been described in detail with particular reference to certain embodiments thereof, it will be understood that variations and modifications can be effected within the spirit and scope of the following claims. [Explanation of symbols]

[0091] C Clear Circuit M multiplication circuit / multiplier O Output Value P product S Switch / Switch circuit VM Voltage Multiplier 10 qmac / single-bit multiply-accumulate circuit 11 iqmac / Iterative single-bit multiply-accumulate circuit 12 Single-bit storage element 13 Multi-bit memory element 14-bit multiplier / bit multiplier circuit 15, 15A, 15B Serial switch circuit 16 Capacitor / Analog Memory Circuit / Product Memory Circuit 17 Capacitor / Analog memory circuit / Integrated value memory circuit 18 Switch / Switch Circuit 19 Clear / Clear Circuit 20 Hybrid multiply-accumulate circuit 21 Product Column 22 Hybrid Multi-bit Multiplier 24 Hybrid matrix multiply-accumulate circuit 30 Analog to Digital Converter 32 digital bit accumulator 34 Accumulation digital memory circuit 36 State machine and digital shift circuit 40 Operational Amplifier / Op-Amp 50 Multiplexer 51 Digital Demultiplexer 52 Digital shift integrator 53 Analog Demultiplexer 54 Adder 56 Registers / Memory 60 Accumulation Switch 70 Control circuit 100 qmac provided steps 102 A value B value provision step Step 105: Set count M=0 in B bit 108 Bbit M Selection Steps 110 C M and C. A Clear Step 115 A Bit Number N=0 Set Step 120 Abit N Selection Steps 125 Steps to switch to multiplication mode 130 Step of multiplying bits N and storing the product Step 135 to set the switch to accumulate mode 140 Integration Steps 145 All A-bit integration test steps 150 Steps to increment bit count N 155 Analog to Digital Conversion Steps 160 Full B-bit Multiplication Test Steps 165-bit product M memory steps 170 B bits set in M~M+1 count steps 175 Steps for calculating the sum of bit products M 200 Steps to Multiply a Multi-Bit Value by a Single Bit

Claims

1. A storage circuit and a multiplication circuit operable to receive a first input value, to receive a second input value, to generate a product of said first input value and said second input value, and to store the product in a product storage circuit; an integrated value storage circuit for storing an integrated value; an accumulation switch that connects the product storage circuit to the integrated value storage circuit, the accumulation switch operating to electrically connect the product storage circuit and the integrated value storage circuit in parallel or operating to electrically disconnect the product storage circuit from the integrated value storage circuit; A time-division multiply-and-accumulate circuit comprising:

2. a first multiplexer operable to select one of the first input values ​​input thereto; 2. The time-multiplexed multiply-add circuit of claim 1, wherein the multiplier circuit is operable to receive a selected one of a plurality of first input values ​​and a second input value from the first multiplexer and to generate a product of the selected one of the plurality of first input values ​​and the second input value.

3. a second multiplexer operable to select one of the second input values ​​input thereto; 3. The time-multiplexed multiply-add circuit of claim 2, wherein the multiplier circuit is operable to receive a selected one of the second input values ​​from the second multiplexer and to generate a product of the selected one of the plurality of first input values ​​and the selected one of the second input values.

4. 4. The time-division multiply-add circuit according to claim 1, wherein the product storage circuit and the integrated value storage circuit are analog storage circuits that store electric charges.

5. 5. The time-division multiply-accumulate circuit according to claim 4, wherein said product storage circuit and said integrated value storage circuit are capacitors.

6. 6. The time-division multiply-add circuit according to claim 1, wherein the multiplying circuit is a single-bit multiplying circuit.

7. 7. The time-division multiply-add circuit according to claim 1, wherein the multiplication circuit is composed of series switch circuits connected in series.

8. 8. The time-division multiply-accumulate circuit according to claim 7, wherein the accumulation switch is a serial switch circuit connected in series with the serial switch circuit of the multiplication circuit.

9. the multiplication circuit is made up of series switch circuits connected in series; 9. The time-division multiply-accumulate circuit according to claim 7, wherein at least one of the series switch circuit of the multiplier circuit and the series switch circuit of the accumulation switch is a differential switch.

10. 10. The time-division product-sum operation circuit according to claim 1, wherein when the accumulation switch is operated to connect the product storage circuit and the integrated value storage circuit in parallel, the integrated value of the integrated value storage circuit and the product of the integrated value storage circuit are combined to obtain a composite value stored in the product storage circuit and the integrated value storage circuit.

11. (i) supplying a first input value and a second input value to a multiplier and switching an integration switch to store the product in a product storage circuit; (ii) A control circuit for switching the accumulation switch to electrically connect the product storage circuit and the integrated value storage circuit in parallel and combine the product and the integrated value of the product storage circuit to provide a combined value. The time-division product-sum operation circuit according to any one of claims 1 to 10, further comprising:

12. A time-division multiply-add circuit according to any one of claims 1 to 11, an adder that adds up the integrated values ​​of the time-division product-sum operation circuit; A hybrid matrix multiplier comprising:

13. 13. The hybrid matrix multiplier of claim 12, wherein the multiplication values ​​are analog values ​​and further comprising an analog-to-digital converter that converts the multiplication values ​​to digital values, and wherein the adder is a digital adder.

14. 13. The hybrid matrix multiplier of claim 12, wherein the multiplication values ​​are analog values ​​and the summers are analog summers.

15. a) providing a multi-bit value having N bits; b) providing a time-division multiply-add circuit according to any one of claims 1 to 11; c) providing an input bit of a multi-bit value, providing a second input bit to the multiplier, and setting the accumulation switch to connect the product storage circuit to the time-multiplexed multiply-accumulate circuit and to disconnect the product storage circuit from the accumulation value storage circuit; d) multiplying said input bit of said multi-bit value by said second input bit to form a bitwise product in said product storage circuit; e) switching the accumulation switch to disconnect the product storage circuit from the time-division multiply-and-accumulate circuit and connect the product storage circuit to an integrated value storage circuit, and combine the product in the product storage circuit with an accumulation value to generate a combined value in the integrated value storage circuit; f) repeating steps c) to e) above N times until all bits of the multi-bit value have been provided in bit order and products of each bit of the multi-bit value with the second input bit have been generated.

16. a) providing a first multi-bit value having N bits and a second multi-bit value having M bits; b) providing M time-division multiply-add circuits according to any one of claims 1 to 11; c) providing input bits of the first multi-bit value and second input bits of the second multi-bit value to a multiplier of each of the M time-multiplexed multiply-accumulate circuits, and setting the accumulation switches to connect the product storage circuit to the time-multiplexed multiply-accumulate circuit and to disconnect the product storage circuit from an accumulation value storage circuit of each of the M time-multiplexed multiply-accumulate circuits; d) multiplying an input bit of the first multi-bit value by a second input bit to form bit products stored in each of the M time-multiplexed multiply-accumulate circuits and in the product storage circuit; e) switching an accumulation switch to disconnect the product storage circuit from the time-division product-sum operation circuit, connect the product storage circuit to the integrated value storage circuit, and combine the product of the product storage circuit and the integrated value to generate a combined value in each integrated value storage circuit of the M time-division product-sum operation circuits; f) repeating steps c) to e) for each of the N bits of the first multi-bit value until all bits of the first multi-bit value have been provided in bit order; g) scaling the integrated values ​​of the M time-division multiply-and-accumulate circuits; h) adding up the respective integrated values ​​of the M time-division multiply-and-accumulate circuits to generate a product; A hybrid matrix multiplication method including:

17. a) providing a first multi-bit value having N bits and a second multi-bit value having M bits; b) providing a time-division multiply-add circuit according to any one of claims 1 to 11; c) providing input bits of a first multi-bit value and providing second input bits of a second multi-bit value to the multiplier and setting an accumulation switch to connect the accumulation value storage circuit to the time-multiplexed multiply-accumulate circuit and to disconnect the accumulation value storage circuit from the accumulation value storage circuit of the time-multiplexed multiply-accumulate circuit; d) multiplying the input bit of the first multi-bit value by the second input bit of the second multi-bit value to form a bit product stored in a product storage circuit; e) switching an integration switch to disconnect the integration value storage circuit from the time-division product-sum operation circuit and connect it to the integration value storage circuit, and synthesize the integration value of the integration value storage circuit and the integration value to generate a composite value in each of the integration value storage circuits of the M time-division product-sum operation circuits; f) repeating steps c) to e) for each of the N bits of the first multi-bit value until all bits of the first multi-bit value have been provided in bit order; g) scaling the integrated value of the time-multiplexed multiply-accumulate circuit to generate a scaled value; h) adding the scaled value to the multi-bit product; i) repeating steps c) through h) to generate a multi-bit product; A hybrid matrix multiplication method including:

18. A time-division multiply-add circuit according to any one of claims 1 to 11, A memory circuit for storing the integrated value; (i) providing a first input value to a multiplier, providing a second input value to the multiplier, and setting an integration switch to connect an integration value storage circuit to the multiplier and to disconnect the integration value storage circuit from the integration value storage circuit; (ii) switching an integration switch to electrically disconnect the integration value storage circuit from the time-division multiply-and-accumulate circuit and electrically connect the integration value storage circuit to the integration value storage circuit, combining the product of the integration value storage circuit with the integration value, and providing a combined value stored in the integration value storage circuit and the integration value storage circuit; a control circuit that operates to repeatedly perform the above steps and store the integrated value in a memory circuit; A hybrid matrix multiplier with

19. memory circuits, each memory circuit being for storing an integrated value; an adder that adds up the integrated values ​​of the memory circuits; 20. The hybrid matrix multiplier of claim 18, wherein the control circuitry is operative to provide different first input values, provide different second input values, and store multiplication values ​​in respective memory circuits.

20. a multiplication circuit operable to receive a first input value and a second input value and to generate a product of said first input value and said second input value; an integrated digital storage circuit operable to store the integrated digital value; a digital bit accumulator operable to receive the product, combine the product with an accumulated digital value stored in an accumulated digital storage circuit, and output an accumulated digital value; a time-division multiply-add circuit that, when combining the product and the integrated digital value, (i) stores a value in an integrated digital storage circuit if the product is one and the integrated digital value is zero, (ii) maintains the same integrated digital value if the product is one and the integrated digital value is not zero, or (iii) doubles the integrated digital value if the product is zero.

21. a product storage circuit operable to receive the product; a 1-bit analog-to-digital converter connected to the product storage circuit and the digital bit integrator; 21. The time-multiplexed multiply-add operation circuit according to claim 20, wherein the product storage circuit supplies the product to a 1-bit analog-to-digital converter, which receives the product, converts the product to a digital bit product, and supplies the digital bit product to the digital bit accumulator.

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