Digital-to-analog converter with cascaded least significant bit (LSB) interpolator circuits - Patents.com

Abstract

A digital-to-analog converter (DAC) (100) for converting a digital input word to an analog output signal includes a string DAC (104), a first interpolator (130), and a second interpolator (150). The string DAC (104) outputs a first voltage and a second voltage in response to M most significant bits of the digital input word. The first interpolator (130) interpolates between the first and second voltages in response to the middle Q least significant bits of the digital input word to provide a first interpolated voltage. The second interpolator (150) interpolates between the first and second voltages in response to the lower P least significant bits of the digital input word.

Description

[Technical field]

[0001] This description relates generally to digital-to-analog converters (DACs), and more particularly to DACs with cascaded least significant bit (LSB) interpolator circuits. [Background technology]

[0002] In a DAC, multiple resistors are connected in series between a high reference voltage and a low reference voltage. The voltage at the node between the series connected resistors (the tap point) is selectively switched to the output in response to a digital input. The voltage at the output is an analog representation of the digital input. For an N-bit DAC, there are 2 N resistors are needed, which results in 2 N +1 nodes (tap points) are formed. For a 7-bit DAC, 128 resistors are needed, for an 8-bit DAC, 256 resistors are needed. So, for a DAC with more than 7 bits, the number of resistors is too large.

[0003] One existing approach is to separate the DAC into a string DAC section and an interpolator DAC section. The string DAC section includes a number of series-connected resistors, all with equal resistance. Each resistor is associated with a pair of switches, each constituting an upper switch and a lower switch. The lower terminal of each resistor is connected to a corresponding lower switch, and the upper terminal of each resistor is connected to a corresponding upper switch. A digital input word is split into M most significant bit (MSB) sub-words and N least significant bit (LSB) sub-words. The MSB sub-word is decoded to close one of the switch pairs associated with the selected resistor, thereby providing a voltage (e.g., V1) at the lower terminal of the selected resistor and a voltage (e.g., V2) at the upper terminal. The voltage V1 at the lower terminal of the selected resistor is a coarse analog representation of the MSB sub-word. The coarse analog representation (i.e., V1) is monotonic, since increasing the MSB sub-word increases V1 and decreasing the MSB sub-word decreases V1.

[0004] The voltage drop across the selected resistor (V2-V1) is the sum of the two resistors placed in the differential transconductance stage. N The N-bit LSB sub-word is provided as an input to an interpolator DAC section that includes pairs of transistors. The differential transconductance stage is a voltage controlled current source where the differential input voltage produces an output current. Each transistor in the differential transconductance stage receives the same current (also called the "tail current"). The voltage drop across the resistor (V2-V1) is provided as an input to the differential transconductance stage and the N-bit LSB sub-word is incremented to modulate the input offset voltage of the differential transconductance stage. As a result, the interpolator DAC section produces an output voltage VOUT that is a fine interpolation between V2 and V1. The sum (V1+VOUT) is an analog representation of the digital input word.

[0005] Separating the DAC into a string DAC section and an interpolator DAC section reduces the total number of resistors in the string DAC section, but this approach requires a large number of differential transconductance stages in the interpolator DAC section, which requires a relatively large area in the integrated circuit. Summary of the Invention

[0006] In one aspect, a digital-to-analog converter (DAC) for converting a digital input word to an analog output signal includes a string DAC including a plurality of series-connected resistors. The string DAC includes a most significant bit (MSB) switching circuit including a pair of switches. Each switch pair includes an upper switch and a lower switch. Each upper switch is connected to an upper terminal of one of the plurality of series-connected resistors, and each lower switch is connected to a lower terminal of one of the plurality of series-connected resistors. The MSB switching circuit provides a first voltage and a second voltage in response to an MSB control signal. The DAC includes a first least significant bit (LSB) interpolator coupled to the string DAC. The first LSB interpolator includes an output, a plurality of non-inverting inputs, and a plurality of inverting inputs coupled to the output. One of the non-inverting inputs is coupled to receive the first voltage, and the other non-inverting input is coupled to receive the first or second voltage. The first LSB interpolator provides a first interpolated voltage at the output in response to a first LSB control signal. The DAC includes a second LSB interpolator coupled to the string DAC and to the first LSB interpolator. The second LSB interpolator includes an output, a number of non-inverting inputs, and a number of inverting inputs coupled to the output. One of the non-inverting inputs is coupled to receive the first interpolated voltage, and the other non-inverting input is coupled to receive either the first voltage or the second voltage. The second LSB interpolator provides an output voltage at the output in response to a second LSB control signal.

[0007] In an additional aspect, the string DAC includes an MSB decoder having an input coupled to receive an MSB subword and providing the MSB control signal by decoding the MSB subword, the MSB subword including the M most significant bits of the digital input word, where M is an integer.

[0008] In an additional aspect, the first interpolator includes a first LSB decoder having an input coupled to receive the first LSB sub-word and providing the first LSB control signal by decoding the first LSB sub-word, the first LSB sub-word including the lower P least significant bits of the digital input word.

[0009] In an additional aspect, the second interpolator includes a second LSB decoder having an input coupled to receive a second LSB sub-word and providing the second LSB control signal by decoding the second LSB sub-word, the second LSB sub-word including the middle Q least significant bits of a digital input word.

[0010] In an additional aspect, a DAC for converting a digital input word to an analog output signal includes a first LSB interpolator circuit including a plurality of non-inverting inputs and a plurality of inverting inputs coupled to an output. One of the non-inverting inputs is coupled to receive a voltage of the coarse representation and the other non-inverting input is selectively coupled to receive either the voltage of the coarse representation or a second voltage higher than the voltage of the coarse representation. The first LSB interpolator circuit provides a first interpolated voltage at the output. The DAC includes a second LSB interpolator including a plurality of non-inverting inputs and a plurality of inverting inputs coupled to the output. One of the non-inverting inputs is coupled to receive the first interpolated voltage and the other non-inverting input is selectively coupled to receive either the voltage of the coarse representation or the second voltage. The second LSB interpolator circuit provides an output voltage. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a schematic block diagram of an example digital-to-analog converter (DAC).

[0012] [Diagram 2] FIG. 2 is a schematic diagram of an example string DAC section.

[0013] [Diagram 3]FIG. 4 is a schematic diagram of an example first LSB interpolator section.

[0014] [Figure 4] FIG. 13 is a schematic diagram of another example first LSB interpolator portion.

[0015] The use of the same reference numbers or other reference designators in the drawings indicates the same or similar (structural and / or functional) features. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] 1 is a block diagram of an example digital-to-analog converter (DAC) 100. DAC 100 converts a digital input D_IN (also referred to as a "digital input word") to an analog output signal VOUT. The digital input D_IN (not shown in FIG. 1) is divided into M most significant bits MSB_SUB (shown in FIG. 2), lower P least significant bits LSB_SUB1 (shown in FIG. 3), and middle Q least significant bits LSB_SUB2 (shown in FIG. 4), which are used by DAC 100 to generate the output signal VOUT.

[0017] DAC 100 includes a string DAC section 104 that generates an output (V1 and / or V2) based on the M most significant bits of D_IN, which is a coarse representation of the digital input word D_IN. String DAC section 104 includes a number of resistors (e.g., R1 through RN, where N is 256 in the example shown in FIG. 1 ) connected in series between a reference voltage terminal 110 and a common potential (e.g., ground) terminal 112. Two resistors of equal resistance are connected between reference voltage (V_REF) terminal 110 and ground terminal 112 to convert the M MSBs. M 1, 256 resistors (R1 to R256) are connected in series to convert 8 bits. The reference voltage terminal 110 may be connected to a reference voltage V_REF, and the ground terminal 112 may be connected to an electrical ground.

[0018] The string DAC section 104 includes an MSB switching circuit 120 that can be selectively coupled to resistors (e.g., R1-R256). The MSB switching circuit 120 has a first output 122 and a second output 124. In response to an MSB control signal MSB_CNTR, the MSB switching circuit 120 selects one of the resistors and couples the lower terminal of the selected resistor to the first output 122 and the upper terminal of the selected resistor to the second output 124. As a result, a voltage V1 at the lower terminal of the selected resistor is coupled to the first output 122 and a voltage V2 at the upper terminal of the selected resistor is coupled to the second output 124. By changing the MSB control signal MSB_CNTR, any one of the resistors (i.e., R1-R256) can be selected and the voltage V1 at the lower terminal of the selected resistor and the voltage V2 at the upper terminal of the selected resistor can be accessed from the first output 122 and the second output 124. In one example, MSB_CNTR is generated by decoding the M most significant bits of D_IN. V1 is referred to as a coarse representation of the digital input word because V1 is an approximate analog representation of the digital input word. Although switching circuit 120 is illustrated in FIG. 1 as including two switches, in other examples, switching circuit 120 may include any number of switches (and / or other circuit elements) connected in series and / or parallel.

[0019] DAC 100 includes a first LSB interpolator section 130 that interpolates between voltages V1 and V2 based on the lowest P LSBs of the digital input word D_IN. DAC 100 also includes a second LSB interpolator section 150 that interpolates between V2 and the output voltage generated by first LSB interpolator section 130 based on the middle Q LSBs of the digital input word D_IN. First LSB interpolator section 130 is connected to switches SL(1)-SL(2) for selecting a voltage between V2 and the output voltage V2. P ) and the respective outputs 136(1) to 136(2 P 1, the switch SL(1) connects to V1, so that V1 appears at the output 136(1). The remaining switches SL(2) to SL(2P ) are arranged so that they may connect their respective outputs to V2 or V1. For example, switch SL(2) may connect to V2, in which case V2 appears at output 136(2), or switch SL(2) may connect to V1, in which case V1 appears at output 136(2). P ) may be connected to V2, in which case V2 may be connected to output 136(2 P ) or switch SL(2 P ) may be coupled to V1, in which case V1 may be coupled to output 136(2 P ) appears.

[0020] The first interpolator section 130 includes a first interpolator circuit 140 that interpolates between voltages V2 and V1. The first interpolator circuit 140 has a plurality of positive inputs 142(1) to 142(2). P ) and multiple negative inputs 144(1) to 144(2 P ) and output 146. Positive inputs 142(1) to 142(2 P ) are the outputs 136(1) to 136(2) of the switching circuit 134. P ), and negative inputs 144(1) to 144(2 P ) is coupled to output 146. One of the switches in switching circuit 134 (e.g., SL(1)) is coupled to V1, so that positive input 142(1) receives V1. The other positive inputs 142(2)-142(2) P ) are the switches SL(2) to SL(2) of the switching circuit 134. P ) is coupled to either V1 or V2. In response to the first LSB control signal LSB1_CNTR, the switches SL(2) to SL(2 P ) is positive input 142(2)~142(2 P ) to either V1 or V2. In one example, LSB1_CNTR is generated by decoding the least significant P bits of D_IN. A first interpolator circuit 140 interpolates between voltages V2 and V1 and provides a first interpolated voltage V_INT1 at output 146.

[0021] The DAC 100 includes a second interpolator section 150. The second interpolator section 150 includes switches SW(1) to SW(2). Q ) and their respective outputs 156(1) to 156(2 Q The switch SW(1) connects its output 156(1) to V_INT1. The remaining switches SW(2) to SW(2 Q ) may connect their respective outputs to V2 or V1. For example, switch SW(2) may connect to V2, in which case V2 appears at output 156(2), or switch SW(2) may connect to V1, in which case V1 appears at output 156(2). Q ) may be connected to V2, in which case V2 will be connected to output 156(2 Q ) or switch SL(2 Q ) may be connected to V1, in which case V1 may be connected to output 156(2 Q ) appears.

[0022] The second interpolator section 150 includes a second LSB interpolator circuit 160 that interpolates between the voltage V_INT1 (i.e., the output of the first interpolator circuit 140) and V2. The second LSB interpolator circuit 160 has a plurality of positive inputs 162(1) to 162(2). Q ) and multiple negative inputs 164(1) to 164(2 Q ), and an output 166. One of the positive inputs, for example 162(1), is coupled to the output 146 of the first LSB interpolator circuit 140 via a switch SW(1), so that V_INT1 (the output of the first interpolator circuit 140) is applied to the positive input 162(1). The other positive inputs 162(2)-162(2) are Q ) is switch SW(2)~SW(2 Q ) and is coupled to V1 or V2 via negative inputs 164(1) to 164(2) Q ) is coupled to the output 166 (VOUT) of the second LSB interpolator circuit 160.

[0023] In response to the second LSB control signal LSB2_CNTR, the switches SW(2) to SW(2 Q ) is the positive input 142(2)~142(2Q ) to either V1 or V2. In one example, LSB2_CNTR is generated by decoding the middle Q bits of D_IN. A second LSB interpolator circuit 160 linearly interpolates between V_INT1 and V2 and provides an output VOUT at output 166.

[0024] Thus, in the example of Figure 1, the digital input word D_IN is divided into three sub-word groups: (1) the M most significant bits, (2) the middle Q bits, and (3) the lower P bits. The string DAC section 104 provides a coarse representation of D_IN in response to the M most significant bits. To provide higher granularity, further interpolation is performed in two cascaded stages. The first interpolator section 130 interpolates between V2 and V1 in response to the lower P bits to provide V_INT1, and the second interpolator section 150 interpolates between V_INT1 and V2 in response to the middle Q bits to provide the output VOUT.

[0025] 2 is a schematic diagram of the string DAC section 104. The string DAC section 104 comprises two equal resistance DACs connected in series between a reference voltage terminal 210 and a ground terminal 212. M The string DAC unit 104 includes resistors (2 M +1) tap points, one tap point is connected to a reference voltage terminal 210, another tap point is connected to a common potential 212, and the other tap points are disposed between resistors. For example, one terminal of switch S1(B) is connected to one tap point, and one terminal of switches S1(A) and S2(B) is connected to another tap point. In this example, 256 resistors (R1 to R256) are connected in series to convert 8 bits. The reference voltage terminal 210 may be coupled to a reference voltage V_REF, and the ground terminal 212 may be coupled to an electrical ground.

[0026] The string DAC section 104 includes an MSB switching circuit 220 having switch pairs associated with resistors connected in series. Each switch pair includes an upper switch and a lower switch. In the example of FIG. 2, switches S1(A) and S1(B) are associated with R1, switches S2(A) and S2(B) are associated with R2, and switches S256(A) and S256(B) are associated with R256. The upper switch S1(A) is associated with the upper terminal of R1, the lower switch S1(B) is associated with the lower terminal of R1, the upper switch S2(A) is associated with the upper terminal of R2, the lower switch S2(B) is associated with the lower terminal of R2, the upper switch S256(A) is associated with the upper terminal of R256, and the lower switch S256(B) is associated with the lower terminal of R256.

[0027] The MSB switching circuit 220 includes an MSB decoder 222 having an input 224 coupled to receive an MSB sub-word MSB_SUB consisting of a predetermined number of the most significant bits of the digital input word. For example, MSB_SUB may consist of the eight most significant bits of the 16-bit D_IN.

[0028] The MSB decoder 222 decodes the MSB subword MSB_SUB and provides an MSB control signal MSB_CNTR at output 225 to control the switching of each switch in the MSB switching circuit 220. In response to the MSB control signal MSB_CNTR, the MSB switching circuit 220 closes (e.g., makes the switch conductive) only one of the switch pairs associated with the selected resistor and opens (e.g., makes the switch non-conductive) all other switch pairs. The closed switch pairs couple the upper terminal of the selected resistor to output 226 and the lower terminal of the selected resistor to output 228. The effect of this is that the voltage at the upper terminal of the selected resistor (e.g., V2) appears at output 226 and the voltage at the lower terminal of the selected resistor (e.g., V1) appears at output 228. Closing any pair of switches couples the voltages V2 and V1 at the upper and lower terminals of the selected resistor to the respective outputs 226 and 228.

[0029] For example, if the MSB sub-word MSB_SUB consists of all zeros, the MSB switching circuit 220 closes the switches S1(A) and S1(B) associated with resistor R1. Therefore, V2 is equal to the voltage at the upper terminal of R1, and V1 is equal to the voltage at the lower terminal of R1. If the MSB sub-word MSB_SUB consists of all ones, the MSB switching circuit 220 closes the switches S256(A) and S256(B) associated with resistor R256. Therefore, V2 is equal to the voltage at the upper terminal of R256, and V1 is equal to the voltage at the lower terminal of R256. Because the voltage V1 is approximately the desired analog representation of the digital input word D_IN, we refer to V1 as a coarse representation of the digital input word.

[0030] 3 is a schematic diagram of a first LSB interpolator section 130 for interpolating between voltages V2 and V1. The first LSB interpolator section 130 includes a number of switches SL(1)-SL(2) each having an output. P 3, P is equal to two (P=2), so switching circuit 304 includes four switches SL(1) through SL(4) having outputs 308(1), 308(2), 308(3), and 308(4), respectively.

[0031] Switch SL(1) couples its output 308(1) to V1. The remaining switches SL(2)-SL(4) couple their respective outputs to V2 or V1. For example, switch SL(2) may couple output 226 to output 308(2), such that voltage V2 appears at output 308(2), or switch SL(2) may couple output 228 to output 308(2), such that voltage V1 appears at output 308(2). Switch SL(3) may couple output 226, such that voltage V2 appears at output 308(3), or switch SL(2) may couple output 228, such that voltage V1 appears at output 308(1).

[0032] The first LSB interpolator section 130 includes a first LSB decoder 340 having an input 342 coupled to receive the first LSB sub-word LSB_SUB1. The first LSB decoder 340 decodes the first LSB sub-word LSB_SUB1 and provides a first LSB control signal LSB_CNTR1 at an output 344. In one example, the first LSB sub-word consists of the least significant P bits of the digital input word D_IN. In response to the first LSB control signal LSB_CNTR1, the switching circuit 304 closes switches SL(2)-SL(4) to couple their respective outputs to V2 or V1.

[0033] The first LSB interpolator section 130 includes a first transconductance circuit 350 having multiple differential stages. For an N-bit LSB sub-word, the transconductance circuit 350 includes identical or substantially identical differential stages. In another example, the differential stages may be binary weighted.

[0034] In the example of FIG. 3, the transconductance circuit 350 includes four differential stages (e.g., 2 P The amplifier has three differential stages, P equal to 2 in this example. Transistors MP1A and MP1B form a first differential stage, transistors MP2A and MP2B form a second differential stage, transistors MP3A and MP3B form a third differential stage, and transistors MP4A and MP4B form a fourth differential stage. Transistors MP1A, MP1B, MP2A, MP2B, MP3A, MP3B, and MP4A, MP4B have respective first (current) terminals 361, 362, 363, 364, 365, 366, 367, 368 (e.g., sources) coupled to a current source I. In some examples, the first terminals 361, 362, 363, 364, 365, 366, 367, 368 (e.g., sources) of these transistors may be connected to respective current sources (e.g., I1, I2, I3....), which supply currents of equal or unequal magnitude.

[0035] One of the transistors MP1A in the differential stage has a control terminal 370 (e.g., gate) coupled to output 228 via switch SL(1) to receive V1. Transistors MP2A, MP3A, and MP4A have respective control terminals 371, 372, and 373 (e.g., gates) coupled to either output 226 or 228 via switches SL(2)-SL(4) to receive either V1 or V2. Transistors MP1B, MP2B, MP3B, and MP4B have respective control terminals 381, 382, ​​383, and 384 (e.g., gates) coupled to output 390.

[0036] Variations of first LSB interpolator portion 130 are possible within the scope of this description. For example, in some instances, control terminal 370 (e.g., a gate) of MP1A may be coupled directly to output 228 without the need for switch SL(1), and in such instances, switching circuit 334 may include only three switches instead of four switches as shown in FIG.

[0037] Transistors MP1A, MP1B, MP2A, MP2B, MP3A, MP3B, and MP4A, MP4B have respective second (current) terminals 392, 393, 394, 395, 396, 397, 398, and 399 (e.g., drains) that are coupled to the current mirror circuit CM1.

[0038] In one example, the current mirror circuit CM1 includes transistors MN1 and MN2 having respective control terminals (e.g., gates) 3002 and 3004 coupled together. Transistor MN1 has a first terminal 3006 (e.g., drain) coupled to the drains of transistors MP1A-MP4A, and transistor MN2 has a first terminal 3008 (e.g., drain) coupled to the drains of transistors MP1B-MP4B. The control terminals 3002, 3004 of transistors MN1, MN2 are also coupled to the first terminal 3008 of MN2. Transistors MN1 and MN2 have respective second terminals 3010 and 3012 (e.g., sources) coupled to a negative reference terminal 3014 that may be coupled to a negative voltage V−.

[0039] The first interpolator section 130 includes a feedback amplifier A1 having an inverting input 3020, a non-inverting input 3022, and an output 390. The inverting input 3020 is coupled to a first terminal 3006 of transistor MN1, and the non-inverting input 3022 is coupled to a first terminal 3008 of transistor MN2. The output 390 is coupled to the control terminals of transistors MN1B-MN4B. A transconductance stage and current mirror circuit CM1 provides a negative feedback path between the output 390 and the inverting input 3020 of amplifier A1.

[0040] Initially, the first LSB subword may be [0,0]. In response, switches SL(2), SL(3), and SL(4) couple control terminals 370, 371, 372, and 373 (e.g., gates) of transistors MP1A, MP2A, MP3A, and MP4A, respectively, to V1. Because drains 392, 394, 396, and 398 of MP1A, MP2A, MP3A, and MP4A, respectively, are coupled to drain 3006 of MN1, the sum of the currents through MP1A, MP2A, MP3A, and MP4A flows through MN1. Also, because MN1 and MN2 are coupled in a current mirror configuration, the current through MN2 must be equal to the current through MN1. As a result, the voltages at the control terminals 381, 382, ​​383, and 384 (e.g., gates) of transistors MP1B, MP2B, MP3B, and MP4B must be equal to the voltages at the control terminals 370, 371, 372, and 373 of transistors MP1A, MP2A, MP3A, and MP4A, respectively. Due to the negative feedback effect of amplifier A1, the voltages at the control terminals of MP1B, MP2B, MP3B, and MP4B are set equal to the voltages at the control terminals of MP1A, MP2A, MP3A, and MP4A. Therefore, the voltage V_INT1 at the output 390 of amplifier A1 is equal to V1. In this case, the four differential stages of the transconductance circuit 350 are considered to be balanced.

[0041] Next, in response to the value of the first LSB subword being incremented from [0,0] to [0,1], one of the switches (e.g., switch SL(2)) couples the control terminal 371 (e.g., gate) of MP2A to V2. Thus, the control terminals (e.g., gates) of MP1A, MP3A, and MP4A are coupled to V1, while the control terminal of MP2A is coupled to V2.

[0042] For example, if V2 is 4 mV higher than V1, the current through MP2A will decrease, which will result in a decrease in the current through MN1. The current through MN2 must equal the current through MN1, and the negative feedback action of amplifier A1 will increase the voltage V_INT1 at output 390, which will decrease the sum of the currents through MP1B, MP2B, MP3B, and MP4B. When the feedback action of A1 makes the current through MN1 equal to MN2, the sum of the currents through MP1A, MP2A, MP3A, and MP4A will equal MP1B, MP2B, MP3B, and MP4B.

[0043] In response to the value of the first LSB subword being further incremented to [1,0], switch SL(3) couples the control terminal 372 (e.g., gate) of MP3A to V2. Thus, the control terminals of MP2A and MP3A are both coupled to V2. As the current through MN1 decreases, the negative feedback action of amplifier A1 causes the voltage V_INT at the output 390 of amplifier A1 to increase in order to reduce the total current through MP1B, MP2B, MP3B, and MP4B, so that the current through MN2 becomes equal to the current flowing through MN1.

[0044] In response to the value of the first LSB sub-word being incremented yet further to [1,1], switch SL(4) couples the control terminal 373 (e.g., gate) of MP4A to V2. Thus, the control terminals of MP2A, MP3A, and MP4A are coupled to V2. As the current through MN1 decreases, the negative feedback action of amplifier A1 increases the voltage V_INT1 at the output 390 of amplifier A1 to reduce the total current flowing through transistors MP1B, MP2B, MP3B, and MP4B, such that the current flowing through MN2 is equal to the current flowing through MN1. Thus, incrementing the first LSB sub-word increases the voltage V_INT1 at output 390.

[0045] Conversely, when the first LSB subword is decremented from [1,1] to [1,0], switch SL(4) couples the control terminal 373 (e.g., gate) of MP4A to V1. Thus, the control terminals (e.g., gates) of MP1A and MP4A are coupled to V1, while the control terminals of MP2A and MP3A are coupled to V2. As a result, the current through MP4A increases. The current flowing through MN2 must equal the current flowing through MN1, and due to the negative feedback effect, the voltage V_INT1 at the output 390 of amplifier A1 decreases, causing the sum of the currents through MP1B through MP4B to increase until the current through MN2 equals the current through MN1.

[0046] When the first LSB sub-word is decremented from [1,0] to [0,1], switch SL(3) couples the control terminal 372 (e.g., gate) of MP3A to V1. Thus, the control terminals of MP4A, MP3A, and MP1A are coupled to V1, while the control terminal of MP2A is coupled to V2. As a result, the current through MP3A increases, which in turn increases the current through MN1. Because the current through MN2 must equal the current through MN1, the voltage V_INT1 at the output 390 of amplifier A1 decreases, so that the current through MN2 equals the current through MN1. Thus, decrementing the first LSB sub-word causes the voltage V_INT1 at output 390 to decrease.

[0047] 4 is a schematic diagram of a second LSB interpolator section 150 for interpolating between voltages V2 and V_INT1. The second LSB interpolator section 150 includes a switching circuit 404 having outputs 408(1)-408(2), respectively. Q ) Q 4, Q is equal to two (Q=2), so switching circuit 404 includes four switches SN(1) through SN(4) with respective outputs 408(1), 408(2), 408(3), and 408(4).

[0048] Switches SN(1)-SN(4) are arranged such that SN(1) couples V_INT1 to its output 408(1). The remaining switches SN(2)-SN(4) may selectively connect their respective outputs to either V2 or V1. For example, switch SN(2) may couple output 226 to output 408(2), such that voltage V2 appears at output 408(2), or switch SN(2) may couple output 228 to output 408(2), such that voltage V1 appears at output 408(2). Switch SN(3) may couple output 226 to output 408(3), such that voltage V2 appears at output 408(3), or switch SN(3) may couple output 226 to output 408(3), such that voltage V1 appears at output 408(3).

[0049] The second LSB interpolator section 150 includes a second LSB decoder 430 having an input 422 coupled to receive the second LSB sub-word LSB_SUB2. The second LSB decoder 430 decodes the second LSB sub-word LSB_SUB2 and provides a second LSB control signal LSB2_CNTR at an output 424. In one example, the second LSB sub-word comprises the middle Q bits of the digital input word D_IN. In response to the second LSB control signal LSB2_CNTR, the switching circuit 404 closes switches SN(2)-SN(4) to couple their respective outputs to V2 or V1.

[0050] The second LSB interpolator section 150 includes a second transconductance circuit 440 having multiple differential stages. For a Q-bit LSB subword, the second transconductance circuit 440 Q In some examples, the differential stages may be binary weighted, or the differential stages may be identical or substantially identical, or may be non-identical.

[0051] In the example of FIG. 4, the transconductance circuit 440 includes two transistors, each of which includes a pair of transistors. Q 451, 452, 453, 454, 456, 457, 458, 459 (e.g., if Q is equal to 2, there are four differential stages). Transistors MP5A and MP5B form a first differential stage, transistors MP6A and MP6B form a second differential stage, transistors MP7A and MP7B form a third differential stage, and transistors MP8A and MP8B form a fourth differential stage. Transistors MP5A, MP5B, MP6A, MP6B, MP7A, MP7B, and MP8A, MP8B have respective first (current) terminals 451, 452, 453, 454, 456, 457, 458, 459 (e.g., sources) coupled to a current source I. In some examples, the first terminals 451, 452, 453, 454, 456, 457, 458, 459 (e.g., sources) of these transistors may be connected to respective current sources (e.g., I1, I2, I3, I4), and the magnitude of the current provided by each current source may or may not be equal.

[0052] One of the transistors MP5A of the differential stage has a control terminal 460 (e.g., gate) coupled via switch SN(1) to receive V_INT1. Transistors MP6A, MP7A, and MP8A have respective control terminals 461, 462, and 463 (e.g., gates) coupled via switches SN(2)-SN(4) to either output 226 or 228, respectively, to receive either V1 or V2. Transistors MP5B, MP6B, MP7B, and MP8B have respective control terminals 466, 467, 468, and 469 (e.g., gates) coupled to output 490 of second LSB interpolator section 440.

[0053] Variations of second LSB interpolator section 150 are possible within the scope of this description. For example, in some examples, control terminal 460 (e.g., a gate) of MP5A may be coupled directly to output 228 without the need for switch SN(1), and in these examples, switching circuit 404 includes three switches instead of the four switches shown in FIG.

[0054] Transistors MP5A, MP5B, MP6A, MP6B, MP7A, MP7B, and MP8A, MP8B have respective second (current) terminals 472, 473, 474, 475, 476, 477, 478, and 479 (e.g., drains) that are coupled to the current mirror circuit CM2.

[0055] In one example, the current mirror circuit CM2 includes transistors MN3 and MN4 having respective control terminals (e.g., gates) 4002 and 4004 coupled together. Transistor MN3 has a first terminal 4006 (e.g., drain) coupled to the drains of transistors MP5A-MP8A, and transistor MN3 has a first terminal 4008 (e.g., drain) coupled to the drains of transistors MP5B-MP6B. The control terminals 4002, 4004 of transistors MN3, MN4 are also coupled to the first terminal 4008 of MN4. Transistors MN3 and MN4 have respective second terminals 4010 and 4012 (e.g., sources) coupled to a negative reference terminal 4014 that may be coupled to a negative voltage V−.

[0056] The second interpolator section 150 includes a feedback amplifier A2 having an inverting input 4020, a non-inverting input 4022, and an output 490. The inverting input 4020 is coupled to a first terminal 4006 of transistor MN3, and the non-inverting input 4022 is coupled to a first terminal 4008 of transistor MN4. The output 490 is coupled to the control terminals of transistors MN5B-MN8B. A transconductance stage and current mirror circuit CM2 provides a negative feedback path between the output 490 and the inverting input 4020.

[0057] The operation of the second LSB interpolator section 150 is similar to that of the first LSB interpolator section. In response to the second LSB sub-word LSB_SUB2, the second LSB interpolator section 150 interpolates a voltage between V_INT1 and V2 and provides an output VOUT at output 490.

[0058] In one example, the output V_INT1 of the first interpolator section and the output VOUT of the second interpolator section may be represented by the following equations, respectively: V_INT1 = V1 + p × (Vref / 2 M+P ) (1) V_OUT=V1+(q×2 P +p) × Vref / 2 (M+P+Q) (2) where p=0,1,..,2 P -1, q=0,1,..,2Q −1, M represents the most significant bit of the digital input word, Q represents the middle least significant bit of the digital input word, and P represents the lower least significant bit of the digital input word.

[0059] In the illustrated example, the DAC 100 offers several advantages over currently existing DACs. From the above equation, the output voltage of the DAC 100 is a function of the coarse component (V1) and the interpolated component ((q×2 P +p) × Vref / 2 (M+P+Q) ) The interpolation component is 2 (M+P+Q) As a result, the DAC 100 provides higher resolution in the output. In contrast, in existing DACs, the interpolation component is 2 (M+Q) as the denominator, which results in a loss of resolution in the output.

[0060] An additional advantage of the DAC 100 is that the area required to build the DAC 100 in an integrated circuit is much smaller than the area required to build existing DACs. An existing 16-bit DAC may include a 7-bit string DAC section and a 9-bit single interpolator section. Thus, the single interpolator section may have 512 (2 9 ) differential stages, which may occupy a relatively large area in an integrated circuit. In contrast, the DAC 100 in the described example includes two cascaded interpolator sections, a first interpolator section 130 and a second interpolator section 150. If the first interpolator section 130 is a 5-bit interpolator section and the second interpolator section 150 is a 4-bit interpolator section, the total number of differential stages required is 48 (2 5 +2 4 ) As such, DAC100 significantly reduces the number of differential stages required, and thus significantly reduces the area required to implement DAC100 on an integrated circuit.

[0061] A further advantage of DAC 100 is that first and second interpolator sections 130 and 150 are independent of each other, so that first and second interpolator sections 130 and 150 can be independently optimized based on the application.

[0062] In accordance with the principles described above, DAC 100 may be configured to include more than one interpolator section. Thus, while example DAC 100 is shown to include first and second interpolator sections 130 and 150, DAC 100 may be modified to include more than two interpolator sections.

[0063] In this description, the term "coupled" may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, (a) in a first example, device A is coupled to device B if device A provides signals to control device B to perform a certain action, or (b) in a second example, device A is coupled to device B via an intervening component C such that device B is controlled by device A via control signals provided by device A, if the intervening component C does not substantially change the functional relationship between device A and device B. Also, in this description, a device that is "configured" to perform a certain task or function may be configured (e.g., programmed and / or hardwired) to perform that function by a manufacturer at the time of manufacture and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuring may be accomplished by firmware and / or software programming of the device, by the construction and / or layout of the hardware components and interconnections of the device, or by a combination of these. Also, in this description, a circuit or device including certain components may instead be adapted to be coupled to those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure, either during or after manufacture, e.g., by an end user and / or a third party.

[0064] As used herein, the terms "terminal," "node," "interconnect," and "pin" are used interchangeably. Unless otherwise noted, these terms are used generally to refer to an interconnection between or among terminals of device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0065] Although particular transistors are described herein, other transistors (or equivalent devices) may be used instead with little or no modification to the remaining circuit elements. For example, metal oxide silicon FETs ("MOSFETs") (such as n-channel MOSFETs, nMOSFETs, or p-channel MOSFETs, pMOSFETs), bipolar junction transistors (BJTs, e.g., NPN or PNP), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in combination with the devices described herein. The transistors may be depletion mode devices, drain extension devices, enhancement mode devices, natural transistors, or other types of device structures. Also, such devices may be implemented in / on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs).

[0066] Although certain components may be described herein as being of a particular process technology, these components may be replaced with components of other process technologies. Circuits described herein are reconfigurable to include the replaced components, thereby providing at least partially similar functionality to that available prior to the replacement of the components. Components illustrated as resistors generally represent any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the illustrated resistor, unless otherwise specified. For example, a resistor or capacitor illustrated and described herein as a single component may be multiple resistors or capacitors coupled in series or parallel between the same two nodes as a single resistor or capacitor, respectively. Additionally, use of the phrase "ground" in this description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable to the teachings of this description. Unless otherwise specified, "about," "approximately," or "substantially" preceding a value means ±10 percent of the stated value.

[0067] Some elements may be included in the integrated circuit and other elements may be external to the integrated circuit, while in other instances additional or fewer features may be incorporated into the integrated circuit. Also, some or all of the functionality illustrated as being external to the integrated circuit may be included within the integrated circuit and / or some of the functionality illustrated as being within the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" refers to one or more circuits that are (1) incorporated within / on a semiconductor substrate, (2) incorporated in a single semiconductor package, (3) incorporated within the same module, and / or (4) incorporated within / on the same printed circuit board.

[0068] Modifications in the described examples are possible, and other examples are possible, within the scope of the claims.

Claims

1. 1. A digital-to-analog converter (DAC) for converting a digital input word into an analog output signal, comprising: A string DAC, a plurality of series-connected resistors; a most significant bit (MSB) switching circuit including pairs of switches, each switch pair having an upper switch and a lower switch, each upper switch connected to an upper terminal of one of the plurality of series connected resistors and each lower switch connected to a lower terminal of one of the plurality of series connected resistors, the MSB switching circuit operable to provide a first voltage and a second voltage in response to an MSB control signal; the string DAC, a first least significant bit (LSB) interpolator coupled to the string DAC, the first LSB interpolator having an output, a plurality of non-inverting inputs and a plurality of inverting inputs coupled to the output, one of the non-inverting inputs coupled to receive the first voltage and the other non-inverting input coupled to receive the first voltage or the second voltage, the first LSB interpolator operable to provide a first interpolated voltage at the output in response to a first LSB control signal; a second LSB interpolator coupled to the string DAC and to the first LSB interpolator, the second LSB interpolator having an output, a plurality of non-inverting inputs and a plurality of inverting inputs coupled to the output, one of the non-inverting inputs coupled to receive the first interpolated voltage and the other non-inverting input coupled to receive the first voltage or the second voltage, the second LSB interpolator operable to provide an output voltage at the output in response to a second LSB control signal; DAC, including:

2. 2. The DAC of claim 1, the string DAC including an MSB decoder having an input coupled to receive an MSB sub-word, the MSB decoder operable to provide the MSB control signal by decoding the MSB sub-word.

3. 3. The DAC of claim 2, The DAC, wherein the MSB sub-word comprises M most significant bits of the digital input word, where M is an integer.

4. 2. The DAC of claim 1, the first LSB interpolator includes a first LSB decoder having an input coupled to receive a first LSB sub-word, the first LSB decoder being operable to provide the first LSB control signal by decoding the first LSB sub-word.

5. 5. The DAC of claim 4, The DAC, wherein the first LSB sub-word comprises the lower P least significant bits of the digital input word.

6. 2. The DAC of claim 1, the second LSB interpolator includes a second LSB decoder having an input coupled to receive a second LSB sub-word, the second LSB decoder being operable to provide the second LSB control signal by decoding the second LSB sub-word.

7. 7. A DAC according to claim 6, The DAC, wherein the second LSB sub-word comprises the middle Q least significant bits of the digital input word.

8. 2. The DAC of claim 1, The MSB switching circuit is further operable to close one of the pair of switches to provide the first voltage and the second voltage.

9. 1. A digital-to-analog converter (DAC) for converting a digital input word into an analog output signal, comprising: a first least significant bit (LSB) interpolator circuit having an output, a plurality of non-inverting inputs, and a plurality of inverting inputs coupled to the output, one of the non-inverting inputs adapted to receive a coarse representation voltage and the other non-inverting input adapted to receive the coarse representation voltage or a second voltage higher than the coarse representation voltage, the first LSB interpolator circuit operable to provide a first interpolated voltage at the output; a second LSB interpolator circuit coupled to the first LSB interpolator circuit, the second LSB interpolator circuit having an output, a plurality of non-inverting inputs and a plurality of inverting inputs coupled to the output, one of the non-inverting inputs adapted to receive the first interpolated voltage and the other non-inverting input adapted to receive the coarse representation voltage or the second voltage, the second LSB interpolator circuit operable to provide an output voltage; An ADC comprising:

10. 10. The DAC of claim 9, The first LSB interpolator circuit is adapted to receive a first LSB sub-word and is further operable to provide the first interpolated voltage in response to the first LSB sub-word.

11. 10. The DAC of claim 9, The second LSB interpolator circuit is adapted to receive a second LSB sub-word and is further operable to provide the output voltage in response to the second LSB sub-word.

12. 10. The DAC of claim 9, the first LSB interpolator circuit comprising: a first transconductance circuit including a plurality of first and second transistors having respective first terminals adapted to receive a tail current, respective second terminals, and a control terminal, wherein one of the control terminals of the first transistors is adapted to be coupled to receive the coarse representation voltage, and the other control terminal of the first transistor is adapted to receive the coarse representation voltage or the second voltage; a first current mirror circuit including third and fourth transistors having respective first terminals, second terminals and control terminals, wherein the first terminal of the third transistor is coupled to the second terminals of the plurality of first transistors, the first terminal of the fourth transistor is coupled to the second terminals of the plurality of second transistors, the control terminals of the third and fourth transistors are coupled to the first terminal of the fourth transistor, and the second terminals of the third and fourth transistors are coupled to a negative reference terminal; a first feedback amplifier having an inverting input coupled to the first terminal of the third transistor, a non-inverting input coupled to the first terminal of the fourth transistor, and an output coupled to a control terminal of the second transistor, the first feedback amplifier providing the first interpolated voltage at its output; DAC, including:

13. 10. The DAC of claim 9, the second LSB interpolator circuit comprising: a second transconductance circuit including a plurality of fifth and sixth transistors having respective first terminals adapted to receive a tail current, respective second terminals, and a control terminal, wherein one of the control terminals of the fifth transistor is coupled to receive the first interpolated voltage and the other control terminal of the fifth transistor is adapted to receive the coarse representation voltage or the second voltage; a second current mirror circuit including seventh and eighth transistors having respective first terminals, second terminals and control terminals, wherein the first terminal of the seventh transistor is coupled to the second terminal of the plurality of fifth transistors, the first terminal of the eighth transistor is coupled to the second terminal of the plurality of sixth transistors, the control terminals of the seventh and eighth transistors are coupled to the first terminal of the eighth transistor, and the second terminals of the seventh and eighth transistors are coupled to a negative reference terminal; a second feedback amplifier having an inverting input coupled to a first terminal of the seventh transistor, a non-inverting input coupled to a first terminal of the eighth transistor, and an output coupled to control terminals of the plurality of second transistors, the second feedback amplifier providing the output voltage; DAC, including:

14. 1. A digital-to-analog converter (DAC) for converting a digital input word into an analog output signal, comprising: A string DAC, a plurality of series-connected resistors; a most significant bit (MSB) switching circuit including pairs of switches, each switch pair having an upper switch and a lower switch, each upper switch connected to an upper terminal of one of the plurality of series connected resistors and each lower switch connected to a lower terminal of one of the plurality of series connected resistors, the MSB switching circuit operable to provide a first voltage and a second voltage in response to M most significant bits of the digital input word; the string DAC, a first least significant bit (LSB) interpolator coupled to the string DAC, the first LSB interpolator having an output and a plurality of inputs, one of the inputs coupled to receive the first voltage and another input adapted to receive the first voltage or the second voltage, the first LSB interpolator operable to interpolate between the first and second voltages in response to the lower P least significant bits of the digital input word to provide a first interpolated voltage; a second least significant bit (LSB) interpolator coupled to the string DAC and to the first LSB interpolator, the second LSB interpolator having an output and a plurality of inputs, one of the inputs coupled to receive the first interpolated voltage and another input adapted to receive the first voltage or the second voltage, the second LSB interpolator operable to provide an output voltage at the output in response to intermediate Q least significant bits of the digital input word; DAC, including:

15. 15. The DAC of claim 14, the first LSB interpolator includes a first transconductance circuit including a plurality of first and second transistors having respective first terminals adapted to receive a tail current, respective second terminals, and a control terminal, one of the control terminals of the first transistors coupled to receive the first voltage, and the other control terminal of the first transistor coupled to receive the first voltage or the second voltage.

16. 15. The DAC of claim 14, the first LSB interpolator includes a first current mirror circuit including third and fourth transistors having respective first terminals, second terminals and control terminals, a first terminal of the third transistor coupled to a second terminal of the plurality of first transistors, a first terminal of the fourth transistor coupled to a second terminal of the plurality of second transistors, the control terminals of the third and fourth transistors coupled to a first terminal of the fourth transistor, and the second terminals of the third and fourth transistors coupled to a negative reference terminal.

17. 15. The DAC of claim 14, the first LSB interpolator includes a first feedback amplifier having an inverting input coupled to a first terminal of the third transistor, a non-inverting input coupled to a first terminal of the fourth transistor, and an output coupled to a control terminal of the second transistor, the first feedback amplifier operable to provide the first interpolated voltage at the output.

18. 15. The DAC of claim 14, the second LSB interpolator includes a second transconductance circuit including a plurality of fifth and sixth transistors having respective first terminals adapted to receive a tail current, respective second terminals, and a control terminal, one of the control terminals of the fifth transistor being coupled to receive the first interpolation voltage and the other control terminal of the fifth transistor being coupled to receive the first voltage or the second voltage.

19. 20. The DAC of claim 18, the second LSB interpolator further includes a second current mirror circuit including seventh and eighth transistors having respective first terminals, second terminals and a control terminal, wherein a first terminal of the seventh transistor is coupled to a second terminal of the plurality of fifth transistors, a first terminal of the eighth transistor is coupled to a second terminal of the plurality of sixth transistors, the control terminals of the seventh and eighth transistors are coupled to the first terminal of the eighth transistor, and the second terminals of the seventh and eighth transistors are coupled to a negative reference terminal.

20. 20. The DAC of claim 19, the second LSB interpolator further comprises a second feedback amplifier having an inverting input coupled to a first terminal of the seventh transistor, a non-inverting input coupled to a first terminal of the eighth transistor, and an output coupled to control terminals of the plurality of second transistors, the second feedback amplifier operable to provide the output voltage.

21. A digital-to-analog converter (DAC), comprising: a first DAC section configured to provide signals at first and second outputs in response to a most significant bit of a digital input word; a plurality of resistors coupled in series between a reference voltage terminal and a common potential terminal, each resistor having a first and second terminal; a first switching circuit coupled to the plurality of resistors, the first switching circuit having the first and second outputs; a first DAC section including: a first least significant bit (LSB) interpolator having an output, a first non-inverting input coupled to the first and second outputs of the first DAC section, and a first inverting input coupled to the output, the first LSB interpolator being configured to provide a first voltage at an output of the first LSB interpolator in response to a first LSB of the digital input word; a second LSB interpolator having a second non-inverting input, a second inverting input, and an output, one of the second non-inverting inputs coupled to the output of the first LSB interpolator, another second non-inverting input coupled to the first and second outputs of the first DAC section, and the second inverting input coupled to the output of the second LSB interpolator, the second LSB interpolator being configured to provide a second voltage at the output of the second LSB interpolator in response to a second LSB of the digital input word; DAC, including:

22. A digital-to-analog converter (DAC), comprising: a first least significant bit (LSB) interpolator having an output, a first non-inverting input, and a first inverting input coupled to the output, the first LSB interpolator being configured to provide a first voltage at the output in response to a first LSB of a digital word; a second LSB interpolator having an output, a second non-inverting input, and a second inverting input coupled to the output, one of the second non-inverting inputs coupled to the output of the first LSB interpolator, the second LSB interpolator being configured to provide a second voltage at the output in response to a second LSB of the digital word; DAC, including:

Images