SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE, AND MANUFACTURING METHOD

Abstract

In one embodiment, the semiconductor device (1) comprises: a semiconductor chip (2) configured for a voltage of at least 0.6 kV and having upper contact regions (21) on a chip top surface (20); a first electrical wiring layer (3) in electrical contact with the upper contact region (21), the first electrical wiring layer (3) having first contact regions (31) electrically assigned to the upper contact region (21); and a second electrical wiring layer (4) located on a side of the first electrical wiring layer (3) remote from the upper contact region (21) and having second contact regions (42) electrically assigned to the upper contact region (31), the second contact regions (42) being configured as external contact regions, at least one of the second contact regions (42) having a different shape than the assigned one of the upper contact regions (21) when viewed in a top view of the chip top surface (20).

Description

[Technical field]

[0001] A semiconductor device and a semiconductor module comprising such a semiconductor device are provided. A method for manufacturing such a semiconductor device is also provided. [Background technology]

[0002] EP 2 988 328 A1 refers to a power semiconductor module.

[0003] DE 10 2014 218 240 A1 discloses a power device integrated into a printed circuit board.

[0004] German Patent Application Publication No. 10 2015 115999, US Patent Application Publication No. 2010 / 0078789, US Pat. No. 8 975 732, German Utility Model No. 20 2011 110547 and European Patent Application Publication No. 3 534 394 refer to electrical devices. Summary of the Invention [Problem to be solved by the invention]

[0005] The problem to be solved is to provide a semiconductor device that can be used at relatively high voltages. [Means for solving the problem]

[0006] This object is achieved, inter alia, by a semiconductor device, a semiconductor module and a method as defined in the independent claims. Exemplary further developments form the subject matter of the dependent claims.

[0007] For example, the semiconductor device comprises at least one intermediate electrical wiring layer within the insulator, the at least one intermediate electrical wiring layer being located between a chip top contact area of ​​the semiconductor chip and a second contact area for external contact of the semiconductor device.

[0008] The at least one intermediate electrical wiring layer allows the shape of the second contact area to be designed independently of the shape of the chip top contact area. Furthermore, the distance between the chip top contact area and the outer surface of the semiconductor device can be increased. Thus, a high voltage can be provided to the semiconductor device, and the second contact area can be designed in a variety of ways for electrical connection of the semiconductor device.

[0009] In at least one embodiment, the semiconductor device comprises: a semiconductor chip configured for a voltage of at least 0.6 kV and having a top contact region on a top surface of the chip; a first electrical wiring layer in electrical contact with the upper contact region, the first electrical wiring layer having a first contact region electrically assigned to the upper contact region; a second electrical wiring layer located on a side remote from the upper contact region of the first electrical wiring layer and having a second contact region electrically assigned to the upper contact region, the second contact region being configured as an external contact region; Equipped with At least one of the second contact regions is shaped differently from an assigned one of the upper contact regions when viewed in a top view of the top surface of the chip.

[0010] For example, the at least one semiconductor chip is selected from the following group: metal-oxide-semiconductor field-effect transistor (MOSFET), metal-insulator-semiconductor field-effect transistor (MISFET), insulated-gate bipolar transistor (IGBT), bipolar junction transistor (BJT), thyristor, gate turn-off thyristor (GTO), gate commutated thyristor (GCT), junction gate field-effect transistor (JFET), and diode. When multiple semiconductor chips are present, all the semiconductor chips may be of the same type, or there may be different types of semiconductor chips.

[0011] For example, semiconductor devices are power devices in vehicles, such as hybrid or plug-in electric vehicles, and even rail, such as commuter trains, that convert direct current from batteries to alternating current for electric motors.

[0012] For example, the semiconductor chip, and thus the semiconductor device, is configured for a maximum voltage of at least 0.6 kV, or at least 1.2 kV, or at least 1.6 kV. Alternatively or additionally, the semiconductor chip, and thus the semiconductor device, is configured for a maximum current of at least 1 A, or at least 20 A, or at least 50 A, which may be up to 1000 A or up to 200 A.

[0013] For example, the first electrical wiring layer is an electrical wiring layer adjacent to the top surface of the chip. Between the top surface of the chip and the first electrical wiring layer are one or more electrical insulating layers. Through the insulating layers, electrical through contacts connect the top contact area of ​​the semiconductor chip to the first contact area. The first contact area may be a structured metallization layer applied onto at least one electrical insulating layer.

[0014] Similarly, at least one electrical insulation layer is present between the first and second electrical wiring layers, and the electrical through contacts extend through the at least one electrical insulation layer. The second electrical wiring layer is the uppermost electrical wiring layer applied to the outer surface of the semiconductor device. For example, the second electrical wiring layer is a further structured metallization layer applied on the uppermost electrical insulation layer. The second electrical wiring layer is therefore the electrical wiring layer furthest from the chip top surface. The second contact area allows the semiconductor device to be contacted externally, for example to a circuit board.

[0015] For example, at least one or some or all of the second contact regions may be shaped differently from the upper contact regions assigned to each of the upper contact regions in a top view of the chip top surface. At least one or some or all of the second contact regions may be shaped differently from the first contact regions assigned to each of the first contact regions.

[0016] According to at least one embodiment, the semiconductor device further comprises one or more third electrical wiring layers. The at least one third electrical wiring layer is located between the first and second electrical wiring layers. Furthermore, the at least one third electrical wiring layer is electrically connected to each of the first and second electrical wiring layers, in particular by electrical through contacts extending through the adjacent additional insulating layer. The at least one third electrical wiring layer comprises, for example, third contact regions formed by at least one additional structured metallization layer.

[0017] According to at least one embodiment, starting from the chip top surface, there is a sequence of the top contact region of the semiconductor chip - insulating layer with electrical through contact - first contact region of the first electrical wiring layer - insulating layer with electrical through contact - second contact region of the second electrical wiring layer. If there are N third electrical wiring layers, there is a sequence of the top contact region of the semiconductor chip - insulating layer with electrical through contact - first contact region of the first electrical wiring layer - N times (insulating layer with electrical through contact - third contact region of the third electrical wiring layer) - insulating layer with electrical through contact - second contact region of the second electrical wiring layer, where N is a natural number greater than or equal to 1. In particular, N=1 or N=2 or N=3. For example, 1≦N≦20, 1≦N≦5, 2≦N≦5 are applicable.

[0018] For example, there is exactly one electrically insulating layer between each electrical wiring layer, and between the top contact region and the first electrical wiring layer.

[0019] According to at least one embodiment, starting from the upper contact region or the first contact region towards the second contact region, the shape of the respectively assigned contact region becomes more similar to the second contact region, for example from the third electrical wiring layer to the third electrical wiring layer and finally towards the second contact region. Thus, the shape of the intermediate electrical wiring layer can be gradually changed to approximate the second contact region.

[0020] According to at least one embodiment, the number of top contact regions is the same as the number of contact regions in each electrical wiring layer. In other words, the number of contact regions does not change from the chip to the second contact region. For example, there can be a one-to-one assignment of contact regions from electrical wiring layer to electrical wiring layer, starting from the top contact region to the second contact region. For example, a contact region of one wiring layer is electrically connected to a contact region of an adjacent wiring layer, in each case by one or more electrical through contacts. The same applies to the top contact region and the first contact region.

[0021] According to at least one embodiment, the thickness of the insulating layers between the wiring layers and between the upper contact region and the first wiring layer is in each case at most 200 μm or at most 120 μm, alternatively or additionally said thickness is at least 10 μm or at least 50 μm or at least 80 μm.

[0022] According to at least one embodiment, at least one or some or each of the wiring layers includes one, two, three or more contact regions.

[0023] The contact areas of different wiring layers can be assigned to each other according to their size. For example, the largest top contact area is assigned to the largest first contact area, the largest second contact area, and the largest third contact area (if present), the smallest top contact area is assigned to the smallest first contact area, the smallest second contact area, and the smallest third contact area (if present), and so on. These assignments can be one-to-one assignments.

[0024] For example, the smallest top contact area and the smallest second contact area are the gate contacts. "Small" and "Large" refer, for example, to the area content of the respective contact areas, i.e., the size of the area to which the respective metallization is applied.

[0025] According to at least one embodiment, in a top view of the chip top surface, at least one of the second contact regions overlaps any one of the upper contact regions by at most 20%, or at most 10%, or at most 5% of the size of the respective second contact region, i.e., in a top view, each second contact region and its assigned upper contact region do not overlap significantly, this may be true for exactly one of the second contact regions, or for some of the second contact regions, or for all of the second contact regions.

[0026] According to at least one embodiment, in a top view of the chip top surface, said at least one of the second contact regions is located completely outside the respective upper contact region, i.e. the respective second contact region and the assigned upper contact region are separate and therefore do not overlap at all in a top view. This can be true for exactly one of the second contact regions, or for several of the second contact regions, or for all of the second contact regions.

[0027] According to at least one embodiment, a first one of the second contact regions extends partially or completely around a second one of the second contact regions, as viewed in a top view of the chip top surface, and thus, as viewed in a top view, a second one of the second contact regions can be completely surrounded by the first one of the second contact regions.

[0028] According to at least one embodiment, a first one of the second contact regions extends coaxially around a second one of the second contact regions. Thus, the respective second contact regions are arranged in a rotationally symmetric and / or point-symmetric manner in a top view. With such a coaxial design, low parasitic inductances can be achieved, as well as improved shielding and reduced stray capacitance.

[0029] The first and second contact regions of the second contact regions are arranged coaxially, which means, for example, that the first and second contact regions of the top contact regions are point-symmetric in shape and have the same center of point symmetry. Alternatively or additionally, this can mean that the first and second contact regions of the second contact regions have the same basic shape, for example a rectangle or a square or a hexagon or an octagon or a circle, as seen in a top view, which basic shapes are oriented in the same way and have corresponding corners, for example on the same straight line passing through a common center of point symmetry. It is possible to map the perimeter lines of the first and second contact regions of the second contact regions onto one another by uniform expansion.

[0030] For example, the first one of the second contact regions may be a frame around the second one of the second contact regions and may be a source or emitter external contact pad. For example, the first one of the second contact regions may be the largest one of the second contact regions. Thus, the second one of the second contact regions may be the smallest external contact pad and may be a gate contact pad.

[0031] Thus, the first and second ones of the second contact regions may provide different external electrical contact regions of the semiconductor device.

[0032] According to at least one embodiment, the upper contact region assigned to the second one of the second contact regions is located at the edge of the chip top surface in a top view of the chip top surface, so that the second contact regions may be arranged in a point-symmetric manner, while the upper contact regions are arranged in a point-asymmetric manner.

[0033] According to at least one embodiment, when viewed in a top view of the top surface of the chip, the third one of the second contact regions is L-shaped and the fourth one of the second contact regions is rectangular and is located within a cutout of the third one of the second contact regions, for example at a corner of the second electrical wiring layer.

[0034] According to at least one embodiment, the upper contact region assigned to the fourth one of the second contact regions is located in a central portion of an edge, such as a longitudinal edge, of the top surface of the chip.

[0035] According to at least one embodiment, in a top view of the top surface of the chip, the fifth and sixth ones of the second contact regions are rectangular and extend parallel to each other.

[0036] According to at least one embodiment, also when viewed in a top view of the chip top surface, the upper contact region assigned to the fifth one of the second contact regions is U-shaped and is located adjacent to all four edges of the chip top surface, and the upper contact region assigned to the sixth one of the second contact regions is located outside the sixth one of the second contact regions.

[0037] According to at least one embodiment, the upper contact region is arranged in a symmetrical manner, for example, in a top view of the chip top surface, there are one or two axes of mirror symmetry with respect to the upper contact region. Alternatively, the upper contact region may be arranged in an asymmetrical manner, i.e. in particular without mirror symmetry or point symmetry.

[0038] According to at least one embodiment, the semiconductor device is a chip-sized package. This may mean that the overall size of the semiconductor device, as viewed in a top view of the top surface of the chip, is 130% or less or 120% or less of the size of the top surface of the chip. Alternatively, or in addition, this may mean that the semiconductor device comprises exactly one semiconductor chip.

[0039] According to at least one embodiment, the total size of all the second contact regions together is larger than the total size of the top contact region or the size of the top surface of the chip. Thus, by having at least one intermediate wiring layer, fan-out and / or extension of the top contact regions towards the second contact regions can be achieved.

[0040] According to at least one embodiment, the thickness of the electrical wiring layer and / or the upper contact region is in each case at least 1 μm or at least 20 μm or at least 40 μm. Alternatively, said thickness is at most 200 μm or at most 100 μm. It is possible for the upper contact region to be thinner than the first and third contact regions and for the second contact region to be thicker than the first and third contact regions.

[0041] According to at least one embodiment, the diameter of the electrical through contact is in any case between 20 μm and 200 μm, for example, this diameter is about 0.1 mm.

[0042] There is further provided a semiconductor module, the semiconductor module comprising a semiconductor device as described in relation to at least one of the above-mentioned embodiments, and therefore features of the semiconductor module are also disclosed for the semiconductor device and vice versa.

[0043] In at least one embodiment, a semiconductor module includes one or more semiconductor devices and an electrical carrier, the second contact region being connected to at least one of an electrical contact surface or a thermal contact surface of the electrical carrier.

[0044] There is further provided a method for manufacturing a semiconductor device, which produces a semiconductor device as described in relation to at least one of the above-mentioned embodiments. Accordingly, features of the semiconductor device are also disclosed for the method and vice versa.

[0045] In at least one embodiment, the method is for manufacturing a semiconductor device. The method comprises the following steps: Providing a semiconductor chip configured for a voltage of at least 0.6 kV and having a top contact region on a top surface of the chip; applying a dielectric material for a first insulating layer onto the upper contact region; forming a first electrical through contact through the first insulating layer and forming a first electrical wiring layer on the first insulating layer, the first contact region being electrically associated with the upper contact region; Optionally, applying at least one dielectric material for at least one third insulating layer on the first electrical wiring layer and forming third electrical through contacts through the at least one third insulating layer and forming at least one third electrical wiring layer on the third insulating layer having third contact areas electrically assigned to the first contact areas; applying a dielectric material for a second insulating layer onto the first electrical wiring layer or onto the uppermost third electrical wiring layer (if present); and forming a second electrical through contact through the second insulating layer and forming a second electrical wiring layer on the second insulating layer, the second electrical wiring layer having a second contact region electrically assigned to the upper contact region and configured as an external contact region of the semiconductor device. for example in the above order, At least one of the second contact regions is shaped differently from an assigned one of the upper contact regions when viewed in a top view of the top surface of the chip.

[0046] In at least one embodiment, the method is for manufacturing a semiconductor device. The method comprises the following steps: Providing a semiconductor chip configured for a voltage of at least 0.6 kV and having a top contact region on a top surface of the chip; applying an insulating layer, a first electrical wiring layer, a second electrical wiring layer, and at least one third electrical wiring layer onto the semiconductor chip; for example in the above order, the first electrical wiring layer has a first contact region electrically connected to the upper contact region and electrically assigned to the upper contact region; the second electrical wiring layer is located on a side farther from the upper contact region of the first electrical wiring layer and has a second contact region electrically assigned to the upper contact region, the second contact region being configured as an external contact region; at least one third electrical wiring layer is located between the first electrical wiring layer and the second electrical wiring layer, is electrically connected to the first electrical wiring layer and the second electrical wiring layer, and has a third contact region; The semiconductor chip is a power metal-insulator field-effect transistor (MISFET) or a power insulated-gate bipolar transistor (IGBT), the first, second and third wiring layers are in each case separated from one another by one of the insulating layers, each made of a dielectric material; at least one of the second contact regions has a different shape, as viewed in a top view of the top surface of the chip, than an assigned one of the upper contact regions; A first one of the second contact regions that is a different shape than the assigned one of the upper contact regions extends completely around a second one of the second contact regions that is a different shape than the assigned one of the upper contact regions, when viewed in a top view of the chip top surface.

[0047] According to the semiconductor device and semiconductor module described herein, the shape of the top contact region and the shape of the external electrical contact regions, such as the second contact region, do not have to correspond. Thus, it becomes possible to design the top contact region to be optimal for the properties of the semiconductor chip, while the second contact region as well as the intermediate contact region can be designed quite independently according to the specific requirements of the application context, such as the available physical space. Thus, geometrical considerations, electrical considerations, such as voltage, current and insulation, as well as thermal considerations, such as heat conduction and heat exchange, can be taken into account simultaneously. For example, a coaxial design of the second contact region can achieve low parasitic inductance, as well as improved shielding, improved suppression of stray capacitance and / or reduced stray inductance. Thus, by making at least one of the second contact regions differently shaped compared to an assigned one of the top contact regions, a multi-faceted optimization can be achieved that is not possible without an intermediate first and possibly even a third electrical wiring layer.

[0048] The semiconductor device, semiconductor module, and method described herein will be described in more detail below by way of exemplary embodiments with reference to the drawings. Identical elements in different figures are indicated by the same reference numerals. However, the relationship between the elements is not shown to scale, and rather, individual elements may be exaggerated to facilitate understanding.

[0049] BRIEF DESCRIPTION OF THE DRAWINGS [Brief description of the drawings]

[0050] [Figure 1] FIG. 2 is a schematic top view of an improved semiconductor device. [Diagram 2] FIG. 2 is a schematic cross-sectional view of the semiconductor device of FIG. [Diagram 3] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 4] FIG. 4 is a vertical schematic top view of the semiconductor device of FIG. [Diagram 5] 1 is a schematic top view of an exemplary embodiment of a semiconductor device described herein; [Figure 6] 1 is a schematic top view of an exemplary embodiment of a semiconductor device described herein; [Figure 7] 1 is a schematic top view of an exemplary embodiment of a semiconductor device described herein; [Figure 8] 1 is a schematic top view of an exemplary embodiment of a semiconductor device described herein; [Figure 9] 1 is a schematic top view of an exemplary embodiment of a semiconductor device described herein; [Figure 10] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 11] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 12] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 13] 1A-1D are various schematic cross-sectional views of exemplary embodiments of semiconductor devices described herein. [Figure 14] 1A-1D are various schematic cross-sectional views of exemplary embodiments of semiconductor devices described herein. [Figure 15] 1A-1D are various schematic cross-sectional views of exemplary embodiments of semiconductor devices described herein. [Figure 16] 1A-1D are various schematic cross-sectional views of exemplary embodiments of semiconductor devices described herein. [Figure 17]1 is a schematic side view of an exemplary embodiment of a semiconductor module comprising a semiconductor device as described herein. [Figure 18] FIG. 1 is a schematic block diagram of an exemplary embodiment of a method for manufacturing a semiconductor device as described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0051] 1 and 2 an improved semiconductor device 9 is shown. The improved semiconductor device 9 comprises a semiconductor chip 2 embedded in an insulator 6. At a chip top surface 20, the semiconductor chip 2 comprises an upper contact area 21. Laterally, i.e. parallel to the chip top surface 20, the semiconductor chip 2 is embedded in an insulating embedment 60 of the insulator 6.

[0052] Starting from the upper contact region 21 a first electrical via contact 71 extends through the first insulating layer 61 of the insulator 6. By means of the via contact 71 the upper contact region 21 is electrically connected to a first contact region 31 of the first electrical wiring layer 3 which is located on the upper body surface 66 of the insulator 6. As an option, the semiconductor chip 2 can be applied on a substrate 8, the side of which can be in contact with the insulator 6.

[0053] Chip-scale packaging (abbreviated CSP) originates from traditional printed circuit board (PCB) manufacturing and was originally conceived for the integration of small and heterogeneous microelectronic and / or optical components (also called System in Package (SiP)) primarily in consumer electronics. However, packages such as those shown in Fig. 1 are not compatible with high voltages, e.g., above 0.6 kV.

[0054] Chip-scale packaging can offer various advantages over TO-like, QFN, and other surface-mount packages, such as improved heat removal, no wire bonds, and fewer parasitics, and can provide an alternative route to power module assembly, such as cleanroom-free assembly. Another key advantage of such embedded solutions is the design freedom to fan out the contact areas, also called bond pads, and integrate multiple layers of signal paths of any shape and complexity as needed. This can make it possible to achieve low-inductance interconnects, integrate sensors and controllers with a large number of I / O channels, and achieve ultra-compact packages that do not require wire bonds, resulting in flatter layouts and / or geometries that are also beneficial for double-sided cooling designs. Finally, such technological developments could impact the current semiconductor power module value chain, i.e., chip manufacturers may adopt the technology, making the current state of the art in power module design and assembly unviable.

[0055] One obvious advantage of CSP is that the chip pad contacts can be fanned out. However, in one-metal prepackage, the fan-out layout is constrained by the layout of the chip contact pads, i.e., the top contact area 21, as shown in FIG. 1. For example, the CSP top metallization must overlap the chip contact pads. Therefore, the layout of the CSP top metallization cannot be arbitrary (it is desirable for the layout of the CSP top metallization to be arbitrary so that there is sufficient flexibility in the placement of the CSP components when designing the power module). Furthermore, the enlargement of, for example, the gate contact pads usually comes at the expense of a reduced drain / emitter contact area and thus a reduced current carrying capacity of the semiconductor chip.

[0056] To overcome these limitations, the semiconductor device 1 described herein comprises at least one intermediate wiring layer located between the top contact region 21 and the top second electrical wiring layer 4, see Figs. 3 and 4. In this way, a multi-layer prepackage is used to create CSP components with an arbitrary layout of the top metallization. This can be done by multiple embedding and stacking steps. Such a solution achieves the desired fan-out without reducing the active area of ​​the semiconductor chip 2 and therefore the current carrying capacity.

[0057] In high voltage applications, the thickness of the encapsulant, and each insulating layer in the case of multi-layer structures, must be properly designed to withstand the blocking voltage. Such requirements can be relaxed if the inner and top metal pads do not cross the termination area of ​​the chip and the component is further encapsulated.

[0058] Thus, a semiconductor device 1 is provided comprising a semiconductor chip 2 configured for a voltage of at least 0.6 kV, the semiconductor chip 2 having an upper contact area 21 on a chip top surface 20, with a plurality of electrical through contacts 71, 72, 73 electrically connected to the upper contact area 21. The semiconductor chip 2 and the electrical through contacts 71, 72, 73 are embedded in an electrically insulating insulator 6, the electrical through contacts 71, 72, 73 extending through the insulator 6 in a direction away from the chip top surface 20. At least one intermediate wiring 3, 5 is present on a side of the upper contact area 21 away from the semiconductor chip 2 and electrically contacts the electrical through contacts 71, 72, 73.

[0059] The wiring layers 3, 4, 5 are designed to avoid short circuits between top contact areas, also called chip terminations, such as gate-source-drain.

[0060] According to Fig. 3 and Fig. 4, above the upper contact region 21 there is a first insulating layer 61 on which a first electrical wiring layer 3 is applied. This first electrical wiring layer 3 is followed by a second insulating layer 62 on which a second electrical wiring layer 4 with a second electrical contact region 42 is applied. The second contact region 42 of the second electrical wiring layer 4 can be the only contact region of the body top surface 66 that is exposed from the insulator 6. However, as an option, the semiconductor chip 2 can be electrically contacted to a substrate 8, which is for example a copper-based lead frame. Thus, the only parts that are exposed from the insulator 6 may be the substrate 8 and the second contact region 42.

[0061] 3 shows a cross-sectional view along the dashed line in FIG. 4. According to FIGS. 3 and 4, the smaller of the rectangular second contact regions 42 is connected to the smaller one of the upper contact regions 21 but does not overlap this upper contact region 21 in top view. This is made possible by the first electrical wiring layer 3 arranged in the insulator 6, which provides a current path parallel to the chip top surface 20. The shape of the second contact region 42 is therefore largely independent of the shape of the upper contact region 21.

[0062] For example, the semiconductor chip 2 is a corresponding power MOSFET or power IGBT configured for a current of more than 10 A and / or less than or equal to 100 A. Alternatively or additionally, the semiconductor chip 2, and thus the semiconductor device 1, is configured for a voltage of at least 1.2 kV or at least 1.5 kV.

[0063] Optionally, the larger of the upper contact regions 21 is shaped like a └┘ or a U when viewed in top view. The smaller of the upper contact regions 21 is located between the legs of the └┘ or U. The arrangement of the upper contact regions 21 can, for example, have at least one axis of mirror symmetry. In FIG. 4, the upper contact regions 21 are symbolized as shaded regions, and the semiconductor chip 2 is also shown diagrammatically for ease of understanding, although the intermediate wiring layer 3 is not shown in FIG. 4.

[0064] For example, the chip top surface 20 has a size of at least 5 mm×5 mm and / or at most 15 mm×15 mm. Alternatively or additionally, the thickness of the semiconductor chip 2 perpendicular to the chip top surface 20 is at least 100 μm and / or at most 1 mm, for example 300 μm to 500 μm.

[0065] For example, the electrical through contacts 71, 72, 73 are metallized holes or even metal blocks. For each contact area 21, 31, 42, 53, there can be only one or several electrical through contacts 71, 72, 73, depending in particular on how the respective contact area 21, 31, 42, 53 is configured for size and current. If the through contacts 71, 72, 73 are metallized holes, the diameter of the through contacts 71, 72, 73 is, for example, 50 μm to 200 μm, and if the through contacts 71, 72, 73 are metal blocks, the through contacts 71, 72, 73 can have a larger lateral extent. Such metal blocks can be bonded to the corresponding contact areas 21, 31, 42, 53, for example by sintering or soldering.

[0066] The height of the via contacts 71, 72, 73 may correspond to the height of the associated insulating layers 61, 62, 63, 65. For example, the via contacts 71, 72, 73 are made from copper or a copper alloy.

[0067] The semiconductor device of Fig. 3 and Fig. 4 comprises two top contact regions 21 and therefore two contact regions 31, 42 in each of the electrical wiring layers 3, 4, but instead there may be only one top contact region 21 and therefore only one contact region 31, 42 in each of the electrical wiring layers 3, 4, or there may be at least three top contact regions 21 and therefore at least three contact regions 31, 42 in each of the electrical wiring layers 3, 4. Furthermore, it is preferred, although not strictly necessary, that the number of top contact regions 21 is the same as the number of contact regions 31, 42 in each of the electrical wiring layers 3, 4. In addition to the electrical contact regions 21, 31, 42, thermal contact regions (not shown) may optionally be present to improve cooling, and these thermal contact regions do not have to have an electrical function. These aspects are also applicable to all other embodiments in any combination.

[0068] Otherwise, the same is applicable to FIGS. 3 and 4 as to FIGS. 1 and 2, and vice versa.

[0069] In FIG. 5, similarly to FIG. 4, another embodiment of the semiconductor device 1 is shown. According to FIG. 5, the second contact regions 42 are arranged in a coaxial manner. Thus, a first second contact region of the second contact regions 42 completely surrounds a second second contact region of the second contact regions 42 in a top view on the chip top surface 20. Thereby, the first second contact region and the second second contact region of the second contact regions 42 belong to the second electrical wiring layer 4 and can be arranged in a common plane as external electrical contact pads. Besides the illustrated, further second contact regions 42 of the second electrical wiring layer 4 can be present as external electrical contact pads.

[0070] For example, the upper contact region 21 assigned to the second one of the second contact regions 42 may be located at the edge of the chip top surface 20 and there may be only a small overlap between these contact regions 21, 42. The upper contact region 21 assigned to the first one of the second contact regions 42 may also be └┘ or U-shaped, also when viewed in a top view of the chip top surface 20.

[0071] When viewed in top view, there may be two or four axes of mirror symmetry for the shape of the second contact regions 42. For example, the track width of a first outer one of the second contact regions 42 may correspond to at least 10% and / or at most 40% of the maximum edge length of the chip top surface 20. The edge length of a second inner one of the second contact regions 42 is, for example, at least 20% and / or at most 60% of the maximum edge length of the chip top surface 20.

[0072] In other respects, the same applies to FIG. 5 as to FIG. 1-FIG. 4, and vice versa. 6, in a top view of the chip top surface 20, the third larger one of the second contact regions 42 is L-shaped, and the fourth smaller one of the second contact regions 42 is rectangular or square and is located within a cutout of the third one of the second contact regions 42. For example, the fourth one of the second contact regions 42 is located at a corner of the second electrical wiring layer 4.

[0073] For example, the top contact region 21 is shaped similarly to Figures 4 and 5. Thus, the fourth smaller second contact region of the second contact regions 42 may not have overlap with the assigned smaller top contact region of the top contact region 21. In addition to being shown in Figure 6, it is also possible for the smaller top contact region 21 to be partially or completely covered by the third second contact region of the second contact regions 42.

[0074] In other respects, the same applies to FIG. 6 as to FIG. 1-FIG. 5, and vice versa. According to Fig. 7, in a top view of the chip top surface 20, the fifth and sixth second contact regions 42 may be rectangular and extend parallel to each other. These second contact regions 42 may have different sizes. For example, the upper contact region 21 is shaped similarly to Figs. 4 to 6.

[0075] Thus, also seen in a top view of the chip top surface 20, the larger upper contact region 21 assigned to the fifth one of the second contact regions 42 may be └┘ or U-shaped and may be located adjacent to all four edges of the chip top surface 20, and the upper contact region 21 assigned to the sixth one of the second contact regions 42 is located outside the sixth one of the second contact regions 42. Thus, there is no overlap or only a small overlap between the sixth one of the second contact regions 42 and the assigned upper contact region 21.

[0076] As with all other embodiments, the overall size of all second contact regions 42 combined can be larger than the size of the chip top surface 20 .

[0077] In other respects, the same applies to FIG. 7 as to FIG. 1-FIG. 6, and vice versa. 8 shows that the central second second contact area of ​​the second contact area 42 is the largest second contact area of ​​the second contact area 42. The second second contact area of ​​the second contact area 42 is, for example, an emitter pad or a source pad, and correspondingly, the peripheral first second contact area of ​​the second contact area 42 has a smaller overall area content and may be a gate contact pad. For example, the track width of the outer first second contact area of ​​the second contact area 42 can correspond to at least 2% and / or at most 15% of the maximum edge length of the chip top surface 20. The edge length of the inner second second contact area of ​​the second contact area 42 is, for example, at least 60% and / or at most 95% of the maximum edge length of the chip top surface 20.

[0078] For example, the upper contact region 21 is shaped similarly to Figures 4 to 8. The second one of the second contact regions 42 may be square-shaped in top view.

[0079] In other respects, the same applies to FIG. 8 as to FIGS. 1-7, and vice versa. According to FIG. 9, the inner second contact area 42 of the second contact area is relatively small, for example, at most 10% or 5% of the overall size of the semiconductor device 1 in top view. Thus, the peripheral first second contact area 42 of the second contact area can cover almost the entire body top surface 66. For example, the inner second contact area 42 of the second contact area is a gate contact pad. In this coaxial design, by placing the gate contact pad in the center, the outer layer contact area 42, for example an emitter or source contact pad, can be maximized and the parasitic inductance can be lowered. The same can be applied for all intermediate wiring layers 3, 5.

[0080] It is possible that, in a top view, a second one of the second contact regions 42 does not overlap with the assigned upper contact region 21 .

[0081] Otherwise, the same as in FIG. 8 is applicable to FIG. 9 and vice versa. 10 shows that all first contact regions 31 of the first electrical wiring layer 3 lie in a common plane on the first insulating layer 61. Furthermore, optionally, a further insulating layer 65 is present around the first contact regions 31 in the lateral direction. The further insulating layer 65 is thus located between the first insulating layer 61 and the second insulating layer 62.

[0082] According to FIG. 10, the substrate 8 is not embedded in the insulator 6, but the insulator 6 may not be present on the sides of the substrate 8. The substrate 8 is connected to the semiconductor chip by a connection means 81, such as solder. The substrate 8 is, for example, a heat sink or a lead frame. Such an arrangement may also be present in all other embodiments. It should be noted that, for the sake of simplicity of the drawing, only one of the contact areas 31, 42 is explicitly shown in FIG. 10.

[0083] In contrast to what is shown in Fig. 10, according to Fig. 11 the first contact regions 31 assigned to the different upper contact regions 21 do not lie in one plane but are rather offset in a direction perpendicular to the chip top surface 20. Thus, there can be two further insulating layers 65, overlapping each assigned to one of the first contact regions 31. As an additional option, there can also be a further insulating layer 65 assigned to the connection means 81.

[0084] In other respects, the same content as in FIGS. 1 to 9 is also applicable to FIGS. 10 and 11, and vice versa.

[0085] 12 shows that the semiconductor device 1 comprises two or more intermediate layers, i.e., in addition to the first electrical wiring layer 3, there is at least one third electrical wiring layer 5 located between the first electrical wiring layer 3 and the second electrical wiring layer 4. In the example of FIG. 12, there are two third electrical wiring layers 5 overlapping each other, but it is also possible that there is only one third electrical wiring layer 3 or that there are at least three third electrical wiring layers 5.

[0086] In Fig. 12, the intermediate wiring layers 3, 4 are configured similarly to Fig. 10, so that all contact regions 31, 53 of a particular wiring layer 3, 4 lie in a common plane. However, the configuration according to Fig. 11 is also possible, so that the contact regions 31, 53 in one of the first and third wiring layers 3, 4 can be displaced in a direction perpendicular to the chip top surface 20.

[0087] Such at least one third electrical wiring layer 5 may also be present in all other embodiments.

[0088] Furthermore, as an option, the intermediate electrical wiring layers 3, 5 can have different patterns of contact regions 31, 53. Thus, starting from the top contact region 21, the respectively assigned contact region 31, 53 is shaped more similarly to the respectively assigned second contact region 42 the closer the respectively assigned contact region 31, 53 is to the associated second contact region 42.

[0089] It is possible for the metallization of the intermediate wiring layers 3, 5 to be thinner than the uppermost second electrical wiring layer 4. For example, the thickness of the first and / or third contact regions 31, 53 is between 30 μm and 70 μm, while the thickness of the second contact region 42 is between 80 μm and 200 μm. The same is possible for all other embodiments.

[0090] In other respects, the same applies to FIG. 12 as to FIGS. 1 to 11, and vice versa.

[0091] 13 to 16 show a cross-sectional view of another embodiment of the semiconductor device 1. In this case, the semiconductor device 1 comprises one third electrical wiring layer 5. As in the embodiment of FIG. 12, the intermediate layers 3, 5 have different shapes so that a more gradual change in the shape of the upper contact region 21 towards the shape of the second contact region 42 can be achieved.

[0092] Therefore, referring to Fig. 13, the upper contact region 21 can be shaped as shown in Fig. 5 to Fig. 7. Next, referring to Fig. 14, the smaller one of the first contact regions 31 of the first electrical wiring layer 3 extends toward the center of the semiconductor device 1, as compared to Fig. 13.

[0093] 15, the smaller of the third contact regions 53 has been shifted toward the center compared to FIG. 14, and the larger of the third contact regions 53 surrounds the smaller of the third contact regions 53. However, the smaller of the third contact regions 53 is still located off-center. Finally, referring to FIG. 16, the smaller of the third contact regions 53 is surrounded by the larger of the third contact regions 53 in a symmetrical manner.

[0094] Such a gradual change in the shape of the contact region towards the shape of the second contact region 42 may also be present in all other exemplary embodiments.

[0095] In other respects, the same content as in FIGS. 1 to 12 is also applicable to FIGS. 13 to 16, and vice versa.

[0096] A semiconductor module 10 is shown in Fig. 17. The semiconductor module 10 comprises one or more semiconductor devices 1, for example as shown in any one of Figs. 1 to 16. The semiconductor module 10 further comprises an electrical carrier 11, such as a circuit board. The electrical carrier 11 has a contact surface 12 to which the second contact region 42 is attached, for example by soldering or sintering.

[0097] The contact surface 12 and the assigned second contact region 42 may be the same size (see the central semiconductor device of the semiconductor device 1), or the contact surface 12 may be larger or smaller than the assigned second contact region 42 (see the left and right semiconductor devices of the semiconductor device 1, respectively).

[0098] As a further option, the semiconductor module 10 includes a cooler 13. The cooler 13 may be attached to the substrate 8 of the at least one semiconductor device 1. This allows for a heat sink to be provided on both major sides of the at least one semiconductor device 1, improving cooling and allowing it to handle higher currents.

[0099] Finally, with reference to FIG. 18, a method for manufacturing a semiconductor device is illustrated generally.

[0100] In a first method step S1, a semiconductor chip 1 is provided having an upper contact region 42. In this step, for example, an optional insulating fill 60 is already present.

[0101] Next, in method step S2, a first insulating layer 31 is provided and a first electrical through contact 71 is created.

[0102] In method step S3 a first electrical wiring layer 3 is formed, the first contact regions 31 of which may all be in the same plane (see FIG. 10) or the first contact regions 31 are formed one after the other by using a further insulating layer 65 (see FIG. 11). The thickness of the further insulating layer 65 corresponds for example to the thickness of the associated first contact region 31.

[0103] In method step S4, a second insulating layer 62 is provided and a second electrical through contact 72 is formed. If a further insulating layer 65 is present, the second electrical through contact 72 may extend through the further insulating layer 65 as well.

[0104] Next, in method step S5, the second contact regions 42 are formed, for example by plating.

[0105] Optionally, there may be method steps S6 and S7 carried out between method steps S3 and S4. In method step S6, a third insulating layer 63 is formed and a third electrical through contact 73 is provided. In method step S7, a third electrical wiring layer 5 is provided. Method steps S6 and S7 can be repeated a different number of times depending on the number of third electrical wiring layers 5.

[0106] Thus, the CSP semiconductor device 1 can be fabricated, for example, by the following sequence of steps: i) bonding the semiconductor chip onto a substrate 8, such as a copper lead frame, for example by sintering; ii) embedding the semiconductor chip 1 and optionally the substrate 8 by laminating copper foil and / or prepreg and cutting the prepreg or, alternatively, by epoxy compression molding; iii) forming electrical through contacts, for example by via drilling; iv) producing the respective electrical wiring layers by electroplating and structuring of copper; Manufactured by.

[0107] It is believed that the thickness of the prepreg foil defines the maximum voltage that the CSP can withstand. Standard materials are FR4 and epoxy, which have a breakdown field of about 2 kV per 100 μm. Including a safety margin, a proper embedding of a semiconductor device 1 at 1.2 kV typically requires a 100 μm thick insulating layer 61, 62, 63, 65 between the semiconductor chip 1 and the top layer of source or gate potential. However, technological limitations, i.e., stacking and drilling thick or multi-layer insulating layers, as well as conformal plating for such deep via structures, have prevented the deployment of CSPs to higher voltages, e.g., above 0.6 kV. With the multi-layer structure of the semiconductor device 1 presented herein, higher voltages can be achieved, e.g., by increasing the thickness of the insulating layers.

[0108] Components depicted in the figures preferably follow one above the other directly or indirectly in the order indicated, unless otherwise indicated. Layers that are not in contact in the figures are preferably spaced apart from one another. Where lines are drawn parallel to one another, corresponding surfaces are preferably oriented parallel to one another. Similarly, unless otherwise indicated, the positions of depicted components relative to one another are accurately reproduced in the figures.

[0109] The invention described herein is not limited by the description based on the embodiments, but rather the invention encompasses any novel feature and any combination of features, including in particular any combination of features in the claims, even if this feature or this combination itself is not explicitly set forth in the claims or in the exemplary embodiments.

[0110] This patent application claims priority to European Patent Application No. 2215 2939.9, the disclosure of which is incorporated herein by reference. [Explanation of symbols]

[0111] Reference sign 1. Semiconductor devices 2. Semiconductor chips 20 Chip top surface 21 Upper Contact Area 3 First electrical wiring layer 31 First Contact Area 4 Second electrical wiring layer 42 Second Contact Area 5 3rd electrical wiring layer 53 Third Contact Area 6. Insulation 60 Insulated buried part 61 First insulating layer 62 Second insulating layer 63 Third insulating layer 65 Extra Insulation 66 Main unit top surface 71 First Electrical Feedthrough Contact 72 Second Electrical Feedthrough Contact 73 3rd Electrical Feedthrough Contact 8 Substrate 81 Connection Method 9 Improved Semiconductor Devices 10 Semiconductor Module 11 Electrical Carrier 12 Contact surface 13 Cooler S. Method Steps

Claims

1. a semiconductor chip (2) configured for a voltage of at least 0.6 kV and comprising an upper contact area (21) on the upper surface (20) of the chip; a first electrical wiring layer (3) in electrical contact with the upper contact region (21), the first electrical wiring layer (3) having a first contact region (31) electrically assigned to the upper contact region (21); a second electrical wiring layer (4) located on the side of the first electrical wiring layer (3) remote from the upper contact region (21) and having a second contact region (42) electrically assigned to the upper contact region (31), the second contact region (42) being configured as an external contact region; at least one third electrical wiring layer (5) located between the first electrical wiring layer (3) and the second electrical wiring layer (4), electrically connected to the first electrical wiring layer (3) and the second electrical wiring layer (4), and having a third contact region (53); It is equipped with at least one of the second contact regions (42) is shaped differently from an assigned one of the upper contact regions (21) in a top view of the chip top surface (20); the semiconductor chip (2) is a power metal-insulator field-effect transistor (MISFET) or a power insulated-gate bipolar transistor (IGBT), said first, second and third wiring layers (3, 4, 5) are in each case separated from one another by insulating layers (61, 62, 63) made of a dielectric material; - A semiconductor device (1), wherein a first one of the second contact regions (42) extends completely around a second one of the second contact regions (42) when viewed in a top view of the chip top surface (20).

2. 10. The semiconductor device (1) according to claim 9, wherein at least one of the second contact regions (42) is located completely outside the assigned upper contact region (21) when viewed in a top view on the chip top surface (20).

3. 10. The semiconductor device (1) of claim 1, wherein the semiconductor device (1) is a chip size package such that, when viewed in a top view of the chip top surface (20), the overall size of the semiconductor device (1) is 130% or less of the size of the chip top surface (20) and the semiconductor device (1) comprises exactly one semiconductor chip (2).

4. At least two third electrical wiring layers (5) each located between the first electrical wiring layer (3) and the second electrical wiring layer (4) and electrically connected to the first electrical wiring layer (3) and the second electrical wiring layer (4); Equipped with 10. The semiconductor device (1) according to the preceding claim, wherein starting from the first contact region (31) towards the second contact region (42), a shape of each assigned third contact region (53) becomes more similar to the second contact region (42) from third electrical wiring layer (5) to third electrical wiring layer (5).

5. The thickness of the insulating layers (61, 62, 63) is 100 μm or less in each case, 10. The semiconductor device (1) of claim 1, wherein an electrical via contact (71, 72, 73) extends through each of the insulating layers (61, 62, 63), the via contact (71, 72, 73) electrically connecting adjacent ones of the electrical wiring layers (3, 4, 5).

6. 10. The semiconductor device (1) of claim 1, wherein, when viewed in a top view of the chip top surface (20), at least one of the second contact regions (42) overlaps any one of the upper contact regions (21) by up to 10% of the size of the respective second contact region (42).

7. 10. The semiconductor device (1) according to the preceding claim, wherein, as viewed in a top view of the chip top surface (20), the at least one of the second contact regions (42) is located completely outside the respective upper contact region (21).

8. 10. The semiconductor device (1) according to claim 1, wherein, in a top view of the chip top surface (20), the first one of the second contact regions (42) extends coaxially around the second one of the second contact regions (42), and the first upper contact region and the second upper contact region of the upper contact regions (41, 42) are point-symmetric in shape and have the same center of point symmetry.

9. 10. The semiconductor device (1) according to the preceding claim, wherein the upper contact area (21) assigned to the second one of the second contact areas (42) is located at the edge of the chip top surface (20).

10. When viewed in a top view of the chip top surface (20), a third one of the second contact regions (42) is L-shaped, and a fourth one of the second contact regions (42) is rectangular and is located within a cutout of the third one of the second contact regions (42) at a corner of the second electrical wiring layer (4); 10. The semiconductor device (1) according to claim 1, wherein the upper contact region (21) assigned to the fourth of the second contact regions (42) is located in a central portion of a longitudinal edge of the chip top surface (20).

11. When viewed in a top view of the chip top surface (20), a fifth second contact region and a sixth second contact region of the second contact regions (42) are rectangular and extend parallel to each other; 10. The semiconductor device (1) according to claim 1, wherein, also viewed in a top view of the chip top surface (20), the upper contact region (21) assigned to the fifth one of the second contact regions (42) is U-shaped and is located adjacent to all four edges of the chip top surface (20), and the upper contact region (21) assigned to the sixth one of the second contact regions (42) is located outside the sixth one of the second contact regions (42).

12. It comprises exactly one semiconductor chip (2), 10. The semiconductor device (1) according to any one of the preceding claims, wherein a total size of all the second contact areas (42) together is greater than a size of the chip top surface (20).

13. The thickness of each of the first, second and third electrical wiring layers (2, 3, 4) is 20 μm or more and 200 μm or less, the diameter of the electrical through contacts (71, 72, 73) is in each case greater than or equal to 20 μm and less than or equal to 200 μm; A semiconductor device (1) according to at least claim 5.

14. at least one semiconductor device (1) according to any one of the preceding claims, Electric carrier (11) and It is equipped with The second contact area (42) is connected to an electrical contact surface (12) of the electrical carrier (11).

15. A method for manufacturing a semiconductor device (1) according to any one of claims 1 to 13, comprising the steps of: Providing the semiconductor chip (2) configured for a voltage of at least 0.6 kV and comprising the upper contact area (21) on the chip top surface (20); - applying the dielectric material for a first one of the insulating layers (61) on the upper contact area (21); forming a first electrical via contact (71) through the first insulating layer (61) and forming the first electrical wiring layer (3) on the first insulating layer (61) with the first contact area (31) electrically assigned to the upper contact area (21); - applying the dielectric material for a second one of the insulating layers (62) onto the first electrical wiring layer (3); forming a second electrical through contact (72) through the second insulating layer (62) and forming on the second insulating layer (62) the second electrical wiring layer (4) having the second contact region (42) electrically assigned to the upper contact region (21) and configured as the external contact region of the semiconductor device (1); Including, At least one of the second contact regions (42) has a different shape than the assigned one of the upper contact regions (21) when viewed in a top view of the chip top surface (20).

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