Stacked FET SRAM Design

Abstract

A compact SRAM design with a stacked architecture is provided. In particular, a six-transistor SRAM bit cell is provided that includes a lower device level containing a lower field effect transistor and an upper device level stacked above the lower device level containing an upper field effect transistor of a different conductivity type than the lower field effect transistor.

Description

[Technical field]

[0001] This application relates to semiconductor technology and, more particularly, to semiconductor structures including stacked field effect transistors (FETs) having a static random access memory (SRAM) design. [Background technology]

[0002] Monolithic stacking of transistors is an attractive architecture for future scaling of complementary metal-oxide-semiconductor (CMOS) and possibly eventually scaled technologies. Significant area scaling can be achieved by stacking one type of FET (e.g., n-type FETs) directly on top of another type (e.g., p-type FETs).

[0003] SRAM is a type of random access memory (RAM) that uses latch circuits (flip-flops) to store each bit. A typical SRAM cell consists of six FETs. Each bit in a conventional SRAM is stored in four transistors that form two cross-coupled inverters. This storage cell has two stable states that are used to represent 0 and 1. Two additional access transistors are responsible for controlling access to the storage cell during read and write operations. In addition to such six-transistor (6T) SRAMs, other types of SRAM chips use four, eight, ten (4T, 8T, 10T SRAMs) or more transistors per bit. Providing an SRAM design with a stacked architecture is a challenge. Summary of the Invention

[0004] The present application provides a compact SRAM design with a stacked architecture. In particular, the present application provides a 6-transistor SRAM bit cell that includes a lower device level containing a lower field effect transistor and an upper device level stacked above the lower device level containing an upper field effect transistor of a different conductivity type than the lower field effect transistor.

[0005] In one aspect of the present application, a semiconductor structure having a compact SRAM design and stacked architecture is provided. In one embodiment, the semiconductor structure includes a lower device level including a first lower field effect transistor (FET) of a first conductivity type, a second lower FET of the first conductivity type, a third lower FET of the first conductivity type, and a fourth lower FET of the first conductivity type, the first lower FET being electrically connected to the second lower FET, the third lower FET being electrically connected to the fourth lower FET, the first lower FET being diagonally positioned relative to the fourth lower FET, the second lower FET being diagonally positioned relative to the third lower FET, and the first lower FET and the fourth lower FET are pass gates. The semiconductor structure further includes an upper device level stacked above the lower device level, the upper device level including a first upper FET of a second conductivity type different from the first conductivity type located directly above the first lower FET, a second upper FET of the second conductivity type located directly above the second lower FET, a third upper FET of the second conductivity type located directly above the third lower FET, and a fourth upper FET of the second conductivity type located directly above the fourth lower FET, the first upper FET being electrically connected to the second upper FET. the third top FET is electrically connected to the fourth top FET, the first top FET is a first dummy transistor wired to be cross-coupled with the third top FET, the fourth top FET is a second dummy transistor wired to be cross-coupled with the second top FET, the second bottom FET and the second top FET are wired to provide a first inverter, and the third bottom FET and the third top FET are wired to provide a second inverter. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a circuit diagram of a semiconductor structure according to an embodiment of the present application. [Figure 2A] FIG. 1 is a top view illustrating an upper device level design layout of a semiconductor structure according to an embodiment of the present application. [Figure 2B] 1B is a top view illustrating a design layout of a lower device level of a semiconductor structure according to one embodiment of the present application, located below the upper device level shown in FIG. 1A. [Figure 3A] FIG. 2B is a cross-sectional view taken through cut line AA shown in FIG. 2A according to one embodiment of the present application. [Figure 3B] FIG. 2B is a cross-sectional view taken through cut line BB shown in FIG. 2A according to an embodiment of the present application. [Figure 3C] FIG. 2B is a cross-sectional view taken through cut CC shown in FIG. 2A according to an embodiment of the present application. [Figure 3D] FIG. 2B is a cross-sectional view taken along cut line DD shown in FIG. 2A according to an embodiment of the present application. [Figure 4A] FIG. 2B is a cross-sectional view taken along the cut line AA shown in FIG. 2A according to another embodiment of the present application. [Figure 4B] FIG. 2B is a cross-sectional view taken through cut line BB shown in FIG. 2A according to another embodiment of the present application. [Figure 4C] FIG. 2B is a cross-sectional view taken through cut line CC shown in FIG. 2A according to another embodiment of the present application. [Figure 4D] FIG. 2B is a cross-sectional view taken along cut line DD shown in FIG. 2A according to another embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] The present application will now be described in more detail with reference to the following description and the drawings accompanying this application, in which it is noted that the drawings are provided for illustrative purposes only and, therefore, are not drawn to scale, and like and corresponding elements are referred to by like reference numerals.

[0008] In the following description, numerous specific details are set forth, such as specific structures, components, materials, dimensions, processing steps and techniques, to provide an understanding of various embodiments of the present application. However, it will be understood that those skilled in the art may practice various embodiments of the present application without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring the present application.

[0009] When an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it is understood that it may be directly on the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. When an element is referred to as being "beneath" or "under" another element, it is understood that it may be directly under the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly beneath" or "directly under" another element, there are no intervening elements present.

[0010] Stacked FETs are considered a device platform for logic CMOS beyond the 2 nm node. The present application provides a compact SRAM design for use with stacked FET technology. In particular, the present application provides a 6-transistor SRAM bit cell that includes a lower device level containing a lower field effect transistor and an upper device level stacked above the lower device level containing an upper field effect transistor of a different conductivity type than the lower field effect transistor. The semiconductor structure of the present application includes two CMOS inverters, with the output potential of each inverter being provided as an input to the other CMOS inverter. Pass gates (or access transistors), word lines (WL), and bit lines (BL) are used to read and write to the cell. These and other aspects of the invention are described in more detail below.

[0011] Reference is first made to FIG. 1, which is a circuit diagram of a semiconductor structure according to one embodiment of the present application. A semiconductor structure having such a circuit diagram is shown in the remaining drawings of the present application. In particular, as illustrated by the circuit diagram shown in FIG. 1, the semiconductor structure of the present application includes a lower device level including a first lower field effect transistor (FET) of a first conductivity type (hereinafter, "FET_1B"), a second lower FET of a first conductivity type (hereinafter, "FET_2B"), a third lower FET of a first conductivity type (hereinafter, "FET_3B"), and a fourth lower FET of a first conductivity type (hereinafter, "FET_4B"). The term "FET" refers to a type of transistor that uses an electric field to control the flow of current in a semiconductor material. A FET is a device that has three terminals: a source region, a gate, and a drain region. A FET controls the flow of current by applying a voltage to the gate, thereby changing the conductivity between the source and drain regions.

[0012] In the semiconductor structure of the present application, and as shown in Figure 1, FET_1B is electrically connected to FET_2B at node A, which represents the shared source / drain region between FET_1B and FET_2B. In the semiconductor structure of the present application, and as shown in Figure 1, FET_3B is electrically connected to FET_4B at node B, which represents the shared source / drain region between FET_3B and FET_4B. In the semiconductor structure of the present application, FET_1B is diagonally opposite FET_3B from FET_4B, and FET_2B is diagonally opposite FET_4B from FET_3B.

[0013] According to an embodiment of the present application, FET_1B and FET_4B act as pass gates (i.e., access transistors). As shown in FIG. 1, each of FET_1B and FET_4B is configured or wired to be connected to a bit line (BL), with one BL connection located on the opposite side of FET_1B from the shared source / drain region (i.e., node A) while the other BL connection is located on the opposite side of FET_4B from the shared source / drain region (i.e., node B). Also as shown in FIG. 1, each of FET_2B and FET_3B is configured or wired to be connected to ground (GND), with one GND connection located on the opposite side of FET_2B from the shared source / drain region (i.e., node A) while the other GND connection is located on the opposite side of FET_3B from the shared source / drain region (i.e., node B). FIG. 1 also shows that FET_1B and FET_4B are each configured, i.e., wired, to be connected to a word line (WL), and in particular, one WL connection contacts the gate of FET_1B, while the other WL connection contacts the gate of FET_4B.

[0014] The semiconductor structure as illustrated in FIG. 1 further includes an upper device level stacked above the lower device level. The upper device level includes a first upper FET of a second conductivity type (hereinafter, "FET_1T") located directly above FET_1B, a second upper FET of a second conductivity type (hereinafter, "FET_2T") located directly above FET_2B, a third upper FET of a second conductivity type (hereinafter, "FET_3T") located directly above FET_3B, and a fourth upper FET of a second conductivity type (hereinafter, "FET_4T") located directly above FET_4B. In particular, the various FETs of the upper device level are stacked above the various FETs of the lower device level. As used herein, the second conductivity type is different from the first conductivity type, i.e., opposite in conductivity. In some embodiments, the first conductivity type can be n-type, while the second conductivity type can be p-type. In other embodiments, the first conductivity type may be p-type and the second conductivity type may be n-type, in which case the locations of VDD and GND would be swapped.

[0015] According to the present application, FET_1T is electrically connected to FET_2T at node C, which represents a shared source / drain region between FET_1T and FET_2T. In the present application's semiconductor structure and as shown in FIG. 1, FET_3T is electrically connected to FET_4T at node D, which represents a shared source / drain region between FET_3T and FET_4T. In the present application's semiconductor structure, FET_1T is diagonally located across from FET_3T and FET_4T, and FET_2T is diagonally located across from FET_4T and FET_3T. As shown in FIG. 1, node A is wired to be connected to node C, and node B is wired to be connected to node D.

[0016] In an embodiment of the present application, each of FET_2T and FET_3T is configured, i.e., wired, to be connected to a power supply (VDD), and in particular, one VDD connection is located on the opposite side of FET_2T from the shared source / drain region (i.e., node C), while the other VDD connection is located on the opposite side of FET_3T from the shared source / drain region (i.e., node D).

[0017] According to the present application, FET_2B and FET_2T are wired to provide a first inverter, and FET_3B and FET_3T are wired to provide a second inverter. As known in SRAM construction, the two inverters are cross-coupled in the sense that the output node of one inverter is connected to the input of the second inverter and vice versa. As shown in FIG. 1, the input of the first inverter is connected to the gate of FET_4T, which serves as one dummy transistor. On the wafer, this is achieved by a shared gate line. The output of the second inverter (node ​​D) is the source / drain region of the dummy transistor FET_4T. The first of the cross-coupled connections is formed by connecting the gate of FET_4T to node D. The input of the second inverter is connected to the gate of FET_1T, which serves as another dummy transistor FET_1. On the wafer, this is achieved by a shared gate line. The output of the first inverter (node ​​C) is the source / drain region of the dummy transistor FET_1T. A second one of the cross-couplings is formed to complete the cross-coupling by connecting the gate of FET_1T to node C. In particular, the cross-coupling of the first dummy transistor (i.e., FET_1T) with FET_3T includes a first contact metal in contact with both the gate electrode and the source / drain region of the first dummy gate region, and the cross-coupling of the second dummy transistor (i.e., FET_4T) with FET_2T includes a second contact metal in contact with both the gate electrode and the source / drain region of the second dummy gate region.

[0018] In an embodiment, the first top FET, the third top FET and the third bottom FET electrically share a common gate electrode, and the fourth top FET, the second top FET and the second bottom FET electrically share a common gate electrode.

[0019] In addition to the cross-coupled inverter pair, the 6T SRAM requires two pass-gate transistors for read and write functions. The gate of each pass-gate transistor is called the word line (WL). FET_1B, with one of its source / drain regions connected to the first inverter output (node ​​A), serves as one of the pass-gate transistors. The other source / drain region serves as the bit line (BL). FET_4B, with one of its source / drain regions connected to the second inverter output (node ​​B), serves as the other pass-gate transistor. The other source / drain region serves as the bit line (BL).

[0020] Reference is now made to Figures 2A and 2B, which are top view diagrams illustrating the design layout of each of the various device levels of a semiconductor structure of the present application. In particular, Figure 2A is a top view diagram illustrating the design layout of an upper device level, while Figure 2B is a top view diagram illustrating the design layout of a lower device level. In accordance with the present application, the top view diagram illustrated in Figure 2A is stacked above the lower device level illustrated in Figure 2B.

[0021] Referring first to the lower device level shown in FIG. 2B, two lower semiconductor channel material structures 10L and 10R are shown spaced apart from each other and oriented parallel to each other. In an embodiment, the lower semiconductor channel material structures 10L and 10R can be semiconductor fins as shown in FIG. 2B. Other types of lower semiconductor channel material structures 10L and 10R can be used instead of the semiconductor fins shown in FIG. 2B, including, for example, semiconductor nanosheets or semiconductor nanowires. The lower semiconductor channel material structures 10L and 10R are composed of a semiconductor material having semiconductor properties. Examples of semiconductor materials that can be used in the present application include silicon (Si), silicon-germanium (SiGe) alloy, silicon-germanium carbide (SiGeC) alloy, germanium (Ge), III / V compound semiconductors, II / VI compound semiconductors, or a multilayer stack including at least two semiconductor materials (e.g., a multilayer stack of Si and SiGe).

[0022] FIG. 2B also shows the presence of two lower gate structures 12A and 12B that are spaced apart from each other and oriented parallel to each other. The two lower gate structures 12A and 12B are oriented perpendicular to the two lower semiconductor channel material structures 10L and 10R. Each lower gate structure straddles a portion of the two lower semiconductor channel material structures 10L and 10R as shown in FIG. 2B. Each lower gate structure 12A and 12B includes a gate dielectric material and a gate electrode, which are described in more detail herein below. In FIG. 2B, two pass gate regions are shown. One of the pass gate regions includes FET_1B shown in FIG. 1, and the other pass gate region includes FET_4B shown in FIG. 1. Other regions of the design layout shown in FIG. 2B include a region that includes a lower portion of a first inverter, i.e., inverter 1, and another region that includes a lower portion of a second inverter, i.e., inverter 2.

[0023] Also shown in FIG. 2B are shared source / drain regions 14L and 14R. Shared source / drain region 14L is equivalent to node A shown in FIG. 1, while shared source / drain region 14R is equivalent to node B shown in FIG. 1. Also shown in FIG. 2B are WL, BL, and GND contacts configured as described above with respect to FIG. 1. The lower device level also includes gate cut CT regions and a lower buried power line BR1. Each gate cut region indicates an area where the gate structure is cut, and the buried power line BR1 is connected to the GND contact. The buried power lines are below the stack and are optional.

[0024] Reference is now made to Figure 2A, which illustrates a top view of the design layout of the present application, which sits on top of the top view illustrated in Figure 2B, such that FET_1T is stacked directly above FET_1B, FET_4T is stacked directly above FET_4B, the inverter 1 region shown on the upper device level is stacked directly above the inverter 1 region shown on the lower device level, and the inverter 2 region shown on the upper device level is stacked directly above the inverter 2 region shown on the lower device level.

[0025] The upper device level includes two upper semiconductor channel material structures 11L and 11R that are spaced apart from each other and oriented parallel to each other. In an embodiment, the upper semiconductor channel material structures 11L and 11R can be semiconductor fins as shown in FIG. 2A, and typically, but not necessarily always, the upper semiconductor channel material structures match the lower semiconductor channel material structures, i.e., their geometric shapes are the same. Instead of the semiconductor fins shown in FIG. 2A, other types of upper semiconductor channel material structures 11L and 11R can also be used, including, for example, semiconductor nanosheets or semiconductor nanowires. The upper semiconductor channel material structures 11L and 11R are composed of one of the semiconductor materials mentioned above. The semiconductor material providing the upper semiconductor channel material structures 11L and 11R can be compositionally the same as the semiconductor material providing the lower semiconductor channel material structures 10L and 10R, or can be compositionally different.

[0026] FIG. 2A also shows the presence of two upper gate structures 13A and 13B that are spaced apart from each other and oriented parallel to each other. The two upper gate structures 13A and 13B are oriented perpendicular to the two upper semiconductor channel material structures 11L and 11R. Each upper gate structure straddles a portion of the two upper semiconductor channel material structures 11L and 11R as shown in FIG. 2A. Each upper gate structure 13A and 13B includes a gate dielectric material and a gate electrode, which are described in more detail herein below. In FIG. 2A, FET_1T and FET_4T are dummy transistors that are wired as described in FIG. 1 to provide cross-coupling with FET_3T and FET_2T, respectively. The design layout shown in FIG. 2A includes a region that includes an upper portion of a first inverter, i.e., inverter 1, and another region that includes an upper portion of a second inverter, i.e., inverter 2.

[0027] Also shown in FIG. 2A are shared source / drain regions 15L and 15R. Shared source / drain region (shared between top and bottom FETs) 15L is equivalent to node C shown in FIG. 1, while shared source / drain region 15R is equivalent to node D shown in FIG. 1. On the wafer, the shared top-bottom source / drain region can be realized by forming contacts that connect to both the top source / drain region and the lower source / drain region directly below it. Also shown in FIG. 2A are cross-coupled contacts 18, WL contacts, BL contacts, and VDD contacts, which are configured as described above with respect to FIG. 1. The top device level also includes a gate cut CT region, as well as a first buried power wiring BR2 and a second buried power wiring BR3. Each gate cut region indicates an area where the gate structure is cut, and the buried power wirings BR2 and BR3 are connected to VDD. The buried power wirings are below the stacked structure and are optional.

[0028] In accordance with the present application, the output of the top portion of inverter 1 (i.e., shared source / drain region 15L) is connected to the input of the top portion of inverter 2 (i.e., gate electrode 13A). In accordance with the present application, the output of the top portion of inverter 2 (i.e., shared source / drain region 15R) is also connected to the input of the top portion of inverter 1 (i.e., gate electrode 13B). The structure labeled 18 in FIG. 2A provides such a connection.

[0029] It should be noted that the top view of the upper device level includes cuts AA, BB, CC, and DD. Cut AA is through the upper semiconductor channel material structure 11L and the lower semiconductor channel material structure 10L, cut BB is through the upper gate structure 13B and the lower gate structure 12B, cut CC is through the side of the upper gate structure 13B and the lower gate structure 12B that does not include the shared source / drain regions, and cut DD is through the other side of the upper gate structure 13B and the lower gate structure 12B that includes the shared source / drain regions 15L, 15R and 14L, 14R. These various cuts are used to further illustrate certain aspects of the semiconductor structures of the present application.

[0030] Reference is now made to Figures 3A, 3B, 3C and 3D, which illustrate the semiconductor structure of the present application through various cross-sectional views. In particular, Figure 3A is a cross-sectional view of the semiconductor structure through cut AA shown in Figure 2A, Figure 3B is a cross-sectional view of the semiconductor structure through cut BB shown in Figure 2A, Figure 3C is a cross-sectional view of the semiconductor structure through cut CC shown in Figure 2A, and Figure 3D is a cross-sectional view of the semiconductor structure through cut DD shown in Figure 2A, according to one embodiment of the present application. In this embodiment, the semiconductor channel material structures in the upper and lower device levels are semiconductor fins.

[0031] In particular, referring initially to FIG. 3A, a pair of lower semiconductor fins 102F are shown extending upward from a surface of a semiconductor substrate 100. The lower semiconductor fins 102F and the semiconductor substrate 100 are comprised of one of the semiconductor materials mentioned above for the lower semiconductor channel material structure. In some embodiments, the semiconductor material providing the lower semiconductor fins 102F is compositionally the same as the semiconductor material providing the semiconductor substrate 100. In such embodiments, and as shown in FIG. 3A, there is no material interface between the semiconductor substrate 100 and the lower semiconductor fins 102F. In other embodiments, the semiconductor material providing the lower semiconductor fins 102F is compositionally different from the semiconductor material providing the semiconductor substrate 100. In such embodiments (not shown), there will be a material interface between the semiconductor substrate 100 and the lower semiconductor fins 102F.

[0032] 3A also includes a pair of upper semiconductor fins 106F stacked above but spaced apart from the lower semiconductor fin 102F. The upper semiconductor fin 106F includes one of the semiconductor materials mentioned above for the lower semiconductor channel material structure. The semiconductor material providing the upper semiconductor fin 106F can be of the same composition as the semiconductor material providing the lower semiconductor fin 102F, or it can be of a different composition. In an embodiment, the semiconductor material providing each lower semiconductor fin 102F is a semiconductor material capable of providing high channel mobility for nFET devices, and the semiconductor material providing each upper semiconductor fin 106F is a semiconductor material capable of providing high channel mobility for pFET devices. In other embodiments, the opposite compositional configuration can be used.

[0033] In the present application and as shown in FIG. 3A, the upper semiconductor fin 106F is separated from the lower semiconductor fin 102F by a stacked device channel isolation structure 104. The stacked device channel isolation structure 104 may comprise, for example, silicon dioxide, silicon nitride, silicon oxynitride, or any combination thereof. In the present application, the stacked channel device isolation structure separates FET_1B from FET_1T, separates FET_2B from FET_2T, separates FET_3B from FET_3T, and separates FET_4B from FET_4T.

[0034] According to the present invention, the lower source / drain regions 108, 108A are laterally adjacent to the lower semiconductor fin 102F. The lower source / drain regions 108 are non-shared source / drain regions, while the lower source / drain regions 108A are shared source / drain regions. The lower source / drain regions 108, 108A have an epitaxial relationship (same crystal orientation as) with the sidewalls of the lower semiconductor fin 102F. As used herein, a "source / drain" region can be a source region or a drain region depending on the application of voltages during subsequent wiring and operation of the FET. The lower source / drain regions 108, 108A include a semiconductor material and a dopant. The semiconductor material providing each lower source / drain region 108, 108A can include one of the semiconductor materials mentioned above. The semiconductor material providing the lower source / drain regions 108, 108A can be compositionally the same as each lower semiconductor fin 102F, or can be compositionally different. The dopants present in each lower source / drain region 108, 108A can be either p-type or n-type dopants. The term "p-type" refers to the addition of an impurity to an intrinsic semiconductor that results in a deficiency of valence electrons. In silicon-containing semiconductor materials, examples of p-type dopants, or impurities, include, but are not limited to, boron, aluminum, gallium, and indium. "N-type" refers to the addition of an impurity that provides free electrons to the intrinsic semiconductor. In silicon-containing semiconductor materials, examples of n-type dopants, or impurities, include, but are not limited to, antimony, arsenic, and phosphorus. In one example, each source / drain region 30 is doped with 4x10 20 atoms / cm 3 ~3x10 21 atoms / cm 3 In one example, each lower source / drain region 46 is comprised of silicon doped with phosphorous.

[0035] According to the present invention, the upper source / drain region 114, 114A is located laterally adjacent to the upper semiconductor fin 106F. The upper source / drain region 114 is a non-shared source / drain region, while the upper source / drain region 114A is a shared source / drain region. The upper source / drain region 114, 114A has an epitaxial relationship with (the same crystal orientation as) the sidewall of the upper semiconductor fin 106F. The semiconductor material providing each upper source / drain region 114, 114A can include one of the semiconductor materials mentioned above. The semiconductor material providing the upper source / drain region 114, 114A can be compositionally the same as or compositionally different from each upper semiconductor fin 106F or the lower source / drain region 108, 108A or both. The dopant present in each upper source / drain region 114, 114A can be either a p-type dopant or an n-type dopant. The upper source / drain regions 114, 114A are of a different conductivity type than the lower source / drain regions 108, 108A. Note that the upper source / drain region 114 does not have a sidewall of the upper semiconductor fin 106F in the area labeled dummy transistor, and thus the dummy transistor is a non-functional device. In an embodiment (not shown), the upper source / drain region may be partially removed from the sidewall of the upper semiconductor fin 106F in the area labeled dummy transistor.

[0036] The upper source / drain regions 114 are spaced apart from one another by source / drain isolation structures 110. The source / drain isolation structures 110 are comprised of one of the dielectric materials mentioned above for the stacked device channel isolation structure 104. The dielectric material providing the source / drain isolation structures 110 is typically compositionally different from the stacked device channel isolation structure 104.

[0037] The upper source / drain region 114A and the lower source / drain region 108A are connected together by an S / D connector 112. The S / D connector 112 is a metal contact that contacts both the upper source / drain region 114A and the lower source / drain region 108A. In this embodiment, the upper source / drain region 114A and the lower source / drain region 108A are connected together as the output of inverter 1.

[0038] The exemplary configuration shown in Figure 3A also includes an upper gate structure including a gate dielectric material 116, an upper gate electrode 118, and an optional upper gate cap 120 located on the top surface of the upper semiconductor fin 106F. The upper gate structure also resides along the sidewalls of the upper semiconductor fin 106F. Although not shown in this cross-sectional view, a lower gate structure, shown in Figure 3B, resides along the sidewalls of the lower semiconductor fin 102F. The lower gate structure includes a gate dielectric material 116 and a lower gate electrode 117. Dielectric spacers 122 reside along the sidewalls of the upper gate structure shown in Figure 3A.

[0039] In an embodiment, the gate dielectric material 116 may include silicon dioxide or a dielectric material having a higher dielectric constant than silicon dioxide (such a dielectric material may be referred to as a high-k gate dielectric material). Examples of high-k gate dielectric materials include, for example, hafnium dioxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO4), zirconium silicon oxynitride (ZrSiO x N y ), tantalum oxide (TaO x), titanium oxide (TiO), barium strontium titanium oxide (BaO6SrTi2), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), yttrium oxide (Yb2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide (Pb(Sc,Ta)O3), or lead zinc niobate (Pb(Zn,Nb)O), or combinations thereof. The high-k gate dielectric material may further include dopants such as lanthanum (La), aluminum (Al), or magnesium (Mg), or combinations thereof.

[0040] In some embodiments, each of the top gate electrode 118 and the bottom gate electrode 117 is composed of a conductive metal-containing material, including, but not limited to, tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), zirconium (Zr), cobalt (Co), copper (Cu), aluminum (Al), lead (Pb), platinum (Pt), tin (Sn), silver (Ag), or gold (Au), tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaCX), titanium carbide (TiC), aluminum titanium carbide, tungsten silicide (WSi2), tungsten nitride (WN), ruthenium oxide (RuO2), cobalt silicide, or nickel silicide. The conductive metal-containing material that provides the top gate electrode 118 is typically compositionally different from the conductive metal-containing material that provides the bottom gate electrode 117.

[0041] In some embodiments, a layer of work function metal (WFM) can be used alone as one of the conductive metal-containing materials mentioned above or in combination with one of the conductive metal-containing materials mentioned above to provide the top gate electrode 118 and the bottom gate electrode 117. The layer of WFM can be used to set the threshold voltage of the FET to a desired value. In some embodiments, the layer of WFM can be selected to generate an n-type threshold voltage shift. As used herein, "n-type threshold voltage shift" refers to a shift in the effective work function of the work function metal-containing material toward the conduction band of silicon in the silicon-containing material. In one embodiment, the work function of the n-type work function metal ranges from 4.1 eV to 4.3 eV. Examples of such materials that may generate an n-type threshold voltage shift include, but are not limited to, titanium aluminum, titanium aluminum carbide, tantalum nitride, titanium nitride, hafnium nitride, hafnium silicon, or combinations thereof. In other embodiments, the layer of WFM can be selected to generate an n-type threshold voltage shift. In one embodiment, the work function of the p-type work function metal ranges from 4.9 eV to 5.2 eV. As used herein, "threshold voltage" refers to the lowest achievable gate voltage that turns on a semiconductor device, such as a transistor, by creating a channel for device conduction. As used herein, "p-type threshold voltage shift" refers to a shift in the effective work function of a work function metal-containing material toward the conduction band of silicon in a silicon-containing material. Examples of such materials that can cause a p-type threshold voltage shift include, but are not limited to, titanium nitride, tantalum carbide, hafnium carbide, and combinations thereof.

[0042] The optional upper gate cap 120 may be comprised of any dielectric material, such as, for example, silicon dioxide, silicon nitride, or a combination thereof. The dielectric spacer 122 may be comprised of a spacer dielectric material, such as, for example, silicon dioxide, silicon nitride, or a combination thereof. The spacer dielectric material is typically compositionally different from the dielectric material that provides the upper gate cap 120.

[0043] The exemplary structure shown in FIG. 3A also includes an upper interlayer dielectric (ILD) material layer 124 laterally adjacent to the upper gate structure, and as shown in FIGS. 3C and 3D of the present application, a lower ILD material layer 123 may also be present. The lower ILD material layer 123 and the upper ILD material layer 124 may be composed of compositionally the same ILD material, or may be composed of compositionally different ILD materials. Exemplary ILD materials that may be utilized include, for example, silicon oxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), spin-on low-k dielectric layers, chemical vapor deposition (CVD) low-k dielectric layers, or any combination thereof. The term "low-k" as used throughout this specification refers to a dielectric material having a dielectric constant lower than silicon dioxide.

[0044] Also shown in FIG. 3A are VDD contacts 126, BL contacts 128, and cross-coupled contacts 130. VDD contacts 126, BL contacts 128, and cross-coupled contacts 130 can be composed of the same but different conductive contact materials. In some embodiments, a contact liner (not shown) can be present around VDD contacts 126, BL contacts 128, or cross-coupled contacts 130, or combinations thereof. The contact liner (not shown) can include a silicide liner, such as Ti, Ni, NiPt, or the like, and a diffusion barrier material. Exemplary diffusion barrier materials include, but are not limited to, Ru, TiN, TaN, WN, WC, alloys thereof, or stacks thereof, such as Ti / TiN and Ti / WC. Examples of conductive contact materials that can be used in the present application include, for example, W, Cu, Al, Co, Ru, Mo, Os, Ir, Rh, or alloys thereof.

[0045] 3A, the VDD contact 126 is designed to contact one non-shared upper source / drain region 114, the BL contact 128 is designed to contact the lower source / drain region 108 in the area where the dummy transistor will be formed, and the cross-coupled contact 130 contacts the S / D connector 112 located above the upper source / drain region 114A. The cross-coupled contact 130 also contacts the upper gate of the dummy transistor as shown in FIG. 3A.

[0046] Reference is now made to FIG. 3B, which is a cross-sectional view of the exemplary structure along the cut line BB mentioned above. In addition to including the elements / components mentioned above, the exemplary structure shown in FIG. 3B includes a shallow trench isolation region 140, a dielectric structure 142 present in the gate cut region, and a dielectric cap 144. The shallow trench isolation region 140, the dielectric structure 142, and the dielectric cap 144 are composed of compositionally distinct dielectric materials including one of silicon dioxide, silicon nitride, and silicon oxynitride. FIG. 3B also illustrates the presence of a WL contact 146 contacting the surface of the bottom gate electrode 117. The WL contact 146 includes an optional contact liner as described above and one of the conductive contact materials described above. Also illustrated in FIG. 3B is that the top gate electrode 118 forms an extension of one inverter input from where the inverter is to the location of the dummy transistor. This facilitates the formation of a mutual coupling since at this point a simple contact connects the input of one inverter to the output of the other inverter. Although not shown, the top gate electrode of FET_4T forms an extension of the input of the second inverter.

[0047] Reference is now made to Figure 3C, which is a cross-sectional view of the exemplary structure along the above-mentioned section CC, showing the VDD contact 126 and the BL contact 128 already mentioned above.

[0048] Reference is now made to Figure 3D, a cross-sectional view of the exemplary structure along the above-mentioned cut DD. This drawing shows cross-coupled contacts 130 connected to the upper and lower shared source / drain regions 114A, 108A by S / D connectors 112, as mentioned above. The S / D connectors 112 include an optional contact liner as mentioned above and one of the conductive contact materials described above.

[0049] The semiconductor structures shown in Figures 3A-3D can be fabricated utilizing any stacked FET process flow in which semiconductor fins are used at both device levels. Such stacked FET processes include various deposition steps, various patterning steps, various material removal steps, and various planarization steps. These various processing steps will not be described further herein so as not to obscure the semiconductor structures of the present application.

[0050] Reference is now made to Figures 4A, 4B, 4C and 4D, which illustrate another semiconductor structure of the present application through various cross-sectional views. In particular, Figure 4A is a cross-sectional view of a semiconductor structure taken along cut AA shown in Figure 2A, Figure 4B is a cross-sectional view of the semiconductor structure taken along cut BB shown in Figure 2A, Figure 4C is a cross-sectional view of the semiconductor structure taken along cut CC shown in Figure 2A and Figure 4D is a cross-sectional view of the semiconductor structure taken along cut DD shown in Figure 2A, according to one embodiment of the present application. The semiconductor structure illustrated in Figures 4A-4D is similar to that illustrated in Figures 3A-3D, except that the lower semiconductor fin 102F and the upper semiconductor fin 106F are replaced by at least one lower semiconductor nanosheet 102NS and at least one upper semiconductor nanosheet 106NS, respectively. In Figures 4A-4D, a plurality of vertically stacked lower semiconductor nanosheets 102NS and a plurality of vertically stacked upper semiconductor nanosheets 106NS are illustrated. Other differences in the semiconductor structure shown in Figures 4A-4D are the inclusion of a lower dielectric isolation layer 150 located below the plurality of vertically stacked lower semiconductor nanosheets 102NS and the presence of inner spacers 151 between the various nanosheets in both the plurality of vertically stacked lower semiconductor nanosheets 102NS and the plurality of vertically stacked upper semiconductor nanosheets 106NS. The semiconductor structure shown in Figures 4A-4D also includes similar elements to those shown in Figures 3A-3D, which are labeled with the same reference numerals. In the embodiment shown in Figures 4A-4D, a lower gate configuration (116 / 117) surrounds the plurality of lower semiconductor nanosheets 102NS and an upper gate configuration (116 / 118) surrounds the plurality of upper semiconductor nanosheets 106NS. It should be noted that the nanosheet embodiment shown in Figures 4A-4D is the same as the fin embodiment shown in Figures 3A-3D, except for the change in geometry.

[0051] The lower semiconductor nanosheet 102NS and the upper semiconductor nanosheet 106NS comprise one of the semiconductor materials mentioned above in describing the semiconductor channel material structure. The semiconductor material providing the lower semiconductor nanosheet 102NS can be compositionally the same as or compositionally different from the semiconductor material providing the upper semiconductor nanosheet 106NS. The lower dielectric isolation layer 150 and the inner spacer 151 are composed of well-known dielectric materials.

[0052] The semiconductor structures shown in Figures 4A-4D can be fabricated utilizing any stacked FET process flow in which semiconductor nanosheets are used at both device levels. Such stacked FET processes include various deposition steps, various patterning steps, various material removal steps, and various planarization steps. These various processing steps will not be described further herein so as not to obscure the semiconductor structures of the present application.

[0053] While the present application has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and detail may be made without departing from the scope of the present application. It is therefore intended that the present application not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.

Claims

1. 1. A semiconductor structure comprising: a lower device level including a first lower field effect transistor (FET) of a first conductivity type, a second lower FET of the first conductivity type, a third lower FET of the first conductivity type, and a fourth lower FET of the first conductivity type, the first lower FET being electrically connected to the second lower FET, the third lower FET being electrically connected to the fourth lower FET, the first lower FET being diagonally positioned with respect to the fourth lower FET, the second lower FET being diagonally positioned with respect to the third lower FET, and the first lower FET and the fourth lower FET being pass gates; an upper device level stacked above the lower device level, the upper device level including a first upper FET of a second conductivity type different from the first conductivity type located directly above the first lower FET, a second upper FET of the second conductivity type located directly above the second lower FET, a third upper FET of the second conductivity type located directly above the third lower FET, and a fourth upper FET of the second conductivity type located directly above the fourth lower FET, the first upper FET being electrically connected to the second upper FET, an upper device level, wherein T is electrically connected to the fourth upper FET, the first upper FET is a first dummy transistor wired to cross-couple with the third upper FET, the fourth upper FET is a second dummy transistor wired to cross-couple with the second upper FET, the second lower FET and the second upper FET are wired to provide a first inverter, and the third lower FET and the third upper FET are wired to provide a second inverter.

2. 2. The semiconductor structure of claim 1 , wherein the first upper FET comprises a gate electrode that forms an extension of an input of the first inverter, and the fourth upper FET comprises another gate electrode that forms an extension of an input of the second inverter.

3. 2. The semiconductor structure of claim 1 , wherein the first lower FET comprises a gate electrode that is separated from a gate electrode of the first upper FET, and the fourth lower FET comprises a gate electrode that is separated from a gate electrode of the fourth upper FET.

4. 2. The semiconductor structure of claim 1, wherein said first conductivity type is n-type and said second conductivity type is p-type.

5. 2. The semiconductor structure of claim 1, wherein said first conductivity type is p-type and said second conductivity type is n-type.

6. 2. The semiconductor structure of claim 1 , wherein the first upper FET has a source / drain region located on one side and shared with the second upper FET, the third upper FET has a source / drain region located on one side and shared with the fourth upper FET, the first lower FET has a source / drain region located on one side and shared with the second lower FET, and the third lower FET has a source / drain region located on one side and shared with the fourth lower FET.

7. 7. The semiconductor structure of claim 6, wherein the shared source / drain region of the first and second upper FETs is electrically connected to the shared source / drain region of the first and second lower FETs, and the shared source / drain region of the third and fourth upper FETs is electrically connected to the shared source / drain region of the third and fourth lower FETs.

8. 2. The semiconductor structure of claim 1 further comprising a word line electrically connected to a gate electrode of both said first lower FET and said fourth lower FET.

9. 9. The semiconductor structure of claim 8 further comprising a bit line electrically connected to source / drain regions of both said first lower FET and said fourth lower FET.

10. 2. The semiconductor structure of claim 1 , wherein the first lower FET includes a gate electrode separated from a gate electrode of the second lower FET by a dielectric structure, and the third lower FET includes a gate electrode separated from a gate electrode of the fourth lower FET by another dielectric structure.

11. 2. The semiconductor structure of claim 1, wherein the first and second upper FETs comprise a shared gate electrode, and the third and fourth upper FETs comprise another shared gate electrode.

12. 2. The semiconductor structure of claim 1, wherein the second upper FET and the third upper FET are both hardwired to a power supply, and the second lower FET and the third lower FET are both hardwired to ground.

13. 2. The semiconductor structure of claim 1 , wherein each of the first lower FET, the second lower FET, the third lower FET, the fourth lower FET, the first upper FET, the second upper FET, the third upper FET, and the fourth upper FET are located on a semiconductor channel material structure.

14. 14. The semiconductor structure of claim 13, wherein the semiconducting channel material structure is a semiconducting fin.

15. The semiconductor structure of claim 13 , wherein the semiconductor channel material structure is a semiconductor nanowire.

16. 2. The semiconductor structure of claim 1 , wherein a cross-coupling of the first dummy transistor with the third upper FET includes a first contact metal in contact with both a gate electrode and a source / drain region of the first dummy gate region, and a cross-coupling of the second dummy transistor with the second upper FET includes a second contact metal in contact with both a gate electrode and a source / drain region of the second dummy gate region.

17. 2. The semiconductor structure of claim 1, wherein both the first dummy gate region and the second dummy gate region are non-functional gate structures having source / drain regions removed or partially removed.

18. 2. The semiconductor structure of claim 1 , wherein the first upper FET, the third upper FET, and the third lower FET electrically share a common gate electrode, and the fourth upper FET, the second upper FET, and the second lower FET electrically share a common gate electrode.

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