Wide bandgap unipolar / bipolar transistors

Abstract

The power semiconductor device includes a semiconductor layer structure including a drift region of a first conductivity type and first and second contacts on the semiconductor layer structure. The drift region includes a wide bandgap semiconductor material and is configured to provide unipolar conduction between the first and second contacts below a current density threshold and bipolar conduction between the first and second contacts above a current density threshold. Related devices and methods of manufacture are also described.

Description

[Technical field]

[0001] This application claims priority to U.S. Patent Application No. 17 / 589,929, filed February 1, 2022, the disclosure of which is incorporated herein by reference.

[0002] The present specification relates to semiconductor devices, and more particularly to power semiconductor devices. [Background technology]

[0003] Power semiconductor devices are used to carry large currents and support high voltages. A wide variety of power semiconductor devices are known in the art, including, for example, power metal-insulator-semiconductor field effect transistors ("MISFETs," including metal-oxide-semiconductor FETs ("MOSFETs")), bipolar junction transistors ("BJTs"), insulated-gate bipolar transistors ("IGBTs"), junction-barrier Schottky diodes, gate-turn-off transistors ("GTOs"), MOS-controlled thyristors, and a variety of other devices. These power semiconductor devices are typically fabricated from wide bandgap semiconductor materials, such as silicon carbide ("SiC") or Group III-nitrides (e.g., gallium nitride ("GaN")-based semiconductor materials. Here, wide bandgap semiconductor materials refer to semiconductor materials having a bandgap greater than about 1.40 eV, e.g., greater than about 2 eV.

[0004] A conventional power semiconductor device typically has a semiconductor substrate having a first conductivity type (e.g., n-type substrate) on which an epitaxial layer structure having a first conductivity type (e.g., n-type) is formed. A portion of this epitaxial layer structure (which may include one or more separate layers) serves as the drift layer or drift region of the power semiconductor device. The device typically includes an "active region" that includes one or more "unit cells" having junctions, e.g., p-n junctions. The active region may be formed on and / or within the drift region. The active region acts as a primary junction to block voltage in a reverse bias direction and provide current in a forward bias direction. The power semiconductor device may also have an edge termination in a termination region adjacent to the active region. One or more power semiconductor devices may be formed on the substrate, with each power semiconductor device having a unique edge termination. After the substrate is fully processed, the resulting structure may be diced to separate the individual edge-terminated power semiconductor devices.

[0005] A power semiconductor device may have a unit cell configuration, where many individual unit cell structures of the active region are electrically connected in parallel to function as one power semiconductor device. In high power applications, such a power semiconductor device may include thousands or tens of thousands of unit cells implemented on a single chip or "die." A die or chip may include a small block of semiconductor material or other substrate upon which electronic circuit elements are fabricated.

[0006] Power semiconductor devices are designed to block (in forward or reverse blocking conditions) or pass (in forward operating conditions) large voltages and / or currents. For example, in a blocking condition, a power semiconductor device may be designed to maintain a potential of hundreds or thousands of volts. When the applied voltage approaches or exceeds the voltage level that the device is designed to block, a non-trivial level of current (called leakage current) may begin to flow in the power semiconductor device. The blocking capability of the device may be a function of, among other things, the doping density / concentration and thickness of the drift region. When the voltage applied to the device is increased to a critical level beyond the breakdown voltage, the increasing electric field may cause uncontrolled and undesirable runaway generation of charge carriers within the semiconductor device, leading to a condition known as avalanche breakdown.

[0007] A power semiconductor device can have a lateral or vertical structure. In a device having a lateral structure, the device terminations (e.g., drain, gate and source terminals for a power MOSFET device) are on the same major surface (e.g., top or bottom) of the semiconductor layer structure. In contrast, in a device having a vertical structure, at least one terminal is provided on each major surface of the semiconductor layer structure (e.g., in a vertical MOSFET device, the source may be on the top surface and the drain may be on the bottom surface of the semiconductor layer structure). The semiconductor layer structure may or may not include an underlying substrate. Summary of the Invention

[0008] According to some embodiments, a power semiconductor device includes a semiconductor layer structure including a wide bandgap semiconductor material, the semiconductor layer structure including a drift region of a first conductivity type, and first and second contacts on the semiconductor layer structure, the drift region including the wide bandgap semiconductor material and configured to provide unipolar conduction between the first and second contacts below a current density threshold and bipolar conduction between the first and second contacts above a current density threshold.

[0009] In some embodiments, the drift region is about 5×10 14 atoms / cm 3 The concentration of dopants of the first conductivity type in the drift region may be greater than the concentration of dopants of the second conductivity type in the drift region.

[0010] In some embodiments, the first and second contacts may be on opposite first and second surfaces of the semiconductor layer structure, and the drift region may further include a plurality of distinct minority carrier recombination sites spaced apart from the first and second surfaces.

[0011] In some embodiments, a gate can be provided adjacent a first side of the semiconductor layer structure, and the first and second contacts can be a source contact on the first side of the semiconductor layer structure and a drain contact on a second side of the semiconductor layer structure opposite the first side.

[0012] In some embodiments, the semiconductor layer structure may further include a collector region of the second conductivity type between the drift region and the drain contact, and at least one drain gap of the first conductivity type in the collector region adjacent to the drain contact.

[0013] In some embodiments, the semiconductor layer structure may further include a field stop region of the first conductivity type between the collector region and the drift region.

[0014] In some embodiments, the semiconductor layer structure may further include a semiconductor layer between the drain contact and the drift region, the semiconductor layer may define a heterojunction with the wide bandgap semiconductor material of the drift region and may include a field stop region, a collector region, and at least one drain gap therein.

[0015] In some embodiments, the separate minority carrier recombination sites may be multiple doped regions of the first and / or second conductivity type having a higher dopant concentration than the drift region.

[0016] In some embodiments, the separate minority carrier recombination sites may be defects in the crystal lattice of the drift region.

[0017] In some embodiments, the separate minority carrier recombination sites may include argon and / or hydrogen.

[0018] In some embodiments, the separate minority carrier recombination site may be located at a depth between about 15% and about 85% of a thickness defined between the first and second sides of the semiconductor layer structure.

[0019] In some embodiments, the first concentration of dopant in the drift region is about 5×10 14 ~5×10 17 atoms / cm 3 It could be.

[0020] According to some embodiments, a power semiconductor device includes a semiconductor layer structure including a drift region of a first conductivity type and a collector region of a second conductivity type, and first and second contacts on opposing first and second sides, respectively, of the semiconductor layer structure. The collector region is between the drift region and the second side. The drift region has a capacitance of about 5×10 14 atoms / cm 3 A first concentration of dopant of the first conductivity type in the drift region is greater than a first concentration of dopant of the first conductivity type in the drift region. A second concentration of dopant of the second conductivity type in the drift region is less than the first concentration.

[0021] In some embodiments, the drift region can be configured to provide unipolar conduction between the first and second contacts below a current density threshold and bipolar conduction between the first and second contacts above a current density threshold.

[0022] In some embodiments, the semiconductor layer structure may further include a field stop region of the first conductivity type between the collector region and the drift region.

[0023] In some embodiments, the semiconductor layer structure may further include at least one drain gap of the first conductivity type in the collector region.

[0024] In some embodiments, the semiconductor layer structure may further include a source region of the first conductivity type and a well region of the second conductivity type adjacent the first side, and the first and second contacts may include a source contact on the first side and a drain contact on the second side.

[0025] In some embodiments, the drift region can include a wide bandgap semiconductor material. A semiconductor layer can be provided between the drain contact and the drift region. The semiconductor layer can define a heterojunction with the wide bandgap semiconductor material of the drift region and can include a field stop region, a collector region, and at least one drain gap.

[0026] In some embodiments, the drift region may further include a plurality of separate minority carrier recombination sites spaced apart from the opposing first and second faces.

[0027] In some embodiments, the separate minority carrier recombination site may include multiple doped regions of the first and / or second conductivity type having a higher dopant concentration than the drift region.

[0028] In some embodiments, the separate minority carrier recombination sites may be defects in the crystal lattice of the drift region.

[0029] In some embodiments, the separate minority carrier recombination sites may include argon and / or hydrogen.

[0030] In some embodiments, the separate minority carrier recombination site may be located at a depth between about 15% and about 85% of a thickness defined between the first and second sides of the semiconductor layer structure.

[0031] In some embodiments, the first concentration of dopant in the drift region is about 5×10 14 ~5×10 17 atoms / cm 3 It could be.

[0032] According to some embodiments, a power semiconductor device includes a semiconductor layer structure including a drift region of a first conductivity type and first and second contacts on opposite first and second surfaces of the semiconductor layer structure, respectively, the drift region configured to provide majority carrier conduction between the first and second contacts and including a plurality of distinct minority carrier recombination sites spaced apart from the first and second surfaces.

[0033] In some embodiments, the semiconductor layer structure may further include a source region of the first conductivity type and a well region of the second conductivity type adjacent the first side, and the first and second contacts may be a source contact on the first side and a drain contact on the second side.

[0034] In some embodiments, the semiconductor layer structure may further include a gate adjacent to the first surface, and a minority carrier recombination site may be between the gate and the drain contact.

[0035] In some embodiments, the separate minority carrier recombination site may be located at a depth between about 15% and about 85% of a thickness defined between the first and second sides of the semiconductor layer structure.

[0036] In some embodiments, the separate minority carrier recombination sites can be laterally spaced apart from one another by spacings of between about 0.2 μm and about 2.0 μm.

[0037] In some embodiments, the separate minority carrier recombination sites may be multiple doped regions of the first and / or second conductivity type having a higher dopant concentration than the drift region.

[0038] In some embodiments, the separate minority carrier recombination sites may be defects in the crystal lattice of the drift region.

[0039] In some embodiments, the separate minority carrier recombination sites may include argon and / or hydrogen.

[0040] In some embodiments, the semiconductor layer structure may further include a collector region of the second conductivity type between the drift region and the drain contact, a field stop region of the first conductivity type between the collector region and the drift region, and at least one drain gap of the first conductivity type in the collector region adjacent to the drain contact.

[0041] In some embodiments, the drift region may include a wide bandgap semiconductor material.

[0042] In some embodiments, the semiconductor layer structure may further include a semiconductor layer between the drain contact and the drift region, the semiconductor layer defining a heterojunction with the wide bandgap semiconductor material of the drift region and including a field stop region, a collector region, and at least one drain gap.

[0043] In some embodiments, the drift region is about 5×10 14 ~5×10 17 atoms / cm 3 and a concentration of dopant of the second conductivity type in the drift region is less than that of the first conductivity type.

[0044] In some embodiments, the drift region can be configured to provide unipolar conduction of majority carriers between the first and second contacts below a current density threshold and bipolar conduction of minority and majority carriers between the first and second contacts above a current density threshold.

[0045] According to some embodiments, a method of manufacturing a power semiconductor device includes forming a semiconductor layer structure including a drift region of a first conductivity type; and forming a plurality of separate minority carrier recombination sites in the drift region, the separate minority carrier recombination sites spaced apart from opposite first and second surfaces of the semiconductor layer structure.

[0046] In some embodiments, forming the semiconductor layer structure may include forming a drift region on the substrate using an epitaxial growth process, with the first surface opposite the substrate, and forming the separate minority carrier recombination sites may include implanting ions into the drift region.

[0047] In some embodiments, the implantation may occur from the first side.

[0048] In some embodiments, the implantation may occur during a break in the epitaxial growth process.

[0049] In some embodiments, the method may further include removing the substrate in response to completion of the epitaxial growth process, and implantation may be performed from the second side.

[0050] In some embodiments, the ions may include dopants of the first and / or second conductivity type, and the implantation may form separate minority carrier recombination sites as multiple doped regions having a higher dopant concentration than the drift region.

[0051] In some embodiments, the ions may include neutral species and the implantation may create separate minority carrier recombination sites as defects in the crystal lattice of the drift region.

[0052] In some embodiments, the implantation may form separate minority carrier recombination sites at a depth between about 15% and about 85% of a thickness defined between the first and second sides of the semiconductor layer structure.

[0053] In some embodiments, forming the semiconductor layer structure may further include forming a field stop region of a first conductivity type adjacent to the drift region, forming a collector region of a second conductivity type adjacent to the field stop region, and forming at least one drain gap of the first conductivity type between portions of the collector region.

[0054] In some embodiments, at least one drain gap can be configured to provide unipolar conduction between the first and second contacts on opposing first and second sides of the semiconductor layer structure below a current density threshold, and a p-n junction between the collector region and the field stop region can be configured to provide bipolar conduction between the first and second contacts above a current density threshold.

[0055] In some embodiments, forming the backside structure may include implanting ions into the second surface to form a field stop region, a collector region, and at least one drain gap.

[0056] In some embodiments, forming the backside structure can include removing the substrate to expose a surface of the drift region opposite the first surface; forming a semiconductor layer on a surface of the drift region, the semiconductor layer defining a heterojunction with a wide bandgap semiconductor material of the drift region; and implanting ions into the semiconductor layer to form a field stop region, a collector region, and at least one drain gap.

[0057] In some embodiments, the drift region is about 5×10 14 ~5×10 17 atoms / cm 3 and a concentration of dopants of the second conductivity type in the drift region is less than that of the first conductivity type.

[0058] Other devices, apparatus, and / or methods according to some embodiments will become apparent to one of ordinary skill in the art upon review of the following figures and detailed description. Any and all combinations of the above embodiments, as well as all such additional embodiments, are intended to be included within this description, be within the scope of the invention, and be protected by the accompanying claims. [Brief description of the drawings]

[0059] [Figure 1A] 1 is a cross-sectional view illustrating an example structure of a planar power semiconductor device according to some embodiments of the present invention. [Figure 1B] 1 is a cross-sectional view illustrating an example structure of a trench power semiconductor device according to some embodiments of the present invention. [Figure 2A] 1A-1D are cross-sectional views illustrating an exemplary unipolar operation of a planar power semiconductor device according to some embodiments of the present invention. [Figure 2B] 1A-1D are cross-sectional views illustrating an exemplary unipolar operation of a trench power semiconductor device according to some embodiments of the present invention. [Figure 3A] 1A-1D are cross-sectional views illustrating an exemplary bipolar operation of a planar power semiconductor device according to some embodiments of the present invention. [Figure 3B] 1A-1D are cross-sectional views illustrating an exemplary bipolar operation of a trench power semiconductor device according to some embodiments of the present invention. [Figure 4A] 1A-1C are cross-sectional views illustrating example configurations of separate minority carrier recombination sites in a power semiconductor device according to some embodiments of the present invention. [Figure 4B] 1A-1C are cross-sectional views illustrating example configurations of separate minority carrier recombination sites in a power semiconductor device according to some embodiments of the present invention. [Figure 4C] 1A-1C are cross-sectional views illustrating example configurations of separate minority carrier recombination sites in a power semiconductor device according to some embodiments of the present invention. [Figure 4D]1A-1C are cross-sectional views illustrating example configurations of separate minority carrier recombination sites in a power semiconductor device according to some embodiments of the present invention. [Figure 4E] 1A-1C are cross-sectional views illustrating example configurations of separate minority carrier recombination sites in a power semiconductor device according to some embodiments of the present invention. [Figure 4F] 1A-1C are cross-sectional views illustrating example configurations of separate minority carrier recombination sites in a power semiconductor device according to some embodiments of the present invention. [Figure 4H] 1A-1C are cross-sectional views illustrating example configurations of separate minority carrier recombination sites in a power semiconductor device according to some embodiments of the present invention. [Figure 5A] 1 is a cross-sectional view illustrating an example configuration of a back-side collector region and a drain gap in a power semiconductor device according to some embodiments of the present invention. [Figure 5B] 1 is a cross-sectional view illustrating an example configuration of a back-side collector region and a drain gap in a power semiconductor device according to some embodiments of the present invention. [Figure 6A] 1 is a cross-sectional view illustrating an example configuration of a back-side collector region and a drain gap in a power semiconductor device according to some embodiments of the present invention. [Figure 6B] 1 is a cross-sectional view illustrating an example configuration of a back-side collector region and a drain gap in a power semiconductor device according to some embodiments of the present invention. [Figure 7A] 1 through 4 are cross-sectional views illustrating intermediate manufacturing operations in a method of manufacturing a power semiconductor device according to some embodiments of the present invention. [Figure 7B] 1 through 4 are cross-sectional views illustrating intermediate manufacturing operations in a method of manufacturing a power semiconductor device according to some embodiments of the present invention. [Figure 8A] 1 through 4 are cross-sectional views illustrating intermediate manufacturing operations in a method of manufacturing a power semiconductor device according to some embodiments of the present invention. [Figure 8B]1 through 4 are cross-sectional views illustrating intermediate manufacturing operations in a method of manufacturing a power semiconductor device according to some embodiments of the present invention. [Figure 9] 1 through 4 are cross-sectional views illustrating intermediate manufacturing operations in a method of manufacturing a power semiconductor device according to some embodiments of the present invention. [Figure 10] 1 through 4 are cross-sectional views illustrating intermediate manufacturing operations in a method of manufacturing a power semiconductor device according to some embodiments of the present invention. [Figure 11] 1 through 4 are cross-sectional views illustrating intermediate manufacturing operations in a method of manufacturing a power semiconductor device according to some embodiments of the present invention. [Figure 12] 1 through 4 are cross-sectional views illustrating intermediate manufacturing operations in a method of manufacturing a power semiconductor device according to some embodiments of the present invention. [Figure 13A] 1 is a plan view or layout diagram of a semiconductor device or die illustrating an exemplary configuration of a backside structure including a collector region and a drain gap according to some embodiments of the present invention. [Figure 13B] 1 is a plan view or layout diagram of a semiconductor device or die illustrating an exemplary configuration of a backside structure including a collector region and a drain gap according to some embodiments of the present invention. [Figure 14A] 1 is a plan view or layout diagram of a semiconductor device or die illustrating an exemplary configuration of a backside structure including a collector region and a drain gap according to some embodiments of the present invention. [Figure 14B] 1 is a plan view or layout diagram of a semiconductor device or die illustrating an exemplary configuration of a backside structure including a collector region and a drain gap according to some embodiments of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0060] Vertical power semiconductor devices, including MOSFET transistors, may be implemented using a number of different wide bandgap semiconductor materials. For example, planar structures may include a gate electrode design in which the gate electrode of the transistor is formed on the top surface of a semiconductor layer structure. Trench structures may include a gate electrode that extends into (i.e., embedded in) a trench in the surface of the semiconductor layer structure and may be referred to as a gated trench MOSFET. These vertical power semiconductor device structures utilize inversion of pn junction barriers and doped well regions to provide for the flow of electrons from source to drain in a vertical direction (e.g., between opposite sides of the semiconductor layer structure). Although described and illustrated herein with respect to regions of particular conductivity types (i.e., n-type and p-type) as examples, it will be understood that the conductivity type of the regions in any of the illustrated examples may be inverted (i.e., p-type and n-type) in accordance with embodiments of the present invention. As used herein, the term "semiconductor layer structure" refers to a structure that includes one or more semiconductor layers, such as a semiconductor substrate and / or a semiconductor epitaxial layer.

[0061] Some embodiments of the present invention may arise from the recognition that power MOSFET devices may be capable of fast switching and therefore low switching losses, but may have limited current density capabilities, all of which may be due to the majority carrier nature of the device. In contrast, IGBT devices are minority carrier devices that may have high current density capabilities, but may be limited in switching speed by minority carrier lifetime induced tail currents, which may result in extended turn-off times and therefore higher switch-off energy losses, as compared to MOSFETs.

[0062] Embodiments of the invention include devices and associated methods that can achieve many of the advantages of both field effect and bipolar type devices, including fast switching speeds and high current density capabilities. In particular, some embodiments of the invention provide a voltage controlled power semiconductor device having unipolar conduction at low current densities that transitions to bipolar conduction at high current densities. The bipolar conduction is configured to switch on after the unipolar conduction is initiated. The bipolar conduction is configured to switch off before the unipolar conduction switches off. The drift region may include separate minority carrier recombination sites, which allows for faster switching due to a reduction in minority carrier tail current due to enhanced recombination of minority carriers. For example, in some embodiments, the drift region includes heavily doped regions of a first conductivity type (e.g., n-type) and / or a second conductivity type (e.g., p-type), which may provide a reduction in minority carrier tail current due to minority carriers beginning to recombine in the interval between switching off the bipolar conduction and switching off the unipolar conduction, allowing the device to switch off more quickly.

[0063] In some embodiments, wide band gap (WBG) materials may be used to form merged or tandem field effect / bipolar transistor devices that include WBG transistors (such as SiC transistors), where the WBG transistors begin to conduct as fast turn-on FETs (majority carrier devices) and subsequently reach a certain level or threshold FET current density J th When the drift region reaches a critical current density of 1000 MHz, it switches into a high current density bipolar transistor (minority carrier, conductivity modulated device), allowing the device to handle the burst current demands of many switching applications. Separate minority carrier recombination sites can be provided at one or more depths across the thickness of the drift region to allow the device to quickly dissipate the minority carriers when switching off, thereby achieving faster switching.

[0064] Embodiments of the present invention may enable field effect / bipolar power transistor devices including thinner, lower resistance drift regions for higher voltage operation due to the superior critical field characteristics provided by wide band gap (WBG) materials such as SiC, without charge balancing junctions (i.e., without having substantially equal amounts of doping between n-type and p-type regions in the drift region). The width, depth, spacing, doping, and / or density of separate minority carrier recombination sites in the drift region may be selected or optimized to provide minority carrier absorption without charge balancing constraints and may be selected to balance the tradeoff between faster turn-off speed (e.g., using more recombination sites) and lower on-resistance (e.g., using fewer recombination sites).

[0065] 1A-3B are schematic cross-sectional views (e.g., along the X and Z directions) illustrating examples of vertical field effect / bipolar power semiconductor devices, shown as partial unit cells of a planar device 100a or a trench device 100b (collectively 100). In particular, FIGS. 1A, 2A, and 3A illustrate the structure and operation of the planar device 100a, whereas FIGS. 1B, 2B, and 3B illustrate the structure and operation of the trench device 100b. It will be appreciated that the unit cells 100a, 100b may be combined with conventional transistor structures in some embodiments and replicated in one or more dimensions to define the power semiconductor devices described herein.

[0066] 1A and 1B, power devices 100a, 100b (collectively 100) may include a semiconductor layer structure 106 having a drift region 120 of a first conductivity type (e.g., n-type), a first region 160 of the first conductivity type, a second region 140, 150 of a second conductivity type (e.g., p-type), and respective contacts 190, 192 in the semiconductor layer structure 106 (e.g., at first and second opposing faces 106f and 106b). The drift region 120 includes a wide bandgap semiconductor material, such as SiC or a III-nitride. The drift region 120 may further include a separate minority carrier recombination site 125 spaced apart from the first and second faces 106f and 106b. As will be described in more detail, the drift region 120 may include a current density threshold j th unipolar conduction 178u between the respective contacts 190, 192 lower than the current density threshold j th and a bipolar conduction 178b between the respective contacts 190, 192 that is higher than the first conduction potential 178b.

[0067] As shown in Figures 1A and 1B, the power device 100 may be formed on a layer or substrate 110' (see Figures 7A and 7B) of a first conductivity type (e.g., n-type), for example silicon carbide. A drift layer or region 120 of the first conductivity type is provided on the layer 110', for example by epitaxial growth. The drift region 120 may contain impurities of the first conductivity type (e.g., nitrogen (N) or phosphorus (P) for n-type, or boron (B) for p-type). The drift region 120 may have a concentration of about 5 x 10 14 atoms / cm 3 For example, about 5 × 10 14 ~5×10 17 atoms / cm 3 , about 5×10 15 ~5×10 16 , about 8×10 15 ~2×10 16 atoms / cm 3 , or about 9 × 10 15 ~1×10 16 atoms / cm 3The doping of the drift region 120 may include a concentration of dopants of the first conductivity type of about 1×10 13 ~3×10 13 atoms / cm 3 , or up to about 3 × 10 14 atoms / cm 3 Layer 110' may include a concentration of dopants of the first conductivity type of n-type (e.g., n + ) silicon carbide substrate, lightly doped (e.g., n - ) n-type drift layer or region 120 (e.g., a 4H—SiC epitaxial layer) may be epitaxially grown on layer 110′. In some embodiments, a portion of drift region 120 may include a current spreading layer (“CSL”) of a first conductivity type having a higher doping or dopant concentration than drift region 120. Drift region 120 may not be charge balanced; that is, the concentration of dopants of the second conductivity type in the drift region may be less than or otherwise substantially equal to the concentration of dopants of the first conductivity type.

[0068] A moderately or heavily doped region of a second conductivity type (e.g., p-type) is formed (e.g., by epitaxial growth or implantation) in the drift region 120 adjacent the first face 106f to serve as a body or well region (or "well") 140 for the device 100. + A heavily doped source region 160 (e.g., 0.1 to 0.5 μm) is formed in an upper portion of well region 140 adjacent first face 106f, for example by ion implantation. Source region 160 may be doped with n-type impurities and may be about 5×10 18 ~5×10 21 atoms / cm 3 , for example, about 8 x 10 18 ~1×10 21 atoms / cm 3 , about 1×10 19 ~5×10 20 atoms / cm 3 , or about 5 × 10 19 ~1×1020 atoms / cm 3 That is, the source region 160 has a dopant concentration that is greater than the dopant concentration of the drift region 120, for example, by a factor of about 10 or more in some embodiments. + A heavily doped region 150 (which may be referred to as a well-tie) is also formed in an upper portion of well region 140 adjacent first face 106f, for example by ion implantation. Region 150 may be doped with p-type impurities and may be about 5×10 18 ~5×10 20 atoms / cm 3 , for example, about 1 x 10 19 ~3×10 20 atoms / cm 3 , or about 2 × 10 19 ~2×10 20 atoms / cm 3 The region / well tie can provide a relatively low resistance and ohmic contact to the well 140. A heavily doped drain region 185 having a dopant concentration higher than the dopant concentration of the drift region 120 is provided adjacent the second face 106b. The silicon carbide (or other wide bandgap semiconductor) layer structure 106 includes a substrate or layer 110' (including a backside structure 110 formed therein or in place of the drift region 120), a well region 140, a source region 160, and / or various regions / patterns formed therein.

[0069] A control terminal 184 is provided on portions of the drift region 120, the well region 140, and the source region 160. Gate insulation layers 182a, 182b (collectively 182), such as, for example, oxide layers, are formed on portions of the drift region 120, the well region 140, and the source region 160 adjacent the first face 106f. Gate electrodes (or "gates") 184a, 184b (collectively 184) are formed on the gate oxide layer 182. The gate insulation layer 182 and the gate 184 thereon may collectively be referred to herein as a gate structure 182 / 184.

[0070] More specifically, in the planar device 100a of Figures 1A, 2A and 3A, a gate insulating layer 182a is formed on the portions of the drift region 120, well region 140 and source region 160 adjacent the first face 106f of the semiconductor layer structure 106, and a gate 184a is formed on the insulating oxide layer 182a extending along the face 106f of the structure 106. A unipolar conduction channel 178a (with conduction shown by solid arrows in Figures 2A and 3A) for each planar device unit cell 100a is defined through the well 140 and the portion of the drift region 120 below the gate 184a. For example, the inversion channel 178u of a planar SiC device may be on the Si face of the SiC.

[0071] In the trench-type device 100b of Figures 1B, 2B and 3B, a gate trench 180 is formed extending from the first surface 106f of the semiconductor layer structure 106 into the drift region 120, a gate insulating layer 182b is formed on the sidewalls and bottom surface of the gate trench, and a gate 184b is formed on the gate oxide layer 182a to fill the gate trench. A unipolar conduction channel 178u (with conduction indicated by solid arrows in Figures 2B and 3B) for each trench-type device unit cell 100b is defined vertically through the well 140 along the sidewalls of the gate trench 180. For example, the inversion channel 178u of a trench SiC device may be along the sidewalls of the trench in the a-plane or m-plane of SiC. The trench device 100b may further include a shielding pattern below the gate trench 180 to reduce the electric field level in the gate insulating layer 182b, especially at the corners of the gate trench 180 where the electric field level may be more concentrated. The shielding pattern (not shown) may include a doped semiconductor layer having the same conductivity type (p-type in this example) as the well region 140, but with a higher dopant concentration.

[0072] 1A-3B, the power devices 100a, 100b each include conductive contacts 190 and 192, shown, for example, on opposing sides 106f and 106b of the semiconductor layer structure 106. For example, the contact 190 may be a source contact on the source region 160, and the contact 192 may be a drain contact. The contacts 190 and 192 may be ohmic contacts. An ohmic contact may refer to a non-rectifying electrical junction between two conductors (e.g., a metal and a semiconductor) that have a linear current-voltage (IV) curve. Suitable metals for forming ohmic contacts may include refractory metals such as Ti, W, titanium tungsten (TiW), silicon (Si), titanium tungsten nitride (TiWN), tungsten silicide (WSi), rhenium (Re), niobium (Nb), Ni, gold (Au), aluminum (Al), tantalum (Ta), molybdenum (Mo), NiSix, titanium silicide (TiSi), titanium nitride (TiN), WSiN, Pt, etc. Thus, contacts 190 and / or 192 may include ohmic contact portions in direct contact with epitaxial layer 120, or more generally, semiconductor layer structure 106. In some embodiments, contacts 190 and / or 192 may be formed from multiple layers or metals.

[0073] Thus, a wide bandgap field effect / bipolar transistor device 100a, 100b according to an embodiment of the present invention includes a front side or upper portion of a semiconductor layer structure 106, which may be similar to a planar MOSFET structure (as shown in FIGS. 1A, 2A and 3A) or a trench MOSFET structure (as shown in FIGS. 1B, 2B and 3B), including a drift region 120 of a first conductivity type (e.g., n-type), a source region 160 of the first conductivity type, and a well region 140 of a second conductivity type (e.g., p-type).

[0074] 1A-3B, the backside structure or lower portion 110 of the semiconductor layer structure 106 of the wide bandgap field effect / bipolar transistor devices 100a, 100b may be similar to an IGBT structure. The backside structure 110 may be a semiconductor layer (e.g., a SiC growth substrate or a subsequently formed Si layer) disposed between a drain contact 192 and the drift region 120. The backside structure 110 may be the same material as the drift region 120 or may be a different material that defines a heterojunction 120 / 110 with the wide bandgap semiconductor material of the drift region 120. The backside structure 110 includes an IGBT-like field stop region 115 of a first conductivity type, a collector region 130 of a second conductivity type, and one or more drain gaps 115g of the first conductivity type in the collector region 130 adjacent to the drain contact 192.

[0075] Figures 2A and 2B show the current density threshold j along with the low resistance (Rds(on)) MOSFET behavior during device turn-on and turn-off. th The drain gap 115g is configured to permit unipolar conduction 178u to a drain contact 192 disposed beneath the collector region 130 at current levels below a threshold current density j, as will be further described with reference to the illustrative examples of FIGS. th Thus, majority carrier unipolar conduction 178u (indicated by the solid arrow) occurs at a current density threshold j th A current is provided between source contact 190 and drain contact 192 in response to application of a voltage or control signal to gate 184 at a current level lower than

[0076] 3A and 3B show that the p-n junction between the field stop region 115 and the collector region 130 is at a current density threshold j such that it provides bipolar conduction 178b. thThat is, after the initial device turn-on and unipolar conduction as shown in Figures 2A and 2B, the current level rises above the current level threshold j th At this point, the pn junction between the field stop region 115 and the collector region 130 conducts current with minority carriers, providing bipolar conduction 178b (indicated by the dashed arrow) between the source contact 190 and the drain contact 192. When the current level exceeds the current density threshold j th below 178u, the minority carriers may be rapidly annihilated, for example, by the presence of separate minority carrier recombination sites 125, resulting in a transition back to unipolar conduction 178u before the device turns off.

[0077] Figures 4A, 4B, 4C, 4D, 4E, 4F, and 4H are cross-sectional views illustrating exemplary configurations of separate minority carrier recombination sites in power semiconductor devices according to some embodiments of the present invention. The examples illustrated in Figures 4A-4H are shown with respect to planar transistor devices (such as unit cell 100a of Figures 1A, 2A, and 3A), although it will be appreciated that trench transistor devices (such as device 100b of Figures 1B, 2B, and 3B) may be similarly formed.

[0078] 4A-4H, separate minority carrier recombination sites 125 may be formed in a conductive path in the drift region 120 between and spaced apart from the first and second faces 106f and 106b of the semiconductor layer structure 106. The recombination sites 125 may be formed with a width, depth, lateral spacing, doping concentration, and / or density (number of recombination sites 125 per unit area) that may be tailored or otherwise configured to provide a desired or optimal minority carrier recombination for a given application.

[0079] For example, in some embodiments, the separate recombination sites 125 may have respective widths of about 0.1 μm to about 1.0 μm, or at most a few microns (e.g., about 1 μm to about 5 μm), and respective thicknesses (e.g., in the z-direction) of approximately a few tenths of a micron (e.g., about 0.1 μm to about 0.6 μm). The depths (e.g., in the z-direction) of the separate recombination sites 125 may be about 15% to about 85% of the thickness between the faces 106f and 106b, such as about 50% of the thickness (i.e., at the center of the drift region 120), about 33% of the thickness, or about 66% of the thickness of the drift region 120. As shown in FIGS. 4E-4G, the separate recombination sites 125 may be provided at multiple depths. The lateral spacing (e.g., in the x-direction) between adjacent separate recombination sites 125 may be similar to their respective widths, e.g., a few tenths of a micron apart (e.g., about 0.1 μm to about 1.0 μm) up to a few microns apart (e.g., about 1 μm to about 5 μm), e.g., about 0.2 μm to about 2.0 μm apart. The density of the separate recombination sites 125 may range from 0 to a few (e.g., about 1 to 3) per square micron.

[0080] 4A-4G, the separate minority carrier recombination sites 125 may be implemented by multiple doped regions of first and / or second conductivity type 125n and / or 125p having a higher dopant concentration than the drift region 120. For example, the doping concentration of the p-type dopant region 125p and / or the n-type dopant region 125n may be about 1×10 17 ~Approx. 5×10 20 atoms / cm 3 , for example, about 5 x 10 17 ~Approx. 1×10 20 atoms / cm 3 P-type dopant regions 125p and / or n-type dopant regions 125n may be introduced at various locations in drift region 120 (e.g., by implanting dopants of the first and / or second conductivity types having a higher dopant concentration than the drift region).

[0081] FIG 4A shows an example device 400a in which the separate minority carrier recombination sites 125 are n-type doped regions 125n. FIG 4B shows an example device 400b in which the separate minority carrier recombination sites 125 are p-type doped regions 125p. In FIG 4A and FIG 4B, the separate minority carrier recombination sites 125 are provided at respective depths D1 (relative to the front surface 106f) toward a central portion of the drift region 120. Providing separate minority carrier recombination sites 125 in a central or intermediate portion (centrally located in the conduction path) of the drift region 120 may be advantageous for carrier recombination efficiency. However, the separate minority carrier recombination sites 125 may be provided closer to the front face 106f (e.g., at a depth D2 as shown in device 400c of FIG. 4C), closer to the rear face 106b (at a depth D3 as shown in device 400d of FIG. 4D), or both (as shown in device 400e of FIG. 4E), which may be easier to implement from a manufacturing process standpoint (e.g., by implanting ions into the front face 106f and / or the rear face 106). The depths D1, D2, D3 may be about 15% to about 85% of the thickness defined between the first and second faces 106f and 106b of the semiconductor layer structure 106.

[0082] The separate minority carrier recombination sites 125 may also be distributed throughout the drift region 120. For example, device 400f in FIG. 4F shows a columnar distribution of the separate minority carrier recombination sites 125 (e.g., alternating n-type doped regions 125n and p-type doped regions 125p in each column). Device 400g in FIG. 4G shows a staggered or offset distribution of the separate minority carrier recombination sites 125 (e.g., having alternating columns of n-type doped regions 125n and p-type doped regions 125p).

[0083] Additionally or alternatively, as shown in device 400h of FIG. 4H, separate minority carrier recombination sites 125 may be implemented by forming defects 125x in the crystal lattice of drift region 120. For example, neutral ionic species (such as argon (Ar) or hydrogen (H+)) may be implanted into front surface 106f or back surface 106b of the semiconductor layer structure to break bonds or otherwise damage the crystal lattice of drift region 120 to create defects 125x. Thus, defects 125x may include trace amounts of neutral ionic species, such as argon (Ar) and / or hydrogen (H+). Defects 125x may be provided in drift region 120 in any of the configurations and / or depths shown in FIGS. 4A-4G.

[0084] More generally, the separate minority carrier recombination sites 125 may include doped regions (having a higher carrier concentration than the drift region 120) and / or defects in the drift region 120 configured to aid minority carrier recombination. The separate minority carrier recombination sites 125 may be provided in the drift region 120 in any desired order or random distribution between and spaced apart from the first and second faces 106f and 106b of the semiconductor layer structure to help minority carriers recombine more quickly (and thus increase the switching speed of the device), with widths, depths, spacing, doping, and / or densities that may be selected to balance the tradeoff between reducing turn-off speed and reducing on-resistance.

[0085] 5A, 5B, 6A and 6B are cross-sectional views illustrating an exemplary configuration of a backside structure 110 including a collector region 130 and a drain gap 115 in a power semiconductor device according to some embodiments of the present invention. The examples illustrated in Figures 5A-6B are shown with respect to a planar type transistor device (such as unit cell 100a of Figures 1A, 2A and 3A), although it will be appreciated that trench type transistor devices (such as device 100b of Figures 1B, 2B and 3B) may be similarly formed.

[0086] As shown in FIGS. 5A-6B, the width, doping level, depth, and / or density (number of gaps 115g per unit area) of the gaps 115g can be adjusted to achieve a desired current density threshold j at which the device switches from predominantly unipolar to predominantly bipolar operation such that the device operates more like a MOSFET or more like an IGBT. th The current density threshold j may be adjusted or otherwise configured to provide th may refer to the current level that forward biases the pn junction between the collector region 130 and the field stop region 115 such that the IGBT turns on and becomes the predominant conduction mode of the mixed device (bipolar). For example, the (lateral) width Wg and doping level of the drain gap 115g, and the doping level and depth of the collector region 130 into the backside 106b of the structure 106 (which may define the depth Dg of the drain gap 115g) may determine the current density threshold j th At current levels greater than 178b, the voltage drop between the collector node 130 and the surrounding opposite conductivity type region 115 can be configured to be sufficient to forward bias the p-n junction between the collector region 130 and the field stop region 115 at the desired drain current level to initiate bipolar conduction 178b.

[0087] Therefore, the dopant concentration in the drain gap 115g (for example, 1×10 14 ~Approx. 1×10 19 atoms / cm 3 ), density (per unit area) and dimensions Wg, Dg can be configured to provide different desired operational behavior. For example, increasing the dopant concentration of the first conductivity type (e.g., about 5×10 16 ~Approx. 5×10 18 atoms / cm 3 ), increased width Wg and / or depth Dg (as shown in device 500a of FIG. 5A), and / or larger drain gap 115g (as shown in device 500b of FIG. 5B) may result in a higher current density threshold j th, which delays the transition from unipolar to bipolar conduction so that the devices 500a, 500b have a more FET-like behavior. Conversely, a lower dopant concentration of the first conductivity type (e.g., about 5×10 14 ~Approx. 5×10 16 atoms / cm 3 ), reduced width Wg and / or depth Dg (as shown in device 600a of FIG. 6A), and / or smaller drain gap 115g (as shown in device 600b of FIG. 6B) may result in a lower current density threshold j th , resulting in a faster transition from unipolar to bipolar conduction such that devices 600a, 600b have a more BJT-like behavior.

[0088] In some embodiments, backside doping operations may be used to form the field stop region 115, collector region 130, and / or drain gap 115g to provide a desired configuration (e.g., width, depth, dopant concentration, gap density) in the backside structure 110. Laser annealing techniques may be used to activate the implanted dopants. Exemplary fabrication operations are described in more detail below with reference to Figures 7A-12.

[0089] 7A, 7B, 8A, 8B, 9, 10, 11, and 12 are cross-sectional views illustrating intermediate fabrication operations in a method of fabricating a power semiconductor device according to some embodiments of the present invention. The exemplary process illustrated in Figures 7A-12 is illustrated with respect to fabricating the planar transistor device 100a of Figures 1A, 2A, and 3A, although it will be appreciated that the trench transistor device 100b of Figures 1B, 2B, and 3B may be similarly formed. Operations for fabricating the contacts 190, 192 and gate structures 182 / 184 are omitted for ease of explanation.

[0090] 7A and 7B, the semiconductor layer structure 106 is formed by providing a drift region 120 of a first conductivity type on a substrate 110'. For example, the substrate 110' may be a silicon carbide substrate, lightly doped (e.g., n - ) An n-type drift layer or region 120 (e.g., a 4H—SiC epitaxial layer) may be epitaxially grown on the substrate 110′. The drift region 120 has a dopant density of about 5×10 14 atoms / cm 3 For example, about 5 × 10 14 ~5×10 17 atoms / cm 3 The concentration of dopants of the second conductivity type (e.g., p-type) in the drift region 120 may be less than or otherwise not substantially the same as the concentration of the first conductivity type, such that the drift region 120 may not be charge balanced.

[0091] 7A and 7B, a plurality of separate minority carrier recombination sites (125n, 125p, and / or 125x, collectively 125) are formed in the drift region 120 such that they are spaced apart from opposite first and second faces 106f and 106b of the semiconductor layer structure 106. The separate minority carrier recombination sites 125 may be formed by implanting ions into the drift region 120 from the front face 106f and / or the back face 106b of the semiconductor layer structure 106.

[0092] For example, as shown in FIG. 7A, an ion implantation process is performed to form the separate minority carrier recombination sites 125 using a front-side implantation process with one or more implantation energies selected to provide separate minority carrier recombination sites 125 at one or more depths across the thickness of the drift region 120. In another example, as shown in FIG. 7B, an ion implantation process is performed during the breaks between multiple epitaxial growth processes. In particular, the epitaxial growth may be paused after the formation of the first portion 120a of the drift region (indicated by the dashed line), the ion implantation process may be performed by implanting ions into the front-side 106f to form the separate minority carrier recombination sites 125, and the epitaxial growth may be resumed to complete the fabrication of the drift region 120. As yet another example, the growth substrate 110′ may be removed, and an ion implantation process may be performed by implanting ions into the back-side 106b to form the separate minority carrier recombination sites 125, as described below with reference to FIG. 11.

[0093] Separate minority carrier recombination sites 125 are thereby formed in any of the configurations described above with reference to Figures 4A-4H, i.e., the width, depth, spacing, doping, and / or density of the separate minority carrier recombination sites 125 may be formed using the processes described above and / or other processes to provide minority carrier absorption as needed to achieve desired device characteristics (e.g., faster switching speed by forming more recombination sites 125, lower on-resistance by forming fewer recombination sites 125).

[0094] As shown in Figures 8A and 8B, one or more front-side processes (e.g., epitaxial growth, patterning, and / or ion implantation) may be performed adjacent to the first face 106f of the semiconductor layer structure 106 to form a moderately or heavily doped well region 140 of a second conductivity type, a heavily doped source region 160 of a first conductivity type (e.g., n+), and a heavily doped region 150 of a second conductivity type (e.g., p+). For example, using one or more masking or patterning operations, dopants of a second conductivity type may be implanted into the front surface 106f to form well region 140, dopants of a first conductivity type may be implanted into the front surface 106f to form source region 160 in an upper portion of well region 140, and dopants of the second conductivity type may be implanted into the front surface 106f to form region 150 in an upper portion of well region 140 adjacent to source region 160.

[0095] As shown in Figures 9 and 10, one or more backside processes (e.g., patterning, ion implantation, and / or annealing processes) may be performed to form a field stop region 115 of a first conductivity type, a collector region 130 of a second conductivity type, and at least one drain gap 115g of a first conductivity type adjacent the second surface 106b of the semiconductor layer structure 106, which define a backside structure 110. For example, a blanket ion implantation process may be performed to implant dopants of a first conductivity type into the back surface 106b to form the field stop region 115 at a desired depth (relative to the back surface 106b), and a selective ion implantation process using one or more masking or patterning operations may be performed to implant dopants of a second conductivity type into the back surface 106b to form the collector region 130 and the drain gap 115g at a desired depth (relative to the back surface 106b), spacing, and / or dopant concentration that may differ from the field stop region 115. One or more annealing operations may also be performed, for example, for implant activation. For example, the implants in the backside doped regions (e.g., the collector region 130, the field stop region 115, and the drain gap 115g) may be activated using a laser annealing technique.

[0096] Drain gap 115g may thereby be formed in any of the configurations described above with reference to Figures 5A-6B, i.e., the width, doping level, depth, and / or density of drain gap 115g and / or surrounding regions 115 and / or 130 may be adjusted to achieve the desired device characteristics (e.g., whether the device behaves more like a MOSFET or more like an IGBT) in order to achieve the threshold current density j th (This current density threshold j thIn a device, a switching transistor (switching from predominantly unipolar to predominantly bipolar conduction) between source and drain contacts on opposite sides of a wide bandgap semiconductor drift layer may be formed using the above processes and / or other processes.

[0097] In some embodiments, relatively high temperatures (e.g., greater than 1500° C.) may be required for implant activation in WBG materials such as SiC, which may provide manufacturing complexity to avoid damaging or otherwise detrimentally affecting other components of the device. For example, one or more frontside components (such as gate structures 182 / 184 and / or source contacts 190) may be adversely affected by such higher implant activation temperatures. Thus, wafer backside pn junctions 115 / 130 / 115g may be formed in one or more distinct semiconductor layers 110″ that define heterojunctions 110 / 120 with the wide bandgap semiconductor material of drift region 120 such that implant activation can be performed at lower temperatures.

[0098] For example, as shown in Figure 11, the substrate 110' may be removed from the back surface 106b of the semiconductor layer structure 106 to expose the surface of the drift region 120, for example, using wafer backgrinding. As shown in Figure 12, a layer 110'' of a semiconductor material different from the drift region 120 (e.g., Si) may be formed on the exposed surface of the drift region 120 to define a heterojunction 110 / 120 between the semiconductor layer 110'' and the drift region 120. In some embodiments, the semiconductor layer 110'' is an amorphous Si layer formed on the back side of the SiC drift region 120 after removal of the SiC substrate 110'.

[0099] In some embodiments, the semiconductor layer 110'' may be patterned and implanted as described with reference to Figures 9 and 10 to form a field stop region 115, a collector region 130, and a drain gap 115g in the semiconductor layer 110'' to define the backside structure 110. For example, a backside annealing technique, such as laser annealing, may be performed on the backside structure 110 to activate dopants and / or recrystallize the deposited semiconductor (e.g., Si) at a relatively lower temperature (e.g., less than about 900°C) than in SiC.

[0100] In some embodiments, a semiconductor layer 110″ of a different semiconductor material (e.g., Si) may be deposited on an exposed surface of the drift region 120 to define a heterojunction 110 / 120 between the semiconductor layer 110″ and the drift region 120 by sputtering from one or more sputter targets having a desired (or “built-in”) doping. For example, a first silicon sputter target may be provided with a doping level appropriate to achieve or otherwise correspond to a desired dopant concentration of the field stop region 115. The first silicon sputter target may be sputtered to a desired thickness for the field stop region 115. A second target may be provided with a second doping level appropriate to achieve or otherwise correspond to a desired dopant concentration of the drain gap 115g and may be sputtered to a desired thickness for the drain gap 115g. The collector region 130 may be formed using one or more photolithography and implantation processes, and the drain region 185 may then be implanted to define the backside structure 110. Laser annealing may be used to crystallize the backside structure 110 and activate the doped regions 115, 115g, 130, 185. In embodiments where the semiconductor layer 110'' is sputtered in multiple passes, laser annealing may be performed multiple times, for example, once after each sputter deposition, to help achieve better crystallization and dopant incorporation in each layer or region 115, 115g of the backside structure 110.

[0101] Thus, some embodiments of the present invention may require significant backside processing, which may be commonly used in fabricating MOSFETs or IGBTs as well. Thin wafer handling techniques may be used when performing such backside photolithographic patterning, blanket and mask implants, and backside annealing.

[0102] 13A, 13B, 14A, and 14B are plan views or layout views (e.g., along the X and Y directions) of a power semiconductor device or die illustrating exemplary configurations (including exemplary configurations 110p, 110p', 110c, and 110c') of a backside structure 110 including collector region 130 and drain gap 115g according to some embodiments of the present invention integrated with a conventional MOSFET on the same die. The device includes a plurality of individual unit cell structures 100 electrically connected in parallel in an array 1000. Drain contacts 192 are not shown in FIGS. 13 and 14 to facilitate viewing of the underlying backside structure 110.

[0103] As explained above, the local configuration of the drain gap 115g and / or the separate minority carrier recombination sites 125 (e.g., at the level of the unit cell 100) determines the current density threshold j for the transition from unipolar to bipolar conduction. th The drain gap 115g may be selected to provide desired operating characteristics including resistance, on-resistance, and on-off switching speed. For example, a wider and / or more drain gap 115g may result in more MOSFET-like behavior, whereas a narrower and / or fewer drain gap 115g may result in more IGBT-like behavior. Also, more minority carrier recombination sites 125 may result in faster switching speeds, whereas fewer minority carrier recombination sites 125 may result in lower on-resistance.

[0104] In addition, the overall configuration of field effect / bipolar power devices according to embodiments of the present invention (e.g., at the device or array 1000 level) may also be varied to provide desired operating characteristics. In particular, FIGS. 13A and 13B show example layout configurations 110p and 110′ that implement conventional MOSFETs 10 in a central region of the array 1000 along with field effect / bipolar transistor devices 100 (e.g., MOS-IGBTs, also referred to herein as MOSBIPs) in a peripheral region or periphery of the array 1000. The backside structure layout configurations 110p, 110p′ of FIGS. 13A and 13B may provide improved heat dissipation compared to implementing MOS-IGBTs 100 in the central region of the array 100. However, the backside structure layout configurations 110p, 110p′ may provide increased heat in termination regions implemented at the periphery of the array 1000. In some embodiments, a heat sink may be implemented in the backside structure 100 to enhance heat distribution.

[0105] 14A and 14B show example layout configurations 110c, 110c' that implement conventional MOSFETs 10 in the peripheral region or periphery of the array 1000 along with field effect / bipolar transistor devices 100 in the central region of the array 1000. The backside structure layout configurations 110c, 110c' of FIG. 14A and 14B may limit stray bipolar carriers from extended decay in the device termination region. In some embodiments, the backside structure layout configurations 110c, 110c' may provide improved overall heat dissipation and may reduce or avoid heating of the termination region as compared to the layout configurations 110p, 110p'.

[0106] In Figures 13A and 14A, the drain gap 115g is surrounded on multiple sides by the collector region 130 to enhance control of the unipolar to bipolar transition. Although shown as a square in plan view in Figures 13A and 14A, it will be appreciated that the drain gap 115g may be defined by a rectangle, hexagon, octagon, or other polygonal or elliptical shape in plan view and may be matched to the pattern of the corresponding upper cell (i.e., at the front surface 106f). In Figures 13B and 14B, the collector region 130 is implemented as a continuous stripe with the drain gap 115g as the spacing between the stripes of the collector region 130. It will be appreciated that the implementations of Figures 13A-14B are shown by way of example only, and that variations and / or other implementations of collector region 130 and drain gap 115g may be provided to enable unipolar conduction below the current density threshold and bipolar conduction above the current density threshold in accordance with the embodiments described herein.

[0107] The embodiments of the present disclosure may include several advantages over conventional devices. For example, while some conventional devices (such as reverse conducting IGBTs) may include an n-type gap in the p+ collector region, the n-type gap may not be configured for MOSFET operation because the n-type drift region doping of a typical IGBT or RC-IGBT provides MOSFET / unipolar / majority carrier operation with low on-resistance (R dsThe n-type gap in the p+ collector region of an RC-IGBT may instead only support diode operation in reverse conduction mode, with such diode operation being an example of minority carrier conduction as in the forward conduction mode of an IGBT. In other words, a conventional RC-IGBT may not provide a unipolar mode of operation. In contrast to an IGBT or reverse conducting IGBT, embodiments of the present invention may include an epitaxially deposited drift region 120 with a doping level appropriate for a MOSFET, i.e., a higher doping level than is typically used in the lightly doped drift region of an IGBT.

[0108] Also, while some conventional devices may provide a transition from MOSFET to IGBT modes of operation, such devices generally require superjunction (charge-balanced) MOSFETs, where the drift region has multiple columns of one conductivity type with substantially equal doping to the surrounding regions of the opposite conductivity type to cancel charge in the surrounding regions under reverse bias. In contrast, embodiments of the present invention may not require charge-balanced junctions, for example, because the superior critical electric field provided by WBG materials (such as SiC) may allow for a relatively thin (and less resistive) drift region even while supporting higher voltage operation. The drift region may be "broken" at one or more intermediate locations for the fabrication of separate minority carrier recombination sites as described herein. Separate minority carrier recombination sites may allow for faster switching speeds without substantially increasing the on-resistance per unit area. Because the power semiconductor device structures described herein can switch from unipolar (e.g., MOSFET) to bipolar (e.g., IGBT) mode when high currents are required, embodiments of the present invention can supply the burst current requirements of many switching applications without the extremely high operating temperature requirements that might otherwise be required for only unipolar devices.

[0109] Thus, embodiments of the present invention may provide transistor structures that have faster switching speeds and more uniform current distribution (i.e., due to more transistor cells being switched on within a desired switching time frame), i.e., have the advantages of both field effect / voltage controlled devices and bipolar / current controlled devices. More uniform current distribution may also provide less localized transistor cell aging (due to fewer hot spots) and thus longer overall device life. Embodiments of the present invention may be used in power devices, including vertical or lateral power devices, with n-type and p-type contacts to SiC or other wide bandgap semiconductor contact regions.

[0110] It will be understood that the features of the different embodiments disclosed herein may be combined in any manner to provide many additional embodiments. Thus, it will be understood that while various features of the inventive concepts have been described herein with reference to specific examples, these features may be added to and / or substituted for example features of other embodiments to provide many additional embodiments. Thus, it will be understood that the invention encompasses these different combinations.

[0111] In the above description, each exemplary embodiment is described with respect to regions of a particular conductivity type. It will be appreciated that devices of the opposite conductivity type can be formed by simply reversing the conductivity of the n-type and p-type layers in each of the above embodiments. It will be appreciated, therefore, that the present invention covers both n-channel and p-channel for each of the different device structures.

[0112] The present invention has been described above primarily with respect to silicon carbide-based power semiconductor devices. However, it should be understood that silicon carbide is used herein as an example, and the devices described herein may be formed in any suitable wide bandgap semiconductor material system. By way of example, in any of the embodiments described above, a gallium nitride-based semiconductor material (e.g., gallium nitride, aluminum gallium nitride, etc.) may be used instead of silicon carbide. More generally, although described with respect to silicon carbide devices, embodiments of the present invention are not so limited and may have applicability to devices formed using other wide bandgap semiconductor materials, such as gallium nitride, zinc selenide, or any other II-VI or III-V wide bandgap compound semiconductor materials.

[0113]

[0023] The embodiments of the present invention are described above with reference to the accompanying drawings, in which embodiments of the invention are shown. However, it should be understood that the present invention may be embodied in many different forms and should not be construed as being limited to the embodiments set forth above. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.

[0114] As used herein, a first element (e.g., a contact, layer, or region) of a semiconductor device is "vertically overlapping" with a second element of the semiconductor device if an axis perpendicular (i.e., in the vertical direction) to a major surface of the semiconductor layer structure of the device extends through both the first element and the second element.

[0115] It should be understood that although terms such as first, second, etc. are used throughout this specification to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another element. For example, a first element can be called a second element, and similarly, a second element can be called a first element, without departing from the scope of the present invention. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0116] The terms used herein are only for the purpose of describing particular embodiments and are not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural, unless the context clearly indicates otherwise. Furthermore, it will be understood that the terms "comprises", "comprising", "includes" and / or "including" as used herein specify the presence of the mentioned features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0117] It will be understood that when an element, such as a layer, region, or substrate, is referred to as being "on" or extending "upon" another element, the element can be directly on or extending directly onto the other element, or there can be intervening elements. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, the element can be directly connected or coupled to the other element, or there can be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0118] Relative terms such as "below" or "above" or "upper" or "lower" or "top" or "bottom" may be used herein to describe the relationship of one element, layer or region to another element, layer or region as illustrated in the drawings. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation illustrated in the drawings.

[0119] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic representations of idealized embodiments (and intermediate structures) of the invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. In addition, variations from the shapes shown as a result, for example, of manufacturing techniques and / or tolerances, are expected. Embodiments of the invention are also described in terms of manufacturing operations. It should be understood that the steps shown in a manufacturing operation do not have to be performed in the order shown.

[0120] Some embodiments of the invention are described in terms of semiconductor layers and / or regions that are characterized as having a conductivity type, such as n-type or p-type, which refers to the majority carrier concentration in the layer and / or region. Thus, n-type material has a majority equilibrium concentration of negatively charged electrons, while p-type material has a majority equilibrium concentration of positively charged holes. Some materials may be designated with a "+" or "-" (as in n+, n-, p+, p-, n++, n--, p++, p--, etc.) to indicate a relatively larger ("+") or smaller ("-") concentration of majority carriers compared to another layer or region. However, such designations do not imply the presence of a particular concentration of majority or minority carriers in the layer or region.

[0121] In the drawings and specification, exemplary embodiments of the invention have been disclosed and specific terms have been employed, but these terms are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being indicated in the following claims.

Claims

1. a semiconductor layer structure including a drift region of a first conductivity type; first and second contacts on the semiconductor layer structure; Equipped with the drift region comprises a wide bandgap semiconductor material; the drift region is configured to provide unipolar conduction between the first and second contacts below a current density threshold and bipolar conduction between the first and second contacts above the current density threshold.

2. The drift region is approximately 5×10 １４ atoms / cm ３ 2. The power semiconductor device of claim 1 , comprising a concentration of dopants of a first conductivity type greater than 1000 μm and a concentration of dopants of a second conductivity type in the drift region less than that of the first conductivity type.

3. 2. The power semiconductor device of claim 1 , wherein the first and second contacts are on opposite first and second faces of the semiconductor layer structure, and the drift region further includes a plurality of distinct minority carrier recombination sites spaced from the first and second faces.

4. a gate adjacent to the first surface of the semiconductor layer structure; 4. The power semiconductor device according to claim 1 , wherein the first and second contacts comprise a source contact on the first side of the semiconductor layer structure and a drain contact on a second side of the semiconductor layer structure opposite the first side.

5. The semiconductor layer structure comprises: a collector region of a second conductivity type between the drift region and the drain contact; at least one drain gap of the first conductivity type in the collector region adjacent to the drain contact; The power semiconductor device of claim 4 , further comprising:

6. 6. The power semiconductor device of claim 5, wherein the semiconductor layer structure further comprises a field stop region of the first conductivity type between the collector region and the drift region.

7. 7. The power semiconductor device of claim 6, wherein the semiconductor layer structure further comprises a semiconductor layer between the drain contact and the drift region, the semiconductor layer defining a heterojunction with a wide bandgap semiconductor material of the drift region and including therein the field stop region, the collector region, and the at least one drain gap.

8. 8. The power semiconductor device according to claim 3, wherein the separate minority carrier recombination sites comprise a plurality of doped regions of the first and / or second conductivity type having a higher dopant concentration than the drift region.

9. 8. The power semiconductor device of claim 3, wherein the separate minority carrier recombination sites comprise defects in a crystal lattice of the drift region.

10. 10. The power semiconductor device of claim 9, wherein the separate minority carrier recombination sites comprise argon and / or hydrogen.

11. 11. The power semiconductor device according to claim 3, wherein the separate minority carrier recombination site is disposed at a depth of about 15% to about 85% of a thickness defined between the first and second sides of the semiconductor layer structure.

12. The first concentration of dopant in the drift region is about 5×10 １４ ~5×10 １７ atoms / cm ３ 12. The power semiconductor device according to claim 2, wherein:

13. a semiconductor layer structure including a drift region of a first conductivity type and a collector region of a second conductivity type; first and second contacts on opposite first and second surfaces of the semiconductor layer structure; Equipped with the collector region is between the drift region and the second surface; The drift region is approximately 5×10 １４ atoms / cm ３ a first concentration of a dopant of a first conductivity type greater than 1000 nm and a second concentration of a dopant of a second conductivity type in the drift region less than the first concentration.

14. 14. The power semiconductor device of claim 13, wherein the drift region is configured to provide unipolar conduction between the first and second contacts below a current density threshold and bipolar conduction between the first and second contacts above the current density threshold.

15. 14. The power semiconductor device of claim 13, wherein the semiconductor layer structure further comprises a field stop region of the first conductivity type between the collector region and the drift region.

16. 16. The power semiconductor device of claim 15, wherein the semiconductor layer structure further comprises at least one drain gap of the first conductivity type in the collector region.

17. 17. The power semiconductor device of claim 16, wherein the semiconductor layer structure further includes a source region of the first conductivity type and a well region of a second conductivity type adjacent the first side, and the first and second contacts include a source contact on the first side and a drain contact on the second side.

18. the drift region comprises a wide bandgap semiconductor material; 20. The power semiconductor device of claim 17, further comprising a semiconductor layer between the drain contact and the drift region, the semiconductor layer defining a heterojunction with the wide bandgap semiconductor material of the drift region and including the field stop region, the collector region, and the at least one drain gap.

19. 19. A power semiconductor device according to claim 13, wherein the drift region further comprises a plurality of separate minority carrier recombination sites spaced apart from opposite first and second faces.

20. 20. The power semiconductor device of claim 19, wherein the separate minority carrier recombination sites include a plurality of doped regions of the first and / or second conductivity type having a higher dopant concentration than the drift region.

21. 20. The power semiconductor device of claim 19, wherein the separate minority carrier recombination sites comprise defects in a crystal lattice of the drift region.

22. 22. The power semiconductor device of claim 21 , wherein the separate minority carrier recombination sites comprise argon and / or hydrogen.

23. 20. The power semiconductor device of claim 19, wherein the separate minority carrier recombination site is disposed at a depth of about 15% to about 85% of a thickness defined between the first and second sides of the semiconductor layer structure.

24. The first concentration of dopant in the drift region is about 5×10 １４ ~5×10 １７ atoms / cm ３ 24. The power semiconductor device according to claim 13, wherein:

25. a semiconductor layer structure including a drift region of a first conductivity type; first and second contacts on opposite first and second surfaces of the semiconductor layer structure, respectively; Equipped with the drift region is configured to provide majority carrier conduction between the first and second contacts and includes a plurality of distinct minority carrier recombination sites spaced from the first and second faces.

26. 26. The power semiconductor device of claim 25, wherein the semiconductor layer structure further includes a source region of the first conductivity type and a well region of a second conductivity type adjacent the first side, and the first and second contacts include a source contact on the first side and a drain contact on the second side.

27. 27. The power semiconductor device of claim 26, further comprising a gate adjacent said first surface, said minority carrier recombination site being between said gate and said drain contact.

28. 28. The power semiconductor device of claim 27, wherein the separate minority carrier recombination site is disposed at a depth of about 15% to about 85% of a thickness defined between the first and second sides of the semiconductor layer structure.

29. 29. The power semiconductor device of any one of claims 25 to 28, wherein the separate minority carrier recombination sites are laterally spaced apart from one another by a spacing of between about 0.2 μm and about 2.0 μm.

30. 30. The power semiconductor device of claim 25, wherein the separate minority carrier recombination sites comprise a plurality of doped regions of the first and / or second conductivity type having a higher dopant concentration than the drift region.

31. 30. The power semiconductor device of claim 25, wherein the separate minority carrier recombination sites comprise defects in a crystal lattice of the drift region.

32. 32. The power semiconductor device of claim 31 , wherein the separate minority carrier recombination sites comprise argon and / or hydrogen.

33. a collector region of the second conductivity between the drift region and the drain contact; a field stop region of the first conductivity type between the collector region and the drift region; at least one drain gap of the first conductivity type in the collector region adjacent to the drain contact; 33. The power semiconductor device according to any one of claims 26 to 32, further comprising:

34. 34. The power semiconductor device of claim 33, wherein the drift region comprises a wide bandgap semiconductor material.

35. 35. The power semiconductor device of claim 34, further comprising a semiconductor layer between the drain contact and the drift region, the semiconductor layer defining a heterojunction with the wide bandgap semiconductor material of the drift region and including the field stop region, the collector region, and the at least one drain gap.

36. The drift region is approximately 5×10 １４ ~5×10 １７ atoms / cm ３ 36. The power semiconductor device of claim 25, wherein the dopant concentration of the first conductivity type in the drift region is less than that of the first conductivity type.

37. 37. The power semiconductor device of claim 25, wherein the drift region is configured to provide unipolar conduction of majority carriers between the first and second contacts below a current density threshold and bipolar conduction of minority carriers and the majority carriers between the first and second contacts above the current density threshold.

38. forming a semiconductor layer structure including a drift region of a first conductivity type; forming a plurality of separate minority carrier recombination sites in the drift region; wherein the separate minority carrier recombination sites are spaced from opposite first and second sides of the semiconductor layer structure.

39. forming the semiconductor layer structure includes forming the drift region on a substrate using an epitaxial growth process such that the first surface is opposite the substrate; 40. The method of claim 38, wherein forming the separate minority carrier recombination sites comprises implanting ions into the drift region.

40. 40. The method of claim 39, wherein the implantation is from the first surface.

41. 40. The method of claim 39, wherein the implantation occurs during a break in the epitaxial growth process.

42. further comprising removing the substrate in response to completion of the epitaxial growth process; 40. The method of claim 39, wherein the implantation occurs from the second surface.

43. 43. The method of any one of claims 39 to 42, wherein the ions comprise dopants of the first and / or second conductivity type, and the implantation forms the separate minority carrier recombination sites as a plurality of doped regions having a higher dopant concentration than the drift region.

44. 43. The method of any one of claims 39 to 42, wherein the ions comprise neutral species and the implantation forms the separate minority carrier recombination sites as defects in a crystal lattice of the drift region.

45. 45. The method of any one of claims 39 to 44, wherein the implantation forms the separate minority carrier recombination site at a depth of about 15% to about 85% of a thickness defined between the first and second sides of the semiconductor layer structure.

46. Forming a semiconductor layer structure includes: forming a field stop region of the first conductivity type adjacent to the drift region; forming a collector region of the second conductivity type adjacent to the field stop region; forming at least one drain gap of said first conductivity type between portions of said collector region; 46. ​​The method of any one of claims 38 to 45, further comprising:

47. 47. The method of claim 46, wherein the at least one drain gap is configured to provide unipolar conduction between first and second contacts on opposing first and second faces of the semiconductor layer structure below a current density threshold, and a p-n junction between the collector region and the field stop region is configured to provide bipolar conduction between the first and second contacts above the current density threshold.

48. 47. The method of claim 46, wherein forming the backside structure comprises implanting ions into the second surface to form the field stop region, the collector region, and the at least one drain gap.

49. forming the backside structure removing the substrate to expose a surface of the drift region opposite the first surface; forming a semiconductor layer over a surface of the drift region, the semiconductor layer defining a heterojunction with the wide bandgap semiconductor material of the drift region; implanting ions into the semiconductor layer to form the field stop region, the collector region, and the at least one drain gap; 47. The method of claim 46, comprising:

50. The drift region is approximately 5×10 １４ ~5×10 １７ atoms / cm ３ 50. The method of claim 38, wherein the concentration of dopants of the first conductivity type in the drift region is less than that of the first conductivity type.

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