Trigger unit for clock gating based on data comparison

Abstract

The present application discloses a trigger unit for clock gating based on data comparison, the trigger unit includes an edge-triggered flip-flop and a clock gating circuit, the clock gating circuit enables or disables a first clock signal to generate a second clock signal based on a data comparison result between input data and output data, the second clock signal provides a trigger edge for the edge-triggered flip-flop, the clock gating circuit copies the first clock signal to the second clock signal in a clock cycle in which the input data is inverted, and maintains the second clock signal at a predetermined level in a clock cycle in which the input data is unchanged, the trigger unit enables the clock inversion of the edge-triggered flip-flop only in a clock cycle in which the input data is inverted, thereby improving circuit performance and reducing power consumption.

Description

[Technical field]

[0001] This application claims priority to a Chinese patent application bearing application number 202210107334.3 and entitled "Trigger Unit for Clock Gating Based on Data Comparison" filed on January 28, 2022, and hereby incorporates by reference all of the specification, claims, accompanying drawings and abstract of the above-mentioned Chinese patent application.

[0002] The present invention relates to the art of integrated circuits, and more particularly to a trigger unit for clock gating based on data comparison. [Background technology]

[0003] Electronic design automation software (EDA) is an important tool for the processes of functional design, integration, verification, physical design, etc. of integrated circuits. In digital circuit design EDA, standard unit libraries are a fundamental part of the back-end design process of integrated circuit chips. Using pre-designed optimized library units, automatic logic integration and layout routing can be performed to enhance design efficiency. Through optimized library units, circuit performance can be improved and power consumption can be reduced.

[0004] In the digital part of an integrated circuit, a gate circuit is used to perform combinational logic on multiple signals to generate a logical operation result, and an edge-triggered flip-flop is used to store the logical operation result. According to the difference in logical operation, the gate circuit can be divided into AND gate, OR gate, NOT gate, NAND gate, ANDOR gate, XOR gate, etc. The logical operation result of the gate circuit is, for example, a pulse signal, and a steady level signal according to the logical state is generated based on this pulse signal.

[0005] An edge-triggered flip-flop is an information storage device with a memory function, and is used to store the result of a memory logic operation. For example, an edge-triggered flip-flop is the most basic logic unit that constitutes various sequence digital circuit modules, and is an important unit circuit in a digital circuit module. Referring to FIG. 1 and FIG. 2, depending on the type of edge-triggered flip-flop, the edge-triggered flip-flop 110 is triggered by the rising edge or the falling edge of a clock signal, allowing the input data to be transmitted from the input end to the output end to obtain the output data. The edge-triggered flip-flop 110 is, for example, a D-type flip-flop. For example, the D-type flip-flop transmits data at the trigger edge of the clock signal and holds the data unchanged until the next trigger edge.

[0006] The power consumption of an edge-triggered flip-flop can be divided into static power consumption and dynamic power consumption. The static power consumption is mainly caused by leakage current, and the dynamic power consumption is mainly caused by power consumption due to signal inversion. The inversion of the data signal of the edge-triggered flip-flop causes additional data power consumption in the downstream combinational logic, and the inversion of the clock signal also causes clock power consumption of the edge-triggered flip-flop itself. Therefore, it is necessary to optimize the design of edge-triggered flip-flops in the digital circuit EDA standard unit library, and it is expected to further reduce the dynamic power consumption of edge-triggered flip-flops. Summary of the Invention

[0007] In view of the above problems, an object of the present invention is to provide a trigger unit for clock gating based on data comparison, which enables clock inversion of edge-triggered flip-flops only in clock cycles where the input data inverts, thereby improving circuit performance and reducing power consumption.

[0008] According to the present invention, a trigger unit is provided, the trigger unit including an edge-triggered flip-flop including a data input end, a clock input end and a first data output end, and a clock gating circuit including a first input end, a second input end, a clock input end and an output end, the first input end of the clock gating circuit receives input data of the edge-triggered flip-flop, the second input end receives output data of the edge-triggered flip-flop, the clock input end receives a first clock signal, and the output end is coupled to the clock input end of the edge-triggered flip-flop to provide a second clock signal, the clock gating circuit enables or disables the first clock signal to generate the second clock signal based on a data comparison result between the input data and the output data, the second clock signal provides a trigger edge of the edge-triggered flip-flop, in a clock cycle in which the input data is inverted, the clock gating circuit copies the first clock signal to the second clock signal, and in a clock cycle in which the input data is unchanged, the clock gating circuit maintains the second clock signal at a predetermined level.

[0009] Preferably, a clock cycle of the first clock signal includes successive first and second level stages, and the input data is inverted at the first level stage of the first clock signal.

[0010] Preferably, the predetermined level is the level of the first level stage, and the second clock signal provides a trigger edge in a clock cycle following a clock cycle in which the input data is inverted.

[0011] Preferably, the starting edge of the first level step is a rising edge.

[0012] Preferably, the clock gating circuit includes an XOR gate including a first input terminal, a second input terminal and an output terminal, where the first input terminal and the second input terminal receive the input data and the output data of the edge triggered flip-flop, respectively, and the output terminal provides a first clock control signal; an OR gate including a first input terminal, a second input terminal and an output terminal for receiving the first clock signal; and a NOT gate including an input terminal and an output terminal and connected between the output terminal of the XOR gate and the second input terminal of the OR gate, where the NOT gate inverts the first clock control signal and provides it to the second input terminal of the OR gate, and the output terminal of the OR gate provides the second clock signal.

[0013] Preferably, the OR gate further includes a third input terminal for receiving an inverted signal of the second clock control signal.

[0014] Preferably, when the second clock control signal is valid, the clock gating circuit enables a data comparison function, and when the second clock control signal is invalid, the clock gating circuit disables the data comparison function.

[0015] Preferably, the starting edge of the first level step is a falling edge.

[0016] Preferably, the clock gating circuit includes an XOR gate having a first input terminal, a second input terminal and an output terminal, where the first input terminal and the second input terminal receive the input data and the output data of the edge triggered flip-flop, respectively, and the output terminal provides a first clock control signal, and an AND gate having a first input terminal, a second input terminal and an output terminal, where the first input terminal receives the first clock signal, the second input terminal receives the first clock control signal, and the output terminal provides the second clock signal.

[0017] Preferably, the AND gate further includes a third input terminal for receiving a second clock control signal.

[0018] Preferably, when the second clock control signal is valid, the clock gating circuit enables a data comparison function, and when the second clock control signal is invalid, the clock gating circuit disables the data comparison function.

[0019] Preferably, the data input terminal of the edge trigger flip-flop receives an inverted signal of its own output data as input data.

[0020] Preferably, the edge-triggered flip-flop further includes a second data output end, the first data output end and the second data output end of the edge-triggered flip-flop respectively provide the output data and the inverted signal of the output data of the edge-triggered flip-flop, and the data input end and the second data output end of the edge-triggered flip-flop are coupled to each other and receive the inverted signal of its own output data.

[0021] Preferably, a high level of each of the first clock control signal and the second clock control signal indicates a valid state, and a low level of each of the first clock control signal and the second clock control signal indicates an invalid state.

[0022] Preferably, the edge triggered flip-flop receives input data from the data input terminal at the trigger edge and transmits the input data to the first data output terminal.

[0023] According to an embodiment of the present invention, in the trigger unit, the clock gating circuit copies a first clock signal to a second clock signal in a clock cycle in which the input data is inverted, and maintains the second clock signal at a predetermined level in a clock cycle in which the input data is unchanged. Thus, the clock gating circuit enables the transmission of a clock signal only in one clock cycle in which the input data of the edge-triggered flip-flop is inverted, thereby minimizing the dynamic power consumption of the edge-triggered flip-flop due to clock inversion. Furthermore, the clock gating circuit provides a trigger edge only in the next clock cycle in which the input data of the edge-triggered flip-flop is inverted, thereby minimizing the dynamic power consumption of the edge-triggered flip-flop due to data transmission.

[0024] Furthermore, edge-triggered flip-flops prevent data from entering downstream digital circuitry during most clock cycles in which the input data does not change, avoiding additional data power consumption due to inversion of the data signal in downstream combinational logic.

[0025] In the trigger unit, by utilizing the circuit performance of the clock gating circuit in the cycle in which the clock control signal is inverted, even though the clock gating circuit does not have an additional latch, the clock signal glitch generated by the clock gating circuit is eliminated, the number of logic elements in the clock gating circuit is reduced, and the power consumption of the clock gating circuit is reduced. Because the operating power consumption of the clock gating circuit itself is low, the increase in power consumption due to the power consumption of the clock gating circuit itself is much smaller than the reduction in power consumption of the edge trigger flip-flop due to clock gating.

[0026] Furthermore, any number of edge-triggered flip-flops in a trigger unit can form a flip-flop group that shares a clock gating circuit, and the trigger unit can always achieve reduced power consumption when the flip-flop group includes any number of edge-triggered flip-flops, for example, one, two, or more.

[0027] Furthermore, in the design of the digital circuit, the minimum delay and maximum delay of the signal delay of the input data of the edge-triggered flip-flop are set to the first level stage of the clock signal, thereby preventing the edge-triggered flip-flop from operating normally due to glitches appearing in the clock signal of the edge-triggered flip-flop.Even if the circuit design of the clock gating circuit in the trigger unit is simplified, the clock inversion and data transmission of the edge-triggered flip-flop can be reliably disabled to reduce dynamic power consumption.

[0028] Furthermore, the trigger unit simplifies circuit design, reduces layout area, and can be used as a library unit in a standard cell library together with conventional edge-triggered flip-flop designs and applied under various conditions to improve the performance and design efficiency of digital circuits.

[0029] In a preferred embodiment, the data input terminal of the edge triggered flip-flop receives the inverted signal of its own output data as input data. The edge triggered flip-flop includes a first data output terminal and a second data output terminal, respectively providing the output data of the edge triggered flip-flop and the inverted signal of the output data, and the data input terminal of the edge triggered flip-flop and the second data output terminal are coupled to each other. On the one hand, the logic circuit of the previous stage does not need to provide input data to the edge triggered flip-flop of the trigger unit, but only needs to provide input data to the clock gating circuit of the trigger unit, so that the load pressure of the logic circuit of the previous stage can be reduced. On the other hand, the edge triggered flip-flop does not need to receive input data from the outside, so that the adverse effect of the signal delay fluctuation of the external input data on the operation stability of the edge triggered flip-flop can be reduced. Hereinafter, embodiments of the present invention will be described with reference to the drawings, whereby the above and other objects, features and advantages of the present invention will become more apparent. [Brief description of the drawings]

[0030] [Figure 1] FIG. 1 shows a schematic circuit diagram of an edge-triggered flip-flop in an integrated circuit. [Diagram 2] FIG. 2 shows a waveform diagram of an edge-triggered flip-flop in an integrated circuit. [Diagram 3] FIG. 3 shows a schematic circuit diagram of a trigger unit according to the prior art. [Figure 4] FIG. 4 shows a schematic circuit diagram of another trigger unit according to the prior art. [Diagram 5] FIG. 5 shows a schematic circuit diagram of a clock gating circuit in the trigger unit shown in FIG. [Figure 6] FIG. 6 shows a waveform diagram of the clock gating circuit in the trigger unit shown in FIG. [Figure 7] FIG. 7 shows a schematic circuit diagram of a trigger unit according to a first embodiment of the present invention. [Figure 8]FIG. 8 shows a schematic circuit diagram of a clock gating circuit in the trigger unit shown in FIG. [Figure 9] FIG. 9 shows a schematic circuit diagram of another clock gating circuit in the trigger unit shown in FIG. [Figure 10] FIG. 10 shows a waveform diagram of the clock gating circuit shown in FIG. [Figure 11] FIG. 11 shows a waveform diagram of the clock gating circuit shown in FIG. [Figure 12] FIG. 12 shows a schematic circuit diagram of a trigger unit according to a second embodiment of the present invention. [Figure 13] FIG. 13 shows a schematic circuit diagram of a clock gating circuit in the trigger unit shown in FIG. [Figure 14] FIG. 14 shows a schematic circuit diagram of a trigger unit according to a third embodiment of the present invention. [Figure 15] FIG. 15 shows a schematic circuit diagram of a clock gating circuit in the trigger unit shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] The present invention will now be described in more detail with reference to the accompanying drawings, in which like elements are designated by similar reference numerals in the various drawings, and in which, for clarity, parts of the drawings are not drawn to scale, and some well-known components may not be shown.

[0032] In order to provide a clearer understanding of the present invention, numerous specific details of the invention are set forth below, such as device structures, materials, dimensions, processing and techniques, etc. However, as will be appreciated by those skilled in the art, the present invention may be practiced without these specific details.

[0033] The present invention can be embodied in various forms, some examples of which are described below: For convenience of explanation, the following embodiment description takes an edge-triggered flip-flop triggered by a rising edge as an example.

[0034] 3 shows a schematic circuit diagram of a trigger unit according to the prior art. The trigger unit 100 includes an edge-triggered flip-flop 110 and a data selector 120. The data selector 120 is used for gating the input data Di of the edge-triggered flip-flop 110. In this embodiment, the edge-triggered flip-flop 110 is, for example, a D-type flip-flop.

[0035] The edge-triggered flip-flop 110 includes a data input end, a data output end, and a clock input end. The data selector 120 includes a control terminal, a first data input end, a second data input end, and an output end. The control terminal of the data selector 120 receives a data control signal EN, the first data input end receives the input data Di of the edge-triggered flip-flop 110, the second data input end receives the output data Do of the edge-triggered flip-flop 120, and the output end provides the selected data Ds. The data input end of the edge-triggered flip-flop 110 receives the selected data Ds, the clock input end receives the clock signal CLK, and the data output end provides the output data Do.

[0036] At a trigger edge, such as a rising edge, of the clock signal CLK, the edge-triggered flip-flop 110 transfers the input data from the data input to the data output. Therefore, the signal level corresponding to the output data of the edge-triggered flip-flop 110 depends on the signal level of the input data at the data input before the rising edge of the clock signal CLK arrives, and does not change in the clock cycle after the rising edge of the clock signal CLK. The data output of the edge-triggered flip-flop 110 can include two complementary outputs.

[0037] When the data control signal EN is valid, the data selector 120 provides the input data Di to the input terminal of the edge triggered flip-flop 110, and when the data control signal EN is invalid, the data selector 120 connects the first input terminal and the output terminal of the edge triggered flip-flop 110 to each other and masks the input data of the edge triggered flip-flop 110. The data selector 120 can disable the edge triggered flip-flop 110 from receiving data so as to keep the output data of the edge triggered flip-flop 110 unchanged.

[0038] In the above-mentioned trigger unit, the data selector 120 controls the data reception of the edge-triggered flip-flop 110 according to the state of the data control signal EN.

[0039] When the data selector 120 disables the edge-triggered flip-flop 110 from receiving data, the edge-triggered flip-flop 110 can no longer receive input data but keeps its output data unchanged, thereby preventing the input data from entering downstream digital circuits and avoiding additional data power consumption due to inversion of the data signal in the downstream combinational logic.

[0040] However, the data selector 120 cannot disable the clock inversion of the edge-triggered flip-flop 110. The clock input of the edge-triggered flip-flop 110 always receives the clock signal CLK. Since data is transmitted at the trigger edge of the clock signal CLK, the dynamic power consumption of the edge-triggered flip-flop 110 due to the inversion of the clock signal CLK cannot be reduced.

[0041] 4 shows a schematic circuit diagram of another trigger unit according to the prior art. The trigger unit 200 includes an edge-triggered flip-flop 110 and a clock gating circuit 130. The clock gating circuit 130 is used to gate the clock signal CK of the edge-triggered flip-flop 110. In this embodiment, the edge-triggered flip-flop 110 is, for example, a D-type flip-flop.

[0042] The edge-triggered flip-flop 110 includes a data input end, a data output end, and a clock input end. The clock gating circuit 130 includes an input end, an output end, and a control terminal. The input end of the clock gating circuit 130 receives a clock signal CLK, the output end provides a clock signal CK, and the control terminal receives a clock control signal EN. The data input end of the edge-triggered flip-flop 110 receives input data Di, the clock input end receives the clock signal CK, and the data output end provides output data Do.

[0043] At a trigger edge, such as a rising edge, of the clock signal CK, the edge-triggered flip-flop 110 transmits the input data from the data input to the data output. Therefore, the signal level corresponding to the output data of the data output of the edge-triggered flip-flop 110 depends on the signal level of the input data at the data input before the trigger edge of the clock signal CK arrives, and does not change in the clock cycle after the trigger edge of the clock signal CK. The data output of the edge-triggered flip-flop 110 can include two complementary outputs.

[0044] The clock gating circuit 130 performs a combinational logic operation on the input data Di, the output data Do, and the clock signal CLK to generate the clock signal CK for the edge-triggered flip-flop 110 .

[0045] In the trigger unit, a clock gating circuit 130 controls the transmission of a clock signal according to the state of a clock control signal EN.

[0046] In clock cycles in which the clock control signal EN remains in an enabled state, the clock gating circuit 130 copies the clock signal CLK to the clock signal CK and provides the clock signal CK to the clock input terminal of the edge-triggered flip-flop 110, and in clock cycles in which the clock control signal EN remains in an disabled state, the clock gating circuit 130 disables the clock signal CLK and maintains the clock signal CK at a predetermined level.

[0047] When the clock signal CK is maintained at a predetermined level, the clock signal CK cannot provide a trigger edge for the edge-triggered flip-flop 110, and thus can disable the clock inversion and data transmission of the edge-triggered flip-flop 110. Thus, the dynamic power consumption of the edge-triggered flip-flop 110 due to the inversion of the clock signal CK and the dynamic power consumption due to the data transmission can be reduced. Furthermore, the edge-triggered flip-flop 110 can prevent data from entering the downstream digital circuit, thereby avoiding additional data power consumption due to the inversion of the data signal of the downstream combinational logic.

[0048] Figure 5 shows a schematic circuit diagram of the clock gating circuit in the trigger unit shown in Figure 4. Referring to Figure 4, the clock gating circuit 130 and the edge triggered flip-flop 110 together form a trigger unit, and the clock gating circuit 130 provides a clock signal CK to the edge triggered flip-flop 110.

[0049] The clock gating circuit 130 includes a latch 131 and an AND gate 132. The latch 131 latches the clock control signal EN at a first level stage T1 of the clock signal CLK and transmits the clock control signal EN at a second level stage T2 of the clock signal CLK, and the AND gate performs a logical AND operation on the latch signal EN_a and the clock signal CLK to generate a clock signal CK.

[0050] The latch 131 includes a first input end, a second input end, and an output end. The AND gate 132 includes a first input end, a second input end, and an output end. The first input end of the latch 131 receives the clock signal CLK, and the second input end receives the clock control signal EN. The first input end of the AND gate 132 receives the clock signal CLK, the second input end is connected to the output end of the latch 131, and the output end provides the clock signal CK.

[0051] Taking an edge-triggered flip-flop triggered by a rising edge as an example, the clock control signal EN is described with a high level indicating an active state and a low level indicating an inactive state. Each clock cycle of the clock signal CLK includes a first level stage T1 and a second level stage T2 having a high level and a low level, respectively, between adjacent rising edges. The clock signal CK provides a trigger edge for the edge-triggered flip-flop 110, and the edge-triggered flip-flop 110 transfers input data from the input end to the output end at the trigger edge.

[0052] 6, the input data Di and the clock control signal EN each have a signal delay Td relative to the edge of the clock signal. The areas between the minimum delay Tdmin and the maximum delay Tdmax of the signal delay Td are represented by the shaded areas. The signal delay Td of the clock control signal EN varies between the minimum delay Tdmin and the maximum delay Tdmax.

[0053] As shown in FIG. 6, the minimum delay Tdmin and the maximum delay Tdmax are in the first level stage T1 and the second level stage T2, respectively, and the inversion operation of the clock control signal EN may occur in the first level stage T1 of the clock signal CLK and may also occur in the second level stage T2 of the clock signal CLK.

[0054] At time t0, the clock signal CLK reaches the first rising edge and the clock control signal EN is valid. In the clock cycle starting at time t0, the clock control signal EN flips from an valid state to an invalid state. At the first level stage T1 of the clock signal CLK, the signal level of the latch signal EN_a at the output end of the latch 131 maintains its previous state, i.e., a high level. At the second level stage T2 of the clock signal CLK, the latch 131 transmits the clock control signal EN from the input end to the output end.

[0055] When the signal delay Td of the clock control signal EN is less than or equal to the first level step T1 of the clock signal CLK, the latch signal EN_a is a copy version of the clock signal CLK in the clock cycle in which the clock control signal is inverted. When the signal delay Td of the clock control signal EN is greater than the first level step T1 of the clock signal CLK, a glitch appears in the latch signal EN_a in the second level step T2 of the clock signal CLK. The clock signal CK is the AND operation result of the clock signal CLK and the latch signal EN_a, which can eliminate the glitch of the latch signal EN_a in the second level step T2 of the clock signal CLK.

[0056] Therefore, in the clock cycle starting from time t0, the clock gating circuit 130 copies the clock signal CLK to the clock signal CK and provides the rising edge of the clock signal CK. The signal level of the output data Do of the edge-triggered flip-flop 110 matches the signal level of the input data Di at time t0, for example, the low level shown in FIG.

[0057] At time t1, the clock signal CLK reaches a second rising edge and the clock control signal EN is invalid. In the clock cycle starting from time t1, the clock control signal EN maintains the invalid state. In the first level stage T1 of the clock signal CLK, the signal level of the latch signal EN_a at the output end of the latch 131 maintains the previous state, i.e., the low level. In the second level stage T2 of the clock signal CLK, the latch 131 transmits the clock control signal EN from the input end to the output end. In this clock cycle, since the clock control signal EN maintains the low level state, EN_a also maintains the low level, and the clock signal CK maintains the low level through the product operation of the clock signal CLK and the latch signal EN_a.

[0058] At time t2, the clock signal CLK reaches the third rising edge, and the clock control signal EN is invalid. In the clock cycle starting from time t2, the clock control signal EN inverts from the invalid state to the valid state. In the first level step T1 of the clock signal CLK, the signal level of the latch signal EN_a at the output end of the latch 131 maintains its previous state, i.e., low level. In the second level step T2 of the clock signal CLK, the latch 131 transmits the clock control signal EN from the input end to the output end. If the signal delay Td of the clock control signal EN is less than or equal to the first level step T1 of the clock signal CLK, in the clock cycle in which the clock control signal inverts, the latch signal EN_a is a copy version of the clock signal CLK. If the signal delay Td of the clock control signal EN is greater than the first level step T1 of the clock signal CLK, a glitch appears in the latch signal EN_a in the second level step T2 of the clock signal CLK. The clock signal CK is a logical AND operation result of the clock signal CLK and the latch signal EN_a, and the logical AND operation can eliminate the glitch of the latch signal EN_a at the second level stage T2 of the clock signal CLK.

[0059] Therefore, in the two clock cycles starting from time t1, the clock gating circuit 130 disables the clock signal CLK and does not provide a rising edge of the clock signal CK, and the signal level of the output data Do of the edge-triggered flip-flop 110 matches the signal level of the previous clock cycle, for example, a low level as shown in FIG. 6.

[0060] At time t3, the clock signal CLK reaches the fourth rising edge, and the clock control signal EN is valid. In the clock cycle starting from time t3, the clock control signal EN maintains the valid state. In the first level stage T1 of the clock signal CLK, the signal level of the latch signal EN_a at the output end of the latch 131 maintains the previous state, i.e., high level. In the second level stage T2 of the clock signal CLK, the latch 131 transmits the clock control signal EN from the input end to the output end. In this clock cycle, the clock control signal EN maintains the high level state, therefore the latch signal EN_a also maintains the high level, and the clock signal CK is a copy version of the clock signal CLK through a multiplication operation of the clock signal CLK and the latch signal EN_a, therefore the clock signal CK is a copy version of the clock signal CLK.

[0061] Therefore, in the clock cycle starting from time t3, the clock gating circuit 130 copies the clock signal CLK to the clock signal CK and provides the rising edge of the clock signal CK. The signal level of the output data Do of the edge-triggered flip-flop 110 matches the signal level of the input data Di at time t3, for example, the high level shown in FIG.

[0062] The above-mentioned clock gating circuit 130 controls the transmission of the clock signal according to the state of the clock control signal EN.

[0063] In the clock cycle when the clock control signal EN flips from an active state to an inactive state, the clock gating circuit 130 copies the clock signal CLK to the clock signal CK. At this time, the clock signal CK provides a trigger edge for the edge-triggered flip-flop 110. The clock gating circuit 130 enables clock inversion and data transmission for the edge-triggered flip-flop 110. The output data Do 110 provided by the edge-triggered flip-flop 110 is the input data Di of the current trigger edge.

[0064] In a clock cycle in which the clock control signal EN is inverted from an invalid state to an valid state, the clock gating circuit 130 disables the clock signal CLK and maintains the clock signal CK at a predetermined level. At this time, the clock signal CK cannot provide a trigger edge for the edge-triggered flip-flop 110, and the clock gating circuit 130 disables the clock inversion and data transmission of the edge-triggered flip-flop 110. The edge-triggered flip-flop 110 holds the input data Di of the previous trigger edge, so that the dynamic power consumption of the edge-triggered flip-flop 110 can be reduced.

[0065] The above-mentioned clock gating circuit 130 does not have high timing requirements for the clock control signal EN. If it is desired to disable data transmission at a predetermined time, the clock control signal EN can be inverted from an active state to an inactive state in the last complete clock cycle before the predetermined time, and the clock control signal EN can be inverted from an inactive state to an active state in the last clock cycle starting from the predetermined time.

[0066] The inventors have noted that the trigger unit provided in the standard cell library of the digital circuit EDA uses the above-mentioned clock gating circuit 130. The clock gating circuit 130 includes a latch 131 for removing glitches that may appear in the clock signal CK of the edge trigger flip-flop 110.

[0067] However, since a lot of hardware logic is used in the latch 131, the operation power consumption of the clock gating circuit 130 itself becomes too high. The operation power consumption of the clock gating circuit 130 itself may even exceed the power consumption of the edge triggered flip-flops reduced by clock gating. In the trigger unit, the clock gating circuit 130 can provide a clock signal CK to multiple edge triggered flip-flops 110 in a flip-flop group. When using the clock gating circuit 130, the circuit design restriction is that the number of edge triggered flip-flops in the flip-flop group is 3 to 8 or more, so that the operation power consumption of the clock gating circuit 130 itself in the trigger unit 200 can be reliably smaller than the power consumption of some edge triggered flip-flops 110 reduced by the clock gating circuit 130.

[0068] Furthermore, the inventors note that the signal delay of the input data of the edge-triggered flip-flop 110 can be set by design so that both are located at the same level stage of the clock signal CLK. Based on the comparison of the input data and the output data of the edge-triggered flip-flop 110, a corresponding delayed clock control signal EN_a can be obtained.

[0069] The inventors have designed clock gating circuits 330 and 430 based on data comparison, which will be described in detail below, and by combining the clock control signal EN obtained based on the data comparison with a redesigned logic circuit, it is possible to obtain the same functionality as the clock gating circuit 130 without using latches.

[0070] In the standard cell library of the digital circuit EDA, the clock gating circuit 330 and the clock gating circuit 430 can be used in the redesigned trigger unit. Therefore, the power consumption of the integrated circuit can be further reduced, the cost of the trigger unit can be reduced, and the power consumption of the clock gating circuit itself can be reduced, so as to break through the limitations of the above circuit design.

[0071] 7 shows a schematic circuit diagram of a trigger unit according to a first embodiment of the present invention. The trigger unit 300 includes an edge-triggered flip-flop 110 and a clock gating circuit 330. The clock gating circuit 330 is used to gate the clock signal CK of the edge-triggered flip-flop 110. In this embodiment, the edge-triggered flip-flop 110 is, for example, a D-type flip-flop.

[0072] The edge-triggered flip-flop 110 includes a data input end, a data output end, and a clock input end. The clock gating circuit 330 includes a first input end, a second input end, a clock input end, and a clock output end. The first input end of the clock gating circuit 330 receives input data Di, the second input end receives output data Do, the clock input end receives a clock signal CLK, and the clock output end provides a clock signal CK. The data input end of the edge-triggered flip-flop 110 receives the input data Di, the clock input end receives the clock signal CK, and the data output end provides output data Do.

[0073] At a trigger edge, such as a rising edge, of the clock signal CK, the edge-triggered flip-flop 110 transmits the input data from the data input to the data output. Therefore, the signal level corresponding to the output data of the data output of the edge-triggered flip-flop 110 depends on the signal level of the input data at the data input before the trigger edge of the clock signal CK arrives, and does not change in the clock cycle after the trigger edge of the clock signal CK. The data output of the edge-triggered flip-flop 110 can include two complementary outputs.

[0074] The clock gating circuit 330 performs a combinational logic operation on the input data Di, the output data Do, and the clock signal CLK to generate the clock signal CK for the edge-triggered flip-flop 110 .

[0075] The above-mentioned clock gating circuit 330 generates a clock control signal EN_a based on a data comparison between the input data Di and the output data Do of the edge trigger flip-flop 110, and controls the transmission of the clock signal according to the state of the clock control signal EN_a.

[0076] In clock cycles in which the input data Di is kept unchanged, the clock gating circuit 330 maintains the clock signal CK at a predetermined level. In clock cycles in which the input data Di is inverted, the clock gating circuit 330 copies the clock signal CLK to the clock signal CK. Thus, the clock gating circuit 330 enables the transmission of the clock signal CLK only in clock cycles in which the input data Di of the edge-triggered flip-flop 110 is inverted, thereby minimizing the dynamic power consumption of the edge-triggered flip-flop 110 due to the inversion of the clock signal CK. Furthermore, the clock gating circuit 330 provides a trigger edge only in the next clock cycle in which the input data Di of the edge-triggered flip-flop 110 is inverted, thereby minimizing the dynamic power consumption of the edge-triggered flip-flop 110 due to data transmission.

[0077] Furthermore, the edge-triggered flip-flop 110 prevents data from entering downstream digital circuitry during most clock cycles in which the input data Di does not change, thereby avoiding additional data power consumption due to inversion of the data signal in the downstream combinational logic.

[0078] Figure 8 shows a schematic circuit diagram of the clock gating circuit in the trigger unit shown in Figure 7. Referring to Figure 7, the clock gating circuit 330 and the edge triggered flip-flop 110 together constitute the trigger unit, and the clock gating circuit 330 provides a clock signal CK to the edge triggered flip-flop 110.

[0079] The clock gating circuit 330 includes an XOR gate 331, a NOT gate 332, and an OR gate 333. In the clock gating circuit 330, a clock control signal EN_a is generated based on a comparison between the input data Di and the output data Do of the edge triggered flip-flop 110. The clock signal CK is a result of a logical OR operation between the clock signal CLK and an inverted signal EN_b of the clock control signal EN_a.

[0080] The XOR gate 331 includes a first input terminal, a second input terminal, and an output terminal. The NOT gate 332 includes an input terminal and an output terminal. The OR gate 333 includes a first input terminal, a second input terminal, and an output terminal. The first data input terminal of the XOR gate 331 receives the input data Di of the edge-triggered flip-flop 110, the second data input terminal receives the output data Do of the edge-triggered flip-flop 110, and the output terminal provides the clock control signal EN_a. The NOT gate 332 is connected between the output terminal of the XOR gate 331 and the second input terminal of the OR gate 331, and is used to generate an inverted signal EN_b of the clock control signal EN_a. The first input terminal of the OR gate 333 receives the clock signal CLK. The second input terminal of the OR gate 333 receives the inverted signal EN_b of the clock control signal EN_a through the NOT gate 332. The output terminal of the OR gate 333 provides the clock signal CK.

[0081] In this embodiment, an edge-triggered flip-flop triggered by a rising edge is taken as an example, and the clock control signal EN is described with a high level indicating an effective state and a low level indicating an ineffective state. Each clock cycle of the clock signal CLK includes a first level stage T1 and a second level stage T2 having a high level and a low level, respectively, between adjacent rising edges. The clock signal CK provides a rising edge as the trigger edge of the edge-triggered flip-flop 110, and the edge-triggered flip-flop 110 transmits the input data from the input end to the output end at the trigger edge.

[0082] 10, the input data Di of the edge-triggered flip-flop 110 has a signal delay Td with respect to an edge of the clock signal. The areas between the minimum delay Tdmin and the maximum delay Tdmax of the signal delay Td are represented by the shaded areas. The signal delay Td of the input data Di of the edge-triggered flip-flop 110 varies between the minimum delay Tdmin and the maximum delay Tdmax.

[0083] In this embodiment, the clock control signal EN_a of the clock gating circuit is obtained based on data comparison between the input data Di and the output data Do of the edge trigger flip-flop 110. The signal delay Td of the clock control signal EN_a is approximately the same as the signal delay Td of the input data Di.

[0084] Using the optimized circuit design and circuit simulation, the signal delay Td of the input data Di of the edge-triggered flip-flop 110 can be calculated and set so that the range of the minimum delay Tdmin and maximum delay Tdmax of the signal delay Td is within the selected first level step T1 of the clock signal CLK.

[0085] Correspondingly, the range between the minimum delay Tdmin and the maximum delay Tdmax of the signal delay Td of the clock control signal EN_a is in the first level stage T1 of the clock signal CLK. The inversion operation of the clock control signal EN_a can only occur in the first level stage T1 of the clock signal CLK. The starting edge of the first level stage T1 is a rising edge.

[0086] At time t0, the clock signal CLK reaches the first rising edge, and the clock signal CK maintains the high level of the previous clock cycle.

[0087] The clock control signal EN_a is a result of an exclusive-OR operation between the input data Di and the output data Do of the edge-triggered flip-flop 110. In a clock cycle starting from time t0, the signal level of the input data Di of the edge-triggered flip-flop 110 inverts from a low level to a high level after a signal delay Td, and the signal level of the output data Do is always at a low level throughout the entire clock cycle. As a result of the exclusive-OR operation, the clock control signal EN_a inverts from a low level to a high level via a signal delay Td, and the inverted signal EN_b of the clock control signal EN_a inverts from a high level to a low level via a signal delay Td.

[0088] The clock signal CK is a logical OR operation result of the inverted signal EN_b of the clock control signal EN_a and the clock signal CLK. In the clock cycle starting from time t0, the clock signal CK is a copy version of the clock signal CLK. The inverted signal EN_b of the clock control signal EN_a has a signal delay Td, but the signal delay Td is at the first level stage T1 of the clock signal CLK, and the combinational logic operation can remove the glitch that may occur in the clock signal CK due to the signal delay Td.

[0089] Therefore, in the clock cycle starting from time t0, the clock gating circuit 330 copies the clock signal CLK to the clock signal CK. Because the level state of the clock signal CK in the previous clock cycle is high level, the clock signal CK cannot provide a trigger edge, i.e., a rising edge, of the edge-triggered flip-flop 110. The signal level of the output data Do of the edge-triggered flip-flop 110 matches the signal level of the input data Di of the previous trigger edge of the clock signal CK, and is, for example, a low level as shown in FIG.

[0090] At time t1, the clock signal CLK reaches a second rising edge, and the clock signal CK inverts from the low level in the second level step of the previous clock cycle to a high level.

[0091] The clock control signal EN_a is a result of an exclusive-OR operation between the input data Di and the output data Do of the edge-triggered flip-flop 110. In a clock cycle starting from time t1, the signal level of the input data Di is maintained at a high level, and the signal level of the output data Do is always at a high level. As a result of the exclusive-OR operation, the clock control signal EN_a is inverted from a high level to a low level at time t1 and is always at a low level in the clock cycle starting from time t1, and the inverted signal EN_b of the clock control signal EN_a is always at a high level in the clock cycle starting from time t1.

[0092] The clock signal CK is a result of a logical OR operation between the inverted signal EN_b of the clock control signal EN_a and the clock signal CLK. Therefore, at time t1, the clock signal CK inverts from low level to high level and maintains the high level in the clock cycle starting from time t1.

[0093] Therefore, in the clock cycle starting from time t1, the clock gating circuit 330 maintains the clock signal CK at a high level. Because the level state of the second level stage of the previous clock cycle of the clock signal CK is a low level, the clock signal CK provides a trigger edge, i.e., a rising edge, of the edge-triggered flip-flop 110. The signal level of the output data Do of the edge-triggered flip-flop 110 matches the signal level of the input data Di of the trigger edge of the current clock cycle of the clock signal CK, for example, a high level as shown in FIG.

[0094] At time t2, the clock signal CLK reaches the third rising edge, and the clock signal CK maintains the high level of the previous clock cycle.

[0095] The clock control signal EN_a is a result of an exclusive-OR operation between the input data Di and the output data Do of the edge-triggered flip-flop 110. In the entire clock cycle starting from time t2, the signal level of the input data Di of the edge-triggered flip-flop 110 inverts from a high level to a low level after a signal delay Td, and the signal level of the output data Do is always at a high level throughout the entire clock cycle. As a result of the exclusive-OR operation, the clock control signal EN_a inverts from a low level to a high level via a signal delay Td, and the inverted signal EN_b of the clock control signal EN_a inverts from a high level to a low level via a signal delay Td.

[0096] The clock signal CK is the logical OR result of the inverted signal EN_b of the clock control signal EN_a and the clock signal CLK. Therefore, in the clock cycle starting from time t2, the clock signal CK is a copy version of the clock signal CLK. The inverted signal EN_b of the clock control signal EN_a has a signal delay Td, but the signal delay Td is at the first level stage T1 of the clock signal CLK, and the combinational logic operation can remove the glitch that may occur in the clock signal CK due to the signal delay Td.

[0097] Therefore, in the clock cycle starting from time t2, the clock gating circuit 330 copies the clock signal CK to the clock signal CK. Because the level state of the clock signal CK in the previous clock cycle is high level, the clock signal CK cannot provide a trigger edge, i.e., a rising edge, of the edge-triggered flip-flop 110. The signal level of the output data Do of the edge-triggered flip-flop 110 matches the signal level of the input data Di in the previous trigger edge of the clock signal CK, for example, the high level shown in FIG.

[0098] At time t3, the clock signal CLK reaches a fourth rising edge, and the clock signal CK inverts from the low level in the second level step of the previous clock cycle to a high level.

[0099] The clock control signal EN_a is a result of an exclusive-OR operation between the input data Di and the output data Do of the edge-triggered flip-flop 110. In the clock cycle starting from time t3, the signal level of the input data Di is maintained at a low level, and the signal level of the output data Do is always at a low level. As a result of the exclusive-OR operation, the clock control signal EN_a is inverted from a high level to a low level at time t3 and is always at a low level in the clock cycle starting from time t3, and the inverted signal EN_b of the clock control signal EN_a is always at a high level in the clock cycle starting from time t3.

[0100] The clock signal CK is a result of a logical OR operation between the inverted signal EN_b of the clock control signal EN_a and the clock signal CLK. Therefore, at time t3, the clock signal CK inverts from low level to high level and maintains the high level in the clock cycle starting from time t3.

[0101] Therefore, in the clock cycle starting from time t3, the clock gating circuit 330 maintains the clock signal CK at a high level. Because the level state of the second level stage of the previous clock cycle of the clock signal CK is a low level, the clock signal CK provides a trigger edge, i.e., a rising edge, of the edge-triggered flip-flop 110. The signal level of the output data Do of the edge-triggered flip-flop 110 matches the signal level of the input data Di of the trigger edge of the current clock cycle of the clock signal CK, for example, a low level as shown in FIG.

[0102] The above-mentioned clock gating circuit 330 generates a clock control signal EN_a based on a data comparison between the input data Di and the output data Do of the edge trigger flip-flop 110, and controls the transmission of the clock signal according to the state of the clock control signal EN_a.

[0103] In successive clock cycles, if the input data Di of the edge-triggered flip-flop 110 does not change, the output data Do of the edge-triggered flip-flop 110 does not change. The input data Di and the output data Do of the edge-triggered flip-flop 110 are the same as each other. The clock gating circuit 330 disables the clock signal CLK and maintains the clock signal CK in a high-level state. Therefore, the clock gating circuit 330 can disable the clock inversion and data transmission of the edge-triggered flip-flop 110, thereby reducing the dynamic power consumption of the edge-triggered flip-flop 110 due to the clock inversion and data transmission.

[0104] In successive clock cycles, when the input data Di of the edge-triggered flip-flop 110 is inverted, the input data Di of the edge-triggered flip-flop 110 is inverted after a signal delay in the clock cycle in which the input data Di is inverted, and the input data Di and Do change from being the same to being different from each other. The clock gating circuit 330 copies the clock signal CLK to the clock signal CK, and provides a trigger edge of the edge-triggered flip-flop in the next clock cycle. Thus, the clock gating circuit 330 can enable the clock inversion and data transmission of the edge-triggered flip-flop 110 in a single clock cycle, thereby reducing the dynamic power consumption of the edge-triggered flip-flop 110 due to the clock inversion and data transmission.

[0105] According to the clock gating circuit 330 of this embodiment, a latch is omitted compared to the clock gating circuit 130 shown in Fig. 5. Even if the input data Di of the edge triggered flip-flop 110 has a signal delay Td, by setting the minimum delay Tdmin and maximum delay Tdmax of the signal delay Td of the input data Di of the edge triggered flip-flop 110 to the first level stage of the clock signal CK, it is possible to remove glitches in the clock signal CK of the edge triggered flip-flop 110.

[0106] In the circuit design of the trigger unit, the clock gating circuit 330 can simplify the circuit configuration and circuit design of the trigger unit because it is only necessary to set the signal delay of the input data Di of the edge trigger flip-flop 110. The clock gating circuit 330 uses less hardware logic and consumes less power in its operation.

[0107] In a trigger unit, any number of edge-triggered flip-flops 110 can share a clock gating circuit 330 to form a flip-flop group. When a flip-flop group includes any number of edge-triggered flip-flops 110, the trigger unit can always achieve reduced power consumption because the increase in power consumption due to the power consumption of the clock gating circuit 330 itself is much smaller than the reduction in power consumption of the edge-triggered flip-flops 110 due to clock gating.

[0108] Figure 9 shows a schematic circuit diagram of another clock gating circuit in the trigger unit shown in Figure 7. Referring to Figure 7, the clock gating circuit 430 and the edge triggered flip-flop 110 together form a trigger unit, and the clock gating circuit 430 provides a clock signal CK to the edge triggered flip-flop 110.

[0109] The clock gating circuit 430 includes an XOR gate 431 and an AND gate 433. In the clock gating circuit 430, a clock control signal EN_a is generated based on a comparison between the input data Di and the output data Do of the edge triggered flip-flop 110, and the clock signal CK is a result of a logical AND operation between the clock signal CLK and the clock control signal EN_a.

[0110] The XOR gate 431 includes a first input terminal, a second input terminal, and an output terminal. The AND gate 433 includes a first input terminal, a second input terminal, and an output terminal. The first data input terminal of the XOR gate 431 receives the input data Di of the edge-triggered flip-flop 110, the second data input terminal receives the output data Do of the edge-triggered flip-flop 110, and the output terminal provides the clock control signal EN_a. The first input terminal of the AND gate 433 receives the clock signal CLK. The second input terminal of the AND gate 433 is connected to the output terminal of the XOR gate 431 and receives the clock control signal EN_a. The output terminal of the AND gate 433 provides the clock signal CK.

[0111] In this embodiment, an edge-triggered flip-flop triggered by a falling edge is taken as an example, and the clock control signal EN is described with a high level representing an active state and a low level representing an inactive state. Each clock cycle of the clock signal CLK includes a first level stage T1 and a second level stage T2 having a low level and a high level, respectively, between adjacent falling edges. The clock signal CK provides a falling edge as the trigger edge of the edge-triggered flip-flop 110, and the edge-triggered flip-flop 110 transmits input data from the input end to the output end at the trigger edge.

[0112] 11, the input data Di of the edge triggered flip-flop 110 has a signal delay Td with respect to the edge of the clock signal. The areas between the minimum delay Tdmin and the maximum delay Tdmax of the signal delay Td are represented by the shaded areas. The signal delay Td of the input data Di of the edge triggered flip-flop 110 varies between the minimum delay Tdmin and the maximum delay Tdmax.

[0113] In this embodiment, the clock control signal EN_a of the clock gating circuit is obtained based on the data comparison between the input data Di and the output data Do of the edge trigger flip-flop 110. The signal delay Td of the clock control signal EN_a is approximately the same as the signal delay Td of the input data Di.

[0114] Using the optimized circuit design and circuit simulation, the signal delay Td of the input data Di of the edge-triggered flip-flop 110 can be calculated and set so that the range of the minimum delay Tdmin and maximum delay Tdmax of the signal delay Td is within the selected first level step T1 of the clock signal CLK.

[0115] Correspondingly, the range between the minimum delay Tdmin and the maximum delay Tdmax of the signal delay Td of the clock control signal EN_a is in the first level stage T1 of the clock signal CLK. The inversion operation of the clock control signal EN_a can only occur in the first level stage T1 of the clock signal CLK. The starting edge of the first level stage T1 is a falling edge.

[0116] At time t0, the clock signal CLK reaches the first falling edge, and the clock signal CK maintains the low level of the previous clock cycle.

[0117] The clock control signal EN_a is a result of an exclusive-OR operation between the input data Di and the output data Do of the edge-triggered flip-flop 110. In a clock cycle starting from time t0, the signal level of the input data Di of the edge-triggered flip-flop 110 inverts from a low level to a high level after a signal delay Td, and the signal level of the output data Do is always at a low level. As a result of the exclusive-OR operation, the clock control signal EN_a inverts from a low level to a high level via a signal delay Td. The clock control signal EN_a inverts from a low level to a high level via a signal delay Td.

[0118] The clock signal CK is a logical AND operation result of the clock control signal EN_a and the clock signal CLK. In the clock cycle starting from time t0, the clock signal CK is a copy version of the clock signal CLK. The clock control signal EN_a has a signal delay Td, but the signal delay Td is at the first level stage T1 of the clock signal CLK, and the combinational logic operation can remove the glitch that may occur in the clock signal CK due to the signal delay Td.

[0119] Therefore, in the clock cycle starting from time t0, the clock gating circuit 430 copies the clock signal CLK to the clock signal CK. Because the level state of the clock signal CK in the previous clock cycle is low level, the clock signal CK cannot provide a trigger edge, i.e., a falling edge, of the edge-triggered flip-flop 110. The signal level of the output data Do of the edge-triggered flip-flop 110 matches the signal level of the input data Di of the previous trigger edge of the clock signal CK, and is, for example, low level as shown in FIG.

[0120] At time t1, the clock signal CLK reaches a second falling edge, and the clock signal CK inverts from the high level of the second level step of the previous clock cycle to the low level.

[0121] The clock control signal EN_a is the result of an exclusive-OR operation between the input data Di and the output data Do of the edge-triggered flip-flop 110. In a clock cycle starting from time t1, the signal level of the input data Di is maintained at a high level, and the signal level of the output data Do is always at a high level. As a result of the exclusive-OR operation, the clock control signal EN_a is inverted from a high level to a low level at time t1, and is always at a low level in the clock cycle starting from time t1.

[0122] The clock signal CK is a result of ANDing the clock control signal EN_a and the clock signal CLK. Therefore, at time t1, the clock signal CK inverts from high level to low level and maintains the low level in the clock cycle starting from time t1.

[0123] Therefore, in the clock cycle starting from time t1, the clock gating circuit 430 maintains the clock signal CK at a low level. Because the level state of the second level stage of the previous clock cycle of the clock signal CK is a high level, the clock signal CK provides a trigger edge, i.e., a falling edge, of the edge-triggered flip-flop 110. The signal level of the output data Do of the edge-triggered flip-flop 110 matches the signal level of the input data Di of the trigger edge of the current clock cycle of the clock signal CK, for example, a high level as shown in FIG.

[0124] At time t2, the clock signal CLK reaches the third falling edge and the clock signal CK remains at the low level of the previous clock cycle.

[0125] The clock control signal EN_a is the result of an exclusive-OR operation between the input data Di and the output data Do of the edge-triggered flip-flop 110. In the entire clock cycle starting from time t2, the signal level of the input data Di of the edge-triggered flip-flop 110 inverts from a high level to a low level after a signal delay Td, and the signal level of the output data Do is always at a high level throughout the entire clock cycle. As a result of the exclusive-OR operation, the clock control signal EN_a inverts from a low level to a high level via a signal delay Td.

[0126] The clock signal CK is a logical AND operation result of the clock control signal EN_a and the clock signal CLK. In the clock cycle starting from time t2, the clock signal CK is a copy version of the clock signal CLK. The clock control signal EN_a has a signal delay Td, but the signal delay Td is at the first level stage T1 of the clock signal CLK, and the combinational logic operation can remove the glitch that may occur in the clock signal CK due to the signal delay Td.

[0127] Therefore, in the clock cycle starting from time t2, the clock gating circuit 430 copies the clock signal CLK to the clock signal CK. Because the level state of the clock signal CK in the previous clock cycle is low level, the clock signal CK cannot provide a trigger edge, i.e., a falling edge, of the edge-triggered flip-flop 110. The signal level of the output data Do of the edge-triggered flip-flop 110 matches the signal level of the input data Di at the previous trigger edge of the clock signal CK, and is, for example, a high level as shown in FIG.

[0128] At time t3, the clock signal CLK reaches the fourth falling edge, and the clock signal CK inverts from the high level of the second level step of the previous clock cycle to the low level.

[0129] The clock control signal EN_a is a result of an exclusive-OR operation between the input data Di and the output data Do of the edge-triggered flip-flop 110. In the clock cycle starting from time t3, the signal level of the input data Di is maintained at a low level, and the signal level of the output data Do is always at a low level. As a result of the exclusive-OR operation, the clock control signal EN_a is inverted from a high level to a low level at time t3, and is always at a low level in the clock cycle starting from time t3.

[0130] The clock signal CK is a result of ANDing the clock control signal EN_a and the clock signal CLK. Therefore, at time t3, the clock signal CK is inverted from high level to low level and maintained at low level in the clock cycle starting from time t3.

[0131] Therefore, in the clock cycle starting from time t3, the clock gating circuit 430 maintains the clock signal CK at a low level. Since the level state of the second level stage of the clock signal CK in the previous clock cycle is a high level, the clock signal CK provides a trigger edge, i.e., a falling edge, of the edge-triggered flip-flop 110. The signal level of the output data Do of the edge-triggered flip-flop 110 matches the signal level of the input data Di of the trigger edge of the current clock cycle of the clock signal CK, and is, for example, a low level as shown in FIG.

[0132] The above-mentioned clock gating circuit 430 generates a clock control signal EN_a based on a data comparison between the input data Di and the output data Do of the edge trigger flip-flop 110, and controls the transmission of the clock signal according to the state of the clock control signal EN_a.

[0133] In successive clock cycles, if the input data Di of the edge-triggered flip-flop 110 does not change, the output data Do of the edge-triggered flip-flop 110 does not change. The input data Di and the output data Do of the edge-triggered flip-flop 110 are the same as each other. The clock gating circuit 430 disables the clock signal CLK and keeps the clock signal CK in a low level state. Therefore, the clock gating circuit 430 can disable the clock inversion and data transmission of the edge-triggered flip-flop 110, thereby reducing the dynamic power consumption of the edge-triggered flip-flop 110 due to the clock inversion and data transmission.

[0134] In successive clock cycles, when the input data Di of the edge-triggered flip-flop 110 is inverted, the input data Di of the edge-triggered flip-flop 110 is inverted after a signal delay in the clock cycle in which the input data Di is inverted, and the input data Di and Do change from being the same to being different from each other. The clock gating circuit 430 copies the clock signal CLK to the clock signal CK, and provides a trigger edge of the edge-triggered flip-flop in the next clock cycle. Thus, the clock gating circuit 430 can enable the clock inversion and data transmission of the edge-triggered flip-flop 110 in a single clock cycle, thereby reducing the dynamic power consumption of the edge-triggered flip-flop 110 due to the clock inversion and data transmission.

[0135] According to the clock gating circuit 430 of this embodiment, a latch is omitted compared to the clock gating circuit 130 shown in Fig. 5. Even if the input data Di of the edge triggered flip-flop 110 has a signal delay Td, if the minimum delay Tdmin and maximum delay Tdmax of the signal delay Td of the input data Di of the edge triggered flip-flop 110 are set to the first level stage of the clock signal CLK, it is possible to remove glitches in the clock signal CK of the edge triggered flip-flop 110.

[0136] In the circuit design of the trigger unit, the clock gating circuit 430 can simplify the circuit configuration and circuit design of the trigger unit because it is only necessary to set the signal delay of the input data Di of the edge trigger flip-flop 110. The clock gating circuit 430 uses less hardware logic and consumes less power during its operation.

[0137] In a trigger unit, any number of edge-triggered flip-flops 110 can share a clock gating circuit 430 to form a flip-flop group. When a flip-flop group includes any number of edge-triggered flip-flops 110, the increase in power consumption due to the power consumption of the clock gating circuit 430 itself is much smaller than the decrease in power consumption of the edge-triggered flip-flops 110 due to clock gating, so the trigger unit can always achieve reduced power consumption.

[0138] 12 shows a schematic circuit diagram of a trigger unit according to a second embodiment of the present invention. The trigger unit 500 includes an edge-triggered flip-flop 110 and a clock gating circuit 530. The clock gating circuit 530 is used to gate the clock signal CK of the edge-triggered flip-flop 110. In this embodiment, the edge-triggered flip-flop 110 is, for example, a D-type flip-flop.

[0139] The edge-triggered flip-flop 110 includes a data input end, a data output end, and a clock input end. The clock gating circuit 530 includes a first input end, a second input end, a clock input end, a clock output end, and a control terminal. The first input end of the clock gating circuit 530 receives the input data Di, the second input end receives the output data Do, the control terminal receives a second clock control signal EN, the clock input end receives the clock signal CLK, and the clock output end provides the clock signal CK. The data input end of the edge-triggered flip-flop 110 receives the input data Di, the clock input end receives the clock signal CK, and the data output end provides the output data Do.

[0140] At a trigger edge, such as a rising edge, of the clock signal CK, the edge-triggered flip-flop 110 transmits the input data from the data input to the data output. Therefore, the signal level corresponding to the output data of the data output of the edge-triggered flip-flop 110 depends on the signal level of the input data at the data input before the trigger edge of the clock signal CK arrives, and does not change in the clock cycle after the trigger edge of the clock signal CK. The data output of the edge-triggered flip-flop 110 can include two complementary outputs.

[0141] The clock gating circuit 530 performs a combinational logic operation on the input data Di, the output data Do, the second clock control signal EN, and the clock signal CLK to generate the clock signal CK for the edge triggered flip-flop 110 .

[0142] The above-mentioned clock gating circuit 530 generates a first clock control signal EN_a based on a data comparison between the input data Di and the output data Do of the edge-triggered flip-flop 110, and controls the transmission of the clock signal according to the state of the first clock control signal EN_a and the received second clock control signal EN.

[0143] The second clock control signal EN includes, for example, an active phase of a number of clock cycles and an inactive phase of a number of clock cycles. When the second clock control signal EN is active, the clock gating circuit 530 disables the data comparison, and the clock gating circuit 530 copies the clock signal CLK to the clock signal CK. When the second clock control signal EN is inactive, the clock gating circuit 530 enables the data comparison and controls the transmission of the clock signal based on the comparison.

[0144] When the clock gating circuit 530 enables the data comparison, in a clock cycle in which the input data Di does not change, the clock gating circuit 530 maintains the clock signal CK at a predetermined level. In a clock cycle in which the input data Di is inverted, the clock gating circuit 530 copies the clock signal CLK to the clock signal CK. Therefore, the clock gating circuit 530 enables the transmission of the clock signal CLK only in a clock cycle in which the input data Di of the edge triggered flip-flop 110 is inverted, thereby minimizing the dynamic power consumption of the edge triggered flip-flop 110 due to the inversion of the clock signal CK. Furthermore, the clock gating circuit 530 provides a trigger edge only in the next clock cycle in which the input data Di of the edge triggered flip-flop 110 is inverted, thereby minimizing the dynamic power consumption of the edge triggered flip-flop 110 due to the data transmission.

[0145] Furthermore, the edge-triggered flip-flop 110 prevents data from entering downstream digital circuitry during most clock cycles during which the input data Di does not change, thereby avoiding additional data power consumption due to inversion of the data signal in downstream combinational logic.

[0146] Figure 13 shows a schematic circuit diagram of a clock gating circuit in the trigger unit shown in Figure 12. Referring to Figure 12, the clock gating circuit 530 and the edge triggered flip-flop 110 together form a trigger unit, and the clock gating circuit 530 provides a clock signal CK to the edge triggered flip-flop 110.

[0147] The clock gating circuit 530 includes an XOR gate 331, a NOT gate 332, an OR gate 533, and a NOT gate 534. In the clock gating circuit 530, a clock control signal EN_a is generated based on a comparison between the input data Di and the output data Do of the edge triggered flip-flop 110. The clock signal CK is a result of a logical OR operation of the clock signal CLK, an inverted signal EN_b of the first clock control signal EN_a, and the received second clock control signal EN.

[0148] The XOR gate 331 includes a first input terminal, a second input terminal, and an output terminal. The NOT gates 332 and 534 each include an input terminal and an output terminal. The AND gate 533 includes a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first data input terminal of the XOR gate 331 receives the input data Di of the edge-triggered flip-flop 110, the second data input terminal receives the output data Do of the edge-triggered flip-flop 110, and the output terminal provides the first clock control signal EN_a. The NOT gate 332 is connected between the output terminal of the XOR gate 331 and the second input terminal of the OR gate 331, and is used to generate an inverted signal EN_b of the first clock control signal EN_a. The first input terminal of the OR gate 533 receives the clock signal CLK. The second input terminal of the OR gate 533 receives the inverted signal EN_b of the first clock control signal EN_a through the NOT gate 332. A third input of OR gate 533 receives an inverse EN_c of the second clock control signal EN via NOT gate 534. An output of OR gate 533 provides the clock signal CK.

[0149] The operating principle of the clock gating circuit 530 used in the trigger unit according to the second embodiment is basically the same as the operating principle of the clock gating circuit 330 used in the trigger unit according to the first embodiment, so a detailed description thereof will be omitted here.

[0150] According to the clock gating circuit 530 of the present embodiment, a latch is omitted compared to the clock gating circuit 130 shown in FIG. 5. The clock gating circuit 530 enables and disables the data comparison function according to the received second clock control signal EN. When the second clock control signal EN is valid, the clock gating circuit 530 enables the data comparison function. When the second clock control signal EN is invalid, the clock gating circuit 530 disables the data comparison function. When the data comparison function is enabled, even if the input data Di of the edge triggered flip-flop 110 has a signal delay Td, the minimum delay Tdmin and maximum delay Tdmax of the signal delay Td of the input data of the edge triggered flip-flop 110 are set to the first level stage of the clock signal CLK, so that the glitch of the clock signal CK of the edge triggered flip-flop 110 can be removed.

[0151] In the circuit design of the trigger unit, the clock gating circuit 530 can simplify the circuit configuration and circuit design of the trigger unit because it is only necessary to set the signal delay of the input data Di of the edge trigger flip-flop 110. The clock gating circuit 530 uses less hardware logic and consumes less power in its operation.

[0152] In a trigger unit, any number of edge-triggered flip-flops 110 can share a clock gating circuit 530 to form a flip-flop group. When a flip-flop group includes any number of edge-triggered flip-flops 110, the increase in power consumption due to the power consumption of the clock gating circuit 530 itself is much smaller than the decrease in power consumption of the edge-triggered flip-flops 110 due to clock gating, so the trigger unit can always achieve reduced power consumption.

[0153] 14 shows a schematic circuit diagram of a trigger unit according to a third embodiment of the present invention. The trigger unit 600 includes an edge-triggered flip-flop 210 and a clock gating circuit 630. The clock gating circuit 630 is used to gate the clock signal CK of the edge-triggered flip-flop 210. In this embodiment, the edge-triggered flip-flop 210 is, for example, a D-type flip-flop.

[0154] The edge-triggered flip-flop 210 includes a data input end, a first data output end, a second data output end, and a clock input end. The clock gating circuit 630 includes a first input end, a second input end, a clock input end, and a clock output end. The first input end of the clock gating circuit 630 receives the input data Di, the second input end receives the output data Do, the clock input end receives a clock signal CLK, and the clock output end provides a clock signal CK. The data input end of the edge-triggered flip-flop 210 receives the input data Di, the clock input end receives the clock signal CK, the first data output end provides the output data Do, and the second data output end provides an inverted signal Dn of the output data Do.

[0155] In this embodiment, the first data output terminal and the second data output terminal of the edge triggered flip-flop 210 are two complementary output terminals. The data input terminal of the edge triggered flip-flop 210 is connected to the second data output terminal, so that the edge triggered flip-flop 210 always takes the inverted signal Dn of its own output data Do as input data.

[0156] At a trigger edge, such as a rising edge, of the clock signal CK, the edge-triggered flip-flop 210 transfers the input data from the data input to the data output. Therefore, the signal level corresponding to the output data of the data output of the edge-triggered flip-flop 210 depends on the signal level of the input data at the data input before the trigger edge of the clock signal CK arrives, and does not change in the clock cycle after the trigger edge of the clock signal CK.

[0157] The clock gating circuit 630 performs a combinational logic operation on the input data Di, the output data Do, and the clock signal CLK to generate the clock signal CK for the edge-triggered flip-flop 210 .

[0158] The above-mentioned clock gating circuit 630 generates a clock control signal EN_a based on a data comparison between the input data Di and the output data Do of the edge trigger flip-flop 210, and controls the transmission of the clock signal according to the state of the clock control signal EN_a.

[0159] In a clock cycle in which the input data Di does not change, the clock gating circuit 630 maintains the clock signal CK at a predetermined level. In a clock cycle in which the input data Di is inverted, the clock gating circuit 630 copies the clock signal CLK to the clock signal CK. Therefore, the clock gating circuit 630 enables the transmission of the clock signal CLK only in a clock cycle in which the input data Di of the edge triggered flip-flop 210 is inverted, thereby minimizing the dynamic power consumption of the edge triggered flip-flop 210 due to the inversion of the clock signal CK. Furthermore, the clock gating circuit 630 provides a trigger edge only in the next clock cycle in which the input data Di of the edge triggered flip-flop 210 is inverted, thereby minimizing the dynamic power consumption of the edge triggered flip-flop 210 due to data transmission. The edge triggered flip-flop 210 outputs an inverted signal of the output data Do from the input end to the output end as input data at the trigger edge of the clock signal CK. Additionally, edge-triggered flip-flop 210 can prevent data from entering downstream digital circuitry at other times, thereby avoiding additional data power consumption due to data signal inversions in downstream combinational logic.

[0160] Figure 15 shows a schematic circuit diagram of the clock gating circuit in the trigger unit shown in Figure 14. Referring to Figure 14, the clock gating circuit 630 and the edge triggered flip-flop 210 together form a trigger unit, and the clock gating circuit 630 provides a clock signal CK to the edge triggered flip-flop 210.

[0161] The clock gating circuit 630 includes an XOR gate 331, a NOT gate 332, or an OR gate 533. In the clock gating circuit 630, a clock control signal EN_a is generated based on a comparison between the input data Di and the output data Do of the edge triggered flip-flop 210, and the clock signal CK is a logical OR operation between the clock signal CLK and an inverted signal EN_b of the clock control signal EN_a.

[0162] The operating principle of the clock gating circuit 630 used in the trigger unit according to the third embodiment is basically the same as the operating principle of the clock gating circuit 330 used in the trigger unit according to the first embodiment, so a detailed description thereof will be omitted here.

[0163] Moreover, the working principle of the edge-triggered flip-flop 210 in the trigger unit according to the third embodiment is basically the same as that of the edge-triggered flip-flop 110 used in the trigger unit according to the first embodiment, and only the main differences between the two will be described here.

[0164] The input data Di received by the trigger unit 600 according to the third embodiment is used only for clock gating, and the edge triggered flip-flop 210 generates the input data based on its own output data Dn, so that the edge triggered flip-flop 210 does not need to receive input data from the outside. For example, the data input terminal of the edge triggered flip-flop is coupled to the second data output terminal and receives the inverted signal Dn of the output data as input data.

[0165] According to the clock gating circuit 630 of this embodiment, a latch is omitted compared to the clock gating circuit 130 shown in Fig. 5. Even if the input data Di of the edge triggered flip-flop 210 has a signal delay Td, if the minimum delay Tdmin and maximum delay Tdmax of the signal delay Td of the input data Di of the edge triggered flip-flop 210 are set to the first level stage of the clock signal CK, it is possible to remove glitches in the clock signal CK of the edge triggered flip-flop 210.

[0166] The edge-triggered flip-flop 210 generates input data based on its own output data DN, and therefore the edge-triggered flip-flop 210 does not need to receive any input data from the outside, thereby reducing the adverse effect of signal delay fluctuations in the external input data on the operational stability of the edge-triggered flip-flop.

[0167] The clock gating circuit 630 can simplify the circuit configuration and circuit design of the trigger unit because it is only necessary to set the signal delay of the input data Di of the edge trigger flip-flop 210. The clock gating circuit 630 uses less hardware logic and consumes low operating power itself.

[0168] In a trigger unit, any number of edge-triggered flip-flops 210 can share a clock gating circuit 630 to form a flip-flop group. When a flip-flop group includes any number of edge-triggered flip-flops 210, the increase in power consumption due to the power consumption of the clock gating circuit 630 itself is much smaller than the decrease in power consumption of the edge-triggered flip-flops 210 due to clock gating, so the trigger unit can always achieve reduced power consumption.

[0169] In the above trigger unit, the flip-flop triggered by the rising edge and the falling edge of the clock signal is taken as an example, and the edge-triggered flip-flop in the trigger unit only has one structure. However, the present invention is not limited thereto. It is understood that other edge-triggered flip-flops, such as edge-triggered flip-flops with reset function, can also be technically improved by applying the present invention.

[0170] It should be noted that in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another and do not necessarily require or imply that an actual relationship or sequence exists between those entities or operations. Furthermore, the terms "comprise", "contain", or any other variation thereof are intended to cover a non-exclusive inclusion, whereby a process, method, article, or device that includes a set of elements includes not only those elements, but also other elements not expressly listed, or elements inherent to the process, method, article, or device. Without further limitation, an element defined by the statement "comprises..." does not exclude the presence of additional identical elements in the process, method, article, or device that includes said element.

[0171] According to the above-mentioned embodiments of the present invention, these embodiments are not exhaustively described in detail, nor are they intended to limit the invention to the specific embodiments described. In light of the above description, it is apparent that many modifications and variations are possible. These embodiments have been selected and described in detail herein in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can effectively utilize the present invention and make modifications based on the present invention. The present invention is limited only by the claims, their full scope and equivalents.

Claims

1. an edge-triggered flip-flop including a data input, a clock input and a first data output; a clock gating circuit including a first input terminal, a second input terminal, a clock input terminal, and an output terminal; a first input of the clock gating circuit receiving input data of the edge triggered flip-flop, a second input of the clock gating circuit receiving output data of the edge triggered flip-flop, a clock input of the clock gating circuit receiving a first clock signal, and an output of the clock gating circuit coupled to the clock input of the edge triggered flip-flop to provide a second clock signal; the clock gating circuit enables or disables the first clock signal to generate the second clock signal based on a data comparison result between the input data and the output data, and the second clock signal provides a trigger edge for the edge-triggered flip-flop; A trigger unit, wherein the clock gating circuit copies the first clock signal to the second clock signal in clock cycles in which the input data is inverted, and maintains the second clock signal at a predetermined level in clock cycles in which the input data does not change.

2. 2. The trigger unit of claim 1, wherein the predetermined level is such that a clock cycle of the first clock signal includes successive first and second level steps, and the input data is inverted at the first level step of the first clock signal.

3. 3. The trigger unit of claim 2, wherein the predetermined level is a level of the first level stage, and the second clock signal provides a trigger edge in a clock cycle following a clock cycle in which input data is inverted.

4. 3. The trigger unit of claim 2, wherein the starting edge of the first level stage is a rising edge.

5. The clock gating circuit includes: an XOR gate including a first input, a second input and an output, the first input and the second input receiving input data and output data of the edge triggered flip-flop, respectively, and the output providing a first clock control signal; an OR gate having a first input for receiving the first clock signal, a second input, and an output; a NOT gate having an input terminal and an output terminal, and connected between the output terminal of the XOR gate and the second input terminal of the OR gate; 5. The trigger unit of claim 4, wherein the NOT gate inverts the first clock control signal and provides it to a second input of the OR gate, an output of the OR gate providing the second clock signal.

6. 6. The trigger unit of claim 5, wherein the OR gate further includes a third input, the third input receiving an inverse signal of the second clock control signal.

7. 7. The trigger unit of claim 6, wherein when the second clock control signal is valid, the clock gating circuit enables a data comparison function, and when the second clock control signal is invalid, the clock gating circuit disables the data comparison function.

8. 3. The trigger unit of claim 2, wherein the starting edge of the first level stage is a falling edge.

9. The clock gating circuit includes: an XOR gate including a first input, a second input and an output, the first input and the second input receiving input data and output data of the edge triggered flip-flop, respectively, and the output providing a first clock control signal; 9. The trigger unit of claim 8, further comprising: an AND gate including a first input, a second input, and an output, the first input receiving the first clock signal, the second input receiving the first clock control signal, and the output providing the second clock signal.

10. 10. The trigger unit of claim 9, wherein the AND gate further comprises a third input for receiving a second clock control signal.

11. 11. The trigger unit of claim 10, wherein when the second clock control signal is valid, the clock gating circuit enables a data comparison function, and when the second clock control signal is invalid, the clock gating circuit disables a data comparison function.

12. 10. The trigger unit according to claim 5 or 9, wherein the data input terminal of the edge trigger flip-flop receives an inverted signal of its output data as input data.

13. the edge-triggered flip-flop further includes a second data output, the first data output and the second data output of the edge-triggered flip-flop respectively providing an output data of the edge-triggered flip-flop and an inverted signal of the output data; 13. The trigger unit of claim 12, wherein the data input and the second data output of the edge-triggered flip-flop are coupled to each other and receive an inverted signal of its output data.

14. 11. The trigger unit of claim 6 or 10, wherein a high level of each of the first clock control signal and the second clock control signal indicates a valid state, and a low level indicates an invalid state.

15. 2. The trigger unit of claim 1, wherein the edge triggered flip-flop receives input data from the data input terminal at the trigger edge and transmits the input data to the first data output terminal.

16. The trigger unit according to claim 1 , wherein the trigger unit is used as a library unit in a standard cell library of digital circuit EDA.

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