Silicon carbide semiconductor device and method for manufacturing same

Abstract

This application discloses a silicon carbide semiconductor device and a method for manufacturing the same. The silicon carbide semiconductor device includes a silicon carbide epitaxial layer having a first surface including a gate region and source regions located on both sides of the gate region, and a second surface facing the first surface, a first trench provided in the surface of the gate region, a first voltage shield structure formed in the silicon carbide epitaxial layer based on the first trench, a gate structure located in the first trench and having a gate metal on its surface, a second voltage shield structure provided in the surface of the source region, a source metal provided on the surface of the source region, and a well region provided in the first surface and located between the first trench and the second voltage shield structure. In a silicon carbide semiconductor device, a first voltage-withstanding shield structure is formed in the silicon carbide epitaxial layer based on the first trench, and a second voltage-withstanding shield structure is formed in the surface of the source region, thereby improving the voltage-withstanding properties of the corner region at the bottom of the first trench and solving the problem of easy breakdown in the electric field concentration region.

Description

[Technical field]

[0001] This application claims priority to China Patent Application No. 202210433930.0, filed with the State Intellectual Property Office of the People's Republic of China on April 24, 2022, entitled "Silicon carbide semiconductor device and manufacturing method thereof," the entire contents of which are incorporated herein by reference.

[0002] This application claims priority to China Patent Application No. 202220975064.3, filed with the State Intellectual Property Office of the People's Republic of China on April 24, 2022, entitled "Silicon Carbide Semiconductor Device," the entire contents of which are incorporated herein by reference.

[0003] This application relates to the field of semiconductor device technology, and more particularly to silicon carbide (SiC) semiconductor devices and methods for fabricating same. [Background technology]

[0004] 2. Description of the Related Art With the development of science and technology, more and more electronic devices are widely used in people's daily life and work, bringing great convenience to daily life and work, and becoming an indispensable tool for modern people.

[0005] In integrated circuits, which are the main structure for electronic devices to realize various functions, semiconductor devices are important constituent electronic elements. Silicon carbide semiconductor devices have excellent characteristics in high power applications and have become the main development direction in the semiconductor field.

[0006] However, silicon carbide semiconductor devices have a problem in that they are often destroyed in areas of electric field concentration due to the presence of a relatively high electric field in high power device application fields. Summary of the Invention [Problem to be solved by the invention]

[0007] In view of the above circumstances, the present invention provides a silicon carbide semiconductor device and a method for manufacturing the same. [Means for solving the problem]

[0008] a silicon carbide epitaxial layer having a first surface including a gate region and a source region located on both sides of the gate region, and a second surface opposite the first surface; a first trench disposed in a surface of the gate region; a first voltage withstanding shield structure formed in the silicon carbide epitaxial layer based on the first trench; a gate structure located in the first trench; a gate metal disposed on a surface of the gate structure; a second voltage withstanding shield structure disposed within a surface of the source region; a source metal disposed on a surface of the source region; A silicon carbide semiconductor device comprising a well region in the first surface located between the first trench and the second voltage withstanding shield structure.

[0009] In a preferred silicon carbide semiconductor device, the first voltage-withstanding shield structure is located in a depth direction of the first trench on a side facing the second surface of the well region without contacting the well region.

[0010] In a preferred silicon carbide semiconductor device, the first trench is a first two-step trench, the gate structure comprises polysilicon filled in the first trench, with a first insulating dielectric layer disposed between the first trench and the filled polysilicon; The first voltage withstand shield structure comprises a doped region located in a sidewall and bottom surface of a single step trench toward the second surface of the first double step trench.

[0011] In a preferred silicon carbide semiconductor device, a depth of the well region relative to the first surface is smaller than a depth of a step between the two steps of the first two-step trench, and the first voltage-withstanding shield structure is located on a side of the step between the two steps of the first two-step trench facing the second surface.

[0012] In a preferred silicon carbide semiconductor device, the first trench is a first double-step trench, the first double-step trench is filled with polysilicon, and a first insulating dielectric layer is provided between the first double-step trench and the filled polysilicon; The thickness of the insulating dielectric layer at the bottom of the first two-step trench is greater than the thickness of the insulating dielectric layer on each step trench sidewall in the first two-step trench and is greater than the thickness of the insulating dielectric layer on the step between two adjacent step trenches.

[0013] In a preferred silicon carbide semiconductor device, a multi-step trench is provided in a surface of the source region, the multi-step trench is filled with polysilicon, and a second insulating dielectric layer is provided between the multi-step trench and the filled polysilicon; The second voltage withstanding shield structure comprises a doped region formed in the silicon carbide epitaxial layer based on the multi-step trench.

[0014] In a preferred silicon carbide semiconductor device, the first trench is a first double-step trench, the multi-step trench is a second double-step trench, and the first double-step trench has the same depth as the second double-step trench. In a preferred silicon carbide semiconductor device, the first trench is a first two-step trench, and the multi-step trench is a three-step trench having a depth greater than a depth of the first two-step trench.

[0015] In a preferred silicon carbide semiconductor device, the second voltage withstanding shield structure comprises a doped region located in the silicon carbide epitaxial layer on the sidewalls, steps, bottom and around the opening of the multi-step trench.

[0016] In a preferred silicon carbide semiconductor device, a thickness of the second insulating dielectric layer at the bottom of the multi-step trench is greater than a thickness of the second insulating dielectric layer on a sidewall of each step of the multi-step trench and is greater than a thickness of the second insulating dielectric layer at a step between two adjacent step trenches.

[0017] In a preferred silicon carbide semiconductor device, the second voltage withstanding shield structure is an ion implanted region formed in the source region.

[0018] In a preferred silicon carbide semiconductor device, the ion implantation region has an implantation depth equal to or greater than the depth of the first trench.

[0019] The present application also provides a method for producing the silicon carbide semiconductor device according to any one of the above aspects, the method comprising the steps of: providing an epitaxial sheet including a silicon carbide epitaxial layer having a first surface including a gate region and a source region located on both sides of the gate region, and a second surface opposite to the first surface; forming a first trench in the gate region; forming a first voltage withstanding shield structure in the silicon carbide epitaxial layer based on the first trench; forming a gate structure in the first trench; forming a gate metal on a surface of the gate structure and a source metal on a surface of the source region; Here, a second voltage-withstanding shield structure is provided in the surface of the source region, and a well region is provided in the first surface and is located between the first trench and the second voltage-withstanding shield structure.

[0020] In a preferred method, the first trench is a first two-step trench, a multi-step trench formed in a surface of the source region; A method for manufacturing the first and second voltage withstanding shield structures includes: performing ion implantation into a sidewall and a bottom of the single-step trench adjacent to the second surface of the first double-step trench based on a dielectric layer on a sidewall of the first double-step trench and a sidewall of a single-step trench adjacent to a first surface of the first double-step trench to form the first voltage-resistant shield structure in a silicon carbide epitaxial layer on the sidewall and bottom of the single-step trench adjacent to the second surface of the first double-step trench; and forming the second voltage-resistant shield structure in a silicon carbide epitaxial layer at the bottom of the multi-step trench, the steps of each step trench, and the sidewalls thereof based on the multi-step trench.

[0021] In a preferred method, the first trench is a first double-step trench, a multi-step trench is formed in a surface of the source region, the first double-step trench and the multi-step trench are both filled with polysilicon, and the gate structure comprises polysilicon filled in the first double-step trench; an insulating dielectric layer is provided between the first two-step trench and the filled polysilicon and between the multi-step trench and the filled polysilicon, and the gate structure comprises polysilicon filled in the first two-step trench; Here, the gate metal is located on a surface of the polysilicon filled in the first two-step trench, and the source metal is located on a surface of the polysilicon filled in the multi-step trench.

[0022] In a preferred manufacturing method, a thickness of the insulating dielectric layer at the bottom of the first two-step trench is greater than a thickness of the insulating dielectric layer on each step trench sidewall in the first two-step trench and is greater than a thickness of the insulating dielectric layer on a step between two adjacent step trenches; The thickness of the insulating dielectric layer at the bottom of the multi-step trench is greater than the thickness of the insulating dielectric layer on each step trench sidewall of the multi-step trench and is greater than the thickness of the insulating dielectric layer on a step between two adjacent step trenches.

[0023] In a preferred manufacturing method, the multi-step trench is a second two-step trench having the same depth as the first two-step trench, or the multi-step trench is a three-step trench having a depth greater than that of the first two-step trench.

[0024] In a preferred manufacturing method, the method of forming the second voltage-resistant shield structure includes the steps of: forming an ion implantation region as the second voltage-withstanding shield structure in the source region by an ion implantation method; The ion implantation region has an implantation depth equal to or greater than the depth of the first trench. Effect of the Invention

[0025] As described above, the silicon carbide semiconductor device in the silicon carbide semiconductor device and the manufacturing method thereof provided in the technical proposal of the present application includes a silicon carbide epitaxial layer having a first surface including a gate region and source regions located on both sides of the gate region, and a second surface opposite to the first surface, a first trench provided in the surface of the gate region, a first voltage-withstanding shield structure formed in the silicon carbide epitaxial layer based on the first trench, a gate structure located in the first trench, a gate metal provided on the surface of the gate structure, a second voltage-withstanding shield structure provided in the surface of the source region, a source metal provided on the surface of the source region, and a well region provided on the first surface and located between the first trench and the second voltage-withstanding shield structure. In the silicon carbide semiconductor device, a first voltage-withstanding shield structure is formed in the silicon carbide epitaxial layer based on the first trench, and a second voltage-withstanding shield structure is formed in the surface of the source region, thereby improving the voltage-withstanding characteristics of the corner region at the bottom of the first trench and solving the problem of easy destruction in the electric field concentration region.

[0026] In order to more clearly describe the embodiments of the present application or the technical solutions of the related art, the following briefly introduces the necessary drawings used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application, and those skilled in the art can also obtain other drawings based on the drawings provided without creative efforts.

[0027] The structures, ratios, sizes, etc. shown in the drawings of this specification are merely used in conjunction with the contents disclosed in this specification so that those familiar with the technology can understand and read the present invention, and are not used to limit the applicable limiting conditions of this application, and therefore have no technically substantial meaning. Any structural modifications, changes in ratio relationships, or size adjustments that do not affect the effects and objectives of this application are intended to be included in the scope of the contents disclosed in this application. [Brief description of the drawings]

[0028] [Figure 1] FIG. 1 is a schematic diagram showing the structure of an example of a DMOSFET. [Diagram 2] FIG. 2 is a schematic diagram of an example of a UMOSFET. [Diagram 3] FIG. 3 is a structural schematic diagram of a silicon carbide semiconductor device provided in an embodiment according to the present application. [Figure 4] FIG. 4 is a structural schematic diagram of another silicon carbide semiconductor device provided in an embodiment according to the present application. [Diagram 5] FIG. 5 is a structural schematic diagram of another silicon carbide semiconductor device provided in an embodiment according to the present application. [Figure 6] FIG. 6 is a structural schematic diagram of another silicon carbide semiconductor device provided in an embodiment according to the present application. [Figure 7] FIG. 7 is a flow chart that illustrates a schematic diagram of a method for manufacturing a silicon carbide semiconductor device provided in an embodiment according to the present application. [Figure 8] FIG. 8 is a flow chart that illustrates a schematic diagram of a method for manufacturing a silicon carbide semiconductor device provided in an embodiment according to the present application. [Figure 9] FIG. 9 is a flow chart that illustrates a schematic diagram of a method for manufacturing a silicon carbide semiconductor device provided in an embodiment according to the present application. [Figure 10] FIG. 10 is a flow chart that illustrates a method for manufacturing a silicon carbide semiconductor device provided in an embodiment according to the present application. [Figure 11] FIG. 11 is a flow chart that illustrates a method for manufacturing a silicon carbide semiconductor device provided in an embodiment according to the present application. [Figure 12] FIG. 12 is a flow chart that illustrates a method for manufacturing a silicon carbide semiconductor device provided in an embodiment according to the present application. [Figure 13] FIG. 13 is a flow chart that illustrates a method for manufacturing a silicon carbide semiconductor device provided in an embodiment according to the present application. [Figure 14]FIG. 14 is a flow chart that illustrates a method for manufacturing a silicon carbide semiconductor device provided in an embodiment according to the present application. [Figure 15] FIG. 15 is a flow chart that illustrates a method for manufacturing a silicon carbide semiconductor device provided in an embodiment according to the present application. [Figure 16] FIG. 16 is a flow chart that illustrates a method for manufacturing a silicon carbide semiconductor device provided in an embodiment according to the present application. [Figure 17] FIG. 17 is a flow chart that illustrates a method for manufacturing a silicon carbide semiconductor device provided in an embodiment according to the present application. [Figure 18] FIG. 18 is a flow chart that illustrates a method for manufacturing a silicon carbide semiconductor device provided in an embodiment according to the present application. [Figure 19] FIG. 19 is a flow chart that illustrates a schematic diagram of a method for manufacturing a silicon carbide semiconductor device provided in an embodiment according to the present application. [Figure 20] FIG. 20 is a flow chart that illustrates a method for manufacturing a silicon carbide semiconductor device provided in an embodiment according to the present application. [Figure 21] FIG. 21 is a flow chart that illustrates a method for manufacturing a silicon carbide semiconductor device provided in an embodiment according to the present application. [Figure 22] FIG. 22 is a flow chart that illustrates a method for manufacturing a silicon carbide semiconductor device provided in an embodiment according to the present application. [Diagram 23] FIG. 23 is a flow chart that illustrates a method for manufacturing a silicon carbide semiconductor device provided in an embodiment according to the present application. [Figure 24] FIG. 24 is a flow chart that illustrates a method for manufacturing a silicon carbide semiconductor device provided in an embodiment according to the present application. [Diagram 25] FIG. 25 is a flow chart that illustrates a method for manufacturing a silicon carbide semiconductor device provided in an embodiment according to the present application. [Figure 26]FIG. 26 is a flow chart that illustrates a method for manufacturing a silicon carbide semiconductor device provided in an embodiment according to the present application. [Figure 27] FIG. 27 is a flow chart that illustrates a method for manufacturing a silicon carbide semiconductor device provided in an embodiment according to the present application. [Figure 28] FIG. 28 is a flow chart that illustrates a method for manufacturing a silicon carbide semiconductor device provided in an embodiment according to the present application. [Figure 29] FIG. 29 is a flow chart that illustrates a method for manufacturing a silicon carbide semiconductor device provided in an embodiment according to the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] Hereinafter, the embodiments of the present application will be described clearly and completely with reference to the drawings of the embodiments of the present application, and obviously, the described embodiments are only a part of the present application, and are not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without inventive efforts shall be within the scope of protection of the present application.

[0030] SiC material has excellent characteristics and is very attractive in terms of high power, making it one of the ideal materials for high-performance power MOSFETs. SiC vertical power MOSFET devices mainly include lateral double-diffused DMOSFETs and vertical trench-gate UMOSFETs.

[0031] As shown in FIG. 1, FIG. 1 is a structural schematic diagram of an example DMOSFET. The DMOSFET includes an n+ (heavily n doped) substrate 2, an n- (lightly n doped) drift region 3 disposed on the surface of the substrate 2, a p-type well region 4 located in the drift region 3, and a source region 5 including an n+ doped region 51 and a p+ (heavily p doped) doped region 52 located in the p-type well region. A gate dielectric layer 7 is disposed on the surface of the drift region 3, and a gate 8 is provided on the surface of the gate dielectric layer 7. A drain electrode 1 is provided on one side of the substrate 2 away from the drift region 3.

[0032] The DMOSFET structure uses a planar diffusion technique to define the p-type base region and n+ source region at the edge of the polysilicon gate using a high melting point material as a mask. The name DMOS comes from this double diffusion process. The difference in diffusion between the sides of the p-type base region and the n+ source region is used to form a surface channel region.

[0033] As shown in FIG. 2, FIG. 2 is a structural schematic diagram of an example of a UMOSFET, which is different from the structure shown in FIG. 1 in that the UMOSFET is provided with a U-shaped trench, the surface of the U-shaped trench is covered with a gate dielectric layer 7, and a gate 8 is filled in the U-shaped trench. The name of the UMOSFET having a vertical trench gate structure is named after the U-shaped trench groove structure. This U-shaped trench groove structure is formed in the gate region by reactive ion etching. The U-shaped trench groove structure has a relatively high channel density (channel density is defined as the channel width of the source region), which greatly reduces the on-state characteristic resistance of the device.

[0034] Planar SiC MOSFETs have been researched in the industry for many years, and some manufacturers have taken the lead in releasing commercial products. With the advancement of modern technology, the on-resistance of conventional lateral DMOSFET structures cannot be reduced even by shrinking the size of the MOS cell. The main reason is that even with smaller photolithography sizes, the on-resistance per unit area remains at 2 mΩ cm. 2 This is believed to be due to limitations in the resistance in the JFET neck region, which is difficult to reduce significantly, but the trench structure can effectively solve this problem. As shown in Figure 2, the U-shaped trench structure changes the conductive channel from horizontal to vertical by adopting trench etching technology used in the manufacturing process of memory storage capacitors, so compared to the normal structure, the JFET neck resistance is eliminated, the cell density is significantly increased, and the current handling capacity of the power semiconductor is improved.

[0035] However, there are still some problems in the practical process manufacturing and application of SiC UMOSFETs. 1) The problem of high electric fields in the SiC drift region leading to high electric fields on the gate dielectric layer is exacerbated at the wrench corners, which causes the gate dielectric layer to break down quickly under high drain voltages and has low resistance to electrostatic effects in harsh environments and high voltage spikes in the circuit. 2) Since the ion implantation depth is limited, many compliant structures and surge-proof designs for protecting the trench gate are difficult to realize in the process. 3) Due to the material properties of SiC itself, the thickness of the silica layer at the bottom of the single rectangular or U-shaped gate trench is often a little thin during the oxidation process in a high-temperature tube furnace, which reduces the voltage resistance capability at the bottom of the trench and the reliability of the device.

[0036] In order to solve the above problems, the technical solution of the present application provides a silicon carbide semiconductor device in which a first withstand voltage shield structure is formed in a silicon carbide epitaxial layer based on a first trench, and a second withstand voltage shield structure is formed in the surface of the source region, thereby improving the withstand voltage of the corner region at the bottom of the first trench, solving the problem of frequent breakdown in the electric field concentration region, and improving the electrostatic withstand capability of the device against harsh environments and the withstand capability against high voltage spikes in the circuit. In addition, since the first withstand voltage shield structure can be formed based on the first trench, the ion implantation depth during the formation of the first withstand voltage shield structure can be increased, making it easier to realize various trench gate protection structures and surge withstand designs in the process. In addition, since a thicker insulating dielectric layer can be formed at the bottom of the trench, the problem of a thick silica layer not being formed in the trench during the oxidation process in a normal high-temperature tube furnace is solved, and the withstand voltage capability of the trench bottom and the reliability of the device are further improved.

[0037] In order to make the objectives, features and advantages of the present application clearer and easier to understand, the present application will be described in more detail below with reference to the drawings and specific embodiments.

[0038] As shown in FIG. 3, FIG. 3 is a structural schematic diagram of a silicon carbide semiconductor device provided in an embodiment of the present application. The silicon carbide semiconductor device includes: a silicon carbide epitaxial layer having a first surface including a gate region and source regions located on both sides of the gate region, and a second surface opposite to the first surface; a first voltage-resistant shield structure 13 formed in the silicon carbide epitaxial layer 11 based on a first trench 12 provided in the surface of the gate region; a gate structure g located in the first trench 12; a gate metal G disposed on a surface of the gate structure; a second voltage resistant shield structure 14 disposed within the surface of the source region; a source metal S provided on a surface of the source region; A well region W is provided on the first surface and is located between the first trench 12 and the second voltage-resistant shield structure 14.

[0039] In the silicon carbide semiconductor device, the first voltage shield structure 13 is formed in the silicon carbide epitaxial layer 11 based on the first trench 12, and the second voltage shield structure 14 is formed on the surface of the source region, thereby improving the voltage resistance of the bottom corner region of the first trench 12, solving the problem of easy destruction in the electric field concentration region, and improving the electrostatic resistance of the device against harsh environments and the resistance against high voltage spikes in the circuit. Furthermore, since the first voltage shield structure 13 can be formed based on the first trench 12, the ion implantation depth when forming the first voltage shield structure 13 can be increased, making it easier to realize various trench gate protection structures and surge resistance designs in the process.

[0040] Furthermore, the ability to form a thick insulating dielectric layer at the bottom of the trench solves the problem of the trench being unable to form a thicker silica layer during the oxidation process in a conventional high temperature tube furnace, further improving the voltage withstand capability at the bottom of the trench and the reliability of the device.

[0041] Optionally, the silicon carbide epitaxial layer 11 is fabricated on the surface of the semiconductor substrate 10 such that the second surface faces the semiconductor substrate 10. A metal drain electrode D is disposed on one side of the semiconductor substrate 10 remote from the silicon carbide epitaxial layer 11. The source metal S and the metal drain electrode D may be Ti or Al, for example. The metal drain electrode D may be a composite metal layer of one or more of Ni, Ti, Al, or Ag.

[0042] The silicon carbide epitaxial layer 11 and the semiconductor substrate 10 have the same doping type, and the well region W, the first withstand voltage shield structure 13 and the second withstand voltage shield structure 14 have the same doping type and opposite to that of the epitaxial layer 11. The P-type doping and the N-type doping are opposite types of doping. In the silicon carbide epitaxial layer 11 adjacent to the first surface of the well region W, an ion implantation region 17 is provided, which has an opposite doping type to that of the well region W. If the well region W is P-type doped, the ion implantation region 17 may be an N+ ion implantation region.

[0043] However, the semiconductor substrate 10 may be an N+ (high concentration N type) silicon carbide substrate, the epitaxial layer 11 may be an N- (low concentration N type) silicon carbide epitaxial layer as a drift region of the semiconductor device, and the well region W is a P-type well region. The first voltage-resistant shield structure 13 and the second voltage-resistant shield structure 14 include a P+ (high concentration P type) ion implantation region. In the embodiment of the present application, the doping type of each region of the device is not limited to those described in the embodiment, and may be set as necessary to form a PMOS or NMOS structure.

[0044] In the depth direction of the first trench, the first voltage-withstanding shield structure 13 is located on the side of the well region W toward the second surface without contacting the well region W. That is, in the vertical direction of FIG. 3, the first voltage-withstanding shield structure 13 is located below the well region W without contacting the well region W.

[0045] 3, the first trench 12 is a first double-step trench, the gate structure g comprises polysilicon filled in the first trench 12, a first insulating dielectric layer 151 is provided between the first trench 12 and the filled polysilicon, and the first voltage-resistant shield structure 13 comprises a doped region located in a sidewall surface and a bottom surface of a single-step trench towards the second surface of the first double-step trench. The first insulating dielectric layer 151 is a gate oxide layer and may be silica.

[0046] The first two-step trench includes a two-step trench and a step structure located between the two-step trench. The first two-step trench has a single step adjacent to the first surface and another step adjacent to the second surface, and the opening of the single step trench adjacent to the first surface is larger than the opening of the single step trench adjacent to the second surface. The sacrificial layer on the sidewall of the single step trench adjacent to the first surface of the first two-step trench prevents ion implantation on the sidewall of the single step trench adjacent to the first surface of the first two-step trench due to ion scattering during ion implantation, and the first voltage shield structure 13 is located below the well region W to avoid contact between the two. As a result, the problem of abnormal channel opening in the semiconductor device caused by this is avoided, and normal operation of the device is ensured.

[0047] A first insulating dielectric layer 151 extends outside the first trench 12 and covers the first surface. The first insulating dielectric layer 151 has an opening on the first surface for providing a metal ohmic contact layer 18. A source metal S is connected to the silicon carbide epitaxial layer 11 through the metal ohmic contact layer 18 in the opening.

[0048] The depth of the well region W relative to the first surface is smaller than the depth of the step between the two-step trenches in the first two-step trench, and the first voltage-withstanding shield structure 13 is located on the side of the step between the two-step trenches in the first two-step trench facing the second surface.

[0049] In the embodiment shown in FIG. 3, a multi-step trench 16 is provided in the surface of the source region, the multi-step trench 16 is filled with polysilicon, a second insulating dielectric layer 152 is provided between the multi-step trench 16 and the filled polysilicon, and the second voltage withstanding shield structure 14 comprises a doped region formed in the silicon carbide epitaxial layer 11 based on the multi-step trench.

[0050] However, the first insulating dielectric layer 151 on the surface of the first trench 12 and the second insulating dielectric layer 152 on the surface of the multi-step trench 16 are made of the same material and are formed at the same time. The polysilicon filled in the first trench 12 and the polysilicon filled in the multi-step trench 16 are formed at the same time.

[0051] The second voltage-withstanding shield structure 14 includes a doped region in the silicon carbide epitaxial layer 11 located on the sidewall, steps, bottom and periphery of the opening of the multi-step trench 16. That is, the second voltage-withstanding shield structure 14 is disposed on all of the silicon carbide epitaxial layer on the sidewall, steps, bottom and periphery of the opening of the multi-step trench 16.

[0052] In the embodiment shown in FIG. 3, the first trench 12 is a first two-step trench and the multi-step trench 16 is a second two-step trench, and the first two-step trench and the second two-step trench have the same depth and can be manufactured by the same process flow.

[0053] In the embodiment of the present application, the multi-step trench 16 is not limited to a two-step trench, and may be a step trench with two or more steps. The number of trench steps of the multi-step trench 16 can be set according to the thickness parameters of the device and the ion implantation depth requirements.

[0054] In an embodiment of the present application, the silicon carbide semiconductor device may be a silicon carbide MOSFET device. In the embodiment shown in Fig. 3, a trench gate is formed in the gate region based on a first trench 12, and a trench source is formed in the source region on both sides of the gate region based on a multi-step trench 16. The first trench 12 and the multi-step trench 16 may both be two-step trenches, in which case a silicon carbide MOSFET device having a two-step trench structure is formed.

[0055] As shown in Fig. 4, Fig. 4 is a structural schematic diagram of another silicon carbide semiconductor device provided in an embodiment of the present application. According to the embodiment shown in Fig. 3 and the embodiment shown in Fig. 4, the first trench 12 is a first two-step trench, the multi-step trench 16 is a three-step trench, and the depth of the three-step trench is greater than the depth of the first two-step trench.

[0056] As shown in FIG. 5, FIG. 5 is a structural schematic diagram of another silicon carbide semiconductor device provided in an embodiment of the present application. In the silicon carbide semiconductor device shown in FIG. 5, the first trench 12 is a first two-step trench, the first two-step trench is filled with polysilicon, the gate structure g comprises polysilicon filled in the first two-step trench, and there is a first insulating dielectric layer 151 between the first two-step trench and the filled polysilicon. In the silicon carbide semiconductor device shown in FIG. 5 based on the form shown in FIG. 3, the thickness of the first insulating dielectric layer 151 at the bottom of the first two-step trench is greater than the thickness of the first insulating dielectric layer 151 at the sidewall of each step trench in the first two-step trench, and is greater than the thickness of the first insulating dielectric layer 151 at the step between the trenches of two adjacent steps.

[0057] 5, the thickness of the second insulating dielectric layer 152 at the bottom 16 of the multi-step trench is greater than the thickness of the second insulating dielectric layer 152 on the sidewalls of each step in the multi-step trench 16 and is greater than the thickness of the second insulating dielectric layer 152 on the step between two adjacent step trenches. The second insulating dielectric layer 152 and the first insulating dielectric layer 151 are the same insulating dielectric layer 15.

[0058] Obviously, in the configuration shown in FIG. 4, the first insulating dielectric layer 151 and the second insulating dielectric layer 152 may be provided such that the thickness at the bottom of the trench is greater than the thickness in other areas of the trench.

[0059] In the silicon carbide semiconductor device described in the embodiment of the present application, a trench gate is formed based on a first trench 12 in the gate region, a trench source is formed based on multi-step trenches 16 in the source regions on both sides of the gate region, a first voltage-resistant shield structure 13 is formed by ion implantation at the bottom of the first trench 12, and a second voltage-resistant shield structure 14 can be formed by ion implantation in the silicon carbide epitaxial layer 11 at the bottom, sidewall and step between the two steps of the multi-step trench 16. Here, both the first voltage-resistant shield structure 13 and the second voltage-resistant shield structure 14 may be P+ (high concentration P-type) regions.

[0060] The first trench 12 and the multi-step trench 16 respectively form the first and second voltage shield structures 13 and 14 in the silicon carbide epitaxial layer 11 by ion implantation, which solves the problems of the difficulty in forming a deep P+ shield layer in silicon carbide material and the damage caused by high-dose and high-dose P+ ion implantation, thereby improving the reliability of the device and better shielding and protecting the gate trench. After forming the first and second voltage shield structures 13 and 14 by ion activation, silica layers are grown on the surfaces of the first trench 12 and the multi-step trench 16 as the first insulating dielectric layer 151 and the second insulating dielectric layer 152, and then the first trench 12 and the multi-step trench 16 are filled with polysilicon and metal electrodes are formed, and a silicon carbide MOSFET device having a two-step trench structure is obtained.

[0061] As shown in FIG. 6, FIG. 6 is a structural schematic diagram of another silicon carbide semiconductor device provided in an embodiment of the present application. The second voltage-resistant shield structure 14 is an ion-implanted region formed in the source region. In this embodiment, there is no need to form a trench in the source region, and an ion-implanted region of a predetermined depth is directly formed as the second voltage-resistant shield structure 14 by an ion implantation process. In the embodiment shown in FIG. 6, in order to achieve a better voltage-resistant shield effect, the implantation depth of the ion-implanted region is set to be equal to or greater than the depth of the first trench 12.

[0062] According to the above embodiment, another embodiment of the present application also provides a method for manufacturing the silicon carbide semiconductor device described in the above embodiment. This manufacturing method is illustrated in FIGS.

[0063] 7 to 29 are schematic flow diagrams of a method for manufacturing a silicon carbide semiconductor device provided in an embodiment according to the present application. This manufacturing method includes the following steps.

[0064] Step S11: As shown in FIG. 7, an epitaxial sheet is provided that includes a silicon carbide epitaxial layer 11 having a first surface and a second surface opposite to the first surface, the first surface including a gate region and source regions located on both sides of the gate region.

[0065] The silicon carbide semiconductor device may be fabricated using an N+ silicon carbide semiconductor substrate 10 having an N- silicon carbide epitaxial layer 11, where a second surface of the silicon carbide epitaxial layer 11 faces towards the semiconductor substrate 10.

[0066] Step S12: As shown in FIGS. 8 to 16, a first trench 12 is formed in the gate region.

[0067] Before forming first trench 12, ion implantation is performed on the first surface to form well region W, ion implantation region 17, and electric field buffer region 19 in silicon carbide epitaxial layer 11. Ion implantation region 17 and electric field buffer region 19 are located in the surface of the source region and in well region W.

[0068] This manufacturing method is described by taking the case where the source region has a multi-step trench 16 as an example, and the second voltage-resistant shield structure 14 is formed based on the multi-step trench 16 in a subsequent process. The electric field buffer region 19 can solve the problems of leakage and breakdown caused by the thin thickness of the second voltage-resistant shield structure 14 at the opening position of the multi-step trench 16, improving the manufacturability and reliability of the device. The electric field buffer region 19 and the second voltage-resistant shield structure 14 have the same doping type, for example, both may be N+ doped. The ion implantation region 17 and the second voltage-resistant shield structure 14 have the opposite doping type, and the ion implantation region 17 may be an N+ doped region. In the example where the first trench 12 is a first two-step trench and the multi-step trench 16 is a second two-step trench, the second two-step trench may be formed at the same time as the first two-step trench. Specifically, the process of forming the first two-step trench and the second two-step trench is as follows.

[0069] Step S121: As shown in FIG. 8, a well region W and an ion implantation region 17 and an electric field buffer region 19 located within the well region are formed by ion implantation on the first surface. Ion implantation into silicon carbide materials is typically performed by a high temperature ion implanter at 500-600° C. to reduce damage to the silicon carbide material crystal lattice.

[0070] Step S122: As shown in FIG. 12, a first stage trench etch is performed on the first surface.

[0071] The first stage trench is formed by etching using a plasma dry etching method, for example, RIE or ICP etching. The principle of etching silicon carbide material is shown in FIG. 9 to FIG. 11. First, as shown in FIG. 9, SiO2 is deposited on the silicon carbide material as a mask layer by a deposition process such as CVD, a photoresist PR is applied on the surface of the mask layer by spin coating, and a photoresist PR of a desired pattern is formed by exposure and development. Then, as shown in FIG. 10, the mask layer is etched based on the patterned photoresist PR to form a patterned mask layer. Finally, as shown in FIG. 11, the silicon carbide material is etched based on the patterned mask layer to form a trench on its surface. General semiconductor processes such as photolithography and etching will not be described in detail in the following process.

[0072] As shown in FIG. 12, when forming the first stage trench by etching, a layer of SiO2 is deposited by CVD as a mask layer 21, and an F-group-containing gas such as CF4 or SF6, or a Cl-group-containing gas such as chlorine gas, and a mixed gas of Ar and oxygen can be used; and the silicon carbide epitaxial layer 11 is etched in the gate region and both side source regions by a plasma etching device such as ICP or RIE, thereby forming the first stage trench in the gate region and the source region, respectively. The depth of the first stage trench is set to 10 nm to 3 μm. Furthermore, in order to improve the performance of the device, the first stage trench depth can be set to 800 nm to 1 μm.

[0073] Step S123: Fill the first-stage trench with a SiO2 dielectric layer 22, as shown in Fig. 13. By a CVD process, deposit a SiO2 dielectric layer 22, so that the SiO2 dielectric layer 22 fills the first-stage trench and covers the mask layer 21.

[0074] Step S124: As shown in FIG. 14, the reticle 23 for the second step trench is aligned.

[0075] Photoresist is spin-coated on the surface of the SiO2 dielectric layer 22, and the photoresist is exposed and developed according to a reticle 23 to pattern the photoresist (the photoresist is not shown in FIG. 14).

[0076] The reticle 23 has areas used to form a first cut-out region and a second cut-out region. The first cut-out region is used to form a second step trench of a trench gate in the gate region, and the second cut-out region is used to form a second step trench of a trench source in the source region. In the reticle 23, the opening of the first cut-out region is smaller than the opening of the first step trench in the gate region, and the opening of the second cut-out region is larger than the opening of the first step trench in the source region.

[0077] Step S125: As shown in FIG. 15, etch based on the photoresist on the surface of the SiO2 dielectric layer 22 to form second step trenches based on the first step trenches of the gate region and the source region respectively.

[0078] To form second-stage trenches in the gate region and the source region, respectively, the silicon carbide epitaxial layer 11 is etched in the gate region and both source regions by a plasma etching apparatus such as ICP or RIE using an F-group-containing gas such as CF4 or SF6, or a Cl-group-containing gas such as chlorine gas, and a mixed gas of Ar and oxygen. The etching depth of the second-stage trench is set to 100 nm to 3 μm. Furthermore, in order to improve the performance of the device, the second-stage trench depth can be set to 300 to 500 nm.

[0079] Since the opening of the first removed region is smaller than the opening of the first step trench in the gate region, it is possible to form a deeper second step trench by etching at the bottom of the first step trench in the gate region, thereby forming the first two-step trench. According to this embodiment, while forming the first two-step trench in the gate region, it is also possible to leave the SiO2 dielectric layer 22 as a sacrificial layer on the sidewall of the single-step trench adjacent to the first surface of the first two-step trench at the same time. This prevents ions from scattering on the sidewall of the single-step trench adjacent to the first surface of the first two-step trench when forming the first voltage-resistant shield structure 13 in the next process, solving the problem of abnormal channel opening caused by this, ensuring normal operation of the device, and improving the reliability of the device.

[0080] Since the opening of the second removed region is larger than the opening of the first-step trench in the source region, when etching downward, the size of the upper part of the first-step trench becomes larger and the depth of the lower part becomes deeper, thus forming a second two-step trench. According to this embodiment, the SiO2 dielectric layer 22 on the surface of the sidewall, step and bottom of the second two-step trench can be removed, and after forming the second two-step trench in the source region, ion implantation can be performed to form the second voltage-resistant shield structure 14 in the silicon carbide epitaxial layer 11 on the sidewall, step and bottom of the second two-step trench.

[0081] 16 is an SEM image of a two-step trench formed in the source region and the gate region by the manufacturing method described in the embodiment of the present application. From this SEM image, it can be seen that the manufacturing method described in the embodiment of the present application can form two-step trenches in good condition in the gate region and the source region.

[0082] Step S13: As shown in FIGS. 17 to 20, a first voltage-resistant shield structure 13 is formed in the silicon carbide epitaxial layer based on the first trench. A second voltage withstanding shield structure 14 is provided in the surface of the source region, and a well region W is provided in the first surface, located between the first trench 12 and the second voltage withstanding shield structure 14.

[0083] The first trench 12 is a first two-step trench. A multi-step trench 16 is formed in the surface of the source region. Further, a method for manufacturing the first voltage-withstanding shield structure 13 and the second voltage-withstanding shield structure 14 includes: forming the first voltage-withstanding shield structure 13 in a silicon carbide epitaxial layer at the sidewall and bottom of the single-step trench adjacent to the second surface of the first two-step trench, based on the dielectric layer 22 on the sidewall of the first two-step trench and the single-step trench adjacent to the first surface of the first two-step trench; and forming the second voltage-withstanding shield structure 14 in the silicon carbide epitaxial layer at the bottom, steps and sidewalls of the multi-step trench, based on the multi-step trench 16, by implanting ions into the bottom, steps and sidewalls of the multi-step trench 16.

[0084] The multi-step trench 16 may be arranged as a second two-step trench having the same depth as the first two-step trench. In another embodiment, the multi-step trench 16 may be arranged as a three-step trench having a depth greater than the depth of the first two-step trench.

[0085] In step S13, first, as shown in Fig. 17, ion implantation is performed based on the patterned mask layer 21 and dielectric layer 22 to form the first and second voltage-resistant shield structures 13 and 14. Using a high-temperature ion implanter, P+ ions are implanted into the sidewalls and bottom of the trench at 500 to 600°C to form the first and second voltage-resistant shield structures 13 and 14, and then, as shown in Fig. 18, the mask layer 21 and the dielectric layer 22 are removed. Here, the silica mask is removed by a buffered HF wet method, whereby the mask layer 21 and the dielectric layer 22 can be removed.

[0086] For P+ ion implantation in silicon carbide devices, typically the implant ion is Al. The implantation energy ranges from a few hundred KeV to a few MeV, and the dose is 1E12 cm. -2 ~1E16cm -2 The implantation depth can be in the range of several hundred nm to several μm.

[0087] In particular, in the first two-step trench, the sidewall of the single-step trench adjacent to the first surface is blocked by a dielectric layer 22 having a thickness of tens to hundreds of nm per layer, or even on the order of microns, so that during ion implantation, the well region W of the channel region is not affected by P+ ion implantation as the first two-step trench.

[0088] As shown in Fig. 19, Fig. 19 is a SEM image after the first and second voltage-withstanding shield structures 13 and 14 are formed by the manufacturing method according to the embodiment of the present application. From Fig. 19, it can be seen that after the P+ ion implantation is completed, the well region W as the channel region is not affected by the P+ ion implantation, and the reliability and stability of the device are improved.

[0089] As shown in FIG. 20, FIG. 20 is a SEM image of a source region before and after P+ ion implantation by a manufacturing method according to an embodiment of the present application. The left image is a SEM image of a region corresponding to a second two-step trench before P+ ion implantation. The right image is a SEM image of a region corresponding to a second two-step trench after P+ ion implantation. The low brightness region in the right image is a SEM slice image formed after Al ion implantation.

[0090] From the above description, according to the method of the present application using the first two-step trench as the trench gate, the first two-step trench can be formed while leaving the dielectric layer 22 on the sidewall of the single-step trench adjacent to the first surface. Therefore, when ion implantation is performed on the first two-step trench, P+ ion implantation can be performed on the bottom and sidewall of the single-step trench adjacent to the second surface, and doping due to P+ ion scattering on the sidewall of the single-step trench adjacent to the first surface can be avoided, thereby solving the problem of abnormal channel opening in the subsequent trench MOSFET caused by this.

[0091] Step S14: As shown in FIGS. 21 to 23, a gate structure g is formed in the first trench.

[0092] The first trench 12 is a first two-step trench, a multi-step trench 16 is formed in the surface of the source region, and both the first two-step trench and the multi-step trench are filled with polysilicon. The gate structure g includes polysilicon filled in the first two-step trench. An insulating dielectric layer 15 is provided between the first two-step trench and the filled polysilicon, and between the multi-step trench 16 and the filled polysilicon. The gate structure g includes polysilicon filled in the first two-step trench. The insulating dielectric layer 15 is a first insulating dielectric layer 151 located in the first trench 12, and a second insulating dielectric layer 152 located in the multi-step trench 16 as a gate dielectric layer of a trench gate.

[0093] In step S14, first, as shown in FIG. 21, an insulating dielectric layer 15 is formed to cover the first surface, the first trench 12, and the surface of the multi-step trench 16, and the insulating dielectric layer in the first trench 12 is used as a gate dielectric layer of the trench gate. Optionally, the insulating dielectric layer 15 is a SiO2 layer. The insulating dielectric layer 15 can be grown in a high-temperature tube furnace, and oxygen gas can be circulated in the high-temperature tube furnace at 1100°C to 1350°C to oxidize and grow SiO2 on the first surface, the first trench 12, and the surface of the multi-step trench 16 to form the insulating dielectric layer 15. The insulating dielectric layer 15 may have a thickness of 40 to 70 nm.

[0094] 22, after forming an insulating dielectric layer 15, the first trench 12 and the multi-step trench 16 are filled with polysilicon. Silane or DCS gas, Ar, and phosphorus-containing or B-containing doping gas such as phosphorane or borane are circulated in the LPCVD furnace tube at 540°C to 800°C, and polysilicon is generated after a chemical decomposition reaction. The thickness of the polysilicon may be 400 nm to several μm.

[0095] As shown in FIG. 23, the polysilicon is etched using a gas mixture of HBr, chlorine, and oxygen to remove the polysilicon at the first surface.

[0096] Step S15: As shown in FIGS. 24 and 25, a gate metal is formed on a surface of the gate structure g, and a source metal is formed on a surface of the source region, thereby forming the silicon carbide semiconductor device shown in FIG.

[0097] Here, the gate metal G is located on a surface of the polysilicon filled in the first two-step trench, and the source metal S is located on a surface of the polysilicon filled in the multi-step trench 16 .

[0098] In step S15, first, an opening exposing the first surface is formed by etching the insulating dielectric layer 15 on the first surface as shown in Fig. 24. The desired opening is formed by etching the first insulating dielectric layer 15 in a preliminary region on the surface of the source region using an F-based gas such as CHF3 or CF4, or a Cl-containing chlorine-based gas.

[0099] 25, in order to reduce the resistance of contact between the source metal S and the first surface, a metal ohmic contact layer 18 is formed in the opening region of the first insulating dielectric layer 15. A single layer of Ni is PVD deposited in the source region, or a multi-layer metal such as Ti / Ni / Al is PVD deposited in the source region, and the metal other than the source region is removed by peeling or etching, and then rapid thermal processing is performed at 900°C to 1100°C to form the metal ohmic contact layer 18. The thermal processing time can be 30 seconds to 5 minutes.

[0100] Finally, a gate metal G is formed on the surface of the trench gate, a source metal S is formed on the surface of the trench source, and a metal drain electrode D is formed on the surface of one side of the semiconductor substrate 10 away from the silicon carbide epitaxial layer 11, thereby forming the silicon carbide semiconductor device shown in Fig. 3. Note that the following metal processes for the gate and source, the passivation layer, the polyimide PI adhesive, and the back surface drain electrode are all common process methods, so no unnecessary description will be given here. 7 to 25 illustrate an example in which the first trench 12 is a first two-step trench and the source region has a second two-step trench, and the silicon carbide semiconductor device shown in FIG. 3 can be manufactured. In this embodiment, when P+ ion implantation is performed at the bottom of the first two-step trench, the problem that P+ ions are also implanted at the upper sidewall of the trench due to scattering of the mask and the sidewall of the trench when P+ ion implantation is performed using a normal single-step trench design, and the voltage-resistant shield structure is connected to the well region W, which is the channel region, and the channel opening becomes abnormal can be avoided.

[0101] According to the method shown in Figures 7 to 25, a silicon carbide MOSFET device having a two-step trench structure can be formed, and two-step trenches can be formed in both the gate region and the source regions on both sides of the gate region. Specifically, the gate region has a first two-step trench for forming a trench gate, and the source region has a second two-step trench for forming a trench source. The first voltage-resistant shield structure 13 is formed in the silicon carbide epitaxial layer 11 at the bottom and sidewalls of the single-step trench adjacent to the second surface of the first two-step trench, and the second voltage-resistant shield structure 14 is formed in the silicon carbide epitaxial layer 11 at the bottom, sidewalls and steps of the second two-step trench. The two two-step trenches solve the problem of the difficulty in forming a deep P+ shield layer in the silicon carbide material, solve the damage caused by high-dose and high-energy P+ ion implantation and the resulting reliability problems, and achieve better shielding and protection of the trench gate.

[0102] If high energy and high dose ions are used alone to implant more than 1-2 μm, serious ion implantation damage will be caused to silicon carbide materials, which may lead to long-term reliability problems for subsequent devices. In the implementation of the present application, by forming a trench source structure based on a two-step trench in the source region, the implantation of a P+ field shield structure in the source region more than 1-2 μm deep can be easily realized, and the sidewalls and bottom of the trench gate can be well shielded and protected, improving the gate reliability of silicon carbide MOSFET devices.

[0103] In addition, for the trench gate having the first two-step trench, when P+ ion implantation is performed at the bottom of the first two-step trench, the problem in the industry's existing method of manufacturing a trench gate using a single step trench, in which P+ ions may also be implanted into the sidewall of the trench due to scattering on the mask and the sidewall of the trench, resulting in abnormal channel opening of the subsequent trench MOSFET, is prevented.

[0104] In the embodiment of the present application, the silicon carbide semiconductor device and manufacturing process with the two-step trench structure can be applied to the scheme of the multi-step trench structure, which can realize a deeper P+ ion implantation distribution depth and a better electric field shield protection for the gate region, and can also form a semi-superjunction structure. Therefore, in order to form a new P+ ion implantation in the source region to form a deeper second voltage-resistant shield structure 14 in the source region, a three-step trench can be formed in the source region, and a deeper P+ shield protection structure can be formed in the source region to manufacture the silicon carbide semiconductor device shown in FIG. 4. As shown in FIG. 26, FIG. 26 is an SEM image of the three-step trench provided in the embodiment of the present application.

[0105] In another embodiment, the method for forming the second voltage shield structure 14 includes forming an ion implantation region in the source region as the second voltage shield structure 14 by ion implantation. The implantation depth of the ion implantation region is equal to or greater than the depth of the first trench. This embodiment can form the silicon carbide semiconductor device shown in FIG. 6. In this embodiment, a two-step trench structure is formed only in the gate region, and high-energy and high-dose P+ ion implantation is directly adopted in the source region to form the second voltage shield structure 14, thereby providing electric field shielding and protection for the trench gate. Note that the process recipe can refer to the process flow of the device structure shown in FIG. 3, and unnecessary descriptions will not be provided in the embodiments of the present application.

[0106] In another embodiment, the thickness of the insulating dielectric layer 15 at the bottom of the first two-step trench can be arranged to be greater than the thickness of the insulating dielectric layer 15 on each step trench sidewall in the first two-step trench and greater than the thickness of the insulating dielectric layer 15 on the step between two adjacent step trenches. The thickness of the insulating dielectric layer 15 at the bottom of the multi-step trench 16 is greater than the thickness of the insulating dielectric layer 15 on each step trench sidewall in the multi-step trench 16 and greater than the thickness of the insulating dielectric layer 15 on the step between two adjacent step trenches, thus forming the silicon carbide semiconductor device shown in FIG.

[0107] Based on the method shown in Fig. 7 to Fig. 25, the process and structure can be further selectively optimized as follows. After completing the ion implantation and high temperature activation and forming the first and second voltage shield structures 13 and 14, the trenches in the gate and source regions are filled using a CVD SiO2 formation process, and then using an ICP gas or RIE gas plasma etching process with a high selectivity ratio to SiO2:SiC, the SiO2 in the trenches and the first surface is etched back, and the SiO2 in the single-step trench adjacent to the first surface, the first two-step trench, and the first surface of the second two-step trench, and the SiO2 at the bottom of the first and second two-step trenches are etched and removed. Then, the SiO2 on the sidewalls is grown in a high-temperature tube furnace and filled with polysilicon. In this way, a thicker insulating dielectric layer can be formed at the bottom of the first and second two-step trenches, and the voltage resistance capability of the gate dielectric layer at the bottom of the trench gate of the device can be increased, thereby improving the reliability of the device. This process is shown in Figure 27 to Figure 29. The specific method is as follows.

[0108] First, as shown in Fig. 27, a SiO2 layer 31 is filled in the two-step trenches in both the gate region and the source region based on the structure shown in Fig. 18. In order to deposit a relatively dense SiO2 layer 31 on the surface of the two-step trench, a thermal oxidation process, for example, a thermal oxidation silica process such as TEOS or HTO, can be used in a relatively dense furnace tube to react with SiH4 or DCS gas and NO or O2.

[0109] 28, the SiO2 layer 31 on the first surface and the SiO2 layer 31 in the two-step trench are etched away to leave a SiO2 layer 31 of a predetermined thickness in the single-step trench adjacent to the second surface side. In order to leave the SiO2 layer 31 of a predetermined thickness at the bottom of the single-step trench adjacent to the second surface side, a plasma etching process can be employed to perform etchback by selecting a gas with a high etching selectivity ratio to SiO2:SiC, such as C4F8.

[0110] As shown in Fig. 29, an SiO2 layer was grown on the first surface and the surfaces of the two double-step trenches. The SiO2 was grown to a thickness of 40-70 nm in a high-temperature tube furnace at 1100°C to 1350°C while circulating oxygen gas. This SiO2 layer forms an insulating dielectric layer 15 together with the SiO2 layer 31 previously left at the bottom of the trench.

[0111] According to the method shown in Figures 27 to 29, a thicker insulating dielectric layer 15 can be formed at the bottom of the trench, which can further increase the voltage resistance at the bottom of the trench gate of the device, thereby improving the reliability of the device.

[0112] Each embodiment in this specification is described in a gradual, parallel, or gradual and parallel combination, and the description of each embodiment focuses on the differences from other embodiments, so that identical or similar parts between each embodiment may be mutually referenced. The apparatus disclosed in the embodiments corresponds to the method disclosed in the embodiments, so that it is briefly described, but the relevant points may be referenced to the description of the method.

[0113] In the description of the present application, the drawings and the description of the embodiments are illustrative and not limiting. Throughout the embodiments of the present specification, the same structures are given the same reference numerals. In addition, the thickness of some layers, films, panels, regions, etc. may be exaggerated in the drawings for ease of understanding and description. In addition, when an element such as a layer, film, region, or substrate is said to be "on" or "on" another element, it will be understood that the element may be directly on the other element, or intermediate elements may be present. In addition, "on" refers to a certain element being located above or below another element, but does not essentially mean that the element is located above the other element according to the direction of gravity.

[0114] Terms such as "upper", "lower", "top", "bottom", "inside", "outside" and the like are used to indicate an orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are used only to facilitate and simplify the description of this application, and do not suggest or imply that the devices or elements referred to must have a particular orientation, or be constructed and operated in a particular orientation, and therefore should not be understood as a limitation on this application. When a module is considered to be "connected" to another module, there may be a module that is directly connected to the other module, or that is centrally located at the same time.

[0115] It should be noted that relational terms such as first and second herein are used only to distinguish one entity or operation from another and do not require or imply that such a relation or sequence necessarily exists in practice between these entities or operations. Furthermore, terms such as "comprises," "comprises," or other variations thereof are intended to cover a non-exclusive inclusion, such that an article or device comprising a set of elements includes not only those elements but also other elements not expressly listed or inherent to such article or device. Unless further limited, an element defined by a statement "comprises / comprises a ..." does not exclude the presence of other identical elements in an article or device comprising the above elements.

[0116] According to the above description of the disclosed embodiments, those skilled in the art can realize or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Thus, the present application is not intended to be limited to the embodiments disclosed herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. a silicon carbide epitaxial layer having a first surface including a gate region and a source region located on both sides of the gate region, and a second surface opposed to the first surface; a first trench disposed in a surface of the gate region; a first voltage withstanding shield structure formed in the silicon carbide epitaxial layer based on the first trench; a gate structure located in the first trench; a gate metal disposed on a surface of the gate structure; a second voltage withstanding shield structure disposed within a surface of the source region; a source metal disposed on a surface of the source region; a well region in the first surface located between the first trench and the second voltage withstanding shield structure.

2. 2 . The silicon carbide semiconductor device according to claim 1 , wherein the first voltage-withstanding shield structure is located in a depth direction of the first trench on a side toward the second surface of the well region without contacting the well region.

3. the first trench is a first two-step trench; the gate structure comprises polysilicon filled in the first trench, with a first insulating dielectric layer disposed between the first trench and the filled polysilicon; 2. The silicon carbide semiconductor device of claim 1 , wherein the first voltage withstanding shield structure comprises a doped region located in a surface of a sidewall and in a surface of a bottom of a single-step trench toward the second surface of the first double-step trench.

4. a depth of the well region relative to the first surface is less than a depth of a step between two steps of the first two-step trench; 4. The silicon carbide semiconductor device according to claim 3, wherein the first voltage-resistant shield structure is located on a side of a step between two trenches of the first two-step trench, facing the second surface.

5. the first trench is a first two-step trench; The first two-step trench is filled with polysilicon, and a first insulating dielectric layer is provided between the first two-step trench and the filled polysilicon; 2. The silicon carbide semiconductor device of claim 1 , wherein a thickness of the insulating dielectric layer at a bottom of the first two-step trench is greater than a thickness of the insulating dielectric layer on each step trench sidewall in the first two-step trench and is greater than a thickness of the insulating dielectric layer on a step between two adjacent step trenches.

6. A multi-step trench is provided in a surface of the source region, The multi-step trench is filled with polysilicon, and a second insulating dielectric layer is provided between the multi-step trench and the filled polysilicon; 2. The silicon carbide semiconductor device of claim 1, wherein the second withstand voltage shield structure comprises a doped region formed in the silicon carbide epitaxial layer based on the multi-step trench.

7. the first trench is a first two-step trench; the multi-step trench is a second two-step trench; 7. The silicon carbide semiconductor device of claim 6, wherein the first double step trench has the same depth as the second double step trench.

8. the first trench is a first two-step trench; 7. The silicon carbide semiconductor device of claim 6, wherein the multi-step trench is a three-step trench having a depth greater than a depth of the first two-step trench.

9. 7. The silicon carbide semiconductor device of claim 6, wherein the second voltage withstanding shield structure comprises a doped region located in the silicon carbide epitaxial layer on the sidewalls, steps, bottom and around the opening of the multi-step trench.

10. 7. The silicon carbide semiconductor device according to claim 6, wherein a thickness of the second insulating dielectric layer at a bottom of the multi-step trench is greater than a thickness of the second insulating dielectric layer on a trench sidewall of each step in the multi-step trench and is greater than a thickness of the second insulating dielectric layer on a step between trenches of two adjacent steps.

11. 2. The silicon carbide semiconductor device of claim 1, wherein the second withstand voltage shield structure is an ion implanted region formed in the source region.

12. 12. The silicon carbide semiconductor device of claim 11, wherein an implantation depth of said ion implanted region is equal to or greater than a depth of said first trench.

13. providing an epitaxial sheet including a silicon carbide epitaxial layer having a first surface including a gate region and a source region located on both sides of the gate region, and a second surface opposite to the first surface; forming a first trench in the gate region; forming a first voltage withstanding shield structure in the silicon carbide epitaxial layer based on the first trench; forming a gate structure in the first trench; forming a gate metal on a surface of the gate structure; and forming a source metal on a surface of the source region. a second voltage withstanding shield structure is provided within a surface of the source region; the first surface having a well region disposed therein and located between the first trench and the second voltage withstanding shield structure.

14. the first trench is a first two-step trench; A multi-step trench is formed in the surface of the source region, A method for manufacturing the first and second voltage withstanding shield structures includes: performing ion implantation into a sidewall and a bottom of the single-step trench adjacent to the second surface of the first double-step trench based on a dielectric layer on a sidewall of the first double-step trench and a sidewall of a single-step trench adjacent to a first surface of the first double-step trench, thereby forming the first voltage-resistant shield structure in a silicon carbide epitaxial layer on the sidewall and bottom of the single-step trench adjacent to the second surface of the first double-step trench; 14. The manufacturing method according to claim 13, further comprising: performing ion implantation into a bottom of the multi-step trench, steps and sidewalls of each step trench based on the multi-step trench, thereby forming the second voltage-resistant shield structure in a silicon carbide epitaxial layer at a bottom of the multi-step trench, steps and sidewalls of each step trench.

15. the first trench is a first two-step trench; a multi-step trench is formed in a surface of the source region; the first two-step trench and the multi-step trench are both filled with polysilicon; the gate structure comprises polysilicon filled in the first double step trench; an insulating dielectric layer is provided between the first two-step trench and the filled polysilicon, and between the multi-step trench and the filled polysilicon; the gate structure comprises polysilicon filled in the first double step trench; the gate metal is located on a surface of the polysilicon filled in the first double-step trench; 14. The method of claim 13, wherein the source metal is located on a surface of the polysilicon filling the multi-step trench.

16. a thickness of the insulating dielectric layer at the bottom of the first two-step trench is greater than a thickness of the insulating dielectric layer on a trench sidewall of each step in the first two-step trench and is greater than a thickness of the insulating dielectric layer on a step between two adjacent step trenches; 16. The method of claim 15, wherein a thickness of the insulating dielectric layer at a bottom of the multi-step trench is greater than a thickness of the insulating dielectric layer on a sidewall of each step of the multi-step trench and greater than a thickness of the insulating dielectric layer on a step between two adjacent step trenches.

17. the multi-step trench is a second two-step trench having the same depth as the first two-step trench; Alternatively, the multi-step trench is a three-step trench having a depth greater than a depth of the first two-step trench.

18. the method for forming the second voltage-withstanding shield structure includes forming an ion-implanted region as the second voltage-withstanding shield structure in the source region by an ion implantation method; 14. The method of claim 13, wherein the ion implantation region has an implantation depth equal to or greater than the depth of the first trench.

Images