Fiber array with side polishing for improved fiber alignment with wafer substrate or chip

Abstract

A fiber array for edge coupling of at least one optical fiber to at least one wafer substrate is provided, the fiber array including an optical fiber core, a cladding covering the optical fiber core, a V-groove mount on top of the cladding, and a polished tapered lid on the bottom of the cladding.

Description

[Technical field]

[0001] The present embodiments relate generally to photonic integrated circuits (PICs), and more particularly to combining fiber optic components with silicon photonics in PICs. [Background technology]

[0002] Photonic Integrated Circuits (PICs), also called integrated optical circuits or planar lightwave circuits, are devices that integrate many optical and electronic components. PICs are fabricated using lithography on substrates of nonlinear crystalline materials including silicon, silica, or lithium niobate. PICs contain large arrays of identical components that are primarily used in fiber optic communications, optical sensors, and metrology.

[0003] In most cases, the substrate material determines the characteristics and limitations of the PIC, e.g., silica-on-silicon integrated optics built on a silicon wafer. Silica waveguides allow the realization of couplers and filters, splitters and combiners. They can also contain active elements with optical gain connected to optical fibers. One way to combine multiple waveguides is to use fiber arrays. In some cases, the photonic functions are implemented directly on the chip. Silicon nitride (Si3N4) platforms are also used to fabricate photonic devices operating in the 1 μm spectral region or at shorter wavelengths.

[0004] Waveguides are also fabricated on silica glasses, such as fused silica glasses, where the waveguides are fabricated far below the surface, forming buried waveguides that allow for three-dimensional circuit designs. Yet another material used as a substrate is lithium niobate (LiNbO3), a nonlinear crystal material suitable for devices performing nonlinear functions, such as electro-optic modulators or acousto-optic transducers.

[0005] In complex optical transmission systems, efficient fiber-to-chip coupling is very important because optical interconnections between fibers and PICs occur frequently throughout the system. However, the dimensional difference between the substrate waveguide and the fiber diameter poses complex challenges. For example, silicon waveguides have small feature sizes of tens of nm, whereas the typical diameter of a single-mode fiber (SMF) is about 125 μm with a core diameter close to 10 μm. This leads to a large size mismatch between the fiber core and the Si waveguide, which results in significant optical transmission loss when the light emitted from the fiber core directly enters the Si waveguide. Fiber-to-chip couplers are a type of optical component that is key to address this issue in optical interconnections. In general, there are two ways for fiber-to-chip coupling, depending on the relative positions of the fiber and the photonic chip: vertical coupling (or off-plane coupling) and butt coupling (or edge coupling / in-plane coupling). In edge coupling, the fiber is usually placed on the wafer facet and aligned horizontally with the Si waveguide, and edge couplers are commonly applied. Edge couplers achieve high coupling efficiency, wide bandwidth, and polarization independence, but also have some limitations, including a relatively larger footprint than grating couplers, a fixed coupling position, and a more stringent requirement for the coupling facet.

[0006] In telecom and datacom applications, some type of fiber-to-PIC coupling is required for the transfer of optical signals to and from the PIC. Edge coupling is one option that can provide low insertion loss (IL), wide spectral bandwidth (BW), and low sensitivity to polarization. However, in the current standard Si-PIC for edge coupling, deep trench etching is applied to form a high-quality optical interface for edge coupling, but this process creates a protrusion that causes a gap of 20-50um between the fiber core and the edge coupler. This gap causes high optical power loss. To avoid the effect of the protrusion, several solutions have been proposed. One solution involves longitudinally positioned fibers to extend the fibers from the V-groove. However, this is a complex process and does not provide any method to ensure fiber end roughness because fiber end polishing cannot be applied coupled with stability issues. Yet another solution involves removing the bottom fiber array lid for fiber array assembly. However, removing the lid increases the process complexity and cost due to loose control of fiber position and epoxy thickness. Summary of the Invention [Problem to be solved by the invention]

[0007] As shown in Figure 1, in a standard fiber array for optical alignment, there is a 20-50 μm gap between the fiber core and the edge coupler of the PIC, which results in high optical loss. For example, the edge coupler can include silicon oxide, a Si substrate, and a portion of the Si substrate that extends toward the lid of the fiber array. However, increasing the trench depth for the fibers to travel makes the wafer fragile and prone to breakage.

[0008] Figure 2 shows a fiber array extending from a V-groove to reduce the aforementioned gap. However, extending fibers from a V-groove requires complex process control to form such a structure and it is difficult to avoid damage or increased roughness to the fiber end face during formation. The V-groove is monolithically integrated with the PIC and allows low-loss edge coupling with passive alignment to a single fiber or fiber array.

[0009] Figure 3 shows a fiber array without a bottom lid for optical alignment of the fibers and the waveguides. However, the fiber array without a bottom lid is difficult to fabricate and the process becomes complicated. This arrangement also makes it difficult to control the thickness of the epoxy because the positioning of the fibers without the bottom lid becomes loose.

[0010] Therefore, it is important to find a cost-effective solution to address the fiber-to-chip optical interconnection problem in silicon photonics as the number of fiber ports per chip increases. As mentioned above, the challenge to be solved is the optical mode size mismatch between silicon photonics chip waveguides and optical fibers.

[0011] Therefore, a solution remains needed to mitigate the effects on the alignment of the fiber array and the Si-PIC caused by protrusions from the etching process in the edge bonding region. [Means for solving the problem]

[0012] In a first aspect, a fiber array for edge coupling of at least one optical fiber to at least one wafer substrate is provided, the fiber array comprising an optical fiber core, a fiber cladding covering the optical fiber core, a V-groove mount on top of the fiber cladding, and a polished tapered fiber array lid on the bottom of the fiber cladding.

[0013] In an embodiment of the first aspect, the optical fibre core is single mode.

[0014] In an embodiment of the first aspect, the optical fibre core is multimode.

[0015] In one embodiment of the first aspect, the fiber array lid is constructed from a polymer.

[0016] In a second aspect, there is provided an optical integrated circuit comprising a wafer substrate, wherein a fiber array as described herein is bonded in-plane to the wafer substrate.

[0017] In an embodiment of the second aspect, the optical fibre core is single mode.

[0018] In an embodiment of the second aspect, the optical fibre core is multimode.

[0019] In one embodiment of the second aspect, the fiber array lid is constructed from a polymer.

[0020] In one embodiment of the second aspect, the V-groove array is fabricated on a separate silicon submount and edge bonded to the wafer substrate by active alignment.

[0021] In one embodiment of the second aspect, the wafer substrate includes a deep trench structure and the fiber array is aligned over the deep trench structure, the alignment including an angle and position of the fiber array lid, the angle of the fiber array lid being determined by a depth of the deep trench structure.

[0022] In a third aspect, there is provided a method of manufacturing an optical integrated circuit as described herein, the method comprising: a) etching a silicon substrate of a wafer substrate to form a deep trench structure, such that the deep trench structure forms an optical interface for edge coupling; b) performing a first polishing of a fiber array lid to form a polished, tapered fiber array lid over the deep trench structure and aligned with the wafer substrate; c) performing a second polishing of the polished tapered fiber array lid to place the polished tapered fiber array lid adjacent to a silicon oxide substrate; d) In a further step, the optical fiber cores are aligned in close proximity to the silicon oxide substrate to achieve good optical interconnection between the fiber array and the wafer substrate.

[0023] In one embodiment of the third aspect, the angle of the polished tapered fiber array lid is about 30° to 45°.

[0024] These and other aspects of the embodiments of the present invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following description, while indicating preferred embodiments and many specific details thereof, is given by way of illustration and not by way of limitation. Many changes and modifications can be made within the scope of the embodiments of the present invention without departing from the spirit thereof, and the embodiments herein include all such modifications. [Brief description of the drawings]

[0025] Other objects, features and advantages will become apparent to those skilled in the art from the following description of the preferred embodiments and the accompanying drawings.

[0026] [Figure 1] FIG. 1 shows a typical fiber array-based optical integrated circuit.

[0027] [Diagram 2] FIG. 2 shows an expanded fiber array-based integrated optical circuit.

[0028] [Diagram 3] FIG. 3 shows a fiber array-based optical integrated circuit without a bottom lid.

[0029] [Figure 4] FIG. 4 shows a fiber array with a polished tapered lid for bonding the fibers to a wafer substrate to form an integrated optical circuit, according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] In the following detailed description, reference is made to the accompanying drawings, which form a part of this specification, and specific embodiments that may be practiced are described. The embodiments are described in sufficient detail to enable one skilled in the art to practice the embodiments, and it should be understood that logical, mechanical, and other changes may be made without departing from the scope of the embodiments. Therefore, the following detailed description should not be taken in a limiting sense.

[0031] It should be understood that the phraseology and terminology used herein is for the purpose of description and not for the purpose of limitation. Thus, although the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the spirit and scope of the claims.

[0032] As previously mentioned, standard fiber arrays for coupling optical fibers to wafer or substrate waveguides still have several limitations. The present invention and disclosure herein overcomes these limitations by providing a fiber array with a polished tapered lid for coupling optical fibers to a wafer substrate or chip.

[0033] The fiber array 400 of Figure 4 includes fiber cores 402, fiber cladding 404, a fiber array V-groove mount 406, and a tapered fiber array lid 408. The fiber cores 402 are encased in the fiber cladding 404 and held in three-point contact by two V-groove sidewalls 406 and the tapered, angled fiber array lid 408. The bottom fiber array lid 408 can be constructed of a polymer. The fiber cores 402 are surrounded by the fiber cladding 404, and the array is constructed of two layers of cladding 404 on either side of the fiber cores 402.

[0034] In one aspect, the fiber core 402 may be a single mode fiber. In another aspect, the fiber core 402 may be a multimode fiber. In one embodiment, the fiber array lid 408 may have a thickness of at least about 200 μm and gradually tapers toward the edge of the cladding layer 404 as it approaches the wafer substrate 410, as shown in FIG.

[0035] In one aspect, the angle polishing of the fiber array lid 408 can be done based on the conventional method according to the standard fiber array shown in Figure 1. The angle α and the rest of the front end lid need to be controlled so that the fiber core 402 is close to the silicon oxide 412 of the edge coupler. In one embodiment, "close" can refer to including a space or gap between them. In one embodiment, the gap can be zero so that the fiber core and silicon oxide are in abutting contact with each other.

[0036] In one embodiment, the angle α can be approximately 45° and can vary up to approximately 30°. Thus, the angle α can range from approximately 30° to 45° relative to the plane of the bottom cladding layer 404 and the horizontal lower surface.

[0037] The taper of the fiber array lid 408 can be achieved by polishing the fiber array lid 408 to a specific angle that allows the fiber array to be placed in close proximity to the edge coupler. The angle of polishing is predetermined by the deep trench depth in layer 410, and thus the position of the fiber array is controlled by the deep trench bottom stage.

[0038] In one embodiment, the polishing can result in a taper angle of about 45°, which can be varied to about 30° to allow for some height tolerance.

[0039] Fabrication of the fiber array 400 of FIG. 4 is compatible with current mature fiber array assembly processes and associated controls, while at the same time improving stability and alignment accuracy.

[0040] The wafer substrate 410 may be comprised of a silicon substrate layer 410 having a deep trench leaving a portion 401 that extends a distance or gap toward the fiber array lid. The substrate may form a deep trench structure based on the deep trench and the extension portion. The deep trench structure forms an optical interface for edge coupling. The wafer substrate may also include a silicon oxide layer 412 disposed over the wafer substrate.

[0041] In one aspect, the wafer substrate can be referred to as an edge coupler. Thus, the edge coupler can include a silicon oxide layer 412, a silicon substrate layer 410, and a portion 401 of the silicon substrate layer that extends a distance toward the lid of the fiber array.

[0042] In one embodiment, the depth of the trench in layer 410 may be about 120 μm and the gap distance of the horizontally extending portion 401 to the front end of the fiber array may be about 20 to 40 μm, assuming no lid remains on the front end. Silicon oxide layer 412 may be about 5 to 6 μm thick.

[0043] In this regard, an edge-coupled photonic integrated circuit (PIC) can be provided. The PIC can include a wafer substrate 410 and a fiber array 400 having optical fiber cores bonded in-plane with the wafer substrate and surrounded by a fiber cladding 404, with a fiber array V-groove 406 mounted on top of the fiber cladding 404 and a polished tapered lid attached to the bottom of the fiber cladding 404.

[0044] In one embodiment, a hybrid integration approach is preferred: the V-groove array is fabricated on a separate silicon submount and edge-bonded to the wafer substrate by active alignment. The silicon V-grooves precisely position multiple fibers in a one-dimensional array with sub-micron accuracy, allowing simultaneous active alignment of multiple fibers.

[0045] In one embodiment, the core-clad concentricity may be less than 0.5 μm, and the thickness of the cladding 404 and fiber core 402 may be approximately 125+ / -0.7 μm.

[0046] In one embodiment, the thickness of the fiber core 402 may be approximately 8-10 μm, and the thickness of the fiber array V-groove 406 may be approximately 500 μm-1 mm.

[0047] In one embodiment, the fiber array lid 408 can be 200-300 μm thick and polishing can be performed down to the edge of the cladding layer 404 above the lid.

[0048] In one embodiment, an integrated circuit structure is provided. The integrated circuit structure includes a substrate and a deep trench structure in the substrate, where a fiber array lid 408 is aligned over the deep trench structure, where the alignment includes an angle and a position of the fiber array lid. The angle of the fiber array lid is determined by the depth of the deep trench structure, and the position of the fiber array lid is controlled by the horizontally extending bottom of the deep trench structure. The circuit further includes a fiber core disposed between two cladding structures, where the cladding structures are disposed over the fiber array lid. The circuit further includes a fiber array groove 406 disposed on the cladding structure, where the fiber array groove is V-shaped.

[0049] In one aspect, a method for fabricating an optical integrated circuit is provided, the method includes etching a silicon substrate of a wafer substrate to form a deep trench structure, which forms an optical interface for edge coupling, performing a first polish of the fiber array lid 408 to align the fiber array lid 408 with the silicon substrate, whereby the fiber array lid 408 is aligned over the deep trench structure, the first polish forms a polished tapered fiber array lid aligned over the wafer substrate and the deep trench structure, and performing a second polish of the polished tapered fiber array lid to place the polished tapered fiber array lid proximate to a silicon oxide substrate. The above steps are performed to control the angle of placement of the polished tapered fiber array lid and the remainder of the front-end lid. In one example, the fiber cores 402 are proximate to the silicon oxide 412. "Proximate" can refer to the space or gap therebetween. In one embodiment, the gap may be zero. The angle of the fiber array lid is between about 30° and 45°. The main purpose of polishing the fiber array front end and lid is to bring the fiber cores 402 in close proximity to the silicon oxide 412, which ensures good optical interconnection between the fiber array and the PIC.

[0050] It will be appreciated that variations of the above-disclosed and other features and functions, or alternatives thereof, may be desirably combined into many other different systems or applications, and various presently unforeseen or unanticipated alternatives, modifications, variations or improvements may be subsequently made by those skilled in the art, which are also intended to be encompassed by the following claims.

[0051] Although the embodiments of the present disclosure have been described in considerable detail and comprehensively to cover possible aspects, those skilled in the art will recognize that other versions of the present disclosure are possible.

Claims

1. 1. A fiber array for edge coupling of at least one optical fiber to at least one wafer substrate, comprising: An optical fiber core; a fiber cladding covering the optical fiber core; a V-groove mount on top of the fiber cladding; a polished tapered fiber array lid at the bottom of the fiber cladding; Equipped with Fiber array.

2. The fiber array of claim 1 , wherein the optical fiber core is single mode.

3. The fiber array of claim 1 , wherein the optical fiber core is multimode.

4. 10. The fiber array of claim 1, wherein the angle of the polished, tapered fiber array lid is about 30 degrees to 45 degrees.

5. A wafer substrate; a fiber array according to claim 1 bonded in-plane to the wafer substrate; Equipped with Optical integrated circuits.

6. The optical integrated circuit of claim 5 , wherein the optical fiber core is single mode.

7. The optical integrated circuit of claim 5 , wherein the optical fiber core is multimode.

8. 6. The optical integrated circuit of claim 5, wherein the angle of the polished, tapered fiber array lid is about 30 degrees to 45 degrees.

9. The V-groove array is fabricated on a separate silicon submount; Edge-bonded to the wafer substrate by active alignment; 7. The optical integrated circuit according to claim 6.

10. the wafer substrate includes a deep trench structure; the fiber array is aligned over the deep trench structure; the alignment includes an angle and a position of the fiber array lid; the angle of the fiber array lid is determined by the depth of the deep trench structure; 6. An optical integrated circuit according to claim 5.

11. 11. A method for manufacturing an optical integrated circuit according to claim 10, comprising the steps of: a) etching a silicon substrate of a wafer substrate to form a deep trench structure, such that the deep trench structure forms an optical interface for edge coupling; b) performing a first polishing of a fiber array lid to form a polished, tapered fiber array lid above the deep trench structure and aligned with the wafer substrate; c) performing a second polishing of the polished tapered fiber array lid to place the polished tapered fiber array lid adjacent a silicon oxide substrate; d) in a further step, the fiber cores are aligned in close proximity to the silicon oxide to achieve good optical interconnection between the fiber array and the wafer substrate; method.

12. The method of claim 11, wherein the angle of the polished tapered fiber array lid is about 30° to 45°.

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