Hybrid Buck Converter

Abstract

Certain aspects of the present disclosure relate generally to electronic circuits, and more particularly to power supply circuits and techniques for voltage regulation. One exemplary method for voltage regulation is performed by a switched mode power supply (SMPS). The method generally includes charging a first capacitive element during a first discharge phase of an SMPS having a first voltage rail and a second voltage rail, the first voltage rail being separate from the second voltage rail. Charging the first capacitive element may include directing a first current from the second voltage rail through the first capacitive element to a reference potential node. In some aspects, the method also includes generating an output voltage at an output node during the first charge phase by directing a second current from the first voltage rail through the first capacitive element to an inductive element of the SMPS.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. patent application Ser. No. 17 / 653,678, filed Mar. 7, 2022, the entire contents of which are incorporated by reference herein.

[0002]

[0002] Certain aspects of the present disclosure relate generally to electronic circuits, and more particularly, to power supply circuits and regulation. [Background technology]

[0003]

[0003] A voltage regulator ideally provides a constant direct current (DC) output voltage regardless of changes in load current or input voltage. Voltage regulators may be classified as linear regulators or switching regulators. Linear regulators tend to be small and compact, but many applications can benefit from the increased efficiency of switching regulators. A linear regulator may be implemented, for example, by a low-dropout (LDO) regulator. A switching regulator may be implemented by a switched-mode power supply (SMPS), such as a buck converter, a boost converter, or a buck-boost converter.

[0004]

[0004] A power management integrated circuit (power management IC or PMIC) is used to manage the power requirements of a host system and may include and / or control one or more voltage regulators (e.g., boost converters). PMICs can be used in battery-operated devices such as mobile phones, tablets, laptops, wearables, etc. to control the flow and direction of power within the device. The PMIC may perform various functions for the device such as DC-DC conversion (e.g., using voltage regulators as described above), battery charging, power source selection, voltage scaling, power sequencing, etc. For example, a PMIC may feature a buck converter to perform voltage regulation based on a DC input voltage. Summary of the Invention

[0005]

[0005] Certain aspects of the present disclosure relate to a switched mode power supply (SMPS), which generally includes an inductive element coupled to an output of the SMPS, a first switch and a second switch, the first switch being coupled between a first voltage rail and the second switch and the second switch being coupled between the first switch and the inductive element, a third switch coupled between the inductive element and a reference potential node, a fourth switch and a fifth switch, the fourth switch being coupled between a second voltage rail and the fifth switch and the fifth switch being coupled between the fourth switch and the second switch, and a sixth switch coupled between the fifth switch and a reference potential node.

[0006]

[0006] Certain aspects of the present disclosure relate to an apparatus that generally includes a SMPS as described herein, a first battery coupled between a first voltage rail and a reference potential node, and a second battery coupled between a second voltage rail and the first battery.

[0007]

[0007] Certain aspects of the present disclosure relate to a method for voltage regulation by a SMPS. The method generally includes charging a first capacitive element during a first discharge phase of the SMPS, the SMPS having a first voltage rail and a second voltage rail, the first voltage rail being separate from the second voltage rail, a voltage at the first voltage rail being less than a voltage at the second voltage rail, and charging the first capacitive element includes directing a first current from the second voltage rail through the first capacitive element to a reference potential node, and generating an output voltage at an output node during the first charge phase by directing a second current from the first voltage rail through the first capacitive element to an inductive element of the SMPS.

[0008]

[0008] Certain aspects of the present disclosure relate to an apparatus for voltage regulation. The apparatus generally includes an inductive element, a capacitive element, a first voltage rail and a second voltage rail separate from the first voltage rail, the voltage at the first voltage rail being set to be less than the voltage at the second voltage rail, means for charging the capacitive element during a discharge phase of the apparatus, the means including directing a first current from the second voltage rail through the capacitive element to a reference potential node, and means for generating an output voltage at an output node during a charge phase by directing a second current from the first voltage rail through the capacitive element to the inductive element.

[0009] To the accomplishment of the foregoing and related ends, the one or more aspects comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative, however, of only a few of the various ways in which the principles of the various aspects may be employed. [Brief description of the drawings]

[0010]

[0010] In order that the above-mentioned features of the present disclosure may be understood in detail, a more particular description, briefly summarized above, may be obtained by referring to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings show only certain exemplary embodiments of the present disclosure, and therefore should not be considered as limiting the scope of the present disclosure, since the present description may admit of other equally effective embodiments. [Figure 1]

[0011] FIG. 1 is a block diagram of an example of a device including a voltage regulator in which aspects of the present disclosure may be implemented. [Figure 2A]

[0012] FIG. 2A illustrates a stacked battery cell configuration used to generate a voltage rail for a hybrid buck converter in accordance with certain embodiments of the present disclosure; FIG. 2B illustrates a single battery cell configuration used to generate a voltage rail for a hybrid buck converter in accordance with certain embodiments of the present disclosure. [Figure 2B] FIG. 2A illustrates a stacked battery cell configuration used to generate a voltage rail for a hybrid buck converter in accordance with certain embodiments of the present disclosure; FIG. 2B illustrates a single battery cell configuration used to generate a voltage rail for a hybrid buck converter in accordance with certain embodiments of the present disclosure. [Figure 3A]

[0013] 1 illustrates an example of a buck converter with a single battery cell configuration in accordance with certain aspects of the present disclosure. [Figure 3B]

[0014] 1 illustrates an example of a buck converter with a stacked battery cell configuration in accordance with certain aspects of the present disclosure. [Figure 4A]

[0015] 4 illustrates current flow during charging and discharging phases of a Buck converter in accordance with certain aspects of the present disclosure. [Figure 4B] 4 illustrates current flow during charging and discharging phases of a Buck converter in accordance with certain aspects of the present disclosure. [Figure 5A] 4 illustrates current flow during charging and discharging phases of a Buck converter in accordance with certain aspects of the present disclosure. [Figure 5B] 4 illustrates current flow during charging and discharging phases of a Buck converter in accordance with certain aspects of the present disclosure. [Figure 6A] 4 illustrates current flow during charging and discharging phases of a Buck converter in accordance with certain aspects of the present disclosure. [Figure 6B] 4 illustrates current flow during charging and discharging phases of a Buck converter in accordance with certain aspects of the present disclosure. [Figure 7]

[0016] FIG. 2 is a flow diagram illustrating example operations for voltage regulation according to certain aspects of the present disclosure.

[0011]

[0017] For ease of understanding, the same reference numbers have been used, where possible, to designate identical elements common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012]

[0018] Certain aspects of the present disclosure relate to apparatus and techniques for voltage regulation. For example, certain aspects provide a hybrid buck converter that can be configured for single or stacked battery cell configurations. In some aspects, based on an input / output conversion ratio associated with the buck converter, the circuitry and operation of the buck converter can be reconfigured, as described in more detail herein.

[0013]

[0019] Various aspects of the present disclosure will now be described more fully with reference to the accompanying drawings. However, the present disclosure may be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout the present disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art will understand that the scope of the present disclosure is intended to encompass all aspects of the present disclosure disclosed herein, regardless of whether they are implemented independently of or in combination with any other aspects of the present disclosure. For example, an apparatus can be implemented or a method can be practiced using any number of the aspects described herein. In addition, the scope of the present disclosure is intended to encompass such an apparatus or method that is practiced using other structures, functions, or structures and functions in addition to or other than the various aspects of the present disclosure described herein. It will be understood that any aspect of the present disclosure disclosed herein can be embodied by one or more elements of a claim.

[0014]

[0020] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0015] Device example

[0021] 1 illustrates a device 100. Device 100 may be a battery-operated and / or wireless device, such as a cellular telephone, a personal digital assistant (PDA), a handheld device, a wireless modem, a laptop computer, a tablet, a personal computer, a head-mounted or other wearable device, an augmented or virtual reality device, etc. Device 100 is one example of a device that may be configured to implement the various systems and methods described herein.

[0016]

[0022] The device 100 may include at least one processor 104 that controls the operation of the device 100. The processor 104 may also be referred to as a central processing unit (CPU). A memory 106, which may include both read-only memory (ROM) and random access memory (RAM), provides instructions and data to the processor 104. A portion of the memory 106 may also include non-volatile random access memory (NVRAM). The processor 104 typically performs logical and arithmetic operations based on program instructions stored in the memory 106. The instructions in the memory 106 may be executable to perform the methods described herein.

[0017]

[0023] The device 100 may also include a housing 108 that may include a transmitter 110 and a receiver 112 to enable transmission and reception of data between the device 100 and a remote location. The transmitter 110 and the receiver 112 may be combined into a transceiver 114. Multiple antennas 116 may be electrically coupled to the transceiver 114. One or more of the antennas 116 may be disposed adjacent to, attached to, or incorporated into the housing 108. The device 100 may also include multiple transmitters, multiple receivers, and multiple transceivers (not shown).

[0018]

[0024] The device 100 may also include a signal detector 118 that may be used to detect and quantify the level of signals received by the transceiver 114. The signal detector 118 may detect signals such as total energy, energy per subcarrier per symbol, power spectral density, and other signals. The device 100 may also include a digital signal processor (DSP) 120 for use in processing the signals.

[0019]

[0025] Device 100 may further include a battery 122 that is used to power various components of device 100. Device 100 may also include a power management integrated circuit (power management IC or PMIC) 124 to manage the power provided from the battery to the various components of device 100. PMIC 124 may perform various functions for the device, such as DC-DC conversion (e.g., with voltage regulator 125), battery charging, power source selection, voltage scaling, power sequencing, etc. In certain aspects, PMIC 124 may include a buck converter, as described in more detail herein.

[0020]

[0026] The various components of the device 100 may be coupled together by a bus system 126, which may include a power bus, a control signal bus, and a status signal bus in addition to a data bus.

[0021] Example of a Voltage Regulation System

[0027] To shorten the battery charging time and reduce the charging loss, stacked battery cell configurations have been introduced. A stacked battery cell configuration contains two or more battery cells in series (called a 2S battery configuration), whereas a single battery cell configuration (called a 1S battery configuration) contains a single battery cell. In many power management unit (PMU) configurations, the boost or buck-boost converter is the performance bottleneck of the system due to the loop bandwidth of the converter. As a result, it is difficult to meet all system specifications such as high speed, large load current, and small bill of materials (BOM).

[0022]

[0028] In a cellular phone platform, an electronic device may have separate voltage rails (V1 and V2) in the case of a stacked battery cell configuration. Each voltage rail may have a wide operating range, for example, 2V to 5.5V for V1 and 4V to 11V for V2. Thus, a switch mode power supply (SMPS) configured in boost mode operation to convert low voltages to high voltages may be used in some corner operating ranges with some buck-boost or three-level buck-boost architectures. Thus, the loop bandwidth of the SMPS must accommodate boost operation, even though the SMPS may operate in boost mode for only a small portion of the time the SMPS is operated (e.g., one-fifth or one-half).

[0023]

[0029] Certain embodiments use a voltage rail input and charge pump configuration to eliminate boost or buck-boost operation in the SMPS, thereby allowing operation in buck mode only to increase bandwidth. For example, certain embodiments use a single or stacked battery cell configuration to implement a four-level hybrid buck operation. Based on the input / output conversion ratio (e.g., the ratio of battery voltage to output voltage (Vout)), the SMPS provided herein performs buck operation between 3S voltage (e.g., 3 times the 1S voltage) and 2S voltage (e.g., 1S voltage in a single cell configuration or 2 times the 2S voltage in a stacked cell configuration), between 2S and 1S, or between 1S and ground.

[0024]

[0030] 2A and 2B show 2S and 1S battery configurations, respectively, used to generate voltage rails V1 and V2 for a hybrid buck converter. As shown in FIG. 2A, in the case of a 2S battery configuration, a first battery (Batt1) may be used to generate a voltage at rail V1, and a second battery (Batt2) may be used to generate a voltage at rail V2, where the voltage at rail V1 is equal to the battery voltage (Vbatt1) associated with Batt1, and the voltage at rail V2 is equal to Vbatt1 plus the battery voltage (Vbatt2) associated with Batt2. As shown in FIG. 2B, in the case of a 1S battery configuration, Batt1 can be used to provide both V1 and V2, such that V1 is equal to V2, as shown. In other words, voltage rail V1 can be shorted to voltage rail V2 in the case of a 1S battery configuration.

[0025]

[0031] In the 2S battery configuration shown in FIG. 2A, a capacitive element 202 (labeled “C1”), an inductive element 204, and a load capacitive element 206 may be implemented for the buck converter. As shown, the capacitive element 202, the inductive element 204, and the load capacitive element 206 may be external to IC 210 (labeled “Dual Input High Conversion 4 Level Hybrid Buck”) that is used to implement various switches and other components for the buck operation described herein. The capacitive element 202 is coupled between nodes CAP1 and CAP2. As shown in FIG. 2B, for the 1S battery configuration, a capacitive element 212 (labeled “C2”) is implemented between nodes CAP3 and CAP4, external to IC 210. The hybrid buck converters shown in FIGS. 2A and 2B can include the capacitive element 202, the inductive element 204, the load capacitive element 206, and IC 210, while the 1S battery configuration of FIG. 2B can further include the capacitive element 212.

[0026]

[0032] FIG 3A illustrates an example hybrid buck converter 300 with a 1S battery configuration (e.g., single battery cell configuration), and FIG 3B illustrates an example hybrid buck converter 301 with a 2S battery configuration (e.g., stacked battery cell configuration). Hybrid buck converter 300 may be an example implementation of the hybrid buck converter of FIG 2B in a 1S battery configuration. Hybrid buck converter 301 may be an example implementation of the hybrid buck converter of FIG 2A in a 2S battery configuration.

[0027]

[0033] As shown in FIG. 3A for a 1S battery configuration, voltage rails V1 and V2 are shorted together (e.g., effectively forming a single voltage rail). As shown in FIG. 3B for a 2S battery configuration, voltage rails V1, V2 are separate rails. Switch 310 (labeled “P3”) and switch 318 (labeled “P3C”) are coupled in a series path between rail V1 and a switching node (VSW), and inductive element 204 and load capacitive element 206 are coupled in a series path between VSW and a reference potential node 380 (e.g., an electrical ground node). Inductive element 204 is coupled between VSW and a buck converter output node 390. As shown, switch 320 (labeled “N3”) is coupled between VSW and the reference potential node. In certain embodiments, switch 318 may be removed and replaced, for example, with a short.

[0028]

[0034] Additionally, switch 308 (labeled "P2"), switch 314 (labeled "P2C"), and switch 306 (labeled "N2") are coupled in a series path between voltage rail V2 (which is the same as rail V1 in a 1S battery configuration, for example) and a reference potential node 380, and switch 302 (labeled "P1") and switch 304 (labeled "N1") are coupled in another series path between voltage rail V1 and the reference potential node. As shown in FIG. 3A for the 1S battery configuration, capacitive element 212 (labeled "C2") has a first terminal coupled to the node between switches 310, 318 and a second terminal coupled to the node between switches 306, 314, and capacitive element 202 (labeled "C1") has a first terminal coupled to the node between switches 308, 314 and a second terminal coupled to the node between switches 302, 304, as shown. As shown in FIG. 3B for the 2S battery configuration, the node between switches 310, 318 is shorted to the node between switches 306, 314 (as opposed to being coupled via capacitive element 212, e.g., as in FIG. 3A). The switches described herein may be implemented by transistors, such as p-type metal-oxide-semiconductor (PMOS) or n-type metal-oxide-semiconductor (NMOS) transistors.

[0029]

[0035] In certain embodiments in a 2S battery configuration, switch 314 may be removed and replaced with, for example, a short. Additionally or alternatively, in certain embodiments in a 2S battery configuration, switch 306 may be removed and replaced with, for example, a short.

[0030]

[0036] FIG. 4A shows the current flow during the charging and discharging phases when Vout is less than the 1S voltage (e.g., the voltage at rail V1) for a single battery cell configuration. FIG. 4B shows the current flow during the charging and discharging phases when Vout is less than the 1S voltage (e.g., the voltage at rail V1) for a stacked battery cell configuration. The reference potential node 380 and the output node 390 are omitted from FIG. 4A and FIG. 4B (as well as from FIG. 5A-FIG. 6B) for simplicity, but remain in their respective positions as shown in FIG. 3A and FIG. 3B. The output voltage Vout corresponds to the voltage at the output node 390 (relative to the reference potential node 380).

[0031]

[0037] Curve 402 shows the current flow during the charging phase, and curve 404 shows the current flow during the discharging phase. When Vout is less than the 1S voltage, for both the single battery cell configuration shown in FIG. 4A and the stacked battery cell configuration shown in FIG. 4B, during the charging phase, switches 310, 318 are closed (not shown) while switch 320 is open, and during the discharging phase, switches 310, 318 are open while switch 320 is closed (not shown). During the charging phase, current flows from the voltage rail V1 to the inductive element 204, thereby charging the energy stored in the inductive element 204. During the discharging phase, current flows from the reference potential node to the inductive element 204, thereby discharging the energy stored in the inductive element 204.

[0032]

[0038] In certain embodiments where Vout is less than 1S voltage, switches 302, 304, 306, 308 and 314 may be open during the charging and discharging phases.

[0033]

[0039] 5A shows the current flow during the charging and discharging phases when Vout is greater than the 1S voltage (e.g., the voltage at rail V1) and less than the 2S voltage for a 1S battery cell configuration. FIG. 5B shows the current flow during the charging and discharging phases when Vout is greater than the 1S voltage (e.g., the voltage at rail V1) and less than the 2S voltage for a stacked battery cell configuration. For a 1S battery cell configuration, the 2S voltage may be equal to twice the 1S voltage, and for a 2S battery cell configuration, the 2S voltage may be equal to the voltage at rail V2.

[0034]

[0040] 5A, when Vout is greater than the 1S voltage and less than the 2S voltage, during the discharge phase, switches 310, 318, and 306 are closed (not shown) while switches 308, 314, and 320 are open, and during the charge phase, switches 308, 314, and 318 are closed (not shown) while switches 306, 310, and 320 are open. Curves 502, 503, and 504 show the current flow in the hybrid buck converter during the discharge phase, and curves 506, 508 show the current flow in the hybrid buck converter during the charge phase.

[0035]

[0041] During the discharge phase, current flows to the output of the hybrid buck converter and across the capacitive element 212, charging the capacitive element 212 to the 1S voltage, as shown by curves 502, 503, 504 in FIG. 5A for a 1S battery cell configuration. During the charge phase, shown by curves 506, 508, current flows in the opposite direction from voltage rail V2 (e.g., equal to voltage rail V1 in a 1S battery cell configuration), across the capacitive element 212, through the inductive element 204, to the output. Thus, the voltage at node 510 between the capacitive element 212 and the inductive element 204 during the charge phase comprises the sum of the 1S voltage (because voltage rail V2 and the capacitive element 212 are in series during the charge phase) and the voltage across the capacitive element 212 (e.g., also equal to the 1S voltage), which is equal to the 2S voltage (or twice the 1S voltage), allowing regulation of Vout in buck mode to any voltage between the 1S and 2S voltages.

[0036]

[0042] For the 2S battery cell configuration shown in Figure 5B, during the discharge phase, switches 310 and 318 are closed (not shown) while switches 306, 308, 314, and 320 are open, and during the charge phase, switches 308, 314, and 318 are closed (not shown) while switches 306, 310, and 320 are open. Curve 520 shows the current flow of the hybrid buck converter during the discharge phase, and curve 522 shows the current flow of the hybrid buck converter during the charge phase. As shown, during the discharge phase, closing switches 310, 318 allows current to flow from voltage rail V1 to inductive element 204, resulting in the discharge of energy in inductive element 204 since the voltage at rail V1 is less than Vout. During the charging phase, current flows from voltage rail V2 to inductive element 204 by closing switches 308, 314, 318, thereby charging the energy stored in inductive element 204 since the voltage at voltage rail V2 is greater than Vout.

[0037]

[0043] For certain embodiments where Vout is greater than the 1S voltage and less than the 2S voltage, switches 302 and 304 may be open during the charging and discharging phases.

[0038]

[0044] Figure 6A shows the current flow during the charging and discharging phases when Vout is greater than the 2S voltage in a 1S battery cell configuration. Figure 6B shows the current flow during the charging and discharging phases when Vout is greater than the 2S voltage in a stacked battery cell configuration.

[0039]

[0045] For a 1S battery cell configuration, when Vout is greater than the 2S voltage, during the discharge phase, switches 310, 318, 306, 308, and 304 are closed (not shown) while switches 302, 314, and 320 are open, and during the charge phase, switches 302, 314, and 318 are closed (not shown) while switches 304, 306, 308, 310, and 320 are open. Curves 602, 604, 606, 608, and 610 show the current flow in the hybrid Buck converter during the discharge phase, and curves 612, 614, 615, and 616 show the current flow in the hybrid Buck converter during the charge phase.

[0040]

[0046] 6A for a 1S battery cell configuration, during the discharge phase, current flows to the output of the hybrid buck converter and into the capacitive element 212, thereby charging it to the 1S voltage, and current also flows into the capacitive element 202, thereby charging it to the 1S voltage. During the charge phase, current flows from the voltage rail V1 across the capacitive elements 202, 212, through the inductive element 204 to the output. Thus, the voltage at node 510 between the capacitive element 212 and the inductive element 204 during the charge phase is the sum of the 1S voltage at the voltage rail V1, the 1S voltage across the capacitive element 202, and the 1S voltage across the capacitive element 212, which is equal to 3S (e.g., three times the 1S voltage), allowing regulation of Vout in buck mode to any voltage between the 1S and 3S voltages. The current flow in FIG. 6A may represent the high load current case where this 3S capability is selected even though Vout is less than twice the 1S voltage.

[0041]

[0047] 6B, during the discharge phase, switches 308, 314, 318, and 304 are closed (not shown) while switches 302, 306, 310, and 320 are open, and during the charge phase, switches 302, 314, and 318 are closed (not shown) while switches 304, 306, 308, 310, and 320 are open. Curves 626, 628, and 630 show the current flow in the hybrid Buck converter during the discharge phase, and curves 620, 622, and 624 show the current flow in the hybrid Buck converter during the charge phase.

[0042]

[0048] During the discharge phase, current flows from the voltage rail V2 (e.g., having a 2S voltage) through the capacitive element 202 to a reference potential node (e.g., electrical ground node). This causes the capacitive element 202 to be charged to the 2S voltage due to the current flow from the voltage rail V2. Current also flows from the voltage rail V2 through the switches 308, 314, 318 and the inductive element 204 to the output during the discharge phase. During the charge phase, the voltage at node 510 between the capacitive element 202 and the inductive element 204 is the sum of the 1S voltage of the voltage rail V1 and the 2S voltage across the capacitive element 202, which is equal to a 3S voltage (e.g., 2S voltage + 1S voltage), thereby allowing regulation of Vout in buck mode to any voltage between the 2S and 3S voltages. Furthermore, similar to the 1S case of FIG. 6A, the operating mode of FIG. 6B may be selected when Vout is less than the 2S voltage (e.g., for high load currents).

[0043]

[0049] Aspects described herein facilitate operation of a voltage regulator in buck mode regardless of whether Vout is less than a 1S voltage, between a 1S and 2S voltage, or greater than a 2S voltage. Operation in buck mode allows for increased bandwidth associated with an SMPS as compared to conventional SMPS implementations that may operate at least partially in boost mode or buck-boost mode.

[0044] Examples of devices for voltage regulation

[0050] Certain aspects of the present disclosure relate to a switched mode power supply (SMPS) (e.g., hybrid buck converter 300 or 301). The SMPS includes an inductive element (e.g., inductive element 204) coupled to an output of the SMPS, a first switch (e.g., switch 310), a second switch (e.g., switch 318), where the first switch is coupled between a first voltage rail and the second switch and where the second switch is coupled between the first switch and the inductive element, a third switch (e.g., switch 320) coupled between the inductive element and a reference potential node, a fourth switch (e.g., switch 308), a fifth switch (e.g., switch 314), where the fourth switch is coupled between a second voltage rail and the fifth switch and where the fifth switch is coupled between the fourth switch and the second switch, and a sixth switch (e.g., switch 306) coupled between the fifth switch and a reference potential node. In some aspects, the first voltage rail is shorted to the second voltage rail.

[0045]

[0051] In some aspects, the SMPS also includes a capacitive element, such as capacitive element 212. The fifth switch may be coupled between the fourth switch and the second switch through the capacitive element.

[0046]

[0052] In some aspects, the SMPS includes a seventh switch (e.g., switch 302) and an eighth switch (e.g., switch 304). The seventh switch may be coupled between the first voltage rail and the eighth switch, and the eighth switch may be coupled between the seventh switch and a reference potential node. The SMPS may also include a first capacitive element (e.g., capacitive element 202) coupled between the seventh switch and the fifth switch. In some aspects, a first current (e.g., as illustrated by curve 606 in FIG. 6A or curve 626 in FIG. 6B) is configured to flow from the second voltage rail through the fourth switch, the first capacitive element, and the eighth switch to the reference potential node during a discharge phase when the voltage at the output of the SMPS is greater than a first voltage at the first voltage rail and possibly greater than a second voltage (e.g., as described in connection with FIGS. 6A and 6B). Additionally, a second current (e.g., as shown by curves 612, 614, 616 in FIG. 6A or curves 620, 622, 624 in FIG. 6B) is configured to flow from the first voltage rail through the seventh switch, the first capacitive element, the fifth switch, and the second switch to the inductive element during the charging phase. In some aspects, the second voltage is a voltage at the second voltage rail (e.g., for a 2S battery cell configuration). In some aspects, a third current (e.g., as shown by curve 630 in FIG. 6B) is configured to flow from the second voltage rail through the fourth switch, the fifth switch, and the second switch to the inductive element during the discharging phase when the voltage at the output of the SMPS is greater than the first voltage and greater than the second voltage at the second voltage rail. In some aspects, the SMPS also includes a second capacitive element (e.g., capacitive element 212), and the fifth switch is coupled between the fourth switch and the second switch through the second capacitive element.When the voltage at the output of the SMPS is greater than the first voltage at the first voltage rail and greater than twice the first voltage (e.g., for a 1S battery cell configuration), a third current (e.g., as shown by curves 602, 608) is configured to flow from the first voltage rail through the first switch, the second capacitive element, and the sixth switch to the reference potential node during the discharge phase, and a second current is further configured to flow through the second capacitive element to the inductive element.

[0047]

[0053] Any of the first through eighth switches may be implemented by one or more transistors, which may be either p-type transistors, n-type transistors, or a combination of p-type and n-type transistors.

[0048]

[0054] In some aspects, when the voltage at the output of the SMPS is less than the voltage at the first voltage rail (e.g., as shown in FIGS. 4A and 4B), a first current (e.g., as shown by curve 402) is configured to flow from the first voltage rail through the first switch and the second switch to the inductive element during a charging phase, and a second current (e.g., as shown by curve 404) is configured to flow from the reference potential node through the third switch to the inductive element during a discharging phase.

[0049]

[0055] In some aspects, when the voltage at the output of the SMPS is greater than a first voltage (e.g., the voltage at the first voltage rail) and less than a second voltage (e.g., as described in connection with FIGS. 5A and 5B), a first current (e.g., as shown by curve 504 in FIG. 5A or curve 520 in FIG. 5B) is configured to flow from the first voltage rail through the first switch and the second switch to the inductive element during the discharge phase, and a second current (e.g., as shown by curves 506, 508 in FIG. 5A or curve 522 in FIG. 5B) is configured to flow from the second voltage rail through the fourth switch, the fifth switch, and the second switch to the inductive element during the charge phase. In some aspects, the second voltage is the voltage at the second voltage rail.

[0050]

[0056] In some aspects, the SMPS also includes a capacitive element (e.g., capacitive element 212), and the fifth switch is coupled between the fourth switch and the second switch through the capacitive element. When the voltage at the output of the SMPS is greater than the first voltage (e.g., the voltage at the first voltage rail) but less than twice the first voltage, a third current (e.g., as shown by curves 502, 503) is configured to flow from the first voltage rail through the first switch, the capacitive element, and the sixth switch to the reference potential node during the discharge phase. In this case, a second current (e.g., as shown by curves 506, 508) is configured to flow from the second voltage rail through the capacitive element to the inductive element during the charge phase.

[0051] Example of operation for voltage regulation

[0057] 7 is a flow diagram illustrating example operations 700 for voltage regulation in accordance with certain aspects of the present disclosure. The operations 700 may be performed by a switched mode power supply (SMPS), such as the hybrid buck converter 300 or the hybrid buck converter 301.

[0052]

[0058] The operations 700 begin at block 702 with the SMPS charging a first capacitive element (e.g., capacitive element 202) during a first discharge phase of the SMPS, the SMPS having a first voltage rail and a second voltage rail, the first voltage rail being separate from (e.g., not shorted to) the second voltage rail. The voltage at the first voltage rail may be less than the voltage at the second voltage rail, in which case charging the first capacitive element includes directing a first current (e.g., as shown by curves 626, 628) from the second voltage rail through the first capacitive element to a reference potential node. At block 704, the SMPS generates an output voltage at an output node (e.g., output node 390) during the first charge phase by directing a second current (e.g., as shown by curves 620, 622, 624) from the first voltage rail through the first capacitive element to an inductive element of the SMPS. In some aspects, the first current and the second current are directed to flow when the voltage at the output node is greater than the voltage at the second voltage rail.

[0053]

[0059] In some aspects, the first current is directed to flow through a first switch (e.g., switch 308) of the SMPS coupled between the second voltage rail and the first capacitive element, through the first capacitive element, and through a second switch (e.g., switch 304) of the SMPS coupled between the first capacitive element and a reference potential node. In this case, the second current may be directed to flow through a third switch (e.g., switch 302) of the SMPS coupled between the first voltage rail and the first capacitive element, the first capacitive element, and a fourth switch (e.g., switch 318) coupled between the first capacitive element and the inductive element.

[0054]

[0060] In some aspects, the operations 700 further include directing a third current (e.g., as shown by curve 522) from the second voltage rail to flow through the first switch to the inductive element during the second charging phase, and directing a fourth current (e.g., as shown by curve 520) from the first voltage rail to flow through the inductive element through a fifth switch (e.g., switch 310 or 318) of the SMPS coupled between the first voltage rail and the inductive element during the second discharging phase. In some cases, the third and fourth currents may be directed to flow when the voltage at the output node is lower than the voltage at the second voltage rail (and in some cases, higher than the voltage at the first voltage rail).

[0055]

[0061] In some aspects, the operations 700 further include directing a third current (e.g., as shown by curve 402) during the second charging phase to flow from the first voltage rail to the inductive element through a fifth switch (e.g., switch 310 or switch 318) of the SMPS coupled between the first voltage rail and the inductive element, and directing a fourth current (e.g., as shown by curve 404) during the second discharging phase to flow from the reference potential node to the inductive element through a sixth switch (e.g., switch 320) of the SMPS coupled between the reference potential node and the inductive element. In some cases, the third and fourth currents may be directed to flow when the voltage at the output node is lower than the voltage at the first voltage rail.

[0056]

[0062] The various operations of the above-described methods may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and / or software components, including but not limited to circuits, application-specific integrated circuits (ASICs), or processors, and / or various hardware and / or software modules. Generally, when operations are illustrated in figures, the operations may have corresponding equivalent means-plus-function components similarly numbered. For example, the means for charging, the means for directing, and the means for generating may include one or more switches, such as switches 302, 304, 308, 314, 306, 310, 318, 320.

[0057]

[0063] As used herein, the term "determining" encompasses a wide variety of actions. For example, "determining" may include determining, calculating, processing, deriving, investigating, searching (e.g., looking up in a table, database, or another data structure), ascertaining, and the like. "Determining" may also include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), and the like. "Determining" may also include resolving, selecting, choosing, establishing, and the like.

[0058]

[0064] As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items, including single members. As an example, "at least one of a, b, or c" is intended to cover a, b, c, ab, ac, bc, and abc, as well as any combination with multiples of the same element (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other permutation of a, b, and c).

[0059]

[0065] The various example logic blocks, modules, and circuits described in connection with this disclosure may be implemented or performed using a general purpose processor, a digital signal processor (DSP), an ASIC, a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but alternatively, the processor may be any commercially available processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0060]

[0066] The methods disclosed herein include one or more steps or actions for achieving the described method. The steps and / or actions of those methods may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order of specific steps and / or actions and / or the use of those steps and / or actions may be modified without departing from the scope of the claims.

[0061]

[0067] The described functions may be implemented in hardware, software, firmware, or any combination thereof. When implemented in hardware, an exemplary hardware configuration may comprise a processing system in a wireless node. The processing system may be implemented using a bus architecture. The bus may include any number of interconnected buses and bridges depending on the particular application of the processing system and the overall design constraints. The bus may link various circuits together, including the processor, the machine-readable medium, and the bus interface. The bus interface may be used to connect a network adapter, among other things, to the processing system via the bus. The network adapter may be used to implement the signal processing functions of the physical (PHY) layer. In the case of a user terminal, a user interface (e.g., keypad, display, mouse, joystick, etc.) may be connected to the bus. The bus may link various other circuits, such as timing sources, peripherals, voltage regulators, power management circuits, etc., which are well known in the art and therefore will not be described further.

[0062]

[0068] The processing system may be configured as a general-purpose processing system having one or more microprocessors providing processor functionality and external memory providing at least a portion of the machine-readable medium, all linked together with other support circuits through an external bus architecture. Alternatively, the processing system may be implemented using an ASIC having a processor, a bus interface, a user interface (in the case of an access terminal), support circuits, and at least a portion of the machine-readable medium integrated into a single chip, or using one or more FPGAs, PLDs, controllers, state machines, gate logic, discrete hardware components, or any other suitable circuitry, or any combination of circuitry capable of performing the various functions described throughout this disclosure. Those skilled in the art will recognize how to best implement the described functionality for the processing system depending on the particular application and the overall design constraints imposed on the overall system.

[0063] Exemplary Aspects

[0069] In addition to the various aspects described above, specific combinations of aspects are within the scope of the present disclosure, some of which are detailed below.

[0064]

[0070] Aspect 1: A switched mode power supply (SMPS) including: an inductive element coupled to an output of the SMPS; a first switch and a second switch, where the first switch is coupled between a first voltage rail and the second switch, and the second switch is coupled between the first switch and the inductive element; a third switch coupled between the inductive element and a reference potential node; a fourth switch and a fifth switch, where the fourth switch is coupled between a second voltage rail and the fifth switch, and the fifth switch is coupled between the fourth switch and the second switch; and a sixth switch coupled between the fifth switch and the reference potential node.

[0065]

[0071] Aspect 2: The SMPS of aspect 1, further comprising: a capacitive element, the fifth switch being coupled between the fourth switch and the second switch through the capacitive element.

[0066]

[0072] Aspect 3: The SMPS of Aspects 1 or 2, further comprising a seventh switch and an eighth switch, the seventh switch being coupled between the first voltage rail and the eighth switch, and the eighth switch being coupled between the seventh switch and a reference potential node, and a first capacitive element coupled between the seventh switch and the fifth switch.

[0067]

[0073] Aspect 4: The SMPS of Aspect 3, wherein a first current is configured to flow from the second voltage rail through the fourth switch, the first capacitive element, and the eighth switch to the reference potential node during a discharging phase, and a second current is configured to flow from the first voltage rail through the seventh switch, the first capacitive element, the fifth switch, and the second switch to the inductive element during a charging phase.

[0068]

[0074] Aspect 5: The SMPS of aspect 4, wherein a third current is configured to flow from the second voltage rail through the fourth switch, the fifth switch, and the second switch to the inductive element during a discharge phase.

[0069]

[0075] Aspect 6: The SMPS of Aspect 4, further comprising a second capacitive element, wherein a fifth switch is coupled between the fourth switch and the second switch through the second capacitive element, wherein a third current is configured to flow from the first voltage rail through the first switch, the second capacitive element, and the sixth switch to the reference potential node during a discharge phase, and wherein a second current is further configured to flow through the second capacitive element to the inductive element.

[0070]

[0076] Aspect 7: The SMPS of any of Aspects 1-6, wherein the first voltage rail is shorted to the second voltage rail.

[0071]

[0077] Aspect 8: The SMPS of any of Aspects 1 to 7, wherein a first current is configured to flow from the first voltage rail through the first switch and the second switch to the inductive element during a charging phase, and a second current is configured to flow from the reference potential node through the third switch to the inductive element during a discharging phase.

[0072]

[0078] Aspect 9: The SMPS of any of Aspects 1 to 8, wherein a first current is configured to flow from the first voltage rail through the inductive element via the first switch and the second switch during a discharging phase, and a second current is configured to flow from the second voltage rail through the inductive element via the fourth switch, the fifth switch, and the second switch during a charging phase.

[0073]

[0079] Aspect 10: The SMPS of Aspect 9, further comprising a capacitive element, wherein a fifth switch is coupled between the fourth switch and the second switch through the capacitive element, wherein a third current is configured to flow from the first voltage rail through the first switch, the capacitive element, and the sixth switch to the reference potential node during a discharging phase, and a second current is configured to flow from the second voltage rail through the capacitive element to the inductive element during a charging phase.

[0074]

[0080] Example 11: An apparatus including the SMPS of any of Examples 1 to 10, further including a first battery coupled between the first voltage rail and a reference potential node, and a second battery coupled between the second voltage rail and the first battery.

[0075]

[0081] Aspect 12: A method for voltage regulation by a switched mode power supply (SMPS), comprising: charging a first capacitive element during a first discharge phase of the SMPS, the SMPS having a first voltage rail and a second voltage rail, the first voltage rail being separate from the second voltage rail, a voltage at the first voltage rail being less than a voltage at the second voltage rail, and charging the first capacitive element comprising directing a first current from the second voltage rail through the first capacitive element to a reference potential node; and generating an output voltage at an output node during the first charge phase by directing a second current from the first voltage rail through the first capacitive element to an inductive element of the SMPS.

[0076]

[0082] Aspect 13: The method of aspect 12, wherein directing the first current includes directing the first current to flow through a first switch of the SMPS coupled between the second voltage rail and the first capacitive element, through the first capacitive element, and through a second switch of the SMPS coupled between the first capacitive element and a reference potential node, and directing the second current includes directing the second current to flow through a third switch of the SMPS coupled between the first voltage rail and the first capacitive element, the first capacitive element, and a fourth switch coupled between the first capacitive element and an inductive element.

[0077]

[0083] Example 14: The method of example 13, further comprising: directing a third current during the second charging phase from the second voltage rail through the first switch to the inductive element; and directing a fourth current during the second discharging phase from the first voltage rail to the inductive element through a fifth switch of the SMPS coupled between the first voltage rail and the inductive element.

[0078]

[0084] Example 15: The method of example 13, further comprising: directing a third current during the second charging phase to flow from the first voltage rail to the inductive element through a fifth switch of the SMPS coupled between the first voltage rail and the inductive element; and directing a fourth current during the second discharging phase to flow from the reference potential node to the inductive element through a sixth switch of the SMPS coupled between the reference potential node and the inductive element.

[0079]

[0085] Aspect 16: The method of any of aspects 13-15, wherein a first battery is coupled between a first voltage rail and a reference potential node, and a second battery is coupled between a second voltage rail and the first battery.

[0080]

[0086] Aspect 17: An apparatus for voltage regulation comprising: an inductive element; a capacitive element; a first voltage rail and a second voltage rail separate from the first voltage rail, the voltage at the first voltage rail being set to be less than the voltage at the second voltage rail; means for charging the capacitive element during a discharge phase of the apparatus, the means comprising means for directing a first current from the second voltage rail through the capacitive element to a reference potential node; and means for generating an output voltage at an output node during a charge phase, the means comprising means for directing a second current from the first voltage rail through the capacitive element to the inductive element.

[0081]

[0087] It should be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. A switch mode power supply (SMPS), comprising: an inductive element coupled to an output of the SMPS; A first switch; a first switch and a second switch, the first switch being coupled between a first voltage rail and the second switch, and the second switch being coupled between the first switch and the inductive element; a third switch coupled between the inductive element and a reference potential node; The fourth switch a fourth switch and a fifth switch, wherein the fourth switch is coupled between a second voltage rail and the fifth switch, and the fifth switch is coupled between the fourth switch and the second switch; a sixth switch coupled between the fifth switch and the reference potential node; a seventh switch; and an eighth switch, wherein the seventh switch is coupled between the first voltage rail and the eighth switch, and the eighth switch is coupled between the seventh switch and the reference potential node; a first capacitive element coupled between the seventh switch and the fifth switch; Equipped with a first current is configured to flow from the second voltage rail through the fourth switch, the first capacitive element, and the eighth switch to the reference potential node during a discharging phase; a second current is configured to flow from the first voltage rail through the seventh switch, the first capacitive element, the fifth switch, and the second switch to the inductive element during a charging phase; Switched mode power supplies (SMPS).

2. 2. The SMPS of claim 1, wherein a third current is configured to flow from the second voltage rail through the fourth switch, the fifth switch, and the second switch to the inductive element during the discharge phase.

3. a second capacitive element, the fifth switch being coupled between the fourth switch and the second switch through the second capacitive element; a third current is configured to flow from the first voltage rail through the first switch, the second capacitive element, and the sixth switch to the reference potential node during the discharging phase; the second current is further configured to flow through the inductive element via the second capacitive element.

2. The SMPS of claim 1.

4. The SMPS of claim 3 , wherein the first voltage rail is shorted to the second voltage rail.

5. 10. An apparatus comprising the SMPS of claim 1, a first battery coupled between the first voltage rail and the reference potential node; a second battery coupled between the second voltage rail and the first battery; The apparatus further comprises:

6. A method for voltage regulation with a switch mode power supply (SMPS) according to claim 1, comprising: charging the first capacitive element during the first discharge phase of the SMPS, wherein the SMPS has the first voltage rail and the second voltage rail, the first voltage rail being separate from the second voltage rail, a voltage at the first voltage rail being less than a voltage at the second voltage rail, and charging the first capacitive element includes directing the first current from the second voltage rail through the first capacitive element to the reference potential node. generating an output voltage at the output node during a first charging phase by directing the second current from the first voltage rail through the first capacitive element to the inductive element of the SMPS; A method comprising:

7. directing the first current includes directing the first current to flow through the first switch of the SMPS coupled between the second voltage rail and the first capacitive element, through the first capacitive element, and through the second switch of the SMPS coupled between the first capacitive element and the reference potential node; directing the second current includes directing the second current to flow through the third switch of the SMPS coupled between the first voltage rail and the first capacitive element, the first capacitive element, and the fourth switch coupled between the first capacitive element and the inductive element. The method of claim 6.

8. directing a third current from the second voltage rail through the first switch and into the inductive element during a second charging phase; directing a fourth current during a second discharge phase from the first voltage rail to the inductive element through the fifth switch of the SMPS coupled between the first voltage rail and the inductive element; The method of claim 7 further comprising:

9. directing a third current during a second charging phase from the first voltage rail to the inductive element through the fifth switch of the SMPS coupled between the first voltage rail and the inductive element; directing a fourth current during a second discharge phase from the node of reference potential to the inductive element through the sixth switch of the SMPS coupled between the node of reference potential and the inductive element; The method of claim 7 further comprising:

10. 8. The method of claim 7, wherein a first battery is coupled between the first voltage rail and the reference potential node, and a second battery is coupled between the second voltage rail and the first battery.

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