Waveguide-based Single-Photon Avalanche Diode (SPAD)

Abstract

Waveguide-type Single-Photon Avalanche Diode (SPAD). The present disclosure generally relates to a single-photon avalanche diode (SPAD) having a rib waveguide with a doping profile having a multiplication junction, an upper cladding layer disposed on a top surface of the rib waveguide, and a lower cladding layer disposed on a bottom surface of the rib waveguide. The SPAD has an anode, a cathode, and two field plates. The anode, cathode, and two field plates are configured to suppress the electric field on the multiplication junction relative to a SPAD without at least two field plates, and the two field plates and / or cathode are disposed adjacent to the intersection of the multiplication junction and the upper cladding layer.

Description

[Technical field]

[0001] The present disclosure relates to the field of silicon photonics and Single-Photon Avalanche Diodes (SPADs), and more particularly to waveguide-based SPADs. [Background technology]

[0002] FIG. 1 shows a conventional waveguide-based SPAD. This waveguide-based SPAD includes a p-n+ junction diode formed in a silicon rib waveguide. As shown, a rib waveguide with asymmetric etch depth is provided to improve charge carrier collection efficiency by reducing sidewall collisions. The width and length of the rib waveguide account for the absorption of nearly unity for operation in the visible band. This waveguide-based SPAD is clad with SiO2 from the top and bottom. The anode and cathode are symmetrically positioned with respect to the center of the rib waveguide. Furthermore, visible photons are edge-launched or evanescently coupled from a silicon nitride (SiN) channel waveguide into the Si waveguide-based SPAD. Furthermore, the photogenerated charge carriers are swept across a high-field depletion region. Generally, electrons have a higher impact ionization coefficient than holes in silicon. Therefore, to obtain a high multiplication gain, more electrons than holes need to undergo the impact ionization process. By heavily doping the n-side of the p-n+ junction, a depletion region is formed in the p- region, where electrons are the minority carriers. Because the depletion region is formed primarily in the waveguide core, photogenerated electron-hole pairs are effectively separated and swept across the high-field depletion region.

[0003] The single photon avalanche diode (SPAD) has an avalanche breakdown voltage (V br ) reverse bias voltage (V B) photodetectors. In SPAD operation, an incident single photon can trigger an avalanche of secondary charge carrier generation via impact ionization processes, and the device ultimately provides a measurable electrical signal. Recent work to achieve Geiger mode operation in waveguide integrated avalanche photodiodes (APDs) has reported early surface breakdown and subsequent walkout of the breakdown voltage due to charge carrier injection and trapping at the Si / SiO2 interface. This is because as more hot carriers are injected and subsequently trapped in the trap states found at the Si / SiO2 interface, the avalanche breakdown continues, resulting in a breakdown voltage V br This is evidenced by the fact that the

[0004] The multiplication gain of an APD is highly dependent on the electric field strength in the depletion region, which can reach 1MV / cm in Geiger mode operation. However, this strong electric field can be weakened by screening of charge carriers trapped near the depletion region, which ultimately reduces the field-dependent multiplication gain.

[0005] Forming a guard ring (GR) around the depletion region can prevent premature edge breakdown and subsequent charge trapping effects. Therefore, it is widely adopted in normal incidence APDs fabricated in various complementary metal oxide semiconductor (CMOS) technologies. However, the conventional ion implantation and ion diffusion steps to form the GR structure impose stringent process controls for waveguide-based SPADs with submicron dimensions. This is because preserving well-defined doped regions in such small geometries is difficult due to dopant diffusion issues. In addition, some GR structures, such as shallow trench isolation, may further introduce interface trap centers if not properly surface passivated. As a result, various performance indices of Geiger-mode APDs, such as dark count rate and afterpulse probability, are degraded.

[0006] An alternative approach to engineer the electric field inside a semiconductor device utilizes field plates adjacent to the device. For example, such field plates have been shown to improve the breakdown resistance of the gate / drain junctions in high-electron mobility transistors (HEMTs) used in power electronics. However, this type of in situ control of electric field strength has not yet been implemented for waveguide-based APD devices, whose operation relies on very high electric fields but which are prone to premature surface breakdown. Summary of the Invention [Problem to be solved by the invention]

[0007] Thus, there remains a need for a system that eliminates premature surface breakdown and its associated secondary effects to achieve Geiger mode operation of silicon waveguide-based APDs for single photon detection.

[0008] The following summary is provided to facilitate understanding of some of the innovative features unique to the disclosed embodiments and is not intended to be a complete description. A complete understanding of the various aspects of the embodiments disclosed herein can be obtained by considering the entire specification, claims, drawings and abstract as a whole. [Means for solving the problem]

[0009] In a first aspect of the present disclosure, a single photon avalanche diode (SPAD) is provided that includes a rib waveguide having a doping profile that includes a multiplication junction, an upper cladding layer disposed on an upper surface of the rib waveguide, and a lower cladding layer disposed on a lower surface of the rib waveguide. The SPAD further includes an anode, a cathode, and at least two field plates. The anode, the cathode, and the at least two field plates are configured to suppress an electric field on the multiplication junction relative to a SPAD without the at least two field plates, and the two field plates are disposed adjacent to a cross point of the multiplication junction.

[0010] In one embodiment, the doping profile is selected from p+ / i / p / n+, p++ / p / i / n+ / n++, and p++ / p / n+ / n++.

[0011] In one embodiment, the single photon avalanche diode with the multiplication junction is i / n+ or p / n+.

[0012] In one embodiment, the multiplication junction forms a multiplication region when an appropriate bias voltage is applied between the anode and cathode.

[0013] In one embodiment, the diode is reverse biased slightly above the avalanche breakdown voltage of the diode to achieve Geiger mode operation, with the anode being maintained at a lower potential than the cathode, which is electrically grounded.

[0014] In another embodiment, the at least two field plates include a first field plate and a second field plate flanking the rib waveguide adjacent the multiplication junction, which are voltage biased.

[0015] In one embodiment, the anode is disposed at a first end of the rib waveguide and extends vertically to form an anode pillar, and the cathode is disposed at a second end of the rib waveguide and extends vertically to form a cathode pillar. The at least two field plates include a first field plate and a second field plate disposed adjacent to a multiplication junction. The first field plate is formed in an upper cladding layer and the second field plate is formed in a lower cladding layer.

[0016] In one embodiment, the first field plate is asymmetrically positioned between the anode and cathode pillars and is voltage biased.

[0017] In one embodiment, the doping profile of the rib waveguide is p++ / p / n+ / n++, the multiplication junction is p / n+, the first field plate is horizontally displaced a distance Δx from the pn junction over the n+ doped region and vertically displaced a distance d1 from the n+ doped region, and the second field plate is vertically aligned with the first field plate and is horizontally displaced a distance Δx from the pn junction below the n+ doped region and vertically displaced a distance d2 from the n+ doped region.

[0018] In another embodiment, the first and second field plates are coupled to a V B A potential difference of 0.01 V is applied to the multiplication junction to generate an electrostatic potential gradient (i.e., E y ) and improve the diode's resilience against premature surface breakdown.

[0019] In one embodiment, the at least two field plates include a first field plate and a second field plate, where the first field plate having an anode forms an L-shaped extended anode and the second field plate having a cathode forms an L-shaped extended cathode, both extending through the upper cladding layer toward the multiplication junction. The L-shaped extended anode and the L-shaped extended cathode generate an electrostatic potential gradient (i.e., E y ) and improve the diode's resilience against premature surface breakdown.

[0020] In another embodiment, the first field plate extends laterally towards the multiplication junction of the second metal layer of the upper cladding layer.The second field plate extends laterally towards the multiplication junction of the first metal layer of the upper cladding layer.

[0021] In one embodiment, the first field plate and the second field plate are separated horizontally by a gap g.

[0022] In one embodiment, the second field plate extends laterally toward the multiplication junction of the first metal layer with a spacing Δx.

[0023] In another embodiment, the doping profile of the rib waveguide is p++ / p / n+ / n++ and the multiplication junction is p / n+. The second field plate extends from the n++ doped region to the n+ doped region and is vertically displaced from the n+ doped region by a distance d4. The first field plate is horizontally displaced from the second field plate by a gap g and vertically displaced from the p doped region by a distance d3.

[0024] In one embodiment, the first field plate extends into the second metal layer rather than into the first metal layer as does the second field plate, thereby preventing the second field plate from disrupting the field suppression on the n+ doped region and avoiding breakdown between the field plates while maintaining adequate field suppression along the intersection of the p doped region and the upper cladding layer.

[0025] Other objects, features and advantages of the present embodiments will become apparent from the following description when read in conjunction with the accompanying drawings, in which like reference numerals indicate corresponding parts throughout the several views.

[0026] The figures are for illustrative purposes only and are therefore not limiting of the disclosure. [Brief description of the drawings]

[0027] [Figure 1] FIG. 1 illustrates a prior art waveguide-based single-photon avalanche diode (SPAD).

[0028] [Diagram 2] FIG. 2 illustrates a cross-sectional view of a waveguide-based SPAD according to one embodiment of the present disclosure.

[0029] [Diagram 3]FIG. 2 illustrates a cross-sectional view of a waveguide-based SPAD according to another embodiment of the present disclosure.

[0030] [Figure 4] FIG. 4 is a graph showing simulation data illustrating suppression of the electric field in the upper cladding layer between a prior art waveguide (Ref), the waveguide-based SPAD of FIG. 2 (SFP with Δx=0 nm), and the waveguide-based SPAD of FIG. 3 (EFP with Δx=0 nm), in accordance with one embodiment of the present disclosure.

[0031] [Diagram 5] FIG. 4 is a graph showing suppression of the electric field in the lower cladding layer (aka buried oxide layer) between a prior art waveguide (Ref), the waveguide-based SPAD of FIG. 2 (SFP with Δx=0 nm), and the waveguide-based SPAD of FIG. 3 (EFP with Δx=0 nm), according to one embodiment of the present disclosure.

[0032] [Figure 6] FIG. 4 is a graph showing simulated electric field profiles of a prior art waveguide (Ref), the waveguide-based SPAD of FIG. 2 (SFP with Δx=0 nm), and the waveguide-based SPAD of FIG. 3 (EFP with Δx=0 nm), according to one embodiment of the present disclosure.

[0033] [Figure 7] FIG. 4 shows a graph of simulated dark current versus reverse bias voltage for a prior art waveguide-based SPAD (Ref), the waveguide-based SPAD of FIG. 2 (SFP with Δx=0 nm), and the waveguide-based SPAD of FIG. 3 (EFP with Δx=0 nm), according to one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] The embodiments of the present specification and various features and advantageous details thereof will be more fully described with reference to the non-limiting embodiments shown in the accompanying drawings and detailed in the following description. Descriptions of well-known components and processing techniques are omitted so as not to unnecessarily obscure the embodiments of the present specification. The examples used in the present specification are merely intended to facilitate the understanding of how to implement the embodiments of the present specification and to further enable those skilled in the art to implement the embodiments of the present specification. Therefore, the examples should not be interpreted as limiting the scope of the embodiments of the present specification.

[0035] Throughout the prior art, there remains a need for a system that eliminates premature surface breakdown and its associated secondary effects to achieve Geiger mode operation of silicon waveguide-based APDs for single photon detection.

[0036] Thus, there is provided a Single Photon Avalanche Diode (SPAD) disclosed herein that provides a solution to premature surface breakdown by including an electric field modulating plate, also referred to herein as a Field Plate (FP). Specifically, FPs can be placed near the intersection of the waveguide and the multiplication region of the cladding layer, which can be highly defective. These FPs can act to reduce the electric field along the oxide interface, and thus significantly reduce the oxide injection current. Thus, hot carrier injection and trapping at the oxide interface and its breakdown voltage walkout are mitigated.

[0037] The shape and placement of the FP can be configured in any manner such that the electric field strength along the oxide interface is reduced compared to a SPAD that does not include the FP. In particular, the shape and placement of the FP in cooperation with the anode and cathode can suppress the electric field on the multiplication junction of the waveguide.

[0038] The single photon avalanche diodes (SPADs) disclosed herein can provide precise, in situ control of the electric field strength along the oxide interface without the need for additional doping, thus making this approach applicable to other devices that operate at high electric fields.

[0039] In one embodiment, the FP can be formed outside of the SPAD active region and light absorbing region and does not affect the quantum efficiency of the diode. The exemplary FP designs and SPADs disclosed herein are compatible with conventional CMOS manufacturing processes and require only an optional back metallization step.

[0040] Thus, in one embodiment, a SPAD is provided that can include a rib waveguide having a doping profile that includes a multiplication junction, comprising an upper cladding layer deposited on a top surface of the rib waveguide, a lower cladding layer disposed on a bottom surface of the rib waveguide, an anode, a cathode, and at least two field plates, where the anode, cathode, and at least two field plates can be configured to suppress an electric field on the multiplication junction relative to a SPAD that does not include the at least two field plates, and where the at least two field plates and / or cathode can be disposed adjacent to an intersection of the multiplication junction and the upper cladding layer.

[0041] In one embodiment, the rib waveguide can be a Si rib waveguide. The rib waveguide can have a thickness of about 340 nm with an asymmetric etch depth of about 90 nm and a width of about 900 nm. The etch depth can form a rib waveguide structure with p- and n-doped regions defined in both the rib and slab portions of the waveguide, as shown in Figures 1, 2 and 3.

[0042] In one embodiment, the rib waveguide can have a length that describes near unity absorption (e.g., 16 μm at about 640 nm) for operation in the visible band. In one embodiment, the length of the APD / SPAD device can be short or long depending on the operating wavelength. Silicon APD / SPAD devices can be used to detect light with wavelengths shorter than about 1.1 μm. Considering the commonly used near-IR (Infrared light) wavelengths of 850 nm and 905 nm (used for short-range data communication and LIDAR (Light Detection And Ranging) applications, respectively), the length of the device can be up to 200 μm to describe light absorption up to 90%. For blue light absorption, a 5 μm long device can provide near unity absorption. Thus, the length of the rib waveguide can vary from 5 μm to 200 μm depending on the operating wavelength.

[0043] In one embodiment, the device thickness may be constrained by the foundry that produces the device. A thicker Si device layer with asymmetric etch depth may be advantageous to reduce hot carrier sidewall collisions and associated charge trapping effects along the oxide interface. Thus, the rib waveguide may have a thickness from 340 nm to 500 nm.

[0044] In one embodiment, the device width can be varied to not significantly excite higher order modes in the Si waveguide, in particular the device width can be up to 1 μm.

[0045] In one embodiment, the doping profile of the rib waveguide can include one or more doped P regions, one or more doped N regions, and optionally an intrinsic region. In one embodiment, the doping profile can include a combination of regions selected from heavily doped P regions (p++), moderately doped P regions (p+), lightly doped P regions (p), intrinsic regions, lightly doped N regions (n), moderately doped N regions (n+), and heavily doped N regions (n++). Terms such as "lightly doped", "moderately doped", and "heavily doped" are used primarily in relative terms and should be interpreted in the context of otherwise standard features of commercial CMOS manufacturing processes.

[0046] The rib waveguide can be doped with an appropriate dopant to form a desired doping profile. Specifically, the rib waveguide can be doped with dopants such as, but not limited to, boron, gallium, etc. to form a P-doped region. Additionally, the rib waveguide can be doped with dopants such as, but not limited to, arsenic, phosphorus, etc. to form an N-doped region.

[0047] The doping profile of the rib waveguide can be designed such that when an appropriate bias voltage is applied between the contacts, the multiplication junction forms a SPAD multiplication region. In one embodiment, when an appropriate bias voltage is applied between the anode and cathode, the multiplication junction forms a multiplication region.

[0048] In one embodiment, the doping profile can be p+ / i / p / n+ or p++ / p / i / n+ / n++ and the multiplication junction can be p / n+ or i / n+, respectively. In one embodiment, the doping profile can be p++ / p / n+ / n++ and the multiplication junction can be p / n+.

[0049] The SPADs disclosed herein can include a silicon rib waveguide having a p / n+ junction defined in the waveguide core, which can be coupled to a silicon nitride (SiN) channel waveguide for coupling visible / near infrared light into the SPAD.

[0050] In one embodiment, the SPAD can be reverse biased above the avalanche breakdown voltage of the SPAD to achieve Geiger mode operation, and the anode can be maintained at a lower potential than the cathode, which is electrically grounded.

[0051] In one embodiment, the anode is the electrode through which conventional electrical current enters a polarized electrical device. The cathode is the electrode through which conventional electrical current exits an electrical device. The anode is disposed at a first end of the rib waveguide and can be contacted above the p-doped region. The anode provides a negative breakdown voltage (i.e., −V B <-V br ) a voltage slightly more negative than -V B can be biased to

[0052] In one embodiment, a cathode may be disposed at the second end of the rib waveguide and contact the n-doped region above the cathode. The cathode may be connected to electrical ground.

[0053] In one embodiment, the anode can be disposed at a first end of the rib waveguide and extend vertically to form an anode pillar, and the cathode can be disposed at a second end of the rib waveguide and extend vertically to form a cathode pillar.

[0054] In one embodiment, the doping profile of the rib waveguide can be p++ / p / n+ / n++, with the anode contacting the p++ doped region and the cathode contacting the n++ doped region.

[0055] In one embodiment, the anode can be maintained at a lower potential than the cathode, which is electrically grounded (i.e., −V B <0V).

[0056] In one embodiment, the anode and cathode can be symmetrically positioned with a distance of about 3 μm between them. As will be appreciated by those skilled in the art, the distance between the anode and cathode can vary and be subject to the manufacturing rules of the manufacturing plant. In one embodiment, the anode and cathode can be symmetrically positioned with a distance of about 2 μm to 5 μm between them.

[0057] In one embodiment, the anode and cathode may be made from common metals used in CMOS processes, such as aluminum and copper.

[0058] In one embodiment, the upper and lower cladding layers refer to the cladding above and below the rib waveguide, respectively. The upper and lower cladding layers can be made of silicon dioxide (SiO2) material. Because SiO2 material is a good dielectric material, SiO2 material can provide better isolation in the waveguide-based SPAD.

[0059] In one embodiment, the upper cladding layer may have a thickness of about 1 to 3 μm.In one embodiment, the lower cladding layer may have a thickness of about 1 to 3 μm.

[0060] Silicon oxide can be deposited on top of the rib waveguide as an upper cladding layer, serving to insulate the anode, cathode, and conductive channel of the waveguide-based SPAD.

[0061] In one embodiment, a substrate layer can be disposed below the lower cladding layer. The substrate layer can be composed of a material such as, but not limited to, silicon (Si). The substrate layer can be partially etched and metallized to enable electric field suppression along the bottom oxide interface of the SPAD multiplication region. In one embodiment, the substrate layer can be a conductive substrate layer by a back metallization process.

[0062] In one embodiment, the distance (d2) between the substrate layer and the lower cladding layer may range from about 500 nm to about 1 μm.

[0063] In one embodiment, the at least two field plates can include a first FP and a second FP configured such that the electric field strength along the oxide interface is reduced compared to the absence of the FPs (e.g., FIG. 1). In particular, the shape and arrangement of the at least two field plates can cooperate with the anode and cathode to suppress the electric field on the multiplication junction of the waveguide.

[0064] In one embodiment, one of the at least two field plates can be horizontally separated or displaced from the vertical axis or plane of the multiplication junction by a distance Δx. In one embodiment, the distance Δx can be about 0 nm. In one embodiment, the distance Δx can be within ±100 nm.

[0065] In one embodiment, the at least two field plates can be positioned asymmetrically such that the electric field intensity is higher on one side of the multiplication junction. In one embodiment, the at least two field plates can be positioned to suppress the electric field intensity along the oxide interface of the multiplication region. For example, the at least two field plates can be positioned adjacent to the p / n+ junction where the multiplication region and the absorption region overlap, and more specifically, on the n+ doped side.

[0066] The at least two field plates may be constructed from materials such as, but not limited to, aluminum or copper.

[0067] (Sandwich Field Plate (SFP)) In one embodiment, the at least two field plates may be concave biased field plates that sandwich a rib waveguide SPAD, and thus this configuration of field plates may be referred to as a sandwiched field plate (SFP).

[0068] In one embodiment of the SFP, the at least two field plates may include a first FP and a second FP that sandwich a rib waveguide adjacent to the multiplication junction and may be electrically biased by a voltage source.

[0069] In one embodiment of the SFP, a first FP may be formed inside the upper cladding layer, and a second FP may be formed inside the lower cladding layer.

[0070] In one embodiment of the SFP, the first FP may be asymmetrically positioned between the anode and the cathode.

[0071] In one embodiment of the SFP, the doping profile of the rib waveguide may be p++ / p / n+ / n++ and the multiplication junction p / n+, the first FP may be horizontally displaced a distance Δx from the multiplication junction over the n+ doped region and vertically displaced a distance d1 from the n+ doped slab region, and the second FP may be vertically aligned with the first FP and horizontally displaced a distance Δx from the multiplication junction below the n+ doped region and vertically displaced a distance d2 from the n+ doped slab region. In particular, Δx refers to the distance between the pn junction and the left edge of the FP located on the right side (RHS) of the device.

[0072] In one embodiment of the SFP, the distance d1 may range from about 500 nm to 1 μm. In one embodiment, the distance d1 may be about 500 nm.

[0073] In one embodiment of the SFP, the distance d2 may range from about 500 nm to 1 μm. In one embodiment, the distance d2 may be about 500 nm.

[0074] In one embodiment of the SFP, V B A potential difference of E is applied to the first FP and the second FP to generate an electrostatic potential gradient (i.e., Ey ) and improve the resilience of the diode against early surface breakdown.

[0075] The bias field plate configuration of the SFP can be fabricated via an additional back metallization process for user-controlled oxide field suppression. In one embodiment, the second FP can be formed by a back metallization process.

[0076] In one embodiment, SFPs can be fabricated starting from an SOI wafer, through etching and ion implantation steps of Si device layers. Then, a SiSPAD can be formed containing doped Si rib waveguides and covered with silicon oxide on top as the first interlayer dielectric. Before the metallization step, the wafer being handled can be selectively etched near the pn junction. Then, a metal layer can be deposited to form the anode and cathode, followed by etching of the top oxide cladding near the highly doped p++ and n++ doped regions. The top oxide layer can be selectively etched with a mask set to form the top field plate. Similarly, the bottom field plate is formed by a back metallization step, and finally, a bond pad opening step is performed on the oxide covered electrodes for electrical contact formation.

[0077] In particular, the first and second FPs can be fabricated to be located near a moderately doped region (i.e., an n+ doped region) of the p-n+ junction, where the electric field strength at the oxide interface is higher.

[0078] FIG. 2 shows an exemplary embodiment of a single-photon avalanche diode (SPAD) 100 configured with a sandwich-type field plate, where the waveguide has a doping profile of p++ / p / n+ / n++ with a multiplication junction of p / n+.

[0079] The waveguide-based SPAD 100 includes a first FP 126 formed adjacent to and over the n+ doped region 116 and horizontally displaced a distance Δx from the p-n+ junction 118. Specifically, the first FP 126 is asymmetrically disposed between the anode 110 and the cathode 112 such that the first FP 126 is adjacent to the n+ doped region 116.

[0080] The first FP 126 is formed in the second metal layer 130 of the upper cladding layer 104 opposite the first metal layer 132 including only a portion of the anode and cathode. Furthermore, the first FP 126 is formed at a distance (d1) from the n+ doped silicon slab region 124. Specifically, the distance (d1) between the first FP 126 and the n+ doped silicon slab region 124 may range from about 0.5 μm to about 1 μm.

[0081] The second FP 128 is formed in the lower cladding layer 106 and is located in the same vertical plane as the first FP 126. The second FP 128 extends within the lower cladding layer 106 across the entire height of the substrate layer 108. The second FP 128 is formed at a distance (d2) from the n+ doped silicon slab region 124. Specifically, the distance (d2) between the first FP 126 and the n+ doped silicon slab region 124 may range from about 0.5 μm to about 1 μm.

[0082] The first FP 126 and the second FP 128 are formed by a two-step metallization process. The first FP 126 and the second FP 128 sandwich the rib waveguide and facilitate reducing the electric field strength along the silicon / oxide interfaces (i.e., the interface between the rib waveguide 102 and the upper cladding layer 104 and the interface between the rib waveguide 102 and the lower cladding layer 106).

[0083] Sandwiching the rib waveguide between the first FP 126 and the second FP 128 increases the breakdown voltage of the p / n+ junction by pushing the high electric field from the rib waveguide edges towards the SPAD core. Additionally, sandwiching between the first FP 126 and the second FP 128 distributes the electric field lines more evenly within the depletion region, creating a more concentrated impingement region within the waveguide core.

[0084] The first FP126 and the second FP128 are connected to ground (i.e. -V B ) with the same magnitude and opposite polarity as the voltage applied to the anode (i.e., V B Specifically, the first FP 126 and the second FP 128 can be biased to a positive voltage V B , which is a voltage biased by the y-axis at the intersection of the p / n+ junction and the cladding layer (e.g., the upper cladding layer 104 and the lower cladding layer 106) interface, creating a gradient of electrostatic potential along the y-axis (i.e., the vector component of the electric field along the y-axis E y ) can be reduced.

[0085] (Extended Field Plate (EFP) configuration) In one embodiment, the at least two field plates can be configured by optimizing the footprint of the anode and cathode. The at least two field plates can extend the cathode / anode toward the multiplication junction to suppress the electric field intensity along the silicon / oxide interface. Therefore, this configuration of field plates and the deformation of the anode and cathode can be called an extended field plate (EFP).

[0086] Thus, the SPAD disclosed herein can utilize a field plate formed by optimizing the anode / cathode footprint in a two-level metallization process to improve the resilience of the SPAD to premature surface breakdown.

[0087] In one embodiment of the EFP, the at least two field plates may include a first FP and a second FP.

[0088] The first FP is formed by optimizing the footprint of the anode to extend toward the multiplication junction of the second metal layer. Similarly, the second FP is formed by designing the footprint of the cathode to extend toward the multiplication junction of the first metal layer. In this regard, the extended anode and extended cathode are configured to optimize the electrostatic potential gradient (i.e., E y ) can be suppressed to improve the resilience of the diode against premature surface breakdown.

[0089] In one embodiment of the EFP, the extended anode and the extended cathode may be separated by a gap g, which may range from about 300 nm to 500 nm, preferably about 300 nm. As will be appreciated, a smaller gap g may increase the electric field strength between the extended FPs and cause breakdown of the upper cladding layer for high bias voltages, while a larger gap g reduces the effect of the extended anode on the p-doped region relative to the fixed position of the extended cathode.

[0090] In one embodiment of the EFP, the extended anode and the extended cathode can be formed in an L-shape. The L-shaped extended anode and the L-shaped extended cathode can function as a first and a second field plate, respectively. In this regard, the first field plate and the anode can form the same structure. Similarly, the second field plate and the cathode can form the same structure.

[0091] In one embodiment of the EFP, the L-shaped cathode can extend horizontally toward the multiplication junction of the first metal layer a distance Δx, and the L-shaped anode can extend laterally toward the multiplication junction of the second metal layer a distance g-Δx relative to the multiplication junction.

[0092] In one embodiment of the EFP, the doping profile of the rib waveguide is p++ / p / n+ / n++ and the multiplication junction is p / n+. Thus, the L-shaped cathode can extend from the n++ doped region to the n+ doped region and can be vertically displaced from the n+ doped silicon slab region by a distance d4. Furthermore, the L-shaped first FP can extend from the p++ doped region to the p doped region, separated by a distance g from the L-shaped cathode and vertically displaced by a distance d3 from the p doped region.

[0093] In one embodiment of the EFP, the distance d3 ranges from about 1 μm to 1.5 μm, and is preferably about 1 μm. As will be appreciated, the greater the distance d3, the greater the bias voltage V B For , the induced electric field at the top of the p-doped rib waveguide section is reduced.

[0094] In one embodiment of the EFP, the distance d4 may range from about 0.5 μm to 0.75 μm, preferably about 0.5 μm. As will be appreciated, a longer distance d4 may result in a larger bias voltage V B This reduces the effect of electric field suppression in the n-doped rib waveguide section on the

[0095] In one embodiment of the EFP, the lower cladding layer can have a thickness d5. This distance d5 is also the distance that separates the lower surface of the waveguide from the substrate layer. In one embodiment of the EFP, the distance d5 can be about 0.7 μm to 3 μm.

[0096] In one embodiment of the EFP, the first FP can be extended into the second metal layer to prevent electric field enhancement on the n+ doped region and breakdown between the extended anode and the extended cathode while maintaining adequate electric field suppression along the intersection of the p-doped region and the upper cladding layer.

[0097] FIG. 3 shows an example embodiment of a single photon avalanche diode (SPAD) 200 configured with extended field plates, where the waveguide 102 has a doping profile of p++ / p / n+ / n++ with the multiplication junction 118 being p / n+.

[0098] The waveguide-based SPAD 200 includes an L-shaped extended anode 226, 226a and an L-shaped extended cathode 228, 228a, which also function as first and second field plates, respectively. The extended field plates are formed by forming the footprints of the anode and cathode into an L-shape. Both L-shaped extended field plates are contained within the first metal layer 132 and second metal layer 130 of the upper cladding layer 104.

[0099] The waveguide-based SPAD 200 is designed and constructed to optimize the footprint of the anode and cathode on different metal layers to reduce the electric field strength along the oxide interface. Note that the combination of the anode and first field plate 226, 226a forms an extended anode, and the combination of the cathode and second field plate 228, 228a forms an extended cathode.

[0100] The first FP 226 is formed by extending the anode over the doped p++ region. Specifically, the first FP 226 forms an L-shaped extended anode with a horizontal portion 226a extending through the upper cladding layer 104 toward the p / n+ multiplication junction 118. The horizontal portion 226a is also formed at a distance (d3) from the p-doped silicon slab region 114.

[0101] The second FP 228 is formed by extending the cathode over the doped n++ region. Specifically, the second FP 228 forms an L-shaped extended cathode with a horizontal portion 228a extending through the upper cladding layer 104 toward the p / n+ multiplication junction 118, with a distance Δx between the multiplication junction 118 and the horizontal portion 228a. Because the electric field strength along the interface between the p / n+ junction and the upper cladding layer 104 is highest at the n-doped region 116, the horizontal portion of the second FP 228a is located closer to this region than the horizontal portion of the first FP 226a, providing better electric field suppression. The horizontal portion 228a is formed a distance (d4) away from the n+ doped silicon slab region 116.

[0102] In the embodiment of FIG. 3, Δx refers to the distance from the left edge of the horizontal portion of the second FP 228a to the pn junction 118.

[0103] The horizontal portion of the first FP 226a and the horizontal portion of the second FP 228a define a horizontal gap (g) therebetween. The horizontal gap (g) can be configured such that the electric field suppression achieved along the interface between the n+ doped region 116 and the upper cladding layer 104 is not disturbed, while maintaining sufficiently high electric field suppression along the interface of the p doped silicon slab region 114 and the upper cladding layer 104 interface. EXAMPLES

[0104] A series of Technology Computer Aided Design (TCAD) simulations were performed to model the SPAD embodiments disclosed herein with variations in their device geometries and doping configurations. Specifically, optimization studies were performed to suppress the electric field intensity along the oxide interface by varying the distance Δx between the pn junction and the left edge of the FP located in the RHS of the device. In the simulation results below, the distance Δx is 0 nm.

[0105] 4 shows a graph 400 between the X coordinate at 5 nm above the rib waveguide versus the electric field associated with a prior art waveguide-based SPAD (reference), a waveguide-based SPAD 100 (SFP), and a waveguide-based SPAD 200 (EFP), according to one embodiment of the present disclosure. As shown, the EFP design suppresses the peak electric field in the upper cladding without extending the high-field oxide interface, while the SFP design provides better electric field suppression at the expense of slightly widening the high-field oxide interface.

[0106] In particular, Figure 4 shows the electric field profile along a lateral cut taken 5 nm above the top of the silicon rib waveguide to show the electric field intensity along the SiSPAD / top oxide interface. The x-axis of the graph shows the position along the cut. x=0 μm corresponds to the center of the rib waveguide. The y-axis shows the electric field intensity in Megavolts (MV) per cm. Figure 4 clearly shows that the SFP and EFP designs suppress the electric field intensity along the top oxide interface compared to the reference device.

[0107] 5 shows a graph 500 between the X coordinate at 5 nm below the rib waveguide and the electric field associated with a prior art waveguide-based SPAD (reference), a waveguide-based SPAD 100 (SFP), and a waveguide-based SPAD 200 (EFP), according to one embodiment of the present disclosure. As shown, the EFP design with a grounded substrate reduces the electric field along the bottom oxide surface, such that the maximum electric field is no longer at the oxide interface but within the depletion region. Additionally, the SFP performs better in suppressing the peak electric field strength, albeit at the expense of additional electrode formation and bias conditions.

[0108] In particular, Figure 5 shows the electric field profile along a cut line taken 5 nm below the silicon rib waveguide to show the electric field intensity along the SiSPAD / bottom oxide interface. The x-axis of the graph shows the position along the cut line. x=0 μm corresponds to the center of the rib waveguide. The y-axis shows the electric field intensity in units of MV / cm. Figure 5 clearly shows that the SFP and EFP designs suppress the peak electric field intensity along the bottom oxide interface compared to the reference device.

[0109] 6 illustrates a simulated electric field profile 600 according to embodiments and configurations of the present disclosure. These graphs show that the SFP and EFP designs can suppress localized electric fields along the oxide interface, thus preventing premature surface breakdown of the device.

[0110] In particular, Figure 6 shows a TCAD simulation of the cross-sectional profile of the electric field intensity near the multiplication region. Here, the device is modeled with the device structure and doping profile. A bias voltage near the breakdown voltage of the corresponding device is applied between the electrodes and the resulting electric field profile is plotted as a 2D contour map. Here, the full cross-section of the device, including the electrodes and the entire rib waveguide, is simulated. However, only the multiplication region is shown to better illustrate the effect. Figure 6 clearly shows that the highest electric field intensity at the top and bottom oxide interfaces occurs in the reference device. However, the SFP and EFP designs suppress the electric field towards the rib waveguide core, leading to a more uniform distribution of the electric field lines in the waveguide core. Thus, a more uniform multiplication region is achieved.

[0111] 7 shows a graph 700 of simulated dark current versus reverse bias voltage for a prior art waveguide-based SPAD (reference), the waveguide-based SPAD of FIG. 2 (SFP), and the waveguide-based SPAD of FIG. 3 (EFP), in accordance with one embodiment of the present disclosure. As shown in FIG. 7, the use of a field plate compared to the reference device results in avalanche breakdown of the device at higher bias voltages due to suppression of the electric field along the oxide interface.

[0112] It will be appreciated that variations of the above-disclosed and other features and functions, or alternatives thereof, may be desirably combined into many other different systems or applications, and various presently unforeseen or unanticipated alternatives, modifications, variations, or improvements may be subsequently made by those skilled in the art, which are also intended to be encompassed by the following claims.

[0113] Although the embodiments of the present disclosure have been described in considerable detail and comprehensively to cover possible aspects, those skilled in the art will recognize that other versions of the present disclosure are possible.

Claims

1. A Single-Photon Avalanche Diode (SPAD), a rib waveguide having a doping profile that includes a multiplication junction; an upper cladding layer disposed on an upper surface of the rib waveguide; a lower cladding layer disposed on a lower surface of the rib waveguide; An anode; A cathode; at least two field plates; Equipped with the anode, the cathode and the at least two field plates are configured to suppress an electric field on a multiplication junction relative to a SPAD not including the at least two field plates; At least two of the field plates are disposed adjacent to the intersection of a multiplication junction.

2. The doping profile is p+ / i / p / n+, p++ / p / i / n+ / n++, p++ / p / n+ / n++, 2. The single photon avalanche diode of claim 1 , wherein the single photon avalanche diode is selected from:

3. 3. The single photon avalanche diode of claim 2, wherein the multiplication junction is i / n+ or p / n+.

4. 4. The single photon avalanche diode of claim 1, wherein the multiplication junction forms a multiplication region when an appropriate bias voltage is applied between the anode and the cathode.

5. 2. The single photon avalanche diode of claim 1, wherein the diode is reverse biased slightly above an avalanche breakdown voltage of the diode to achieve Geiger mode operation, the anode being maintained at a lower potential than the cathode, and the cathode being electrically grounded.

6. 2. The single photon avalanche diode of claim 1, wherein the at least two field plates include a first field plate and a second field plate that sandwich the rib waveguide adjacent the multiplication junction, and which are voltage biased.

7. the anode is disposed at a first end of the rib waveguide and extends vertically to form an anode pillar; the cathode is disposed at a second end of the rib waveguide and extends vertically to form a cathode pillar; the first field plate and the second field plate are disposed adjacent to the multiplication junction; the first field plate is formed in an upper cladding layer; The single photon avalanche diode of claim 6 , wherein the second field plate is formed in a lower cladding layer.

8. 8. The single photon avalanche diode of claim 7, wherein the first field plate is asymmetrically positioned between the anode pillar and the cathode pillar and is voltage biased.

9. the doping profile of the rib waveguide is p++ / p / n+ / n++ and the multiplication junction is p / n+; the first field plate is horizontally displaced from the pn junction by a distance Δx above the n+ doped region and vertically displaced from the n+ doped region by a distance d1; 7. The single photon avalanche diode of claim 6, wherein said second field plate is displaced horizontally from said pn junction below said n+ doped region by a distance Δx and vertically from said n+ doped region by a distance d2.

10. The y-axis along the interface between the multiplication junction and the upper cladding layer (i.e., E ｙ ) to suppress the electrostatic potential gradient of the first field plate and the second field plate, thereby improving the resilience of the diode against premature surface breakdown. Ｂ 7. The single photon avalanche diode of claim 6, wherein a potential difference of

11. the at least two field plates include a first field plate and a second field plate; the first field plate with the anode forms an L-shaped extended anode and the second field plate with the cathode forms an L-shaped extended cathode, both of which extend through the upper cladding layer toward the multiplication junction; The L-shaped extended anode and the L-shaped extended cathode are configured to define an electrostatic potential gradient (i.e., E ｙ 2. The single photon avalanche diode of claim 1, wherein the first and second photons are electrically isolated from each other by a first charge coupled to the first electrode.

12. the first field plate extends laterally toward the multiplication junction of a second metal layer of the upper cladding layer; 12. The single photon avalanche diode of claim 11, wherein the second field plate extends laterally toward the multiplication junction of a first metal layer of the upper cladding layer.

13. 12. The single photon avalanche diode of claim 11, wherein the first field plate and the second field plate are separated laterally by a gap g.

14. 13. The single photon avalanche diode of claim 12, wherein the second field plate extends laterally a distance Δx toward a multiplication junction of the first metal layer of the upper cladding layer.

15. the doping profile of the rib waveguide is p++ / p / n+ / n++ and the multiplication junction is p / n+; The second field plate extends from the n++ doped region to the n+ doped region and is a vertical distance d from the n+ doped region. ４ Displacement by The first field plate is horizontally displaced from the second field plate by a gap g and is a distance d from the p-doped region. ３ 15. The single photon avalanche diode of claim 14, wherein the diode is vertically displaced by

16. The first field plate suppresses the n-doped region by the second field plate while maintaining adequate electric field suppression along the intersection of the p-doped region and the upper cladding layer. ＋ 16. The single photon avalanche diode of claim 15, wherein the field plates extend into the second metal layer of the upper cladding layer to prevent disturbance of electric field suppression on doped regions and to avoid breakdown between the field plates.

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