Epitaxial nitride ferroelectric devices and methods of operation thereof

Abstract

An epitaxial nitride ferroelectric device and method of operation are provided. The device includes a substrate and a heterostructure supported by the substrate. The heterostructure includes a semiconductor layer supported by the substrate and a ferroelectric III-nitride alloy layer supported by the semiconductor layer. The ferroelectric III-nitride alloy layer includes a group IIIB element. The device further includes first and second contacts in electrical communication with the ferroelectric III-nitride ferroelectric alloy layer and the semiconductor layer, respectively. The polarity of a poling voltage applied between the first and second contacts is adapted to establish a state of ferroelectric polarization in the ferroelectric III-nitride alloy layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application entitled "Epitaxial Nitride Ferroelectric Device," filed on February 23, 2022, and assigned Serial No. 63 / 313,002, the disclosure of which is expressly incorporated herein by reference in its entirety. STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0002] This invention was made with Government support under Contract No. N00014-19-1-2225 awarded by the US Office of Naval Research. The Government has certain rights in this invention. [Technical field]

[0003] The present invention relates generally to ferroelectric III-nitride materials. [Background technology]

[0004] The ability to control and tune the electric polarization of semiconductor materials has been explored to enable the design and development of many types of devices, including, for example, microelectronic memory devices for neuromorphic computing and artificial intelligence, reconfigurable filters for mobile communications, micro / nanoelectromechanical systems, and tunable two-dimensional electron / hole gas (2DEG / 2DHG) heterojunctions. Wurtzite III-nitride semiconductors, e.g., AlN, GaN, InN and their alloys, have strong polarization effects along the c-axis, including spontaneous and piezoelectric polarization. However, the polarization direction of conventional III-nitrides cannot be electrically switched without causing dielectric breakdown.

[0005] Recent theoretical studies have suggested that ferroelectric switching in III-nitride semiconductors could potentially be achieved by the incorporation of other noble metal elements and / or strain engineering. For example, the incorporation of Sc into AlN induces a distortion of the wurtzite crystal structure, i.e., a decrease in the c / a ratio accompanied by an increase in the internal u parameter. The resulting tendency to transform to a planar hexagonal structure leads to a destabilization of the crystal structure and an enhancement of the piezoelectric response. As a result, the electric field for ferroelectric polarization switching is higher than that of the wurtzite Sc. x Al 1-x This can potentially be reduced below the dielectric breakdown limit of N.

[0006] Sc x Al 1-x The synthesis and characterization of N has been investigated. x Al 1-x The few studies on N have focused mainly on sputter deposition and investigated ferroelectric switching in the resulting materials. However, ScN has been grown using molecular beam epitaxy (MBE) or metalorganic chemical vapor deposition (MOCVD) for ferroelectric switching. x Al 1-x The controlled synthesis of III-N is also of interest. Epitaxial growth offers significantly improved material quality and allows seamless integration with III-N device technologies. Pure wurtzite phase Sc with Sc contents up to 0.4 has been synthesized using MBE. x Al 1-x Further studies confirmed that the energy band gap decreases linearly with increasing Sc composition, in good agreement with theory. x Al 1-x We have revealed that N is optically active, but the emission is dominated by oxygen vacancy-related emission. x Al 1-x There have been no reports on ferroelectric switching of N. Summary of the Invention

[0007] According to one aspect of the disclosure, a device includes a substrate, a heterostructure supported by the substrate, the heterostructure including a semiconductor layer supported by the substrate and a III-nitride ferroelectric alloy layer supported by the semiconductor layer, the III-nitride ferroelectric alloy layer including a Group IIIB element, and first and second contacts in electrical communication with the III-nitride ferroelectric alloy layer and the semiconductor layer, respectively, where a polarity of a poling voltage applied across the first and second contacts establishes a state of ferroelectric polarization of the III-nitride ferroelectric alloy layer.

[0008] According to another aspect of the present disclosure, a device includes a substrate and a heterostructure supported by the substrate, the heterostructure including a semiconductor layer supported by the substrate and a III-nitride ferroelectric alloy layer supported by the semiconductor layer, the III-nitride ferroelectric alloy layer including a group IIIB element, the semiconductor layer doped to configure the semiconductor layer as an electrode layer having a charge carrier concentration that supports resistive switching of the polarization state of the ferroelectric III-nitride alloy layer.

[0009] According to another aspect of the present disclosure, a memory device includes a substrate, a heterostructure supported by the substrate, the heterostructure including a semiconductor layer supported by the substrate and a ferroelectric III-nitride alloy layer supported by the semiconductor layer, the ferroelectric III-nitride alloy layer including a group IIIB element, and a control circuit in electrical communication with the ferroelectric III-nitride alloy layer and the semiconductor layer for applying a poling voltage and a read voltage across the ferroelectric III-nitride alloy layer and the semiconductor layer, respectively. The polarities of the poling voltages respectively establish a state of ferroelectric polarization of the ferroelectric III-nitride alloy layer. The read voltage is a voltage level that generates a current through the heterostructure, the current having a level indicative of a state of ferroelectric polarization.

[0010] According to yet another aspect of the present disclosure, a method of operating a memory device includes applying a poling voltage across a heterostructure of the memory device to establish a polarization state of a ferroelectric III-nitride layer of the heterostructure, the ferroelectric III-nitride layer being supported by a semiconductor layer of the heterostructure and the ferroelectric III-nitride alloy layer including a Group IIIB element; applying a read voltage across the heterostructure; and determining a level of current through the heterostructure in response to the read voltage to read out the polarization state.

[0011] In relation to any one of the preceding aspects, the device and / or method described herein may alternatively or additionally include or involve any combination of one or more of the following aspects or features: The ferroelectric III-nitride alloy layer is in either a first polarization state or a second polarization state. In the first polarization state, a current through the heterostructure is at a first level in response to a read voltage applied between the first contact and the second contact. In the second polarization state, the current is at a second level in response to the read voltage. The first level is higher than the second level. The ferroelectric III-nitride alloy layer contacts the semiconductor layer to establish a heterointerface. The ferroelectric III-nitride alloy layer and the semiconductor layer are lattice matched. The ferroelectric III-nitride alloy layer is single crystalline. The ferroelectric III-nitride alloy layer has a wurtzite structure. The semiconductor layer is doped to configure the semiconductor layer as an electrode layer with a charge carrier concentration that supports resistive switching of the polarization state of the ferroelectric III-nitride alloy layer. The semiconductor layer includes Si-doped GaN. The semiconductor layer is in contact with a substrate. The ferroelectric III-nitride alloy layer includes ScAlN. The ferroelectric III-nitride alloy layer has a scandium content of about 18%. The ferroelectric III-nitride alloy layer is in contact with the semiconductor layer to establish a heterointerface. The ferroelectric III-nitride alloy layer and the semiconductor layer are lattice matched. The ferroelectric III-nitride alloy layer has a single crystal wurtzite structure. The semiconductor layer is Si-doped. The ferroelectric III-nitride alloy layer includes ScAlN. Applying the poling voltage includes selecting a level of the poling voltage to modulate the conductance of the polarization state. Applying the poling voltage includes selecting a level of the poling voltage based on an operating temperature. Applying the read voltage includes selecting a level of the read voltage based on an operating temperature. Applying the read voltage is performed without performing a cooling procedure.

[0012] For a more complete understanding of the present disclosure, reference should be made to the following detailed description and the accompanying drawings, in which like reference numerals identify like elements throughout. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 shows atomic force microscope (AFM) images of epitaxially grown ScxAl1-xN layers exhibiting ferroelectric properties according to an example, along with graphical plots of polarization-electric field (PE) loops for example ferroelectric layers having a range of scandium contents. [Diagram 2] FIG. 1 shows graphical plots of current density as a function of electric field for several epitaxially grown ScxAl1-xN layers according to some embodiments, along with graphical plots of coercive field, breakdown field, and remnant polarization for various levels of scandium content in the epitaxially grown ScxAl1-xN layers according to some embodiments. [Diagram 3] FIG. 1 illustrates a graphical plot of polarization after positive and negative polarization of an epitaxially grown ScxAl1-xN layer in accordance with an example, and a graphical plot of transient current and voltage profiles during positive-up and negative-down (PUND) measurements of an epitaxially grown ScxAl1-xN layer in accordance with an example. [Figure 4] FIG. 10 illustrates a graphical plot of remanent polarization during durability testing of an epitaxially grown ScxAl1-xN layer in accordance with an example, as well as a graphical plot of current density as a function of electric field for an epitaxially grown ScxAl1-xN layer after various numbers of switching cycles in accordance with an example. [Diagram 5] FIG. 1 illustrates a graphical plot of leakage current as a function of applied voltage for an epitaxially grown ScxAl1-xN layer in accordance with an example. [Figure 6] FIG. 1 is a flow diagram of a method for fabricating a heterostructure having an epitaxially grown ferroelectric wurtzite structure, according to an example. [Figure 7A] FIG. 1 illustrates a cross-sectional schematic of a ferroelectric field effect transistor (FeFET) memory cell having a single crystal or monocrystalline layer of an alloy of III-nitride material (e.g., ScAlN) between a gate electrode and a source-drain conduction region to provide reversible electrical states, according to one example. [Figure 7B]FIG. 13 is a cross-sectional schematic diagram of a ferroelectric field effect transistor (FeFET) memory cell having a single crystal or monocrystalline layer of an alloy of III-nitride material (e.g., ScAlN) between the gate electrode and the source-drain conduction regions to provide reversible electrical states, according to another example. [Figure 8] FIG. 1 is a cross-sectional schematic diagram of a ferroelectric transistor random access memory cell having a metal-ScxAl1-xN-metal capacitor and a silicon or GaN based write-read transistor according to an example. [Figure 9A] 1 is a cross-sectional schematic diagram of a ferroelectric tunnel junction (FTJ) memory device having a single crystal layer of an alloy of III-nitride materials (eg, ScxAl1-xN), according to one example. [Figure 9B] FIG. 1 is a cross-sectional schematic diagram of a ferroelectric tunnel junction (FTJ) memory device having a single crystal layer of an alloy of III-nitride materials (e.g., ScxAl1-xN) according to another example. [Figure 10A] 1 is a cross-sectional schematic diagram of metal-polarity and N-polarity ferroelectric high electron mobility transistor (Fe-HEMT) devices, each having a single crystal layer of an alloy of III-nitride materials (e.g., ScxAl1-xN), according to one example. [Figure 10B] 1A-1C are cross-sectional schematic diagrams of metal-polarity and N-polarity ferroelectric high electron mobility transistor (Fe-HEMT) devices, each having a single crystal layer of an alloy of III-nitride materials (e.g., ScxAl1-xN), according to another example. [Figure 11A] FIG. 1 is a cross-sectional schematic diagram of a reconfigurable Fe-HEMT device having a single crystal layer of an alloy of III-nitride materials (e.g., ScxAl1-xN), according to one example, where the polarization direction indicated by the green arrow in the ferroelectric layer under the gate can be reconfigured by applying an electric field that exceeds the coercive field. [Figure 11B]FIG. 1 is a cross-sectional schematic diagram of a reconfigurable Fe-HEMT device having a single crystal layer of an alloy of III-nitride materials (e.g., ScxAl1-xN), according to one example, where the polarization direction indicated by the green arrow in the ferroelectric layer under the gate can be reconfigured by applying an electric field that exceeds the coercive field. [Figure 12] 1 is a cross-sectional schematic diagram of a ferroelectric-photovoltaic device having a single crystal layer of an alloy of III-nitride materials (e.g., ScxAl1-xN) as a photon absorbing layer, according to an example. [Figure 13A]

[0023] FIG. 1 is a cross-sectional schematic diagram of ferroelectric photovoltaic devices, according to an example, each having a single crystalline layer of an alloy of III-nitride material (e.g., ScxAl1-xN) to provide one or more ferroelectric regions, and further having a single crystalline layer of III-nitride material as a photon absorbing layer. [Figure 13B]

[0023] FIG. 1 is a cross-sectional schematic diagram of ferroelectric photovoltaic devices, according to an example, each having a single crystalline layer of an alloy of III-nitride material (e.g., ScxAl1-xN) to provide one or more ferroelectric regions, and further having a single crystalline layer of III-nitride material as a photon absorbing layer. [Figure 14] FIG. 2 is a cross-sectional schematic diagram of a lateral homojunction device having a single crystal layer of an alloy of III-nitride materials (e.g., ScxAl1-xN) to provide one or more ferroelectric regions, according to an example. [Figure 15] 1 is a schematic diagram of an epitaxial ScAlN / GaN heterostructure according to an example, along with graphical plots of the XRD 2θ-ω scan, PV and IV loops, polarization loops, and amplitude and phase patterns for the example. [Figure 16] FIG. 13 illustrates graphical plots of resistive switching behavior in a ScAlN / GaN heterostructure memory, including graphical plots of IV hysteresis loop, read on / off current levels, retention time, and bipolar switching stability, in accordance with an example. [Figure 17]1 is a graph of conductivity and polarization change measurements of a ScAlN / GaN heterostructure memory according to an example, including a graph of current level showing conductivity hysteresis loop and pulse width dependence. [Figure 18] 1 is a schematic diagram of an energy band diagram for an ScAlN / GaN heterostructure memory in accordance with an example, along with a graphical plot of current level and on / off ratio as a function of charge carrier concentration; [Figure 19] 1 is a graphical plot of PV loop, on / off current levels, and on / off ratio measurements during high temperature operation. [Figure 20] 1 is a schematic diagram of a memory device having a heterostructure with a ferroelectric III-nitride alloy layer according to an example. [Figure 21] 1 is a flow diagram of a method of operating a memory device having a heterostructure with a ferroelectric III-nitride alloy layer, according to an example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] The embodiments of the devices and methods disclosed below may assume various forms. Specific embodiments are shown in the drawings and described below, with the understanding that the disclosure is intended to be exemplary. The disclosure is not intended to limit the invention to the specific embodiments described and illustrated herein.

[0015] Methods are described for the growth of epitaxial (e.g., fully epitaxial) ferroelectric alloys of III-nitride materials. The disclosed methods are configured to incorporate scandium (Sc) or other IIIB elements into the wurtzite crystal structure of III-nitride materials. Ferroelectric III-nitride alloy layers can be achieved using molecular beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), pulsed laser deposition (PLD), and other non-sputter epitaxial growth techniques. The disclosed methods may or may not include the implementation of a post-growth annealing procedure. Devices and structures including such materials are also described. For example, various heterostructures and ferroelectric electronic devices having one or more ferroelectric III-nitride alloy layers are described.

[0016] The disclosed devices and structures include one or more single crystals or single crystalline layers of an alloy of III-nitride materials, such as Sc grown by molecular beam epitaxy (MBE). x Al 1-x The ferroelectric switching is exhibited in GaN films. In some cases, the layers are grown on GaN templates or other III-nitride semiconductor layers. Still other types of semiconductor layers may be used. Sc films with varying Sc content (e.g., Sc content x in the range of about 0.14 to about 0.36) have been used. x Al 1-x The ferroelectric properties of some example N films are presented by polarization and current density versus electric field (PE and JE, respectively) measurements. The polarization retention time and fatigue behavior of the examples are also presented. x Al 1-x All the N films show ferroelectricity. 0.20 Al 0.80 For N, a coercive field of about 4.2MV / cm at 10kHz was measured, and the remanent polarization was about 135μC / cm 2 Further testing showed that up to 3 × 10 5The devices showed no obvious fatigue behavior after 100 switching cycles. The disclosed methods and devices demonstrate the feasibility of controlling the electric polarization of III-V semiconductors grown by MBE and other non-sputter epitaxial growth procedures (e.g., MOCVD, HVPE, and PLD). The use of epitaxial growth procedures allows for thickness scaling (e.g., into the nanometer regime). Epitaxial growth can be useful in the fabrication of a wide range of applications in electronic, photonic, optoelectronic, and ferroelectric devices.

[0017] In some instances, Sc x Al 1-x The N films were grown using a Veeco GENXpolar MBE system equipped with a radio frequency (RF) plasma source. In these examples, a Si-doped GaN layer is first grown on a GaN / sapphire template, which can be used as the bottom contact layer. Sc x Al 1-x N layers were grown on n-GaN. The layers can have a thickness of about 100 nanometers (nm), but the thickness may vary. The Sc content can be varied by adjusting the Sc / Al flux ratio, which can be further confirmed by energy dispersive X-ray spectroscopy (EDS). The electrical properties of these examples were analyzed by a Radiant Precision Multiferroic II Ferroelectric Test System. Ferroelectric characterization of these examples was performed on parallel plate capacitors with 100 nm thick Pt circular top electrodes structured by lift-off and indium solder dots placed on the n-GaN as bottom electrodes. The diameter of the top electrodes was varied in the range of 20-50 μm. The PE and JE hysteresis loops of these examples were measured with a triangular voltage. Standard positive up and negative down (PUND) measurements with a pulse width of 10 μs and an interpulse delay of 1 ms were used to detect ferroelectric loss in fatigue tests of the examples.

[0018] Epitaxially grown Scx Al 1-x Although described with respect to the example of an N-layer, the disclosed methods and devices can be applied to a wide variety of III-nitride alloys. Thus, the disclosed methods and devices can include or involve the incorporation of scandium into other III-nitride wurtzite structures. For example, the disclosed methods and devices can be used to incorporate scandium into one or more epitaxially grown ScN layers. x Al y NGa 1-x-y N layer, Sc x Ga 1-x N layer, or Sc x In 1-x The heterostructure may include or include a N layer. The composition, structure, fabrication, and other characteristics of the heterostructure may also differ from the described examples. For example, the heterostructure may include any number of epitaxially grown layers, both ferroelectric and non-ferroelectric. The disclosed methods and devices are not limited to III-nitride alloys that include scandium. For example, III-nitride alloys may include additional or alternative group IIIB elements, such as yttrium (Y) and lanthanum (La).

[0019] Although described in the context of examples having a III-nitride alloy layer adjacent to (e.g., epitaxially grown on) a III-nitride semiconductor layer, the disclosed methods and devices are not limited to heterostructures that include a III-nitride semiconductor layer as a template, base, or other component. For example, some examples are described in which a III-nitride alloy layer is grown on or otherwise supported by a metal layer, such as an aluminum layer. Other types of materials, additional or alternative, including, for example, other semiconductor materials, may also be used in the heterostructure.

[0020] Although the disclosed method is described in relation to an MBE growth procedure, additional or alternative non-sputter epitaxial growth procedures may be used. For example, metalorganic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), atomic layer deposition (ALD), and atomic layer epitaxy (ALE) growth procedures may be used. Still other procedures may be used, including, for example, pulsed laser deposition procedures.

[0021] Part A of FIG. 1 shows a ScP grown according to an example of the disclosed method. 0.20 Al 0.80 An example of N membrane 10×10μm 2 An atomic force microscope (AFM) image of 10×10 μm 2 The corresponding root mean square (RMS) roughness obtained from the scanned area of ​​is about 1.1 nm. Other examples described herein show similar surface morphologies.

[0022] Part B of FIG. 1 shows the polarization-electric field (PE) loops shown by the examples. Ferroelectric Sc ​​with various Sc contents x Al 1-x PE loops were measured at 40 kHz for N. In these examples, the Sc content x was varied from about 0.14 to about 0.36. Further details regarding the examples are provided below.

[0023] The disclosed method produces many wurtzite phase Sc x Al 1-x was used to grow a ScN / GaN heterostructure. x Al 1-x The N layer exhibited ferroelectric switching behavior. The Sc content, x, varied from about 0.14 to about 0.36 in the examples. The Sc content can be outside this range.

[0024] As described herein, the growth conditions (e.g., growth temperature) are controlled to reduce (e.g., minimize) the formation of leakage current paths, which are useful in establishing the ferroelectric properties of the layer.

[0025] The PE loop shown in part B of Figure 1 was collected with a triangular voltage input having a frequency of 40 kHz. x Al 1-x The N films exhibited clear hysteresis loops due to ferroelectricity and showed clear ferroelectric polarization reversal over the entire Sc content range mentioned above. The near-ideal box-like shape of each of the PE loops indicates uniform incorporation of Sc and high crystal quality. Since the wurtzite structure has a strong spontaneous polarization only along the c-axis, the domain rotation is configured to 180°, which significantly enhances the coercive field compared to other ferroelectric materials such as PZT and In2Se3. In some instances, the unclosed PE loops and unclear polarization saturation can be attributed to non-negligible leakage currents at very high electric fields. Leakage current compensation was not applied to the data presented herein.

[0026] Part A of Figure 2 shows the corresponding JE loop measured with the same triangular voltage input having a frequency of 10 kHz. x Al 1-x The ferroelectric nature of each example N film is clearly supported by instances of switching current. Each case is indicated by a respective black arrow in the graph plot. The increase in current density upon application of a large electric field above the level of the coercive field EC is especially evident for the Sc 0.14 Al 0.86 N and Sc 0.36 Al 0.64 For N, it shows a large contribution from leakage current. Nevertheless, the current bump due to electric dipole switching is still shown in the graph plot. In this example, Sc 0.36 Al 0.64 The leakage current of the N film is the highest. This is mainly due to the deterioration of material quality and the decrease of band gap with increasing Sc incorporation. Defect formation such as high density threading dislocations, stacking faults, and point defects can act as leakage paths. Despite such leakage paths, the leakage current of the ScN film with lower Sc content (e.g., x below about 0.10) and higher Sc content (e.g., x above 0.40) is significantly higher than that of the NN film with higher Sc content (e.g., x above 0.40). x Al 1-xLayers of N may also exhibit ferroelectric switching behavior.

[0027] Part B(i) of FIG. 2 shows, for example, the average coercivity levels over a range of Sc content levels. x Al 1-x The average coercivity of the N film [Ec=(E + cE - c) / 2] can be estimated from the PE and JE loops shown in Figure 1, part B and Figure 2, part A. The EC values ​​reported by Fichtner et al. (measured at 711 Hz)15 and Yasuoka et al. (measured at 100 KHz) are also plotted in Figure 2, part B(i) for comparison. The distortion of the robust wurtzite structure with increasing Sc content, i.e., the shift of the internal u parameter towards that of the hexagonal structure (u = 1 / 2), has been experimentally demonstrated to facilitate polarization switching. Thus, a polarization switching of about 5.7 MV / cm (Sc 0.14 Al 0.86 N) to about 3.4MV / cm (Sc 0.36 Al 0.64 The nearly linear decrease in Ec with increasing Sc content (N) is believed to result from the gradual lowering of the polarization switching barrier with increasing Sc content. It should also be noted that the Ec estimated from the JE loop is slightly lower than that obtained from the PE loop. This is due to the different frequencies used for measuring PE (40 kHz) and JE (10 kHz). Usually, when applying short pulses, a relatively large electric field is used to perform polarization switching. That is, the Ec increases with increasing measurement frequency. Considering the effect of measurement frequency, the polarization switching of MBE-grown Sc x Al 1-x The Ec values ​​of these examples of N films are x Al 1-x This is in good agreement with previous reports on N.

[0028] Part B(i) shows the Sc signals obtained from five electrodes. x Al 1-x Average breakdown field E for example N BDThe breakdown field level is found to be approximately 2-3 MV / cm higher than the coercive field for each Sc content level, allowing polarization switching before breakdown occurs. This corresponds to a figure of merit ratio (E BD / E C ), which corresponds to the Sc formed via sputter deposition. x Al 1-x This is better than that shown by the N membrane.

[0029] B(ii) in Fig. 2 shows the remnant polarization P obtained from the PE loop data. r The P reported by Fichtner et al. and Yasuoka et al. r The values ​​are also plotted for comparison. r The value decreases monotonically with increasing Sc content. 0.20 Al 0.80 Extrapolated P of N r is about 135μC / cm 2 and the epitaxially grown Sc of the disclosed method and device is x Al 1-x The large remanent polarization of N films or layers is demonstrated.

[0030] Due to the large lattice mismatch between sapphire and GaN, epitaxial GaN and Sc x Al 1-x There may be a high density of defects at the N / GaN heterointerface. To exclude that the hysteretic behavior may be related to any trap charging and discharging process, retention tests were performed to clarify the stability of the polarization after switching.

[0031] Part A of Figure 3 shows the Sc 0.20 Al 0.80 The retention behavior of the example containing the N layer is shown. r and -P r ) is 10 5 It remained almost unchanged over seconds (s), indicating little polarization loss, thereby ruling out possible trapped charge effects. The inset shows the voltage pulse sequence used for the retention test.

[0032] Part B of Figure 3 shows the epitaxial growth of Sc x Al 1-x 1 shows the transient current-voltage profile during PUND measurements to investigate the polarization switching rate of an example N-type membrane. In this case, the PUND measurements were taken at 6 MV / cm and Sc 0.20 Al 0.80 Captured for the N membrane. Clear current peaks can be observed in the "P" and "N" sequences. Also note that the current peak is followed by a step-like tail, mainly due to resistive leakage. An abrupt current response is measured immediately after the driving voltage saturates, indicating that the polarization switching time is likely significantly smaller than the resolution (500 ns) of the current experimental setup.

[0033] Durability tests were performed under 6MV / cm pulses with a pulse width of 10 μs to measure the Sc 0.20 Al 0.80 We captured the systematic loss of switchable polarization in an exemplary film of N. The pulse sequence was run in advance to ensure that the ferroelectric dipoles were sufficiently realigned under the selected pulse profile. As shown in part A of Figure 4, a loss of polarization of about 3 × 10 5 No obvious fatigue behavior was observed for up to 10 switching cycles, which is due to the sputter-deposited Sc x Al 1-x The remanent polarization then gradually increases and then decreases, reaching approximately 10 7 It almost disappears in one switching cycle.

[0034] Part B of Figure 4 is 10, 10 3 , 10 5 , 10 7Shown are JE loops recorded after switching cycles. As the number of cycles increases, the polarization switching current gradually decreases and becomes almost invisible, whereas the resistive leakage current shows an observable rise. An unexpected increase in coercivity is also measured. The gradual loss of polarization as well as the decrease in switching current indicate that the polarization fatigue can be attributed to the gradual domain wall stabilization by mobile point defects during cycling. This result is consistent with the results of the experimental study of sputter-deposited ScN, where dielectric breakdown occurs after electrical cycling. x Al 1-x This is different from the fatigue behavior observed for the N membrane.

[0035] Sc grown by epitaxial procedures such as MBE x Al 1-x Ferroelectric switching has been achieved in ScN over the Sc content range of about 0.14 to about 0.36. x Al 1-x This is clearly confirmed by systematic electrical measurements of ScN films. 0.20 Al 0.80 N has a coercive field of 4.2MV / cm and 135μC / cm at 10KHz. 2 More importantly, durability tests show a large remanent polarization of 3×10 5 It does not show any obvious polarization loss until the switching cycle.

[0036] The achievement of epitaxial ferroelectric III-nitride layers (e.g., semiconductor layers), as disclosed herein, can be used to support new and / or improved functionality in III-nitride semiconductor device technology. Several examples are described herein. Epitaxial growth of ferroelectric III-nitride layers also creates several new device configurations in which ferroelectric functionality is integrated (e.g., seamlessly integrated) into electronic, photonic, optoelectronic, photoelectrochemical, and other devices and systems.

[0037] FIG. 5 shows two Sc alloys with the same Sc content produced according to the two examples. x Al 1-xA comparison of leakage current levels 500, 502 for N layers is shown. The leakage current levels 500, 502 are plotted as a function of applied voltage. x Al 1-x One of the N layers is grown under optimized conditions (e.g., within the growth temperature range described herein) and exhibits a leakage current level 500 that is more than an order of magnitude lower than the leakage current level 502 exhibited by the other layer grown under non-optimized conditions (e.g., above the growth temperature range described herein). The significant reduction in leakage current at level 500 allows for the Sc x Al 1-x It becomes possible to apply an electric field exceeding the coercive electric field of the N layer, making it possible to realize ferroelectric switching.

[0038] 6 illustrates a method 600 for fabricating a heterostructure having a wurtzite structure of an alloy of III-nitride materials incorporating scandium, according to one example. As described herein, the method 600 is configured such that the wurtzite structure exhibits ferroelectric behavior. The heterostructure may form a device or a portion of a device in which one or more layers or regions of the device exhibit ferroelectric behavior. The method 600 may be configured to fabricate a heterostructure having a wurtzite structure of an alloy of III-nitride materials incorporating scandium, according to one example. As described herein, the method 600 may be configured such that the wurtzite structure exhibits ferroelectric behavior. The heterostructure may form a device or a portion of a device in which one or more layers or regions of the device exhibit ferroelectric behavior. x Al 1-x It can be used to fabricate an example N membrane.

[0039] Method 600 may begin at act 602 where a substrate is prepared and / or otherwise provided. In some cases, act 602 includes providing a sapphire substrate in act 604. Alternative or additional materials may be used, including, for example, silicon, bulk GaN, bulk AlN, or other semiconductor materials. Still other materials may be used, including, for example, silicon carbide. The substrate may be cleaned in act 606. In some cases, native or other oxide layers may be removed from the substrate surface in act 608. In the example of FIG. 6 (e.g., the sapphire example), act 602 may include performing a nitridation process in act 609. In other cases, additional or alternative processes may be performed, including, for example, doping or deposition procedures. Thus, the substrate may or may not have a uniform composition. The substrate may be a uniform or composite structure.

[0040] In operation 610, one or more growth templates, buffers, or other layers are formed. Thus, the layer(s) is formed on or supported by a substrate. The layer(s) may or may not be in contact with the substrate. In some cases, the layer(s) is composed of or otherwise includes a semiconductor material. For example, operation 610 may include operation 612 in which a semiconductor layer is formed. For example, a III-nitride layer, such as a GaN layer, may be grown or otherwise formed on the substrate. Other compounds, including, for example, AlGaN, or other semiconductor materials may be used. The semiconductor layer(s) may be N-polar or metal-polar. The semiconductor layer(s) may form part of a heterostructure underlying a ferroelectric layer to be grown. The semiconductor layer is undoped or doped (e.g., Si-doped). Thus, operation 612 may be performed prior to (e.g., in preparation for) performing an epitaxial growth procedure in which a wurtzite structure is formed. This allows a wurtzite structure to be formed on the semiconductor layer. The semiconductor layer may be configured or used as a growth template for the wurtzite structure and / or other elements of the heterostructure. In some cases, operation 612 may include growing the semiconductor layer in an epitaxial growth chamber in which an epitaxial growth procedure for the wurtzite structure is performed. As a result, the substrate may remain in the epitaxial growth chamber, e.g., is not removed from the epitaxial growth chamber, between forming the semiconductor layer and performing the epitaxial growth procedure for growing the wurtzite structure.

[0041] Alternatively or additionally, operation 610 includes operation 614 in which one or more metal or other conductive layers are deposited and patterned. For example, an aluminum layer may be deposited on a silicon substrate in preparation for epitaxial growth of a wurtzite structure.

[0042] Method 600 may include act 616 in which one or more electrodes or contacts or other layers are formed. The layer(s) may form part of a heterostructure underlying the ferroelectric layer being grown. The underlying layer(s) may include a bottom electrode or contact of the heterostructure, a channel layer, etc. The nature of the underlying layer(s) may vary depending on the device being fabricated. The Si-doped layer may or may not be grown on the template or buffer layer formed in act 610. In the example of FIG. 6, act 616 includes growing a silicon-doped GaN layer in act 618. The Si-doped GaN layer may be N-polar or metal-polar. Other materials may be used. For example, the underlying layer(s) may be comprised of or otherwise include AlGaN, InAlN, InGaN, or InAlGaN. Still other materials may be used. For example, the channel layer may be composed of or otherwise include other types of semiconductors, such as Ga2O3, diamond, Si, SiGe, GaAs, InGaAs, or InP, in addition to one or more of the III-nitride alloys described above. The Si-doped GaN layer may function as an electrode layer for an element, such as a memory element. In operation 620, additional or alternative conductive structures, such as gate structures, may be deposited and / or patterned.

[0043] In operation 622, a non-sputter epitaxial growth procedure is performed at a growth temperature to form a wurtzite structure supported by the substrate. As described herein, the wurtzite structure is composed of or includes an alloy of III-nitride materials. For example, the III-nitride material may be AlN. Additional or alternative III-nitride materials may be used, including, for example, gallium nitride (GaN), indium nitride (InN), and alloys thereof. As also described herein, the epitaxial growth procedure is configured to incorporate scandium and / or another group IIIB element into the alloy of III-nitride materials. Thus, the alloy may include, for example, Sc x Al 1-xN. In some cases, operation 622 includes operation 624 in which an MBE procedure is performed. In other cases, an MOCVD or other non-sputter epitaxial growth procedure is performed in act 626.

[0044] Act 622 may form part of a continuation or sequence of growth procedures. The growth procedures may be performed in a common or the same growth chamber. Thus, act 622 may include act 628, in which epitaxial growth continues in the same chamber in which one or more other layers of the heterostructure were grown. For example, the growth template and one or more of the underlying semiconductor layer(s) formed in acts 610 and 616 may be formed in the same chamber as the ferroelectric layer. Thus, successive layers of the heterostructure may be grown without exposure to the environment. Thus, the quality of the interfaces between the layers may be improved.

[0045] The growth temperature may be at a level such that the wurtzite structure exhibits a breakdown field strength greater than the ferroelectric coercivity of the wurtzite structure, and therefore ferroelectric switching and other behaviors may be achieved.

[0046] The growth temperature is at a lower level than would be expected given the III-nitride material. In some instances, the growth temperature level is significantly lower than the temperatures at which III-nitride materials are typically grown. For example, the growth temperature level may be such that attempting to grow a structure made of III-nitride material (i.e., containing no scandium) at that growth temperature level is not worthwhile. The resulting structure would be of poor quality (e.g., have too many defects) to be useful. Nevertheless, growth of a single crystal of a scandium-containing alloy (e.g., a single crystal layer of the alloy) at the growth temperature level can be achieved. For example, in some cases, Sc x Al 1-xThe N alloy may be epitaxially grown at a growth temperature of about 650° C. or about 750° C., even though the corresponding (scandium-free) III-nitride material AlN is conventionally grown at much higher temperatures, e.g., about 1000° C. Conversely, attempts to grow AlN at temperatures of about 650° C., about 750° C., or below about 650° C. or 750° C. result in such poor quality structures that they are useless. In contrast, epitaxially grown ScN alloys grown at such low temperatures have been found to have low growth temperatures, e.g., about 1000° C., even though the corresponding (scandium-free) III-nitride material AlN is conventionally grown at much higher temperatures, e.g., about 1000° C. Conversely, attempts to grow AlN at temperatures of about 650° C., about 750° C., or below about 650° C. or 750° C. result in such poor quality structures that they are useless. x Al 1-x The N-layer is unexpectedly single crystalline and of high quality.

[0047] At conventional AlN growth temperatures (and other temperatures beyond the upper limit), x Al 1-x Unexpectedly, when the N layer was grown, Sc x Al 1-x Dislocations and / or other leakage paths form in the N layer. The presence of leakage paths causes the Sc x Al 1-x The breakdown field strength level of the N layer is too low (e.g., below the ferroelectric coercivity level), and therefore this layer does not exhibit ferroelectric behavior.

[0048] In some cases, the growth temperature may be about 650 degrees Celsius or less, or about 750 degrees Celsius or less. The growth temperature may correspond to a temperature measured with a thermocouple in the growth chamber. The growth temperature at the epitaxial surface may be slightly different. Thus, the growth temperature is approximated via the temperature measurement with the thermocouple.

[0049] The upper limit of the growth temperature range may vary depending on the alloy and / or epitaxial growth technique. For example, in other cases, the upper limit of the growth temperature may be higher, such as about 680° C. or about 690° C. In still other cases, the upper limit may be lower, including, for example, about 600° C. or about 620° C.

[0050] At each level within the preferred growth temperature range, the resulting wurtzite structure is single crystalline. x Al1-x The N-layer is monocrystalline to a degree that is not achievable by sputtering-based procedures for forming the N-layer. Such procedures can only produce structures with X-ray diffraction rocking curve linewidths of the order of a few degrees at best. In contrast, structures grown by the disclosed method exhibit X-ray diffraction rocking curve linewidths on the order of hundreds of arc seconds or less, which is well over 11 orders of magnitude. In this way, leakage current paths are minimized or otherwise sufficiently reduced so that the resulting wurtzite structure has a suitably high breakdown field strength level, e.g., a breakdown field strength level that is sufficiently greater than the ferroelectric coercivity.

[0051] The above-mentioned differences in crystal quality as evidenced through X-ray diffraction rocking curve linewidths can also be used to distinguish between single crystal and polycrystalline structures. As used herein, the term "polycrystalline" refers to a structure having an X-ray diffraction rocking curve linewidth of the order of a few degrees or more. As used herein, the term "single crystal" refers to a structure having an X-ray diffraction rocking curve linewidth of at least an order of magnitude less than a few degrees.

[0052] When comparing the wurtzite structure of layers grown by MBE or other non-sputter techniques (e.g., MOCVD or HVPE) with sputter deposition techniques, the microstructure of the former technique is more uniform with a highly ordered stacking arrangement of atoms. Domains with cubic phase or with in-plane misorientation are easily observed in sputter deposited layers. The presence of these misaligned domains inhibits complete switching of the polarization and further leads to rapid loss of polarization during fatigue testing. With regard to phase purity, the highly crystallographic orientation of layers grown by MBE or other non-sputter techniques indicates more repeatable ferroelectric switching, which is useful in many device applications.

[0053] The wurtzite structure of the ferroelectric layer may be nitrogen-polar (N-polar) or metal-polar. The polarity of the underlayer formed in operation 610 and / or operation 616 may be used to establish the polarity of the ferroelectric layer formed in operation 622. The polarity of the underlying layer may then be established by the properties of the substrate. The polarity may continue across the interface between the underlayer and the ferroelectric layer. Thus, either the N-polarity or the metal polarity may persist as the composition changes from the underlayer to the ferroelectric layer.

[0054] The wurtzite structure may then be annealed in act 632. The annealing may be performed at a temperature higher than the growth temperature. In some cases, the annealing temperature is in the range of about 700°C to about 1500°C. Example films prepared with such annealing have shown stable polarization switching with further reduced leakage current compared to unannealed films. The uniformity of the film or device is also improved by annealing, thereby further improving the polarization switching behavior of the ferroelectric Sc-III-N alloy. The underlying mechanism for the improved performance and uniformity with annealing is attributed to the reduction in threading dislocation and defect densities that typically act as electrical leakage paths. Such utility of post-growth annealing is realized despite past concerns that high processing temperatures may result in loss of ferroelectricity.

[0055] Sc x Al 1-x Such post-growth high temperature annealing of N may be performed in situ in the same growth chamber (e.g., the same MBE chamber) in act 634. In other cases, the annealing is performed ex situ in a chamber dedicated to the annealing procedure.

[0056] The annealing process may be carried out under high vacuum (e.g., in situ in the growth chamber) in act 636. In other cases, the annealing may be carried out using nitrogen plasma irradiation or under nitrogen gas flow in act 638.

[0057] The annealing procedure described above can be performed in connection with films grown under any of the growth conditions described above. For example, the annealing procedure may be performed after growth under slightly to moderately N-rich conditions at a growth temperature of about 650 degrees Celsius or less, or about 750 degrees Celsius or less. The annealing procedure may also be performed after growth under unbalanced flux ratios (e.g., N-rich or extremely N-rich conditions) at a growth temperature of more than about 650 degrees Celsius or more than about 750 degrees Celsius.

[0058] Method 600 may include act 640, in which one or more layers (e.g., semiconductor layers) are formed after growth of the wurtzite structure. As a result, the layer(s) may be in contact with the wurtzite structure. For example, in act 642, one or more III-nitride (e.g., GaN or AlGaN) or other semiconductor layers may be epitaxially grown. Act 642 may be performed in the same epitaxial growth chamber used to grow the wurtzite structure. As a result, the substrate (and heterostructure) is not removed from the epitaxial growth chamber between performing operations 622 and 640.

[0059] Alternatively or additionally, operation 640 includes operation 644, in which one or more metal or other conductive layers or structures are formed. The layers or structures may be deposited or otherwise formed. In some cases, the conductive structures are configured as a top portion or top contact. For example, the conductive structures may be gates.

[0060] Method 600 may include one or more additional operations. For example, one or more operations may be directed to forming other structures or regions of a device, including a heterostructure. In the example of a transistor device, the regions may correspond to source and drain regions. The nature of the regions or structures may vary according to the nature of the device.

[0061] The order of operations in method 600 may differ from the example shown in Figure 6. For example, operations 616, 618, and 620, in which contacts and / or other conductive structures are formed, may be performed after growth of the ferroelectric layer.

[0062] Several different types of devices can be fabricated by the method 600 of FIG. 6 and / or other methods of fabricating heterostructures having a wurtzite structure of alloys of III-nitride materials incorporating scandium. For example, the ferroelectric Sc x Al 1-x N or other alloys may be useful in various types of non-volatile memory devices (e.g., FeRAM, FeFET, FTJ and FeSFET devices), various types of reconfigurable electronic and other devices (e.g., Fe-HEMT, Fe-capacitor, and SAW devices), various types of photodetection, photovoltaic and optoelectronic devices (e.g., self-powered photodetectors and solar cell devices), and various homojunction devices (e.g., devices that use laterally distributed charge plates to tune the Fermi levels of adjacent layers). Still other types of devices may be fabricated, including, for example, FE-based thin film bulk acoustic wave resonator (FBAR) devices.

[0063] Several exemplary devices are now described. In each example, the device includes a substrate and a heterostructure supported by the substrate. The heterostructure includes a single crystal layer of an alloy of III-nitride materials. As described herein, the alloy includes scandium. As also described herein, the single crystal layer exhibits a breakdown field strength greater than the ferroelectric coercivity of the single crystal layer. In some cases, the III-nitride material is aluminum nitride (AlN), although other III-nitrides may be used.

[0064] In some of the devices described below, the device also includes a semiconductor layer disposed between the substrate and the heterostructure. The semiconductor layer may include additional III-nitride materials, such as GaN. In some cases, the semiconductor layer is in contact with the heterostructure. Epitaxial growth of the layer may result in a high-quality interface between the layers. Alternatively or additionally, the device also includes a metal or other conductive layer disposed between the substrate and the heterostructure. The metal layer may be in contact with the heterostructure, examples of which are described below.

[0065] 7A and 7B show examples of FeFET memory devices 700, 702. In each device 700, 702, a ferroelectric Sc x Al 1-x The N layer is disposed between the gate electrode and the source-drain conductive region. The ferroelectric layer provides the reversible electrical state for the transistor of the device. The ferroelectric Sc x Al 1-x The large remnant electric field polarization in the N-layer retains the state of the transistor (e.g., on or off) in the absence of any electrical bias, forming a single-transistor non-volatile memory. In some cases, the bulk and / or other semiconductor channel layers are constructed from or otherwise include GaN or silicon, or two-dimensional materials such as MoS2 or graphene. In each device 700, 702, the FeFET memory device 700, 702 includes a ferroelectric ScN, e.g., a III-nitride material. x Al 1-x The device may include a heterostructure including a III-N or other alloy with one or more layers of a III-nitride semiconductor such as AlN as a gate dielectric and barrier. The substrate supporting these layers and structures of the device may be composed of or otherwise include GaN or silicon, for example. The control terminal or gate may be located above or below the heterostructure as shown.

[0066] Other types of memory devices include one transistor one capacitor (1T-1C) FeRAM devices. For example, FeRAM devices are fabricated using Al, Sc, GaN, or GaN supported by pre-processed silicon or GaN substrates. x Al 1-x The present invention may include a MIM ferroelectric capacitor constructed from or otherwise including N, and Al.

[0067] FIG. 8 shows a combined FET structure 800 configured as a memory cell. x Al 1-x During switching of the remanent polarization state in the N layer, a current pulse is generated to indicate the binary information stored in the cell.

[0068] 9A and 9B show examples of FTJ memory devices 900, 902. In the exemplary device 900, an epitaxially grown ferroelectric layer is disposed between metal layers (e.g., nickel and aluminum layers). In another exemplary device 902, a ferroelectric layer is disposed between a III-nitride semiconductor layer (e.g., n-type doped GaN) and a metal layer. Other metal-Fe(insulator)-metal and metal-(insulator)-Fe-(insulator)-semiconductor configurations may be used. In these exemplary devices 900, 902, Sc x Al 1-x The N or other alloy provides ferroelectricity and adjusts the on / off current / resistance ratio as the readout of the memory device. Further details regarding memory devices having heterostructures with ferroelectric layers constructed from or otherwise including III-nitride alloys, as well as additional examples of methods of using such memory devices, are provided below in conjunction with Figures 15-21.

[0069] 10A and 10B show examples of metal-polar and N-polar Fe-HEMT devices 1000, 1002, respectively. In these two examples, each of the devices 1000, 1002 contains a ferroelectric Sc x Al 1-xThe device 1002 of FIG. 10B may include a heterostructure that is composed of or otherwise includes a stack of N-polar, channel, and buffer layers. The order or arrangement of the layers varies as shown between the metal-polar and N-polar examples. The heterostructure may include additional, fewer, or alternative layers. For example, the N-polar buffer layer shown in device 1002 of FIG. 10B may be grown on an additional underlying Si-doped N-polar III-nitride layer, such as a Si-doped N-polar GaN layer.

[0070] The heterostructure may be grown on a bulk or other region that is composed of or otherwise includes III-nitride semiconductor material such as GaN. One or more of the III-nitride semiconductor layers may be doped, e.g., Si or otherwise n-type doped. Other III-nitride semiconductors may also be used, including, for example, AlGaN, InGaN, and InAlGaN as described herein. Thus, a switchable two-dimensional electron gas (2DEG) heterojunction is configured such that, during operation, Sc x Al 1-x It can be formed due to the strong spontaneous polarization in the N layer. To enhance the carrier mobility, Sc x Al 1-x A thin AlN layer may be inserted between the N layer and the channel layer.

[0071] Still other types of transistor devices can utilize the epitaxially grown ferroelectric layers described herein, including, for example, N-polarity bottom-gate and recessed-gate transistor devices, with and without a gate oxide layer.

[0072] 11A and 11B show examples of reconfigurable Fe-HEMT devices 1100, 1102. In these examples, each of the devices 1100, 1102 contains a ferroelectric Sc x Al 1-x As shown in FIG. 11A, the heterostructure includes a ferroelectric ScN layer. x Al 1-x Ferroelectric Sc ​​with switchable polarization in the N-layer x Al1-x The heterostructure may include a stack of N-layers and a channel layer. Alternatively, the heterostructure may be configured such that a 2DHG or depletion region is formed underlying the polarization switch region, as shown in FIG. 11B. The disclosed devices include yet other types of reconfigurable Fe-HEMT devices, including, for example, an Fe-HEMT device including an N-pole structure as shown in FIG. 10B.

[0073] 12 shows an example of a photovoltaic device 1200 in which a ferroelectric layer is incorporated into a heterostructure having one or more III-nitride layers between the electrodes of the device. In the example shown, the heterostructure is made of Sc x Al 1-x Adjacent and in contact with the N layer is an n-type GaN layer. An indium tin oxide (ITO) layer establishes one of the electrodes of the device (e.g., a transparent cathode or anode). x Al 1-x The photon-generated carriers in the N layers are separated and collected by the polarization-induced electric field. The heterostructure may be supported by a sapphire or other substrate.

[0074] 13A and 13B show further examples of photovoltaic devices 1300, 1302. In each example, polarization in the ferroelectric layer attracts electron / hole charges to different regions, thereby creating a built-in electric field in the light absorbing layer that aids in the separation and collection of photo-generated carriers.

[0075] 14 shows an example of a homojunction device 1400 having a ferroelectric layer adjacent to a channel layer or region. The modulated polarization in the ferroelectric layer attracts electrons and holes in opposite directions, thereby forming a lateral homojunction in the channel material. Homojunctions may be formed in semiconductors such as GaN, Si and two-dimensional materials.

[0076] For example, Sc x Al 1-xDevices and structures are described above that exhibit ferroelectricity in a layer of GaN. Methods for growing the structures are also described, including, for example, methods involving plasma-assisted molecular beam epitaxy on GaN templates. x Al 1-x Clear polarization switching is clearly observed in the ScN film, which is nearly lattice matched to GaN. 0.20 Al 0.80 An example of N has a coercive field of about 4.2MV / cm at 10kHz and a capacitance of about 135μC / cm 2 After electrical poling, the Sc 0.20 Al 0.80 An example of N is 10 5 The polarization retention time exceeded 3×10 seconds. 5 The realization of ferroelectric III-V semiconductors using molecular beam and other epitaxy, for example, allows for thickness scaling into the nanometer regime, as well as the integration of high-performance ferroelectric functionality with well-established semiconductor platforms for a wide range of electronic, optoelectronic, and photonic device applications.

[0077] Ferroelectric memory devices. The heterostructures described above having a ferroelectric layer composed of or otherwise including a III-nitride alloy, and methods of forming such heterostructures, can be used to fabricate ferroelectric memory devices. In some cases, the heterostructure can include a heterointerface established by a ScAlN film and a GaN layer in contact therewith. Further details regarding ferroelectric memory devices are described below in connection with several examples.

[0078] Electrically switchable bistable conductance arising in ferroelectric materials has attracted growing interest due to its promising applications in data storage and in-memory computing. Sc-alloyed III-nitrides have emerged as a new class of ferroelectrics that not only enable seamless integration with III-nitride technologies but also provide an alternative solution for CMOS back-end-of-line integration. Examples of resistive switching behavior and memory effects in ultrawide bandgap, high Curie temperature, fully epitaxial ferroelectric ScAlN / GaN heterostructures are described below. Examples show robust on and off states that persist for months at room temperature with rectification ratios of 60-210, and furthermore, stable operation at high temperatures (e.g., around 670 K) that approach or exceed the Curie temperatures of most conventional ferroelectrics. Analysis of examples shows that the underlying mechanism is directly related to ferroelectric field-effect-induced charge reconfiguration at the heterointerface. The robust resistive switching landscape and electric polarization engineering capability in polar heterostructures, together with the prospect of integration with both silicon and GaN technologies, may be useful in next-generation memristors and other multi-function and cross-field applications.

[0079] Ferroelectric materials exhibit spontaneous polarization that can be reoriented by an external electric field, and the principle has been used to modify barrier height or width in metal-ferroelectric-metal capacitors or ferroelectric / semiconductor heterostructures to create resistive switching memristors and programmable homojunctions. With the increasing demand in big data storage and data-centric computing, there has been great interest in ferroelectric resistive switching devices for promising applications in energy-efficient memory, neuromorphic and in-memory computing, and edge intelligence. As a result, significant efforts have been put into the fabrication of resistive switching devices including ferroelectric tunnel junctions (FTJs), ferroelectric field effect transistors (Fe-FETs), and ferroelectric diodes based on traditional perovskite or fluorite ferroelectrics, as well as various newly discovered two-dimensional ferroelectric materials. On the process side, dominated by silicon technology, the strict processing steps and strict device control within CMOS manufacturing lines pose great challenges to the available materials for fabricating ferroelectric memristors for commercialization. On the material side, the low Curie temperature, small coercivity and narrow band gap of most conventional ferroelectrics make the associated devices susceptible to distortion / stoichiometry, read / write operations, depolarization fields and charge injection, etc., leading to limited memory window and stability issues, especially in harsh environments. The demonstration of ferroelectricity in doped hafnium oxide and zirconium oxide and their alloyed variants brought new life to the ferroelectric memory community by being standard materials used in CMOS processes, leading to a boom in Fe-FETs, FTJs and negative capacitance FETs (NC-FETs) in the past decade.

[0080] Sc-alloyed wurtzite III-nitrides (Sc-III-Ns) have the following properties: high temperature phase stability (up to 1100 °C), large and tunable coercivity (1.5–6 MVcm -1 ), with remarkable switchable polarization (80~120μCcm -2), wide band gap (4.9-5.6 eV), and unprecedented resistance to retention even on polar semiconductor electrodes make these new materials candidates for memory applications that may outperform conventional ferroelectrics in terms of lifetime and stability, especially in harsh environments. The wide synthesis window also raises interest in post-CMOS compatible processing techniques. Despite these promises, there are few demonstrations of ScAlN memory devices, which have only been realized by using sputter deposition.

[0081] Compared with conventional sputter deposition, the above-mentioned epitaxial growth of ferroelectric ScAlN by molecular beam epitaxy (MBE) is useful in several respects, including excellent control of crystallinity, stoichiometry, thickness, doping, interfaces, and uniformity. These properties are useful for the performance, stability, and yield of memory cells, arrays, and other devices. The single crystallinity of MBE-grown ScAlN can further provide a useful approach to control threshold variation, which remains an open question for the "era of ferroelectrics". Furthermore, the fully epitaxial method and electrically switchable polarization greatly expand the spontaneous / piezoelectric polarization engineering space in III-nitrides, further promising the seamless integration of ferroelectricity with the superior properties of III-nitrides and nitride-based electronics, optoelectronics, and piezoelectric electronics, which may be useful in conjunction with all-nitride-based energy-efficient memory circuits for harsh environments and edge intelligence (EI) applications. Furthermore, given the mature nitride-on-silicon technology, high-quality ScAlN films and other layers can be readily grown on Si substrates over a wide range of growth conditions, enabling Si-based memory applications and seamless integration with other devices.

[0082] In support of these applications and devices, the examples described below demonstrate ferroelectric and polarization engineering in Sc-III-N / III-N heterostructure devices. In one example, a fully epitaxial ferroelectric ScAlN / GaN heterostructure memory device is realized. The coupling between the distinct resistive switching behavior and the polarization orientation is analyzed in further detail. The structure exhibits robust on and off states at room temperature depending on the electric polarization direction, with on / off ratios of 60-210 and retention times of 3×10. 6 seconds, and the bipolar cycle is 10 4 times. Polarization-resistance correlation measurements provided direct evidence of a ferroelectric polarization-coupled resistive switching process. The conductance and capacitance rectification ratios were found to decrease with increasing carrier concentration in the GaN electrode layer, suggesting a ferroelectric field-effect-induced charge reconfiguration at the heterointerface, an effect useful for incorporating ScAlN into III-nitride devices. The operating temperature dependence of the memory effect was also small. The maximum rectification ratio of about 10 is well maintained even at 670 K, a temperature range close to or even above the Curie temperature of most conventional ferroelectrics. These analyses establish ScAlN-based ferroelectric / III-nitride heterostructures as useful candidates for ferroelectric resistive memory devices, including next-generation memristors and all-nitride-based monolithic integrated circuits for energy-efficient applications and harsh environments.

[0083] In one set of examples, single crystal ScAlN films having a thickness of about 100 nm were fabricated using a thickness of about 120 nm and a thickness of about 1×10 19 cm -3Following the growth of a Si-doped GaN bottom electrode layer with a carrier concentration of 1000 Å, the GaN / sapphire heterostructures were grown on a commercial GaN / sapphire template by radio frequency plasma assisted MBE. Ti / Au metal pillars with different diameters (3-50 μm) were then deposited as the top electrodes, as shown diagrammatically in part (a) of Figure 15. The Sc content of the ScAlN layer was set to about 18% to match the lattice of GaN to reduce misfit defects and dislocations. The heterostructures were fabricated as described herein. Further details regarding the fabrication are presented below.

[0084] Figure 15 shows that the carrier concentration of the GaN electrode is approximately 1×10 19 cm -3 The results are collected from examples where the top electrode diameter is 20 μm (unless otherwise stated). As shown in the scanning transmission electron microscope (STEM) image on the right side of part (a) of Figure 15, an atomically ordered interface can be observed, indicating good epitaxial quality. Part (b) of Figure 15 shows the X-ray 2θ-ω scan for one ScAlN / n-GaN example. The characteristic diffraction peak of ScAlN (0002) can be clearly observed, further confirming the wurtzite structure of the ScAlN films. The (0002) rocking curve full width at half maximum (FWHM) of all ScAlN films is less than 400 arcsec, nearly an order of magnitude smaller than that of conventional sputtering, further confirming the excellent structural properties. Part (c) of Figure 15 shows typical current-voltage (IV) and polarization-voltage (PV) hysteresis loops recorded using a Radiant ferroelectric tester II at 20 kHz at room temperature. The remnant polarization is about 90 μCcm -2was estimated and was consistent with previous reports. The asymmetry in the PV loops is due to the asymmetric electrode materials. Ferroelectricity in the ScAlN / GaN heterostructure was also confirmed by piezoresponse force microscopy (PFM). As shown in part (d) of Figure 15, the butterfly-shaped amplitude diagram and box-shaped phase diagram separated by about 180° suggested that the polarity of the film could be switched externally by an electric field. Parts (e) and (f) of Figure 15 further show the PFM out-of-plane phase and amplitude images of the domains after writing at ±30 V and mapping at VAC=0.6 V, 30 kHz. The 180° phase contrast, clear domain boundaries, and uniform contrast in each polarization region reveal that stable antiparallel domains can be written in the ScAlN layer. The low amplitude signal along the domain boundaries indicates the canceling contributions of the opposite domains, which is characteristic of ferroelectrics. These patterns were still detectable after 24 h, indicating the stability of the polarity-switched domains.

[0085] Thus, Figure 15 shows ferroelectricity in an example epitaxial ScAlN / GaN heterostructure. The initial piezoelectric phase shows the same contrast as the pattern written by +30 V and exhibits a downward polarization, which coincides with the substrate polarity. The opposite phases under the same polarization direction in parts (d) and (f) result from the renormalization of the phase values ​​due to the different initial phase states during the measurement.

[0086] FIG. 16 illustrates the resistive switching behavior in the exemplary ScAlN / GaN heterostructure memory device of FIG. 15. To investigate the resistive switching behavior, static IV hysteresis loops were measured at room temperature with a step size of 100 mV by a B1500 semiconductor analyzer. All voltages were applied to the top electrode and the bottom electrode was grounded. The scan direction was followed: −35 V, then 35 V, then −35 V. As shown in FIG. 16 (a), the device exhibited a clear and stable bipolar hysteresis loop with good repeatability and remained substantially unchanged after 100 bipolar scans. A reverse sweep from a positive bias indicates a high current state, and a reverse scan from a negative bias indicates a low current state, indicating a counterclockwise-clockwise rotation direction.

[0087] Part (b) of Fig. 16 is intended to show the non-destructive readout of the on / off currents, with the inset showing the measurement sequence. Part (b) shows the currents measured at small voltages after poling with a voltage pulse. Under a poling pulse of +35 V (20 ms wide) on the top electrode, a high-current state, i.e. the on-state, is established, characterized by a high current density under both bias directions. Then, after a poling pulse of -35 V (20 ms wide), a low-current state, i.e. the off-state, is achieved, giving a rectification ratio of about 100 at a read voltage level of -17 V. The off-current shows diode-like conduction, i.e. the current under positive bias is larger than the current under negative bias, while the on-current appears more symmetrical at nearly identical absolute turn-on voltages (±10 V).

[0088] For some devices, a relatively low off-current or a large on-current is measured during the first few scans, and the 4 On / off ratios of more than 10 ...

[0089] Part (c) of Figure 16 relates to the retention characteristics of the example device. The non-volatile nature of the on and off states was investigated by measuring the device current at -17 V after pulse poling for different retention times. As shown in (c), the on current is slightly reduced, while the off current appears to be stable by the detection limit. An on / off ratio of about 46 represents a retention time of less than 1 month (3 × 10 6 It can still be held even after the expiration time of the period.

[0090] Part (d) of FIG. 16 relates to the testing of the bipolar switching characteristics of the ScAlN / GaN heterostructure. The characteristics were tested by repeatedly poling the ScAlN / GaN heterostructure with ±35 V pulses and reading the current at −17 V. As shown in part (d), the on and off currents increased over a period of 10 4 remain stable over 10 write / read cycles, and both 5 The increase in the off-current is faster than the increase in the on-current, and the rectification ratio is 10 5 After a bipolar switching period, the polarization fatigue measurement shows a maximum of 10 7 The ScAlN / GaN heterostructures showed a significant remanent polarization over 100 switching cycles. The initial setting of resistance fatigue may be related to charge injection at the ScAlN / GaN interface. The increased off-current can be partially recovered with a larger negative poling voltage or a longer negative voltage poling time. Nevertheless, these results indicate the great potential of ScAlN / GaN heterostructures as memory devices.

[0091] Taken together, the graph plots shown in Figures 15 and 16 show that a positive polarization corresponds to the ON state, followed by a downward polarization and an upward polarization corresponds to the OFF state. To elucidate the relationship between resistive switching and ferroelectric switching, a modified write / read process can be used. For example, a preset pulse (±35V, 20ms) is used to first drive the device into the OFF (ON) state. Then, a voltage- and width-adjustable write pulse is applied, followed by a non-destructive current readout. Finally, two identical trapezoidal waveforms ((switching + non-switching) were used to extract the polarization change. In this scenario, the conductivity of the heterostructure, and the polarization state corresponding to this conductivity, can be obtained simultaneously after each write pulse.

[0092] As shown in part (a) of Figure 17, the hysteretic resistance switching of the device shows almost identical shape to the PV loop with almost the same threshold voltage and saturation behavior, which provides clear and direct evidence of the ferroelectric polarization modulated resistance switching process. Parts (b) and (c) of Figure 17 further show the write pulse width dependence of the resistance switching and polarization switching processes. When the write pulse width is small, negligible polarization or conductivity change is observed. As the write pulse width increases, the polarization difference before and after the write pulse increases slowly and becomes 2P when the pulse width exceeds a certain value. r The device current levels sensed at -17V show the same trend. These results indicate ferroelectric polarization orientation modulated resistive switching behavior in ScAlN / GaN heterostructures. Thus, the stepwise modulation of conductance with different pulse widths can be further used to provide modulated memory states in memory arrays and other devices. Such modulation can be used to mimic a biological learning rule called spike-timing dependent plasticity (STDP).

[0093] Figure 17 shows simultaneous measurements of conductivity and polarization change. In part (a) of Figure 17, the conductivity hysteresis loop of an example ScAlN / GaN heterostructure is shown with the corresponding relative polarization state. The two branches are plotted together to form a complete loop. Parts (b) and (c) show the pulse-width dependent measurements. In this case, a preset pulse is first used to drive the off (on) state. Then, an adjustable write pulse is applied, followed by a non-destructive current readout. Finally, two fixed trapezoidal waveforms are used to study the relative polarization change after the write pulse.

[0094] Part (a) of FIG. 18 shows a schematic diagram of an energy band diagram of an example ScAlN / GaN heterostructure modulated by the polarization orientation in the ScAlN layer. φ up , φ down is the effective barrier height for electron transport. Ferroelectric field effects and charge screening build up a space charge region and a higher effective barrier during polarized P-up operation. (b) shows the carrier concentration dependence of the on / off currents on the GaN contact layer. In part (c) the corresponding on / off ratios are shown. The error bars in c) are the standard deviations calculated from 10 different devices in each sample. The measurements were performed with a top electrode of 50 μm diameter to allow a better comparison of the off currents. The broadening of the on / off ratios with decreasing GaN carrier concentration indicates the enhancing effect of the depolarizing electric field.

[0095] The band diagram of the ScAlN / GaN heterostructure is provided to explain the experimentally observed IV hysteresis loop. The ferroelectric field effect and real space charge reconstruction at the ScAlN / GaN interface are considered. As shown diagrammatically in part (a) of Figure 18, due to the ferroelectric field effect, if the ferroelectric polarization of ScAlN is downward after positive pulse writing, the positive polarization charge at the ScAlN / GaN interface attracts electrons near the interface, causing a downward bending of the band profile and an accumulation region. If the ferroelectric polarization of ScAlN is upward after negative pulse writing, the negative polarization charge at the ScAlN / GaN interface repels electrons near the interface, resulting in an upward bending of the band profile and a depletion region. In the latter case, the total barrier height increases and there is an additional interface barrier, which blocks the electron transport and leads to the off state.

[0096] This behavior is confirmed by growing ScAlN on GaN with different doping concentrations. As shown in Fig. 18(b), as the carrier concentration in the GaN electrode increases, both the on-current and the off-current increase. The off-current increases faster as the carrier concentration in n-GaN increases to about 7 × 10 17 cm -3 From about 1×10 20 cm -3 When the doping is increased to , the maximum on / off ratio drops from about 210 to 60. This behavior occurs because, in the on state, the polarization is downwards and the interface is already accumulating. Further filling of the interface with electrons causes a negligible reduction in the barrier height. During the off state, the polarization is upwards and the screening of the polarization charges is strongly enhanced by the high doping concentration in the electrode layers, resulting in a more significant reduction in the depletion region width and the interface barrier height.

[0097] The depletion width was calculated based on capacitance-voltage (CV) measurements at small voltages and is estimated to be approximately 7×10 17 cm -3 From about 1×10 20 cm -3The results show a reduction in the equilibrium depletion width from about 10 nm to less than 1 nm when V is increased to 0.5 V, consistent with the behavior proposed above. Fitting of the experimental IV data shows a linear dependence of ln(I / V) on the square root of V. However, the dielectric constants extracted using the Poole-Frenkel radiation model (in the range of 6–8) are much smaller than those from the CV measurements (about 12), suggesting that the conduction involved here is not dominated by the polarization-coupled trap filling factor changes previously reported for metal / ScAlN / metal capacitors. The rapid increase in current with voltage could indicate some degree of tunneling current from the triangular barrier formed at the electrode / ferroelectric interface due to the strong applied electric field. Instead, the Poole-Frenkel radiation model is found to fit the IV curves very well after resistive fatigue, indicating a transition from interface barrier modulated conduction to bulk Poole-Frenkel radiation limited transport after cycling. It is suspected that during bipolar cycling, excess charge is injected at the ScAlN / GaN interface, which lowers the overall barrier height and causes a leakage path. This explains the early set-up and recovery behavior of resistive fatigue, considering that charge injection has been reported to occur before domain wall pinning and can be partially released upon backfilling or heating. Moreover, the shape of the I-V hysteresis loops was found to be independent of the electrode material, which further indicates that the rectification effect arises from the ScAlN / GaN interface and not from the Schottky barrier. Due to the large oxygen affinity of Sc and Al, a thin oxide layer may exist between the top electrode and the ScAlN surface. If conduction is modulated by the barrier height of the thin oxide layer, changing the electrode material may also change the work function of the electrode, thereby changing the electrode-oxide interface barrier height and resulting in a different rectification ratio. However, this was not observed. These results together demonstrate ferroelectric field-effect-dominated resistive switching in ScAlN / GaN heterostructures.

[0098] The extracted depletion width is much smaller than the value from theoretical calculations considering large polarization discontinuities and an ideal ScAlN / GaN interface. The polarization charge at the interface may be slightly screened by interface traps introduced during growth interruption or from a low-purity Sc source (99.9%). Furthermore, due to the strong chemical bonds at the ScAlN / GaN interface and the relatively small dielectric constant of ScAlN (hence the stronger depolarization field), there may be a thin unswitchable paraelectric ScAlN layer or pinning domains, which significantly compensate the overall switchable polarization and weaken the ferroelectric field effect, resulting in an overly damped depletion width. The latter is believed to be the main reason for the tailored depletion region in the examples described herein. In addition, vacancies may accumulate at the interface and screen the polarization charge. Nevertheless, an effective remnant polarization can be introduced to quantitatively represent the charge reconfiguration at the interface.

[0099] Due to the significant electromigration of oxygen vacancies, filamentary conduction or electronic conductor-insulator transition may occur and dominate or contribute to the resistance switching process in ferroelectrics. In the examples described herein, the complete reorientation of the wurtzite structure involves the global replacement of metal or nitrogen atoms, which may cause some vacancy migration events. However, by varying the electrode diameter from 3 μm to 50 μm, the I-V hysteresis loop was found to be independent of the junction area, and no electroforming or current compliance was required to stabilize the switchable resistance, thereby eliminating the formation of conductive filaments. Meanwhile, the on-current in the examples described herein appears symmetrical and is always larger than the off-current under both bias conditions, which is different from the typical diode-like hysteresis loop during the electronic conductor-insulator transition. Also, the electromigration model itself is bulk conduction and cannot explain the carrier concentration dependence shown in Figure 18(b)(c). Therefore, in the examples of ScAlN / GaN heterostructures described herein, electromigration of defects such as vacancies may exist but does not play a significant role.

[0100] The disclosed devices are capable of high temperature operation. A wide band gap of about 5.5 eV is reported for ScAlN with 18% Sc content, which exceeds most reported ferroelectric materials. Also, the conduction band offset between ScAlN with 18% Sc content and GaN is predicted to be about 1.74 eV from first-principles calculations and about 2.09 eV from X-ray photoelectron spectroscopy (XPS) measurements. These wide band gap properties are expected to carry over from III-nitrides to ScAlN and help suppress thermally activated currents at high temperatures.

[0101] FIG. 19 shows the high temperature performance of an ScAlN / GaN heterostructure memory device according to an example. Part (a) shows the PV loops operating at 670K on a hotplate. Part (b) shows the on and off current levels for operation probed at 670K, indicating bistable conductivity. (c) shows the operating temperature dependence of the on / off ratio. Due to the strong temperature dependence of the coercivity, the write and read voltages gradually decreased with increasing temperature. The on / off ratio is calculated as the maximum on / off ratio in the non-destructive IV readout. Part (d) shows the results of the retention test at 670K on a hotplate using a Keithley 2400.

[0102] Part (a) of Figure 19 compares the PV loops at room temperature and at 670 K. A dramatic drop in the coercivity is observed at 670 K while the remanent polarization is stable. As a result, the write pulse is changed to ±23 V, 20 ms. Surprisingly, even at 670 K, the on / off state is still achievable with a commutation ratio of about 10, as shown in part (b) of Figure 19. This temperature is already quite close to the Curie temperature of many ferroelectric materials, including HfO2. In this case, the maximum test temperature was limited by the available setup. Thus, even higher operating temperatures are possible. Furthermore, it is worth mentioning that most of the integrated circuits based on Si technology have been operated up to 400 °C, which is higher than or close to the Curie temperature of most conventional ferroelectrics. Thus, these results demonstrate that the ScAlN / GaN-based memory devices and other examples described herein are compatible with Si integrated circuits suitable for harsh operating environments such as high temperature operation.

[0103] Figure 19(c) further shows the temperature dependence of the maximum on / off ratio of the ScAlN / GaN heterostructure memory. With increasing ambient temperature, the maximum on / off ratio slowly decreases from about 200 to 10 at 670 K, in contrast to the rapid decrease in the on / off ratio in the BaTiO3-based FTJ device. The stability of the two states at high temperatures is shown in part (d) of Figure 19, which shows a maximum on / off ratio of 10 at 670 K. 3 The results show a retention time of more than 100 seconds. After optimization, an on / off ratio of about 100 was still obtained even at 433 °C. These results confirm the excellent stability of ScAlN / GaN-based memory devices and provide a viable route to realizing memory devices for harsh environments such as aerospace and military applications.

[0104] The exemplary memory device heterostructures described above were grown to a dislocation density of approximately 5×10 using a Veeco GENxplor MBE system equipped with a radio frequency (RF) plasma-assisted nitrogen source and a high temperature effusion cell for Sc. 8 cm -2GaN / sapphire templates were grown on a commercial GaN / sapphire template of 100 nm. In this case, a growth temperature of 200° C. and a V / III ratio of 1.2 were used, although growth conditions including, for example, those described above in connection with FIG. 6 may be used. In the example, a 100 nm ScAlN layer and a 120 nm Si-doped n-GaN contact layer were grown. For the n-GaN contact layer, the carrier concentration was increased to approximately 7×10 by adjusting the silicon cell temperature from 1050° C. to 1250° C. 17 cm -3 From about 1×10 20 cm -3 and further calibrated by room temperature Hall effect measurements. Ti / Au and Pt / Au circular electrodes with diameters of 3–50 μm were lithographically patterned. A 200 nm thick SiO2 layer deposited by PECVD with small dry-etched openings was used to define the electrode area with a diameter of less than 10 μm.

[0105] 20 illustrates a memory device 2000 according to an example. The memory device 2000 includes a substrate 2002 and a heterostructure 2004 supported by the substrate 2002, as described herein. The heterostructure 2004 includes a semiconductor layer 2006 (e.g., a III-nitride semiconductor layer) supported by the substrate 2002, and a ferroelectric III-nitride alloy layer 2008 supported by the semiconductor layer 2006, as also described herein. The ferroelectric III-nitride alloy layer 2008 is composed of or otherwise includes a group IIIB element, such as Sc, and may have a single crystal wurtzite structure, as described herein.

[0106] The memory device 2000 also includes write / read or other control circuitry 2010 in electrical communication with the ferroelectric III-nitride alloy layer 2008 and the semiconductor layer 2006 (e.g., III-nitride semiconductor layer), respectively. The control circuitry 2010 can be integrated with the heterostructure 2004 to any desired degree. The control circuitry 2010 is configured to apply poling and read voltages across the ferroelectric III-nitride alloy layer 2008 and the semiconductor layer 2006 (e.g., III-nitride semiconductor layer), as described herein.

[0107] The poling voltage and the read voltage may be applied through the contacts 2012, 2014 in electrical communication (e.g., in contact) with the ferroelectric III-nitride alloy layer 2008 and the semiconductor layer 2006 (e.g., III-nitride semiconductor layer), respectively. As a result, the polarity of the poling voltage applied between the contacts 2012, 2014 establishes a state of ferroelectric polarization of the ferroelectric III-nitride alloy layer 2008. In this example, application of the poling voltage causes the ferroelectric III-nitride alloy layer 2008 to be in either a first polarization state or a second polarization state. The composition, thickness, size, layout, position, and other characteristics of the contacts 2012, 2014 may vary.

[0108] The read voltage is a voltage level that generates a current through the heterostructure, the current having a level indicative of a state of ferroelectric polarization. When the device is in a first polarization state, the current through the heterostructure is at a first (e.g., high or higher) level in response to a read voltage applied between the first and second contacts. In a second polarization state, the current is at a second (e.g., low or lower) level in response to the read voltage. The degree to which the first level is higher than the second level may vary.

[0109] As described above, the ferroelectric III-nitride alloy layer can be in contact with a semiconductor layer (e.g., a III-nitride semiconductor layer) to establish a heterointerface. In some cases, the ferroelectric III-nitride alloy layer and the semiconductor layer are lattice matched. In other cases, the ferroelectric III-nitride alloy layer and the semiconductor layer are not lattice matched. As described herein, the ferroelectric III-nitride alloy layer can have a scandium content of about 18% for that purpose, although other compositions can be used (e.g., in conjunction with other alloys). The scandium content can be, for example, on the order of 10-40%. The III-nitride or other semiconductor layer can be doped (e.g., Si-doped) to configure the semiconductor layer as an electrode layer. As described herein, the doping can result in a charge carrier concentration that supports resistive switching of the polarization state of the ferroelectric III-nitride alloy layer.

[0110] 21 illustrates a method 2100 of operating a memory device according to an example. The method 2100 may be directed to the operation of the memory device of FIG. 20 or another memory device. The method 2100 may be implemented by one or more components of the control circuitry illustrated in FIG. 20 or another control circuitry.

[0111] The method 2100 may include act 2102 in which a poling voltage is applied across a heterostructure of the memory device to establish a polarization state of a ferroelectric III-nitride layer of the heterostructure, the ferroelectric III-nitride layer being supported by a III-nitride semiconductor layer of the heterostructure and consisting of or otherwise including a Group IIIB element, as described herein.

[0112] Operation 2102 may include selecting a polarity (e.g., positive or negative) of a polling voltage in operation 2104. In operation 2106, a voltage level of the polling voltage may be selected. For example, the voltage level may be +35V or -35V. The level or magnitude of the polling voltage may be selected based on operating conditions (e.g., temperature), characteristics of the heterostructure, and / or other factors. The polling voltage may then be generated by an amplifier or other voltage source circuit or generator of the control circuit in operation 2108.

[0113] In operation 2110, a read voltage is applied to the heterostructure. Operation 2110 may include operation 2112, in which a voltage level of the read voltage is selected. The voltage level may be selected based on an operating temperature, one or more characteristics of the heterostructure, and / or other factors. The read voltage may then be generated in operation 2114 by a voltage source circuit or voltage generator.

[0114] The selection of the levels of the polling and read voltages may be useful in the absence of a cooling device or procedure. For example, the device may lack a heat sink or other components intended for cooling. Alternatively or additionally, the device may not be configured to perform procedures directed to cooling. In these and other cases, the polling and read voltages may nevertheless be applied without such cooling techniques due to (1) the compatibility of the device with high temperature operation, and (2) the selection of the voltage levels.

[0115] Then, in act 2116, the level of current through the heterostructure in response to the read voltage for reading out the polarization state is determined. The manner in which the current level is measured or determined may vary. For example, the control circuitry may include any type of current detector or detection circuitry.

[0116] In the example of FIG. 21, method 2100 includes act 2118 in which output data indicative of the polarization state is generated. In act 2120, the output data may be generated based on or according to the current level. In act 2122, one or more other outputs may also be determined based on the current level. For example, the current level may be indicative of a write voltage that has been modulated as described herein, in which case information on which the modulation is based may be determined and provided as an output.

[0117] As discussed above, the heterostructure can be configured for high temperature operation. Thus, in some cases, one or more of the acts of method 2100 can be performed at an operating temperature greater than about 670 K. Other operating conditions (e.g., temperature) may also be present.

[0118] Above, an example of a stable epitaxial ScAlN / GaN heterostructure resistive memory device has been described. An analysis of the coupling between resistive switching and ferroelectric polarization has also been provided. The structure exhibits rectification ratios of about 60 to about 210, and 3×10 in response to an external bias at room temperature. 6 Retention times greater than 10 seconds, and 4The ScAlN-based ferroelectric / III-nitride heterostructures exhibited clear on and off states for more than 10 ...

[0119] Although the present disclosure has been described with reference to particular embodiments, these embodiments are merely illustrative and are not intended to limit the present disclosure. Modifications, additions, and / or deletions can be made to the embodiments without departing from the spirit and scope of the present disclosure.

[0120] The foregoing description is given for clarity of understanding only, and no unnecessary limitations should be understood therefrom.

Claims

1. A device, comprising: A substrate; a heterostructure supported by the substrate, the heterostructure having a semiconductor layer supported by the substrate, and a ferroelectric III-nitride alloy layer supported by the semiconductor layer and including a Group IIIB element; first and second contacts in electrical communication with the ferroelectric III-nitride alloy layer and the semiconductor layer, respectively; a polarity of a poling voltage applied between said first and second contacts establishes a state of ferroelectric polarization in said ferroelectric III-nitride alloy layer.

2. the ferroelectric III-nitride alloy layer is in either a first polarization state or a second polarization state; in the first polarization state, in response to a read voltage applied between the first contact and the second contact, a current flowing through the heterostructure is at a first level; in the second polarization state, the current is at a second level in response to the read voltage; The device of claim 1 , wherein the first level is higher than the second level.

3. The device of claim 1 , wherein the ferroelectric III-nitride alloy layer is in contact with the semiconductor layer to establish a heterointerface.

4. The device of claim 1 , wherein the ferroelectric III-nitride alloy layer and the semiconductor layer are lattice matched.

5. The device of claim 1 , wherein the ferroelectric III-nitride alloy layer is single crystalline.

6. The device of claim 1 , wherein the ferroelectric III-nitride alloy layer has a wurtzite structure.

7. 10. The device of claim 1, wherein the semiconductor layer is doped to configure the semiconductor layer as an electrode layer having a charge carrier concentration that supports resistive switching of the polarization state of the ferroelectric III-nitride alloy layer.

8. The device of claim 1 , wherein the semiconductor layer comprises Si-doped GaN.

9. The device of claim 1 , wherein the semiconductor layer is in contact with the substrate.

10. The device of claim 1 , wherein the ferroelectric III-nitride alloy layer comprises ScAlN.

11. The device of claim 10 , wherein the ferroelectric III-nitride alloy layer has a scandium content of about 18%.

12. A device, comprising: A substrate; a heterostructure supported by the substrate; The heterostructure comprises: a semiconductor layer supported by the substrate; a ferroelectric Group III nitride alloy layer supported by the semiconductor layer and including a Group IIIB element; the semiconductor layer is doped to configure the semiconductor layer as an electrode layer having a charge carrier concentration that supports resistive switching of the polarization state of the ferroelectric III-nitride alloy layer.

13. 1. A memory device comprising: A substrate; a heterostructure supported by the substrate, the heterostructure having a semiconductor layer supported by the substrate, and a ferroelectric III-nitride alloy layer supported by the semiconductor layer and including a Group IIIB element; a control circuit electrically connected to the ferroelectric III-nitride alloy layer and the semiconductor layer, respectively, to apply a poling voltage and a read voltage to the ferroelectric III-nitride alloy layer and the semiconductor layer, the polarities of the poling voltages respectively establish a state of ferroelectric polarization of the ferroelectric III-nitride alloy layer; A memory device, wherein the read voltage is a voltage level that produces a current through the heterostructure, the current having a level indicative of a state of ferroelectric polarization.

14. The memory device of claim 13 , wherein the ferroelectric III-nitride alloy layer is in contact with the semiconductor layer to establish a heterointerface.

15. The memory device of claim 13 , wherein the ferroelectric III-nitride alloy layer and the semiconductor layer are lattice matched.

16. The memory device of claim 13 , wherein the ferroelectric III-nitride alloy layer is of a single crystal wurtzite structure.

17. The memory device of claim 13 , wherein the semiconductor layer is Si-doped.

18. The memory device of claim 13 , wherein the ferroelectric III-nitride alloy layer comprises ScAlN.

19. 1. A method of operating a memory device, comprising: applying a poling voltage to a heterostructure of the memory device to establish a polarization state in a ferroelectric III-nitride layer of the heterostructure; the ferroelectric III-nitride layer is supported by the semiconductor layer of the heterostructure, the ferroelectric III-nitride layer comprising a Group IIIB element; The method further comprises: applying a read voltage to the heterostructure; determining a level of current flowing through the heterostructure in response to the read voltage for reading out the polarization state.

20. 20. The method of claim 19, wherein applying the poling voltage comprises selecting a level of the poling voltage to modulate the conductance of the polarization state.

21. applying the poling voltage includes selecting a level of the poling voltage based on an operating temperature; 20. The method of claim 19, wherein applying the read voltage comprises selecting a level of the read voltage based on the operating temperature.

22. The method of claim 21 , wherein applying the read voltage is performed without performing a cooling procedure.

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