Oscillator circuit with improved fault detection

Abstract

An apparatus and method for non-invasively monitoring an oscillation signal to provide a more reliable oscillation signal. An exemplary oscillation circuit generally includes an oscillator comprising an oscillator configured to generate an oscillation signal, the oscillator core circuit coupled to the resonator configured to generate the oscillation signal to enable the resonator to resonate, and an adjustable current source coupled to the oscillator core circuit and configured to control the amplitude of the oscillation signal, a first automatic gain control (AGC) circuit having an input coupled to an output of the oscillator and having an output coupled to a control input of the adjustable current source, a second AGC circuit configured to replicate the first AGC circuit, and a logic circuit having a first input coupled to an output of the first AGC circuit and a second input coupled to an output of the second AGC circuit.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of and priority to U.S. Patent Application No. 17 / 652,716, filed February 28, 2022, which is incorporated by reference herein in its entirety.

[0002] Certain aspects of the present disclosure relate generally to electronic circuits, and more particularly, to circuits that monitor oscillator signals. [Background technology]

[0003] Electronic devices include computing devices such as desktop computers, notebook computers, tablet computers, smartphones, wearable devices such as smart watches, and Internet servers. These various electronic devices provide information, entertainment, social interaction, security, safety, productivity, transportation, manufacturing, and / or other services to human users. These various electronic devices rely on wireless communication for many of their functions and may generate and utilize one or more oscillatory signals for wireless communication and / or clock signals for synchronous digital logic circuits. The oscillatory signal may be generated, for example, using a resonator (e.g., a quartz crystal or an inductor-capacitor (LC) tank, also called a resonant tank) and an oscillatory core circuit that allows the resonator to resonate.

[0004] Wireless communications may include various types of communication content, such as voice, video, packet data, messaging, broadcasts, etc. Wireless communication devices may transmit and / or receive radio frequency (RF) signals over any of a variety of suitable radio access technologies (RATs), including, but not limited to, 5G New Radio (NR), Long Term Evolution (LTE), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Wideband CDMA (WCDMA), Global System for Mobility (GSM), Bluetooth, Bluetooth Low Energy (BLE), ZigBee, wireless local area network (WLAN) RATs (e.g., IEEE 802.11), and the like. To transmit or receive data and / or control information, a radio frequency front end of a wireless communication device may include one or more frequency synthesizers for generating oscillator signals used to upconvert baseband signals and downconvert RF signals. For example, at least one of the frequency synthesizers may include a voltage-controlled oscillator (VCO) that tunes the oscillator signals to different frequencies.

[0005] To ensure reliable operation of electronic devices in many applications, the oscillator signal should be robust in many applications despite process, voltage, and temperature (PVT) variations. For example, it may be desirable for the oscillator signal to have a sufficiently high amplitude despite variations in the oscillator circuit due to PVT. Summary of the Invention

[0006] The systems, methods, and devices of the present disclosure each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of the present disclosure as expressed by the following claims, several features will now be briefly discussed. After considering this discussion, and in particular after reading the section entitled "Description of the Preferred Embodiments," one will understand how the features of the present disclosure provide the advantages described herein.

[0007] Certain aspects of the present disclosure generally relate to techniques and apparatus for monitoring oscillator signals.

[0008] Some aspects provide an oscillator circuit, the circuit generally including an oscillator configured to generate an oscillation signal, the oscillator comprising an oscillator core circuit coupled to the resonator configured to generate the oscillation signal to enable the resonator to resonate, and an adjustable current source coupled to the oscillator core circuit and configured to control an amplitude of the oscillation signal, a first automatic gain control (AGC) circuit having an input coupled to an output of the oscillator and having an output coupled to a control input of the adjustable current source, a second AGC circuit configured to replicate the first AGC circuit, and a logic circuit having a first input coupled to an output of the first AGC circuit and a second input coupled to an output of the second AGC circuit.

[0009] Some embodiments provide a method of oscillation monitoring that generally includes generating an oscillation signal with an oscillator that drives a resonator, generating a first signal with a first AGC circuit based on the oscillation signal, controlling a bias current of the oscillator based on the first signal, generating a second signal with a second AGC circuit, where the second AGC circuit replicates the first AGC circuit, and effectively monitoring the oscillation signal based on the first signal and the second signal.

[0010] Some aspects provide an apparatus with oscillation monitoring, generally including means for generating an oscillation signal, means for generating a first AGC signal based on the oscillation signal, means for controlling a bias current of the means for generating the oscillation signal based on the first AGC signal, means for generating a second AGC signal, where the means for generating the second AGC signal replicates the means for generating the first AGC signal, and means for effectively monitoring the oscillation signal based on the first AGC signal and the second AGC signal.

[0011] To the accomplishment of the foregoing and related ends, the one or more aspects comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative, however, of only a few of the various ways in which the principles of the various aspects may be employed.

[0012] So that the above-mentioned features of the present disclosure may be understood in detail, a more particular description thereof, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the accompanying drawings, in which it is to be noted, however, that the accompanying drawings show only certain exemplary embodiments of the present disclosure, and therefore should not be considered as limiting the scope of the present disclosure, since the present description may admit of other equally effective embodiments. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 illustrates an example wireless communication network in which aspects of the present disclosure may be practiced. [Diagram 2] 1 is a block diagram of an example access point (AP) and an example user terminal capable of implementing aspects of the present disclosure. [Diagram 3] 1 is a block diagram of an example transceiver circuit in which aspects of the present disclosure can be practiced. [Figure 4A]FIG. 1 is a block diagram of an example oscillator circuit with a main oscillator and a backup oscillator in which aspects of the present disclosure can be practiced. [Figure 4B] 1 is a graph illustrating an example of detecting a fault in a system after the system's output oscillating signal is lost. [Figure 4C] 11 is a graph illustrating improved fault detection in which a fault in a system is detected before the system's output oscillating signal is lost, in accordance with some aspects of the disclosure. [Figure 5A] 1 is a graph illustrating a constant failure threshold of an automatic gain control (AGC) circuit output that does not change with process, voltage, and temperature (PVT) variations. [Figure 5B] 1 is a graph illustrating a failure threshold of an AGC circuit output as a function of PVT variation, in accordance with some aspects of the present disclosure. [Figure 6] FIG. 2 is a block diagram of an example oscillator circuit including a process monitor coupled to an AGC circuit in accordance with some aspects of the present disclosure. [Figure 7A] FIG. 7 is a block diagram of an example implementation of the process monitor and AGC circuit of FIG. 6 in accordance with certain aspects of the disclosure. [Figure 7B] FIG. 7B is a schematic diagram of an example implementation of the process monitor and AGC circuit of FIGS. 6 and 7A in accordance with some aspects of the present disclosure. [Figure 8] FIG. 1 is a flow diagram illustrating an example operation of oscillation monitoring according to some aspects of the present disclosure.

[0014] For ease of understanding, the same reference numbers have been used, where possible, to designate identical elements common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Some aspects of the present disclosure generally relate to techniques and devices for non-invasively monitoring an oscillating signal. In this manner, the oscillating signal amplitude and the automatic gain control (AGC) circuit gain may be evaluated without monitoring. For example, a main automatic gain control (AGC) circuit and a replica AGC circuit may be used to evaluate the oscillating signal amplitude and the AGC circuit gain without sensing the oscillating signal amplitude. Constructed of transistors fabricated with the same semiconductor process and powered by the same voltage rail, the main AGC circuit and the replica AGC circuit may each use a constant transconductance bias generator to self-generate a process, voltage, and temperature (PVT) dependent reference. In this way, rather than using a fixed threshold, a process tracking threshold (e.g., AGC output current amplitude threshold) is effectively generated against which the main AGC circuit is tested. In this way, a weak fault (where the oscillating signal amplitude is just beginning to decrease, but the device using the oscillating signal may still be able to function) may be detected earlier (and in some cases may be corrected by switching to a backup oscillator) before a more serious fault occurs (e.g., the device is unable to function). Thus, some aspects of the present disclosure may provide a more robust oscillator signal.

[0016] Various aspects of the present disclosure will now be described more fully with reference to the accompanying drawings. However, the present disclosure may be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout the present disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art will appreciate that the scope of the present disclosure is intended to encompass any aspect of the present disclosure disclosed herein, whether implemented independently of or in combination with any other aspect of the present disclosure. For example, an apparatus can be implemented or a method can be practiced using any number of the aspects described herein. In addition, the scope of the present disclosure is intended to encompass such an apparatus or method that is practiced using other structures, functions, or structures and functions in addition to or other than the various aspects of the present disclosure described herein. It should be understood that any aspect of the present disclosure disclosed herein can be embodied by one or more elements of a claim.

[0017] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0018] As used herein, the term "connected with" in various tenses of the verb "connect" can mean that element A is directly connected to element B, or that other elements may be connected between element A and element B (i.e., element A is indirectly connected to element B). In the case of electrical components, the term "connected with" can also be used herein to mean electrically connecting element A and element B (and any components electrically connected between them) using a wire, trace, or other conductive material.

[0019] Exemplary Wireless System FIG. 1 illustrates a wireless communication system 100 with an access point 110 and a user terminal 120 in which aspects of the disclosure can be practiced. For simplicity, only one access point 110 is shown in FIG. 1. An access point (AP) is generally a fixed station that communicates with user terminals and may also be called a base station (BS), evolved Node B (eNB), or some other terminology. A user terminal (UT) may be fixed or mobile and may also be called a mobile station (MS), access terminal, user equipment (UE), station (STA), client, wireless device, or some other terminology. A user terminal may be a wireless device such as a cellular phone, a personal digital assistant (PDA), a handheld device, a wireless modem, a laptop computer, a tablet, a personal computer, etc.

[0020] The access point 110 may communicate with one or more user terminals 120 at any given moment on the downlink and uplink. The downlink (or forward link) is the communication link from the access point to the user terminals, and the uplink (or reverse link) is the communication link from the user terminals to the access point. The user terminals may also communicate peer-to-peer with other user terminals. A system controller 130 couples to the access points and provides coordination and control for the access points.

[0021] The wireless communication system 100 employs multiple transmit antennas and multiple receive antennas for data transmission on the downlink and uplink. The access point 110 may employ N transmit antennas to achieve transmit diversity for downlink transmissions and / or receive diversity for uplink transmissions. apIt can be equipped with N antennas. u A set of selected user terminals 120 may receive downlink transmissions and transmit uplink transmissions. Each selected user terminal transmits user-specific data to and / or receives user-specific data from the access point. In general, each selected user terminal may be equipped with one or multiple antennas (i.e., N ut ≧1). N u The selected user terminals may have the same or different number of antennas.

[0022] The wireless communications system 100 may be a time division duplex (TDD) system or a frequency division duplex (FDD) system. For a TDD system, the downlink and uplink share the same frequency band. For an FDD system, the downlink and uplink use different frequency bands. The wireless communications system 100 may also utilize a single carrier or multiple carriers for transmission. Each user terminal 120 may be equipped with a single antenna (e.g., to keep costs down) or multiple antennas (e.g., where additional cost can be supported). In some aspects of the disclosure, the access point 110 and / or the user terminal 120 may include circuitry to monitor an oscillating signal, as described in more detail herein.

[0023] 2 shows a block diagram of an access point 110 and two user terminals 120m and 120x in a wireless communication system 100. The access point 110 has N ap The user terminal 120m is equipped with N antennas 224a to 224ap. ut,m The user terminal 120x is equipped with N antennas 252ma to 252mu. ut,xEach user terminal 120 is equipped with antennas 252xa-252xu. The access point 110 is a transmitting entity for the downlink and a receiving entity for the uplink. Each user terminal 120 is a transmitting entity for the uplink and a receiving entity for the downlink. As used herein, a "transmitting entity" is an independently operated apparatus or device that can transmit data over a frequency channel, and a "receiving entity" is an independently operated apparatus or device that can receive data over a frequency channel. In the following description, the subscript "dn" refers to the downlink, the subscript "up" refers to the uplink, and the subscript "n" refers to the N up user terminals are selected for simultaneous transmission on the uplink, and N dn user terminals are selected for simultaneous transmission on the downlink, and N up is N dn may or may not be equal to N up and N dn , may be a static value or may change every scheduling interval. Beam-steering or some other spatial processing technique may be used at the access point and user terminal.

[0024] On the uplink, at each user terminal 120 selected for uplink transmission, a TX data processor 288 receives traffic data from a data source 286 and control data from controller 280. TX data processor 288 generates traffic data for the user terminal based on a coding and modulation scheme associated with the rate selected for the user terminal. up} to process (e.g., encode, interleave, and modulate) N ut,m A data symbol stream {s upA transceiver front end (TX / RX) 254 (also known as a radio frequency front end (RFFE)) receives and processes (e.g., converts to analog, amplifies, filters, and frequency upconverts) each symbol stream to generate an uplink signal. The transceiver front end 254 also provides N ut,m A controller 280 may route the uplink signal to one of the antennas. A controller 280 may control the routing within the transceiver front end 254. A memory 282 may store data and program codes for the user terminal 120 and may interface with the controller 280.

[0025] N up User terminals 120 may be scheduled for simultaneous transmission on the uplink, each of which transmits its set of processed symbol streams on the uplink to the access point.

[0026] At the access point 110, N ap The antennas 224a through 224ap transmit on the uplink. up The access point's transceiver front end 222 receives uplink signals from the user terminals. For receive diversity, the transceiver front end 222 may select a signal received from one of the multiple antennas 224 for processing. The signals received from the multiple antennas 224 may be combined for enhanced receive diversity. The access point's transceiver front end 222 also performs processing that is complementary to that performed by the user terminal's transceiver front end 254 and provides a recovered uplink data symbol stream. The recovered uplink data symbol stream may be a composite of the data symbol stream {s up} is an estimate of the uplink data symbol stream. The RX data processor 242 processes (e.g., demodulates, deinterleaves, and decodes) the recovered uplink data symbol stream in accordance with the rate used for that stream to obtain decoded data. The decoded data for each user terminal may be provided to a data sink 244 for storage and / or to controller 230 for further processing.

[0027] In some aspects, the transceiver front end (TX / RX) 222 of the access point 110 and / or the transceiver front end 254 of the user terminal 120 may include one or more frequency synthesizers to generate oscillator signals used for signal transmission and / or reception. In some aspects, the controller 230 of the access point 110 and / or the controller 280 of the user terminal 120 may include or be coupled to oscillator circuits that generate oscillator signals used to clock the synchronization logic. At least one of the frequency synthesizers and / or at least one of the oscillator circuits may include or be coupled to circuitry that monitors the oscillator signals, as described in more detail herein.

[0028] On the downlink, at access point 110, a TX data processor 210 processes N dn The TX data processor 210 receives traffic data for the N user terminals from a data source 208, control data from a controller 230, and possibly other data from a scheduler 234. Various types of data may be sent on different transport channels. The TX data processor 210 processes (e.g., encodes, interleaves, and modulates) the traffic data for each user terminal based on a rate selected for that user terminal. The TX data processor 210 processes (e.g., encodes, interleaves, and modulates) the traffic data for the N user terminals based on a rate selected for that user terminal. ap N to be transmitted from one of the antennas. dnThe transceiver front end 222 may provide a downlink data symbol stream for one or more of the user terminals. The transceiver front end 222 receives and processes (e.g., converts to analog, amplifies, filters, and frequency upconverts) the symbol stream to generate a downlink signal. The transceiver front end 222 may also provide an N 1 1 1 ap A controller 230 may route downlink signals to one or more of the antennas 224. A controller 230 may control routing within the transceiver front end 222. A memory 232 may store data and program codes for the access point 110 and may interface with the controller 230.

[0029] In each user terminal 120, N ut,m The antennas 252 receive downlink signals from the access point 110. For receive diversity at the user terminal 120, the transceiver front end 254 may select a signal received from one of the multiple antennas 252 for processing. Signals received from the multiple antennas 252 may be combined for enhanced receive diversity. The user terminal's transceiver front end 254 also performs processing that is complementary to that performed by the access point's transceiver front end 222 and provides a recovered downlink data symbol stream. An RX data processor 270 processes (e.g., demodulates, deinterleaves, and decodes) the recovered downlink data symbol stream to obtain decoded data for the user terminal.

[0030] 3 is a block diagram of an example transceiver circuit 300, such as the transceiver front-end 222, 254 in FIG. 2, in which aspects of the disclosure may be practiced. The transceiver circuit 300 includes at least one transmit (TX) path 302 (also known as a "transmit chain") that transmits signals via one or more antennas, and at least one receive (RX) path 304 (also known as a "receive chain") that receives signals via the antenna. When the TX path 302 and the RX path 304 share an antenna 303, the paths may be connected to the antenna via an interface 306, which may include any of a variety of suitable RF devices, such as duplexers, switches, diplexers, and the like.

[0031] Receiving an in-phase (I) or quadrature-phase (Q) baseband analog signal from a digital-to-analog converter (DAC) 308, the TX path 302 may include a baseband filter (BBF) 310, a mixer 312, a driver amplifier (DA) 314, and a power amplifier (PA) 316. The BBF 310, the mixer 312, and the DA 314 may be included within one or more radio frequency integrated circuits (RFICs). The PA 316 may be external to the RFIC(s) in some implementations.

[0032] The BBF 310 filters the baseband signal received from the DAC 308, and the mixer 312 mixes the filtered baseband signal with a transmit local oscillator (LO) signal to convert the baseband signal of interest to a different frequency (e.g., upconvert from baseband to RF). This frequency conversion process generates sum and difference frequencies between the LO frequency and the frequency of the signal of interest. The sum and difference frequencies are called "beat frequencies." The beat frequency may be in the RF range, and thus the signal output by the mixer 312 may be an RF signal and may be amplified by the DA 314 and / or amplified by the PA 316 before transmission by the antenna 303. Although one mixer 312 is illustrated, several mixers may be used to upconvert the filtered baseband signal to one or more intermediate frequencies and then upconvert the intermediate frequency (IF) signal to a frequency for transmission.

[0033] The RX path 304 includes a low noise amplifier (LNA) 322, a mixer 324, and a baseband filter (BBF) 326. The LNA 322, mixer 324, and BBF 326 may be included in one or more RFICs. The RFIC may or may not be the same RFIC(s) that includes the TX path components. RF signals received via the antenna 303 may be amplified by the LNA 322, and the mixer 324 mixes the amplified RF signal with a receive local oscillator (LO) signal to convert (i.e., downconvert) the RF signal of interest to a different baseband frequency. The baseband signal output by the mixer 324 may be filtered by the BBF 326 before being converted by an analog-to-digital converter (ADC) 328 to digital I or Q signals for digital signal processing.

[0034] Some transceivers may employ a frequency synthesizer with a voltage controlled oscillator (VCO) to generate a stable, tunable LO with a particular tuning range. Thus, the transmit LO frequency may be generated by the TX frequency synthesizer 318, which may be buffered or amplified by the amplifier 320 before being mixed with the baseband signal in the mixer 312. Similarly, the receive LO frequency may be generated by the RX frequency synthesizer 330, which may be buffered or amplified by the amplifier 332 before being mixed with the RF signal in the mixer 324. In some aspects, the TX frequency synthesizer 318 and / or the RX frequency synthesizer 330 may include or be coupled to circuitry that monitors the oscillator signal, as described in more detail herein.

[0035] Although FIGS. 1-3 provide a wireless communication system as an example application in which certain aspects of the present disclosure may be implemented for ease of understanding, certain aspects described herein may be used to monitor an oscillator signal in any of a variety of other suitable systems.

[0036] EXEMPLARY OSCILLATOR CIRCUIT WITH IMPROVED FAULT DETECTION An electronic device (e.g., a wireless communication device) may include an oscillator circuit and a performance monitoring system to ensure robust operation in the oscillator circuit and switch to a backup circuit when instructed. In some oscillator circuits (e.g., oscillator circuits in automotive safety systems), a non-invasive performance monitoring system is desirable. One or more automatic gain control (AGC) circuits may act as a primary monitor for the oscillator circuit. The AGC circuit may monitor the amplitude of an output signal of an oscillator in the oscillator circuit and adjust the bias current of the oscillator based on the amplitude of the output signal.

[0037] 4A is a block diagram of an example oscillator circuit 400A. The oscillator circuit 400A may include a first AGC circuit 402, a second AGC circuit 408, a safety monitor 416, a resonator 418, a first oscillator 420 (e.g., a main oscillator), and a second oscillator 422 (e.g., a backup oscillator). The first oscillator 420 may include a first oscillator core circuit 404 and a first current source 406, and the second oscillator 422 may include a second oscillator core circuit 410 and a second current source 412. The first and second oscillator core circuits 404, 410 may be coupled to the resonator 418 and configured to generate an oscillation signal to enable the resonator 418 to resonate. The first and second oscillator core circuits 404, 410 may include any suitable type of oscillator core, such as a crystal oscillator core, that drives the resonator. An output node 426 of the oscillator circuit 400A may provide a clock signal to one or more other systems.

[0038] As shown, the first AGC circuit 402 may have an input coupled to an output of a first oscillator 420 and may have an output coupled to a control input of a first current source 406. Similarly, the second AGC circuit 408 may have an input coupled to an output of a second oscillator 422 and may have an output coupled to a control input of a second current source 412. The first current source 406 and the second current source 412 may be adjustable current sources.

[0039] The first AGC circuit 402 may be configured to monitor the amplitude of the signal output from the first oscillator 420. In one exemplary case, if the first AGC circuit 402 senses that the amplitude of the signal output by the first oscillator 420 is too low, the first AGC circuit 402 may control the first current source 406 to increase the current supplied to the first oscillator core circuit 404. The second AGC circuit 408 may be configured to monitor the amplitude of the signal output from the second oscillator 422 and control the second current source 412 in a similar manner.

[0040] If one of the AGC circuits 402 and 408 fails, the oscillator circuit 400A may be left without a primary monitoring system to monitor the health of the oscillators 420 and 422. Thus, both the first AGC circuit 402 and the second AGC circuit 408 may be communicatively coupled to a safety monitor 416. The safety monitor 416 may be configured to monitor the performance (e.g., health) of the first AGC circuit 402 and the second AGC circuit 408. In some aspects, the safety monitor 416 may send a query (e.g., a ping) to each of the first AGC circuit 402 and the second AGC circuit 408. In response to the query, the first AGC circuit 402 and / or the second AGC circuit 408 may respond with a status signal indicating whether each AGC circuit is functional and operating correctly. In other aspects, the first AGC circuit 402 and / or the second AGC circuit 408 may send such status signals to the safety monitor 416 periodically or continuously.

[0041] The oscillator circuit 400A (more specifically, the safety monitor 416) can select between the signal generated by the first oscillator 420 and the signal generated by the second oscillator 422 as an output signal at the output node 426. In some aspects, the safety monitor 416 can output (e.g., over a bus) a first enable signal that enables and / or disables the first oscillator 420 and a second enable signal that enables and / or disables the second oscillator 422, as shown in FIG. 4A. In some aspects, for example, the first oscillator 420 can be enabled first and the second oscillator 422 can be disabled first. If the first AGC circuit 402 fails (e.g., as indicated by its associated status signal) or if the first AGC circuit 402 detects a failure from the first oscillator 420, the safety monitor 416 can instruct (e.g., via an enable signal) the oscillator circuit 400A to switch to using the signal generated by the second oscillator 422 as an output signal (e.g., the safety monitor 416 can disable the first oscillator 420 and enable the second oscillator 422). Thus, the first oscillator 420 can be considered a primary oscillator and the second oscillator 422 can be considered a backup oscillator.

[0042] In one example, the oscillator circuit 400A may include additional circuitry (not shown) configured to monitor the output signal of the first oscillator 420 at the output node 426. In response to a detected fault at this location, the oscillator circuit 400A may switch to using the signal generated by the second oscillator 422 as the output signal. However, sensing the output node 426 of the oscillator circuit 400A may introduce frequency shifts and / or phase noise degradation into the oscillating signal. In one example, the additional circuitry may include a clock stop detector. However, the stop detector is generally configured to monitor for complete clock failure (e.g., after the clock signal has already been lost), which may lead to fault detection occurring too late.

[0043] FIG. 4B is a graph 400B illustrating an example of detecting a fault after an output signal (e.g., a signal at an output node 426) of an oscillator (e.g., the first oscillator 420) is lost. As shown, before time 430, the system may operate using the main oscillator (e.g., the first oscillator 420). At time 430, the main oscillator core circuit (e.g., the first oscillator core circuit 404) may fail and the output signal may begin to droop (e.g., the amplitude of the output signal may decrease). As shown, the system (more specifically, a circuit such as a clock stop detector) may not detect the fault until time 440, when the output signal has significantly drooped (e.g., lost). Once the fault is detected, the system may switch to a backup oscillator (e.g., the second oscillator 422). However, if the output signal is lost, even if the system switches to the backup oscillator, other systems using the output signal may be reset, restarted, or enter an unintended state, which is undesirable.

[0044] Accordingly, some aspects of the present disclosure provide a system with improved fault detection in which a fault may be detected before the output signal is lost. Figure 4C is a graph 400C illustrating an example of improved fault detection according to some aspects of the present disclosure. As shown, when a primary oscillator fails at time 430, a system with improved fault detection detects the fault at time 450 before the output signal is lost. As a result, the system can switch to a backup oscillator before the output signal is lost, thereby avoiding undesirable consequences for other components that use the output signal as a clock signal.

[0045] To achieve this improved fault detection, aspects of the disclosure provide apparatus and techniques that use the output of an AGC circuit (as opposed to the output of an oscillator) and a logic circuit (as opposed to, e.g., a failure detector) to monitor the health of the oscillator core circuit.

[0046] There are several methods to monitor the health of the oscillator core circuit and the AGC circuit based on the output of the AGC circuit. However, these methods tend to be invasive, unreliable, and / or adversely affect the performance of the oscillator circuit. For example, one method involves breaking the feedback loop between the oscillator and the AGC circuit and verifying the gain of the AGC circuit using a test input signal with a known amplitude. However, this invasive method may only be used in a factory test mode (as opposed to a mission mode) where the oscillator system is in a factory test mode and does not provide real-time fault detection in the mission mode. Another method involves using an analog-to-digital converter (ADC) to measure the amplitude of the AGC input signal, but the ADC may generate kickback noise that may cause frequency shifts and / or phase noise degradation in the oscillator circuit. The ADC also consumes additional power and occupies additional area. Yet another method involves monitoring only the amplitude of the output signal of the AGC circuit. In this case, the gain cannot be calculated accurately because only the output amplitude (and not the input amplitude) is known. This method can be unreliable because the amplitude of the AGC output signal is sensitive to variations in process, voltage, and temperature (PVT) conditions and therefore the monitoring system may not be able to capture all faults across PVT variations.

[0047] For example, FIG. 5A is a graph 500A illustrating a constant failure threshold of the AGC circuit output that does not change with PVT variations. In this case, the fixed threshold of the AGC output may be set high enough to avoid false failures across PVT variations. As illustrated, when a constant threshold is used to indicate a failure, the system may not be able to detect a failure across all PVT variations. That is, the amplitude of the output of the AGC circuit may be below the failure threshold (pass indication) in some PVT conditions even when the oscillator circuit (more specifically, the AGC circuit and / or the oscillator core circuit of the oscillator circuit) is faulty. Thus, a constant failure threshold may cause the monitoring system to generate a false "pass" indication. Furthermore, using a constant threshold cannot detect a situation called a "weak failure" where, across PVT variations, the oscillator circuit is still functioning but performance is degraded (e.g., in terms of phase noise and / or frequency accuracy).

[0048] Accordingly, some aspects of the present disclosure provide techniques and apparatus for detecting faults based on the output of an AGC circuit that takes into account the PVT variations of the system and effectively provides a PVT tracking threshold for oscillation monitoring. FIG. 5B is a graph 500B illustrating a fault threshold of an AGC circuit output that varies with PVT variations, according to some aspects of the present disclosure. The PVT tracking threshold allows the system to avoid false passes and detect even "weak" faults (e.g., before the clock signal is lost, as at time 450 in FIG. 4C) regardless of the PVT variations. The PVT tracking threshold can be effectively self-generated by a constant transconductance bias generator, which is described further below.

[0049] 6 is a block diagram of an example oscillator circuit 600 according to some aspects of the disclosure. The oscillator circuit 600 may be similar to the oscillator circuit 400A, but with a process monitor 604 (also referred to herein as a "logic circuit"). In addition to the process monitor 604, the oscillator circuit 600 may generally include an oscillator health monitor 602, an AGC circuit 606, an oscillator core circuit 608, a current source 610, and a resonator 618. The oscillator core circuit 608 and the current source 610 may constitute an oscillator, such as the oscillator 420 or 422 of FIG. 4A. In some aspects, at least a portion of the process monitor 604 may be integrated with the AGC circuit 606.

[0050] The oscillator core circuit 608 may be configured to generate an oscillation signal to enable the resonator 618 to resonate. The current source 610 may be adjustable and may be configured to control the amplitude of the oscillation signal by providing an adjustable bias current.

[0051] The AGC circuit 606 may have an input coupled to an output of the oscillator core circuit 608. The AGC circuit 606 may be configured to output a first output signal at 614 to control a current source 610, as described above with reference to FIG. 4A. Additionally, the first output signal may also be used as a first input of the process monitor 604, as shown at 616. The AGC circuit 606 may be further configured to output a second output at 612 to be used as a second input of the process monitor. The second output of the AGC circuit 606 may be a replica output generated by a replica AGC circuit configured to replicate the primary AGC circuit in the AGC circuit 606, as described below. For example, the replica AGC circuit may have the same or similar topology as the main AGC circuit and may be fabricated using the same semiconductor process as the main AGC circuit.

[0052] The oscillator health monitor 602 may be configured to check (e.g., periodically, intermittently, or continuously) whether the oscillator is functioning properly (e.g., generating a proper output signal). For example, the oscillator health monitor 602 may send (e.g., ping) a request to the process monitor 604 for an indication regarding the health of the oscillator. The process monitor 604 may be configured to compare a first output signal (e.g., at 616) and a second output signal (e.g., at 612) of the AGC circuit 606 and report the comparison to the oscillator health monitor 602. Thus, the process monitor 604 may be configured to effectively monitor the oscillation signal generated by the oscillator based on the two outputs of the AGC circuit 606. In this way, the AGC amplitude and gain are evaluated without monitoring the AGC input amplitude. Instead, the AGC output amplitude is monitored by process tracking amplitude sensing, as described below.

[0053] 7A is a block diagram of an example implementation of the process monitor 604 and the AGC circuit 606 of FIG. 6 in accordance with some aspects of the disclosure. The AGC circuit 606 may include a first AGC circuit 702 and a second AGC circuit 704 configured to replicate the first AGC circuit 702. The process monitor 604 may include a comparator 706, which may be adjustable. The comparator 706 may have a first input (e.g., a negative input) coupled to an output of the first AGC circuit 702 and a second input (e.g., a positive input) coupled to an output of the second AGC circuit 704. The comparator 706 may be configured to compare output signals from the first AGC circuit 702 and the second AGC circuit 704 to determine whether the oscillator circuit 600 (more specifically, the AGC circuit 606 and / or the oscillator core circuit 608) has failed.

[0054] The output of the first AGC circuit 702 (labeled “OUT”) may be determined as follows: OUT=(REF-IN) * A where IN is the input signal of the first AGC circuit 702 (the output signal from the oscillator), and A is the gain of the first AGC circuit 702. REF may be a self-generated reference signal. That is, the oscillator circuit (e.g., the first AGC circuit 702 and the second AGC circuit 704) may generate REF via a constant transconductance bias generator.

[0055] When the oscillator circuit is functioning properly, the amplitude of the input signal IN will be sufficiently high and the amplitude of the output signal OUT will be relatively low (due to the reduced difference between REF and IN). Thus, in some cases, the health of the oscillator circuit can be monitored by monitoring the output of the first AGC circuit 702 and determining when the output signal OUT is sufficiently high.

[0056] One exemplary method of monitoring when the output signal OUT is high enough involves comparing the output signal OUT to another signal (e.g., a threshold). As discussed with respect to FIGS. 5A and 5B, it is desirable to vary the threshold according to the PVT variation so that soft faults can be detected across PVT conditions. Accordingly, some aspects of the present disclosure provide a method of comparing the output signal OUT to a replica output signal from the second AGC circuit 704. The output of the second AGC circuit 704 ("OUT REP ") may be determined as follows: OUT REP =REF * A REP In the formula, A REP is the gain of the second AGC circuit 704. The second AGC circuit 704 is configured to replicate the first AGC circuit 702, so that the output signal OUT REP varies with the PVT in the same way as the output signal OUT, thereby providing a PVT-dependent threshold. Thus, OUT and OUT REP A relative comparison is performed between

[0057] The comparator 706 may be configured to effectively monitor the oscillating signal generated by an oscillator (e.g., the oscillator core circuit 608 and the current source 610 in FIG. 6) based on the output of the first AGC circuit 702 and the output of the second AGC circuit 704. Thus, the oscillator circuit may be able to effectively monitor the oscillating signal generated by the oscillator without directly sensing the amplitude of the oscillating signal. According to some aspects, the comparator 706 may compare the output signal OUT with the amplitude of the output signal OUT REP Compared with OUT REP A logic circuit (labeled "AGC_OK") may be configured to output a high signal (e.g., logic 1) when the amplitude of AGC is greater than or equal to the amplitude of OUT, thereby indicating that the oscillator circuit is functioning properly.

[0058] Based on the above formula and this circuit setup, OUT REP When AGC_OK is greater than or equal to OUT, the comparator 706 should indicate that the oscillator circuit is OK (AGC_OK=1). In this situation: REF * A REP ≧(REF-IN) * A

[0059] Rearranging these equations to solve for IN leads to the following:

number

[0060] Therefore, A REP The gain ratio of A to A can be set such that this equation is true when the amplitude of IN is acceptable (e.g., when the oscillator circuit, and more specifically, the oscillator core circuit and the AGC circuit, are functioning properly).

[0061] The ratio of the gain of the second AGC circuit 704 to the gain of the first AGC circuit 702 (e.g., A REP to A) can be calculated as follows:

number

[0062] where n depends on the transistor size ratio between the transistors in the first AGC circuit 702 and the transistors in the comparator 706, and m depends on the transistor size ratio between the transistors in the second AGC circuit 704 and the transistors in the comparator 706, as described further below. REP The gain ratio of A to A may be set by designing (and in some cases adjusting during factory calibration) the transistor sizes in the first AGC circuit 702, the second AGC circuit 704, and the comparator 706, as described further below.

[0063] 7B is a schematic diagram of an oscillator circuit 700 with an example implementation of the first AGC circuit 702, the second AGC circuit 704, and the comparator 706 of FIG. 7A in accordance with some aspects of the disclosure. As shown, the oscillator circuit 700 also includes an oscillator 701 coupled to the first AGC circuit 702.

[0064] Oscillator 701 may be similar to oscillator 420 or 422 in FIG. 4A and may include an adjustable current source (e.g., implemented by transistor 708) and an oscillator core circuit 705 having an input coupled to the drain of transistor 708 and having an output coupled to resonator 707. Oscillator 701 may be configured to generate an oscillation signal. More specifically, oscillator core circuit 705 may be configured to generate the oscillation signal to enable resonator 707 to resonate. The adjustable current source (implemented by transistor 708) may be adjusted to adjust the amplitude of the oscillation signal ("I OUT ").

[0065] The comparator 706 may include a first transistor 718, a second transistor 720, and an inverter 730. The comparator 706 may have a first input (e.g., a gate of transistor 718) coupled to an output of the first AGC circuit 702 (e.g., node 711 coupled to a gate of transistor 708) and a second input (e.g., a gate of transistor 720) coupled to an output of the second AGC circuit 704 (node ​​721). The transistor 718 may be a p-type transistor and may have a source coupled to a power rail (labeled "VDD") of the oscillator circuit 700. The transistor 720 may be an n-type transistor that may have a source coupled to a reference potential node (e.g., electrical ground) for the oscillator circuit 700 and may have a drain coupled to the drain of the transistor 718. In some examples, at least one of the transistors 718 and 720 may be adjustable. Inverter 730 may have an input coupled to the drain of transistor 718 and the drain of transistor 720, and an output coupled to the output of comparator 706 (labeled “AGC_OK”).

[0066] The first AGC circuit 702 may have an input coupled to the output of the oscillator 701 and may have an output (e.g., at node 711) coupled to a control input of an adjustable current source (e.g., the gate of transistor 708). The first AGC circuit 702 may include a first transistor 710 having a source coupled to a power rail. The transistor 710 may be a p-type transistor. The first AGC circuit 702 may also include a second transistor 712 having a source coupled to a reference potential node and having a drain coupled to the drain of the transistor 710. The transistor 712 may be an n-type transistor. The first AGC circuit 702 may also include a third transistor 714 having a source coupled to a power rail and having a gate coupled to the drain of the transistor 714, the gate of the transistor 710, and the gate of the transistor 718 of the comparator 706. The transistor 714 may be a p-type transistor. The first AGC circuit 702 may also include a fourth transistor 716 having a drain coupled to the drain and gate of the transistor 714. The transistor 716 may be an n-type transistor. The first AGC circuit 702 may also include a first resistive element R1 coupled between a source of the transistor 716 and a reference potential node.

[0067] In some examples, the first AGC circuit 702 may further include a second resistive element R2 coupled between the gate of transistor 712 and the drain of transistor 712, and a third resistive element R3 coupled between the drain of transistor 712 and the gate of transistor 716. In some examples, the first AGC circuit 702 may also include a first capacitive element C1 coupled between the gate of transistor 716 and a reference potential node. According to some aspects, the transistors 710, 712, 714, 716, the first resistive element R1, the second resistive element R2, and the third resistive element R3 are process, voltage, and temperature (PVT) dependent (referred to as "PVT"). REF7A , forming at least a portion of a constant transconductance bias generator configured to generate a reference current (labeled "REF" in the equation above with respect to FIG. 7A ). The reference current is represented by REF in the equation above with respect to FIG. 7A .

[0068] According to some aspects, the oscillator circuit 700 may also include a second capacitive element C2 coupled between the gate of the transistor 712 and the output of the oscillator 701. The second capacitive element C2 may be used to AC-couple the output of the oscillator 701 to the input of the first AGC circuit 702.

[0069] The second AGC circuit 704 may be configured to replicate the first AGC circuit 702. For example, the second AGC circuit 704 may have the same or similar topology as the first AGC circuit 702 and may be fabricated using the same semiconductor process as the first AGC circuit 702. The second AGC circuit 704 may include a first transistor 722 having a source coupled to a power supply rail, and a second transistor 726 having a drain coupled to a reference potential node, the drain of transistor 722, the gate of transistor 726, and the gate of transistor 720 (e.g., node 721). Transistor 722 may be a p-type transistor and transistor 726 may be an n-type transistor. The second AGC circuit 704 may also include a third transistor 724 having a source coupled to a power supply rail and a drain coupled to the gate of transistor 724 and the gate of transistor 722. Transistor 724 may be a p-type transistor. The second AGC circuit 704 may also include a fourth transistor 728 having a drain coupled to the drain and gate of transistor 724 and a gate coupled to the gate and drain of transistor 726, and a resistive element R4 coupled between the source of transistor 728 and a reference potential node. Transistor 728 may be an n-type transistor.

[0070] Transistor 722, transistor 726, transistor 724, and transistor 728 are connected to a second reference current ("I REF7B, the second AGC circuit 704 forms at least a portion of another constant transconductance bias generator configured to generate a REF (also labeled "REF"). According to some aspects, as shown in FIG. 7B, the input of the second AGC circuit 704 is an open circuit such that the input of the second AGC circuit 704 is configured to have zero current. In this manner, the second AGC circuit 704 amplifies the difference between REF and 0, as illustrated in FIG. 7A.

[0071] According to some aspects, the transistor size ratio between transistors 720, 726, and 728 may be m:1:1 (m≧1), and the transistor size ratio between transistors 718, 710, and 714 may be n:1:1 (n≧1). The value of m may represent the gain of the second AGC circuit 704, and the value of n may represent the gain of the first AGC circuit 702 (or at least the ratio of m to n may represent the gain of the first AGC circuit 702). REP Therefore, as described above, the gain of the second AGC circuit 704 (e.g., A REP ) to the gain (e.g., A) of the first AGC circuit 702 can be set by adjusting transistor sizes in the first AGC circuit 702, the second AGC circuit 704, and the comparator 706.

[0072] As explained above, the first AGC circuit 702 may generate a first reference current (e.g., I REF ), and the second AGC circuit 704 may include another constant transconductance bias generator configured to generate a second reference current. If the transistors in the first and second AGC circuits are fabricated using the same semiconductor process, receive the same power supply rail voltage (Vdd), and are exposed to the same temperature, the second reference current should be equal to the first reference current. In this case, the ratio of m to n may be set such that the comparator 706 is configured to output a logic high signal when the amplitude of the oscillating signal is estimated to be equal to or greater than the amplitude of the reference current multiplied by (1-m / n).

[0073] In some aspects, the adjustable current source may be implemented using transistor 708. As shown, transistor 708 may have a source coupled to a power rail, a drain coupled to oscillator core circuit 705, and a gate coupled to a gate of transistor 710 and to transistor 714. In some aspects, transistor 708 may be a p-type transistor. In some aspects, the transistor size ratio between transistor 708, transistor 710, and transistor 714 is x:1:1, where x≧1.

[0074] According to some aspects, the oscillator circuit 700 may also include a backup oscillator (e.g., similar to oscillator 701 described with respect to FIG. 4A ) configured to generate another oscillation signal, a third AGC circuit (similar to the first AGC circuit 702), a fourth AGC circuit (similar to the second AGC circuit 704), and another comparator (similar to comparator 706). In some aspects, the backup oscillator may include another oscillator core circuit coupled to the resonator, and another adjustable current source coupled to the other oscillator core circuit and configured to control the amplitude of the other oscillation signal. In this case, the third AGC circuit may have an input coupled to an output of the backup oscillator and an output coupled to a control input of the other adjustable current source. In some aspects, the process monitor 604 (or other comparator similar to comparator 706) may have a third input coupled to an output of the third AGC circuit and a fourth input coupled to an output of the fourth AGC circuit. In some aspects, the fourth AGC circuit may be configured to replicate (eg, replicate the topology of) the third AGC circuit.

[0075] Example Operation of Oscillation Monitoring 8 is a flow diagram illustrating an example operation 800 of oscillation monitoring according to some aspects of the disclosure. The operation 800 may be performed by an oscillator circuit such as the oscillator circuit 600 of FIG. 6 or the oscillator circuit 700 of FIG. 7B. The flow diagram includes blocks representing the operation 800.

[0076] The operations 800 may begin in block 802 by generating an oscillation signal (e.g., IN) using an oscillator (e.g., oscillator 701) that drives a resonator (e.g., resonator 618, 707). In block 804, a first automatic gain control (AGC) circuit (e.g., first AGC circuit 702) may generate a first signal (e.g., OUT) based on the oscillation signal. In block 806, the first AGC circuit may control a bias current (e.g., I OUT In block 808, the second AGC circuit (e.g., the second AGC circuit 704) may control the second signal (e.g., OUT REP ). The second AGC circuit may replicate the first AGC circuit. For example, the second AGC circuit may have the same or similar topology as the first AGC circuit and may be fabricated using the same semiconductor process as the first AGC circuit. In block 810, the oscillator circuit may effectively monitor the oscillation signal (e.g., using logic circuits such as comparator 706 or process monitor 604) based on the first signal and the second signal.

[0077] According to some aspects, effectively monitoring the oscillating signal at block 810 may involve effectively monitoring the oscillating signal without directly sensing the amplitude of the oscillating signal.

[0078] According to some aspects, effectively monitoring the oscillating signal in block 810 may involve comparing the first signal to the second signal and outputting a status signal indicative of a fault (e.g., AGC_OK is logic low) when the amplitude of the second signal is less than the amplitude of the first signal. According to some aspects, the operations 800 may further involve generating another oscillating signal using a backup oscillator (e.g., oscillator 422 of FIG. 4A ) and switching to using the other oscillating signal instead of the oscillating signal in response to the status signal indicating a fault.

[0079] According to some aspects, a first transistor size ratio between the first n-type transistor of the comparator (e.g., transistor 720) and the second n-type transistor of the second AGC circuit (e.g., transistor 726 or transistor 728) is m:1, and a second transistor size ratio between the first p-type transistor of the comparator (e.g., transistor 718) and the second p-type transistor of the first AGC circuit (e.g., transistor 710 or transistor 714) is n:1. In some aspects, a second signal from the second AGC circuit controls the first n-type transistor of the comparator and the second n-type transistor of the second AGC circuit, and a first signal from the first AGC circuit controls the first p-type transistor of the comparator and the second p-type transistor of the first AGC circuit. According to some aspects, the ratio of m to n determines the gain (e.g., gain A REP ) to the gain of the first AGC circuit (e.g., gain A).

[0080] According to some aspects, generating the first signal includes using a constant transconductance bias generator (e.g., transistors 710, 712, 714, and 716) of the first AGC circuit to generate a process, voltage, and temperature (PVT) dependent first reference current (e.g., I through transistor 710) of the first AGC circuit. REF In some aspects, generating the second signal may involve using a second AGC circuit to generate a second reference current (e.g., I through transistor 726) equal to the first reference current. REF ).

[0081] According to some aspects, effectively monitoring the oscillating signal in block 810 may involve outputting a logic high signal (e.g., AGC_OK is logic high) from the comparator when the amplitude of the oscillating signal is estimated to be greater than or equal to the amplitude of the first reference current multiplied by (1-m / n).

[0082] Exemplary Aspects In addition to the various aspects described above, specific combinations of aspects are within the scope of the present disclosure, some of which are detailed below.

[0083] Aspect 1: An oscillator configured to generate an oscillation signal, the oscillator comprising: an oscillator core circuit coupled to a resonator configured to generate an oscillation signal to enable the resonator to resonate; and an adjustable current source coupled to the oscillator core circuit and configured to control an amplitude of the oscillation signal; a first automatic gain control (AGC) circuit having an input coupled to an output of the oscillator and having an output coupled to a control input of the adjustable current source; a second AGC circuit configured to replicate the first AGC circuit; and a logic circuit having a first input coupled to the output of the first AGC circuit and a second input coupled to the output of the second AGC circuit.

[0084] Aspect 2: The oscillator circuit of aspect 1, wherein the logic circuit is configured to effectively monitor the oscillator signal based on an output of the first AGC circuit and an output of the second AGC circuit.

[0085] Aspect 3: The oscillator circuit of aspect 1 or 2, wherein the oscillator circuit is configured to effectively monitor the oscillator signal without directly sensing the amplitude of the oscillator signal.

[0086] Aspect 4: An oscillator circuit as described in any of the preceding aspects, wherein the logic circuit comprises a comparator having a first input coupled to the output of the first AGC circuit and having a second input coupled to the output of the second AGC circuit.

[0087] Aspect 5: The oscillator circuit of aspect 4, wherein the comparator comprises: a first p-type transistor having a source coupled to the power supply rail; a first n-type transistor having a source coupled to a reference potential node for the oscillator circuit and having a drain coupled to the drain of the first p-type transistor, where at least one of the first p-type transistor or the first n-type transistor is adjustable; and an inverter having an input coupled to the drain of the first p-type transistor and the drain of the first n-type transistor and having an output coupled to the output of the comparator.

[0088] Aspect 6: The oscillator circuit of aspect 5, wherein the first AGC circuit comprises: a second p-type transistor having a source coupled to the power supply rail; a second n-type transistor having a source coupled to a reference potential node and having a drain coupled to the drain of the second p-type transistor; a third p-type transistor having a source coupled to the power supply rail and a gate coupled to the drain of the third p-type transistor, the gate of the second p-type transistor, and the gate of the first p-type transistor; a third n-type transistor having a drain coupled to the drain and gate of the third p-type transistor; and a first resistive element coupled between the source of the third n-type transistor and the reference potential node.

[0089] Aspect 7: The oscillator circuit of aspect 6, wherein the first AGC circuit further comprises a second resistive element coupled between a gate of the second n-type transistor and a drain of the second n-type transistor, a third resistive element coupled between the drain of the second n-type transistor and a gate of the third n-type transistor, and a first capacitive element coupled between the gate of the third n-type transistor and a reference potential node.

[0090] Example 8: The oscillator circuit of example 7, further comprising a second capacitive element coupled between the gate of the second n-type transistor and the output of the oscillator.

[0091] Aspect 9: The oscillator circuit of aspect 7 or 8, wherein the second n-type transistor, the third n-type transistor, the first resistive element, the second resistive element, and the third resistive element form at least a portion of a constant transconductance bias generator configured to generate a reference current that is process, voltage, and temperature (PVT) dependent.

[0092] Embodiment 10: An oscillator circuit according to any one of embodiments 6 to 9, wherein a transistor size ratio of the first p-type transistor, the second p-type transistor, and the third p-type transistor is n:1:1, where n≧1.

[0093] Example 11: An oscillator circuit as described in any of examples 6 to 10, wherein the adjustable current source comprises a fourth p-type transistor having a source coupled to the power supply rail, a drain coupled to the oscillator core circuit, and a gate coupled to the gate of the second p-type transistor and the third p-type transistor, wherein the transistor size ratio of the fourth p-type transistor, the second p-type transistor, and the third p-type transistor is x:1:1, where x≧1.

[0094] Aspect 12: An oscillator circuit as described in any of aspects 6 to 10, wherein the second AGC circuit comprises: a fourth p-type transistor having a source coupled to the power supply rail; a fourth n-type transistor having a source coupled to a reference potential node and having a drain coupled to the drain of the fourth p-type transistor, the gate of the fourth n-type transistor, and the gate of the first n-type transistor; a fifth p-type transistor having a source coupled to the power supply rail and having a drain coupled to the gate of the fifth p-type transistor and the gate of the fourth p-type transistor; a fifth n-type transistor having a drain coupled to the drain and gate of the fifth p-type transistor; and a second resistive element coupled between the source of the fifth n-type transistor and the reference potential node.

[0095] Example 13: The oscillator circuit of example 12, wherein a transistor size ratio of the first n-type transistor, the fourth n-type transistor, and the fifth n-type transistor is m:1:1, where m≧1.

[0096] Example 14: The oscillator circuit of example 13, wherein a transistor size ratio of the first p-type transistor, the second p-type transistor, and the third p-type transistor is n:1:1, where n≧1.

[0097] Aspect 15: The oscillator circuit of aspect 14, wherein a ratio of m / n is equal to a ratio of a gain of the second AGC circuit to a gain of the first AGC circuit.

[0098] Aspect 16: The oscillator circuit of aspect 15, wherein the first AGC circuit comprises a constant transconductance bias generator configured to generate a reference current, and the ratio of m / n is set such that when the amplitude of the oscillator signal is estimated to be greater than or equal to the amplitude of the reference current multiplied by (1-m / n), the comparator is configured to output a logic circuit high signal.

[0099] Aspect 17: The oscillator circuit of any of aspects 4 to 16, wherein the comparator is configured to output a logic high signal when the amplitude of the signal at the output of the second AGC circuit is greater than or equal to the amplitude of the signal at the output of the first AGC circuit.

[0100] Aspect 18: An oscillator circuit as described in any of the preceding aspects, wherein the first AGC circuit comprises a constant transconductance bias generator configured to generate a first reference current that is dependent on the process, voltage, and temperature (PVT) of the first AGC circuit.

[0101] Example 19: The oscillator circuit of example 18, wherein the second AGC circuit is configured to generate a second reference current equal to the first reference current.

[0102] Aspect 20: An oscillator circuit as described in any of the preceding aspects, wherein the input of the second AGC circuit is an open circuit such that the input of the second AGC circuit is configured to have zero current.

[0103] Aspect 21: The oscillator circuit of any of the preceding aspects, further comprising: a backup oscillator configured to generate another oscillation signal, the backup oscillator comprising: another oscillator core circuit coupled to the resonator; and another adjustable current source coupled to the other oscillator core circuit and configured to control an amplitude of the other oscillation signal; and a third AGC circuit having an input coupled to an output of the backup oscillator and having an output coupled to a control input of the other adjustable current source, the logic circuit having a third input coupled to the output of the third AGC circuit.

[0104] Example 22: The oscillator circuit of example 21, further comprising a fourth AGC circuit configured to replicate a topology of the third AGC circuit, the logic circuit having a fourth input coupled to the output of the fourth AGC circuit.

[0105] Aspect 23: A method of oscillation monitoring comprising: generating an oscillation signal using an oscillator that drives a resonator; generating a first signal using a first automatic gain control (AGC) circuit based on the oscillation signal; controlling a bias current of the oscillator based on the first signal; generating a second signal using a second AGC circuit, the second AGC circuit replicating the first AGC circuit; and effectively monitoring the oscillation signal based on the first signal and the second signal.

[0106] Aspect 24: The method of aspect 23, wherein effectively monitoring includes effectively monitoring the oscillating signal without directly sensing an amplitude of the oscillating signal.

[0107] Aspect 25: The method of aspect 23 or 24, wherein the effectively monitoring includes comparing a first signal to a second signal, and outputting a status signal indicating a fault when an amplitude of the second signal is smaller than an amplitude of the first signal.

[0108] Aspect 26: The method of aspect 25, further comprising generating another oscillating signal using a backup oscillator, and switching to using the other oscillating signal instead of the oscillating signal in response to a status signal indicating a fault.

[0109] Example 27: The method of any of examples 23 to 26, wherein a first transistor size ratio between the first n-type transistor of the comparator and the second n-type transistor of the second AGC circuit is m:1, a second transistor size ratio between the first p-type transistor of the comparator and the second p-type transistor of the first AGC circuit is n:1, a second signal from the second AGC circuit controls the first n-type transistor of the comparator and the second n-type transistor of the second AGC circuit, a first signal from the first AGC circuit controls the first p-type transistor of the comparator and the second p-type transistor of the first AGC circuit, and the ratio of m / n is equal to a ratio of a gain of the second AGC circuit to a gain of the first AGC circuit.

[0110] Example 28: The method of any of examples 23 to 27, wherein generating the first signal includes generating a first reference current that is dependent on process, voltage, and temperature (PVT) of the first AGC circuit using a constant transconductance bias generator of the first AGC circuit.

[0111] Example 29: The method of example 28, wherein generating the second signal includes generating a second reference current equal to the first reference current using a second AGC circuit.

[0112] Aspect 30: The method of aspect 28 or 29, wherein the effectively monitoring includes outputting a logic high signal from the comparator when the amplitude of the oscillating signal is estimated to be greater than or equal to the amplitude of the first reference current multiplied by (1-m / n).

[0113] Aspect 31: An apparatus with oscillation monitoring, comprising: a means for generating an oscillation signal; a means for generating a first automatic gain control (AGC) signal based on the oscillation signal; a means for controlling a bias current of the means for generating the oscillation signal based on the first AGC signal; a means for generating a second AGC signal, the means for generating the second AGC signal replicating the means for generating the first AGC signal; and a means for effectively monitoring the oscillation signal based on the first AGC signal and the second AGC signal.

[0114] Additional Considerations The various operations of the methods described above may be performed by any suitable means capable of performing the corresponding functions, which may include various hardware and / or software component(s) including, but not limited to, circuits, application-specific integrated circuits (ASICs), or processors, and / or various hardware and / or software module(s). Generally, when operations are illustrated in figures, they may have corresponding equivalent means-plus-function components that are similarly numbered.

[0115] For example, the means for generating an oscillation signal may include an oscillator (e.g., oscillator 420 or 422 shown in FIG. 4A, or oscillator 701 shown in FIG. 7B) that drives a resonator (e.g., resonator 418 shown in FIG. 4A, resonator 618 shown in FIG. 6, or resonator 707 shown in FIG. 7B). The means for generating a first AGC signal may include a main AGC circuit (e.g., first AGC circuit 702 shown in FIG. 7A and FIG. 7B). The means for controlling the bias current of the means for generating a first signal may include an adjustable current source (e.g., current source 406 or 412 shown in FIG. 4A, current source 610 shown in FIG. 6, transistor 708 shown in FIG. 7B). The means for generating a second AGC signal may include a replica AGC circuit (e.g., second AGC circuit 704 shown in FIG. 7A and FIG. 7B). Effective monitoring means may include logic circuitry such as a processor or a process monitor (e.g., safety monitor 416 shown in FIG. 4A, process monitor 604 and / or oscillator health monitor 602 shown in FIG. 6, or comparator 706 shown in FIGS. 7A and 7B).

[0116] As used herein, the term "determining" encompasses a wide variety of actions. For example, "determining" may include calculating, computing, processing, deriving, investigating, searching (e.g., looking up in a table, database, or another data structure), ascertaining, and the like. "Determining" may also include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), and the like. "Determining" may also include resolving, selecting, choosing, establishing, and the like.

[0117] As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items, including single members. By way of example, "at least one of a, b, or c" is intended to encompass a, b, c, ab, ac, bc, and abc, as well as any combination having multiples of the same element (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or a, b, and c in any other order).

[0118] The various example logic circuit blocks, modules, and circuits described in connection with this disclosure may be implemented or performed using discrete hardware components designed to perform the functions described herein.

[0119] The methods disclosed herein include one or more steps or actions for achieving the described method. The steps and / or actions of those methods may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order of specific steps and / or actions and / or the use of those steps and / or actions may be modified without departing from the scope of the claims.

[0120] It should be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. 1. An oscillator circuit, comprising:

1. An oscillator configured to generate an oscillator signal, comprising: an oscillator core circuit coupled to a resonator and configured to generate the oscillation signal to enable the resonator to resonate; an adjustable current source coupled to the oscillator core circuit and configured to control the amplitude of the oscillation signal; an oscillator comprising: a first automatic gain control (AGC) circuit having an input coupled to an output of the oscillator and having an output coupled to a control input of the adjustable current source; a second AGC circuit configured to replicate the first AGC circuit; a logic circuit having a first input coupled to the output of the first AGC circuit and having a second input coupled to the output of the second AGC circuit; An oscillator circuit comprising:

2. 2. The oscillator circuit of claim 1, wherein the logic circuit is configured to effectively monitor the oscillator signal based on the output of the first AGC circuit and the output of the second AGC circuit.

3. 10. The oscillator circuit of claim 1, wherein the oscillator circuit is configured to effectively monitor the oscillator signal without directly sensing the amplitude of the oscillator signal.

4. 2. The oscillator circuit of claim 1, wherein the logic circuit comprises a comparator having a first input coupled to the output of the first AGC circuit and having a second input coupled to the output of the second AGC circuit.

5. The comparator, a first p-type transistor having a source coupled to the power rail; a first n-type transistor having a source coupled to a reference potential node for the oscillator circuit and having a drain coupled to a drain of the first p-type transistor, at least one of the first p-type transistor or the first n-type transistor being adjustable; an inverter having an input coupled to the drain of the first p-type transistor and the drain of the first n-type transistor, and having an output coupled to an output of the comparator; The oscillator circuit of claim 4 , comprising:

6. The first AGC circuit comprises: a second p-type transistor having a source coupled to the power rail; a second n-type transistor having a source coupled to the reference potential node and a drain coupled to the drain of the second p-type transistor; a third p-type transistor having a source coupled to the power rail and having a gate coupled to a drain of a third p-type transistor, a gate of the second p-type transistor, and a gate of the first p-type transistor; a third n-type transistor having a drain coupled to the drain and to the gate of the third p-type transistor; a first resistive element coupled between the source of the third n-type transistor and the reference potential node; 6. The oscillator circuit of claim 5, comprising:

7. The first AGC circuit comprises: a second resistive element coupled between the gate of the second n-type transistor and the drain of the second n-type transistor; a third resistive element coupled between the drain of the second n-type transistor and the gate of the third n-type transistor; 7. The oscillator circuit of claim 6, further comprising: a first capacitive element coupled between the gate of the third n-type transistor and the reference potential node.

8. 8. The oscillator circuit of claim 7, further comprising a second capacitive element coupled between the gate of the second n-type transistor and the output of the oscillator.

9. 8. The oscillator circuit of claim 7, wherein the second n-type transistor, the third n-type transistor, the first resistive element, the second resistive element, and the third resistive element form at least a portion of a constant transconductance bias generator configured to generate a process, voltage, and temperature (PVT) dependent reference current.

10. 7. The oscillator circuit of claim 6, wherein a transistor size ratio of the first p-type transistor, the second p-type transistor, and the third p-type transistor is n:1:1, where n>=1.

11. the adjustable current source comprises a fourth p-type transistor having a source coupled to the power supply rail, a drain coupled to the oscillator core circuit, and a gate coupled to the gate of the second p-type transistor and to the third p-type transistor; a transistor size ratio of the fourth p-type transistor, the second p-type transistor, and the third p-type transistor is x:1:1, where x≧1; 7. The oscillator circuit according to claim 6.

12. The second AGC circuit comprises: a fourth p-type transistor having a source coupled to the power rail; a fourth n-type transistor having a source coupled to the reference potential node and having a drain coupled to the drain of the fourth p-type transistor, the gate of a fourth n-type transistor, and the gate of the first n-type transistor; a fifth p-type transistor having a source coupled to the power rail and a drain coupled to a gate of the fifth p-type transistor and to a gate of the fourth p-type transistor; a fifth n-type transistor having a drain coupled to the drain and to the gate of the fifth p-type transistor; a second resistive element coupled between the source of the fifth n-type transistor and the reference potential node; 7. The oscillator circuit of claim 6, comprising:

13. 13. The oscillator circuit of claim 12, wherein a transistor size ratio of the first n-type transistor, the fourth n-type transistor, and the fifth n-type transistor is m:1:1, where m>1.

14. 14. The oscillator circuit of claim 13, wherein a transistor size ratio of the first p-type transistor, the second p-type transistor, and the third p-type transistor is n:1:1, where n>1.

15. 15. The oscillator circuit of claim 14, wherein the ratio of m / n is equal to the ratio of the gain of the second AGC circuit to the gain of the first AGC circuit.

16. the first AGC circuit comprises a constant transconductance bias generator configured to generate a reference current; the m / n ratio is set such that when the amplitude of the oscillating signal is estimated to be greater than or equal to the amplitude of the reference current multiplied by (1-m / n), the comparator is configured to output a logic high signal.

16. The oscillator circuit of claim 15.

17. 5. The oscillator circuit of claim 4, wherein the comparator is configured to output a logic high signal when the amplitude of the signal at the output of the second AGC circuit is greater than or equal to the amplitude of the signal at the output of the first AGC circuit.

18. 2. The oscillator circuit of claim 1, wherein the first AGC circuit comprises a constant transconductance bias generator configured to generate a first reference current that is process, voltage, and temperature (PVT) dependent of the first AGC circuit.

19. 20. The oscillator circuit of claim 18, wherein the second AGC circuit is configured to generate a second reference current equal to the first reference current.

20. 2. The oscillator circuit of claim 1, wherein the input of the second AGC circuit is an open circuit such that the input of the second AGC circuit is configured to have zero current.

21. a backup oscillator configured to generate another oscillation signal, another oscillator core circuit coupled to the resonator; another adjustable current source coupled to the another oscillator core circuit and configured to control the amplitude of the another oscillating signal; a backup oscillator comprising: a third AGC circuit having an input coupled to an output of the backup oscillator and having an output coupled to a control input of the other adjustable current source, the logic circuit having a third input coupled to the output of the third AGC circuit; The oscillator circuit of claim 1 further comprising:

22. 22. The oscillator circuit of claim 21, further comprising a fourth AGC circuit configured to replicate a topology of the third AGC circuit, the logic circuit having a fourth input coupled to an output of the fourth AGC circuit.

23. 1. A method for monitoring oscillations, comprising: generating an oscillation signal using an oscillator driving a resonator; generating a first signal using a first automatic gain control (AGC) circuit based on the oscillation signal; controlling a bias current of the oscillator based on the first signal; generating a second signal using a second AGC circuit, the second AGC circuit replicating the first AGC circuit; effectively monitoring the oscillating signal based on the first signal and the second signal; A method comprising:

24. 24. The method of claim 23, wherein the step of effectively monitoring comprises the step of effectively monitoring the oscillating signal without directly sensing an amplitude of the oscillating signal.

25. said effectively monitoring step comprising: comparing the first signal and the second signal; and outputting a status signal indicating a fault when the amplitude of the second signal is less than the amplitude of the first signal.

26. generating a second oscillator signal using a backup oscillator; switching to using the alternative oscillating signal instead of the oscillating signal in response to the status signal indicating the fault; 26. The method of claim 25, further comprising:

27. a first transistor size ratio between the first n-type transistor of the comparator and the second n-type transistor of the second AGC circuit is m:1; a second transistor size ratio between the first p-type transistor of the comparator and the second p-type transistor of the first AGC circuit is n:1; the second signal from the second AGC circuit controls the first n-type transistor of the comparator and the second n-type transistor of the second AGC circuit; the first signal from the first AGC circuit controls the first p-type transistor of the comparator and the second p-type transistor of the first AGC circuit; the ratio of m / n is equal to the ratio of the gain of the second AGC circuit to the gain of the first AGC circuit; 24. The method of claim 23.

28. 28. The method of claim 27, wherein generating the first signal comprises generating a process, voltage, and temperature (PVT) dependent first reference current of the first AGC circuit with a constant transconductance bias generator of the first AGC circuit.

29. 30. The method of claim 28, wherein generating the second signal comprises generating, with the second AGC circuit, a second reference current equal to the first reference current.

30. 29. The method of claim 28, wherein the step of effectively monitoring includes the step of outputting a logic high signal from a comparator when the amplitude of the oscillating signal is estimated to be greater than or equal to the amplitude of the first reference current multiplied by (1-m / n).

31. An apparatus with oscillation monitoring, means for generating an oscillating signal; means for generating a first automatic gain control (AGC) signal based on the oscillation signal; a means for controlling a bias current of the means for generating the oscillation signal based on the first AGC signal; a means for generating a second AGC signal, the means replicating the means for generating the first AGC signal; means for effectively monitoring the oscillating signal based on the first AGC signal and the second AGC signal; An apparatus comprising:

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