Semiconductor package having integrated capacitors - Patents.com

Abstract

In one aspect, a capacitor or network of capacitors for a vertical feed in a package is provided, where the capacitor is embedded in or forms entirely within a package substrate core. In a second aspect, a plurality of thin film capacitor structures are provided for implementing a vertical feed in a package. In a third aspect, a method for manufacturing a hermetically sealed thin film capacitor is provided.

Description

[Technical field]

[0001] The present invention relates to semiconductor packages, particularly flip chip packages having integrated capacitors, as well as thin film capacitor structures and encapsulation of thin film capacitors. [Background technology]

[0002] Semiconductor packages, such as flip chip packages, are known in the art to interconnect surface mountable devices (e.g., semiconductor devices, IC chips, integrated passive devices, microelectromechanical systems (MEMS) or other electrical, optical, mechanical, thermal, magnetic, quantum, etc. devices) to an external circuit (e.g., a printed circuit board (PCB)) via interconnects. A first level of interconnects is located between the surface mountable device and the package, and a second level of interconnects is located between the package and the substrate. Interconnects may also be disposed between the package and capacitors for power delivery, noise filtering, etc.

[0003] To mount a conventional flip chip to an external circuit such as a circuit board, the chip is singulated or cut into individual chips and then flipped over so that the top side faces down. The chip pads are aligned with matching pads on the external circuit and the solder bumps are then reflowed to make the connections between the singulated chip and the external circuit.

[0004] The package may include a redistribution layer (RDL) that forms the interface between the surface mountable device and the package. The RDL is an additional metal layer consisting of traces on top of the core metal that can be used, for example, to make the I / O pads of the semiconductor die available for bonding elsewhere, such as to bump pads. The bumps are typically arranged in a grid pattern, each molded with two pads (one on the top and one on the bottom), and then attached to the RDL and the package substrate, respectively. The RDL thus acts as a layer that connects the I / O pads to the bump pads.

[0005] In flip-chip design, a 2D architecture is defined as an architecture in which two or more active silicon devices are placed side-by-side on a package and interconnected on the package. For example, a 2.5D package contains multiple dies in the same package and communication between the chips is achieved using either silicon or organic interposers, while a 2.1D package contains multiple dies in the same package and has several dense wiring layers to interconnect the chips, and coarser wiring layers to fan out to external circuits. A typical 2.1D package can replace 2.5D interposers and traditional organic substrate packages.

[0006] It is known to use decoupling capacitors in flip chips to suppress power supply noise in DC signals transmitted from external circuitry to the semiconductor die. Such decoupling capacitors typically include terminals on the left and right sides to laterally feed power while simultaneously filtering AC noise from being transmitted to the die, which requires either lateral signal routing through the capacitor or placement of the capacitor on the surface of the package, both of which contribute to RC signal delays and negatively impact device density. Summary of the Invention

[0007] It is an aspect of the present invention to provide a capacitor for a vertical feed within a package, where the capacitor is embedded within, or forms entirely within, the package substrate core.

[0008] In another aspect, a plurality of thin film capacitor structures are provided for vertical power distribution within a package.

[0009] In a further aspect, a method for manufacturing an encapsulated thin film capacitor is provided.

[0010] According to one embodiment, in a package having at least one surface mountable device, a substrate core having a semiconductor die attached to one side via a first level of interconnects, and a second level of interconnects on an opposite side of the substrate core for connection to an external circuit, the improvement includes at least one capacitor forming at least a portion of the substrate core, and at least one redistribution layer adjacent to the capacitor and at least one of the first level of interconnects and the second level of interconnects, the at least one redistribution layer having wiring for either interconnecting the multiple surface mountable devices, fanning out external connections from the multiple surface mountable devices, or powering the multiple surface mountable devices from an external circuit, the at least one redistribution layer including at least one vertical connection on at least one side of the capacitor for connecting the capacitor to the external circuit, the at least one surface mountable device for filtering AC noise, and at least one further vertical connection through the at least one capacitor.

[0011] According to another embodiment, a method for manufacturing a plurality of encapsulated thin film capacitors is provided, comprising: coating a thin film sheet on both sides with an encapsulant to prevent moisture / gas / chemicals from entering the functional layers of the capacitor, the thin film sheet including an insulator, a conductive core within the insulator, and a current collector separated from the conductive core by a dielectric; producing at least one first terminal forming either a cathode or an anode connected to the conductive core through the insulator, and at least one second terminal forming the other of the cathode or an anode connected to the current collector; singulating the thin film sheet into a plurality of individual thin film capacitors, each sealed on both sides but not on an adjacent side; and coating the adjacent non-sealed side with additional encapsulant.

[0012] According to another embodiment, there is provided a method of making a package having at least one semiconductor die, a substrate core to which the semiconductor die is attached via a first level of interconnects on one side, and a second level of interconnects on an opposite side of the substrate core for connection to an external circuit, the method comprising: making a thin film capacitor having an insulator, a conductive core within the insulator, at least one first terminal forming either a cathode or an anode connected to the conductive core through the insulator, a current collector separated from the conductive core by a dielectric, and at least one second terminal forming the other of the cathode or the anode connected to the current collector; singulating the thin film sheet into a plurality of individual thin film capacitors; coating all sides of the singulated thin film capacitors with an encapsulant; and embedding the thin film capacitors in the substrate core.

[0013] According to another embodiment, there is provided a method of making a package having at least one semiconductor die, a substrate core to which the semiconductor die is attached via a first level of interconnects on one side, and a second level of interconnects on an opposite side of the substrate core for connection to an external circuit, the method comprising: making a thin film stack including a conductive core and a current collector separated from the conductive core by a dielectric; coating the top and bottom of the thin film stack with an encapsulant; making an insulator around the thin film stack; and drilling one or more vertical connections, including at least two vertical connections, in the thin film stack to make at least one first terminal forming either a cathode or an anode connected to the conductive core through the insulator, and at least one second terminal forming the other of the cathode or an anode connected to the current collector through the insulator.

[0014] According to another embodiment, there is provided a method of making a package having at least one semiconductor die, a substrate core to which the semiconductor die is attached via a first level of interconnects on one side, and a second level of interconnects on an opposite side of the substrate core for connection to an external circuit, the method including making a thin film stack including a conductive core and a current collector separated from the conductive core by a dielectric, drilling one or more vertical connections through the thin film stack, coating all sides of the thin film stack with an encapsulant, surrounding the encapsulated thin film stack with an insulator, making at least one first terminal forming either a cathode or an anode connected to the conductive core using one of the vertical connections through the insulator and the encapsulant, and making at least one second terminal forming the other of the cathode or anode connected to the current collector using a further one of the vertical connections through the insulator and the encapsulant.

[0015] According to another embodiment, there is provided a method of making a package having at least one semiconductor die, a substrate core to which the semiconductor die is attached via a first level of interconnects on one side, and a second level of interconnects on an opposite side of the substrate core for connection to an external circuit, the method including: making a thin film stack including an insulator, a conductive core within the insulator, and a current collector separated from the conductive core by a dielectric; drilling one or more vertical connections through the thin film stack; making at least one first terminal forming either a cathode or an anode connected to the conductive core using one of the vertical connections through the insulator and encapsulant, and making at least one second terminal forming the other of either a cathode or an anode connected to the current collector using a further one of the vertical connections through the insulator and encapsulant; and making a seal ring surrounding the thin film stack as a barrier against one or more of moisture, gases, and chemicals entering the dielectric and current collector.

[0016] These, together with other aspects and advantages which will become apparent hereinafter, reside in the details of construction and operation which are more fully described and claimed hereinafter with reference to the accompanying drawings which form a part hereof, in which like numerals refer to like parts throughout and in which: [Brief description of the drawings]

[0017] [Figure 1A] 1A-1D show cross-sectional views of different embodiments of a capacitor for vertical power supply within a package, where the capacitor is embedded within or forms entirely within the package substrate core, in accordance with aspects of the present invention. [Figure 1B] 1A-1D show cross-sectional views of different embodiments of a capacitor for vertical power supply within a package, where the capacitor is embedded within or forms entirely within the package substrate core, in accordance with aspects of the present invention. [Figure 1C]1A-1D show cross-sectional views of different embodiments of a capacitor for vertical power feed in a package, where the capacitor is embedded in or forms entirely within the package substrate core, in accordance with aspects of the present invention. [Figure 1D] 1A-1D show cross-sectional views of different embodiments of a capacitor for vertical power feed in a package, where the capacitor is embedded in or forms entirely within the package substrate core, in accordance with aspects of the present invention. [Figure 1E] 1A, 1C, and 1D, but with different capacitor sizes, shapes, and thicknesses, according to an embodiment of the invention. [Figure 1F] 1A, 1C, and 1D, but with different capacitor sizes, shapes, and thicknesses, according to an embodiment of the invention. [Figure 1G] 1A, 1C, and 1D, but with different capacitor sizes, shapes, and thicknesses, according to an embodiment of the invention. [Figure 1H] 2 illustrates a cross-sectional view of a network of capacitors formed by terminal metallization or redistribution layers of a semiconductor package, according to an embodiment of the present invention. [Figure 2A] 2 is a plan view of a sheet of thin-film capacitors having terminal metal that can be used as alignment datums for embedding the capacitors in a package substrate core, according to one aspect of the present invention. [Figure 2B] 1 is an exploded plan view of a sheet of thin-film capacitors having terminal metal that can be used as alignment datums for embedding the capacitors in a package substrate core, according to one aspect of the present invention. [Figure 2C] 1 is a cross-sectional view of a sheet of thin-film capacitors having terminal metal that can be used as alignment datums for embedding the capacitors in a package substrate core, according to one aspect of the present invention. [Figure 2D] 1 is a cross-sectional view illustrating terminal metal that can be used as an alignment fiducial for embedding a network of capacitors within a package substrate core in accordance with one aspect of the present invention. [Diagram 3]1A-1D show cross-sectional views of different embodiments of a thin film capacitor according to aspects of the present invention. [Figure 3A] 2A-2C show two cross-sectional views of two types of first terminals and a plan view of a second terminal according to a first embodiment of a thin-film capacitor; [Figure 3B] 4A-4C show two cross-sectional views of two types of first terminals and a plan view of a second terminal according to a second embodiment of a thin-film capacitor; [Figure 3C] 13 shows two cross-sectional views of two types of first terminals and a plan view of a third terminal according to a third embodiment of a thin-film capacitor. [Figure 3D] 13 shows two cross-sectional views of two types of first terminals and a plan view of a fourth terminal according to a fourth embodiment of a thin-film capacitor. [Figure 4A] 1 shows a cross-sectional view of an encapsulated thin film capacitor before singulation and after drilling vertical connections and metal plating to complete the capacitor, according to an embodiment of the present invention. [Figure 4B] 4B is a flow chart of a method for manufacturing the multiple encapsulated thin film capacitors of FIG. 4A. [Diagram 5] 2 illustrates a cross-sectional view of a thin film capacitor embedded and encapsulated within a flip chip substrate core in accordance with an aspect of the present invention. [Figure 6] 1 illustrates a cross-sectional view of a thin film capacitor encapsulated after singulation and prior to embedding within a flip-chip substrate core, in accordance with an aspect of the present invention. [Figure 7A] 2 illustrates a cross-sectional view of a thin film capacitor embedded within a flip chip substrate core and then encapsulated by gap filling, according to an aspect of the present invention. [Figure 7B] 7B is a flow chart of a method for manufacturing the multiple encapsulated thin film capacitors of FIG. 7A. [Figure 8A] 1 shows a cross-sectional view of one embodiment of a thin film stack that has been encapsulated prior to drilling vertical connections and metal plating to complete a capacitor in accordance with aspects of the present invention. [Figure 8B] 8B is a flow chart of a method for manufacturing the multiple encapsulated thin film capacitors of FIG. 8A. [Figure 9A]1 illustrates a cross-sectional view of one embodiment of a thin film stack that has been encapsulated after drilling vertical connections and prior to dielectric and metal formation, in accordance with aspects of the present invention. [Figure 9B] 9B is a flow chart of a method for manufacturing the multiple encapsulated thin film capacitors of FIG. 9A. [Figure 10] 1 illustrates a cross-sectional view of one embodiment of a thin film stack sealed using a seal ring surrounding a capacitor(s). [Figure 11] 1 illustrates a cross-sectional view of one embodiment of a semiconductor package having a single or combination of capacitors under the shadow of a single or combination of surface mountable devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] As mentioned above, this specification describes several general aspects, including a first aspect in which a capacitor or a network of capacitors is provided for vertical power supply within a package, where the capacitor(s) is embedded within or forms the entirety of a package substrate core; a second aspect in which a plurality of thin film capacitor structures are provided to implement vertical power supply within a package; and a third aspect in which a method for manufacturing an encapsulated thin film capacitor is provided.

[0019] With respect to a first general aspect, Figures 1A, 1B, 1C, and 1D show cross-sectional views of different embodiments of a capacitor for vertical power distribution in a package, such as a flip-chip package 100, in which the capacitor is embedded or forms entirely within a package substrate core, in accordance with an aspect of the invention. As described below, the capacitor may be formed as a single component, or as multiple components that are then embedded in the flip-chip substrate, or packaged / molded as one component before being embedded in the flip-chip substrate. As described below, multiple capacitors may also be interconnected using capacitor terminal metal or package redistribution layers (RDLs) to form a capacitor network.

[0020] The flip chip package 100 has at least one surface mountable device 110 and a substrate core 120 (e.g., plastic and / or fiberglass) to which the surface mountable device 110 is attached via first level interconnects (FLI) 130, such as solder bumps, on one side, and second level interconnects (SLI) 140, such as a plurality of solder balls, on the other side of the substrate core 120 for connection to an external circuit 150, such as a printed circuit board (PCB). Those skilled in the art will appreciate that the FLI and SLI are not limited to solder balls / bumps, but can include LGA, BGA, etc. In some applications, as discussed above, the semiconductor die 110 can be replaced with other semiconductor devices, integrated passive devices, microelectromechanical systems (MEMS), or other components for connection to the external circuit 150.

[0021] At least one capacitor (Cap 1 , Cap 2 , , , Cap n-1 , Cap n, and Cap in FIG. 1B) form at least a portion of the substrate core 120. At least one redistribution layer RDL 160 is disposed adjacent to the capacitor and at least one of the FLI 130 and SLI 140. Wiring 170 / 172 is provided in the RDL 160 for signal routing between the external circuit 150 and at least one die 110 and the capacitor(s) through vertical connections such as vias 175 having top and bottom terminal metals 178 on the top and bottom sides of the capacitor(s). At least one further via 180 is provided for passing DC power vertically from the external circuit 150 through the capacitor(s) to the surface mountable device 110. In an embodiment, one or more of the vertical connections 175 and 180 can be plated-through holes (PTHs). Fine pitch wiring 190 can also be provided in the RDL 160 for signal transmission between the semiconductor dies 110.

[0022] In Figure 1A, the capacitor Cap 1 , Cap 2 , , , Cap n-1 , Cap n 2B, a single capacitor Cap forms the entire core 120. In FIG. 1C, the capacitor Cap 1 , Cap 2 , , , Cap n-1 , Cap n are integrated into a capacitor module 182 and then embedded in a cavity in the substrate core 120, whereas in FIG. 1D, multiple capacitors Cap 1 , Cap 2 , , , Cap n-1 , Cap n forms a portion 183 of the core 120 .

[0023] Capacitor 1 , Cap 2 , , , Cap n-1 , Cap ncan be of any (regular or irregular) shape, size, or thickness that follows the contours of the die 110, as shown in Figures 1E, 1F, and 1G, and is designed to support powering the die 110. The capacitor(s) can be MLCC (multilayer ceramic cap), thin film based (Al, Ta, etc.), polymer cap, etc., and can be a combination of different types of capacitors with different voltages (1.2V, 5V, 100V depending on the capacitor), frequencies, and densities.

[0024] By forming at least a portion of the substrate core 120 with a capacitor(s), at least some of the multiple vertical connections in the RDL 160 can connect the capacitor(s) to the external circuitry 150 and at least one surface mountable device 110 for filtering AC noise from DC power. Furthermore, by embedding or forming the substrate core 120 with the capacitor(s) and providing vertical delivery of DC power through the capacitor(s), the prior art problems of RC signal delay and insufficient device density resulting from using decoupling capacitors with left and right terminals for lateral power delivery and signal routing through the capacitor, or placement of the capacitor on the surface of the package are avoided.

[0025] 1A, 1B, 1C, and 1D configurations, the terminal metals can be very close to each other (e.g., solder bumps on 130 on the bottom of die 110 as small as 80 micron pitch can be made to align with solder balls 140 on 80 micron pitch without DC routing through RDL 160), and the resulting area dependent cathode and anode provide improved ESR / ESL and current carrying capabilities due to an increased number of current carrying vertical connections through and between the capacitors.

[0026] The package 100 includes an RDL 160 between the substrate core 120 and the FLI 130 to interconnect the multiple semiconductor dies 110, and a capacitor Cap 1 , Cap 2 , , , Cap n-1 , Cap n In one embodiment, the RDL 160 between the substrate core 120 and the SLI 140 includes fine pitch wiring 170 for at least one of forming a network of interconnects 172 for connecting the SLI 140 to the external circuitry 150. In another embodiment, the RDL 160 between the substrate core 120 and the SLI 140 includes coarser density wiring 172 for fanning out signals to the external circuitry 150.

[0027] In FIG. 1H, RDL 160 (or terminal metal 178) is a capacitor (Cap 1 , Cap 2 , Cap 3 ) network.

[0028] To embed the capacitors in the substrate 120, the capacitors must be picked and placed, which requires alignment fiducials. This uses up the area of ​​the capacitors and results in loss of capacitance. Thus, according to the embodiment of Figures 2A, 2B, 2C, and 2D, a sheet of thin film capacitors is fabricated with terminal metal 178 that can be used as alignment fiducials 195 for embedding the capacitors in the package substrate core 120 of the flip chip package shown in Figures 1A, 1C, and 1D, and the vertical connections 178 from the RDL 160 can be dropped onto the terminal metal / alignment fiducials 195. The fiducials 195 can be any shape, such as a square, a rectangle, a "plus" sign, a circle, etc.

[0029] With regard to a second general aspect, FIG. 3 shows cross-sectional views of different embodiments of a thin film capacitor having an insulator 305, a conductive core 310 within the insulator, at least one first terminal (terminal 1) forming either a cathode or an anode connected to the conductive core 310 through the insulator 305, a current collector 320 separated from the conductive core by a dielectric 330, and at least one second terminal (terminal 2) connected to the current collector forming the other of the cathode or anode.

[0030] Terminal 1 can be connected to either the top or bottom surface of conductive core 310 using at least one blind via 340, or to a side of conductive core 310 using at least one plated through hole that makes metallic contact with core 310.

[0031] The terminal 2 may include at least one plated through hole 350 for passing DC current through the conductive core 310 and via(s) 360 for connection to the current collector 320 .

[0032] In embodiments, the thin film capacitor of Figure 3 can be sealed with metal rings in various patterns on the top and bottom of the capacitor periphery for use as moisture / oxidation barriers, crack stops, ion collectors, etc. The metal rings can also be used as terminal metal for passing DC power or as alignment marks for pick and place, as described above with reference to Figures 2A, 2B, and 2C.

[0033] 3A shows two cross-sectional views of two kinds of terminal 1 (types A and B) and a plan view of terminal 2 according to a first type (type A) of a thin-film capacitor. In the embodiment of FIG. 3A, multiple ganged vias 340 and 360 (i.e., isolation holes) are used to connect terminal 1 and terminal 2 to conductive core 310 and current collector 320, respectively, and multiple plated through holes 300 and 350 are used for vertical DC feed and to connect terminal 1 to conductive core 310.

[0034] Figure 3B shows two cross-sectional views of two kinds of terminals 1 (types A and B) and a plan view of terminal 2 according to a second type (type B) of thin film capacitor. In the embodiment of Figure 3B, a plated through hole 350 for vertical DC feed and a number of vias 300 / 340 are grouped together in a slot 370 of an insulator 305, respectively. Since there is no need to drill the vias individually, the embodiment of Figure 3B allows for a more densely packed flip chip package than the embodiment of Figure 3A.

[0035] Figure 3C shows two cross-sectional views of two kinds of terminals 1 (types A and B) and a plan view of terminal 2 according to a third type (type C) of thin-film capacitor. In the embodiment of Figure 3C, the plated through hole 350 and the vias 300 / 340 of Figure 3B are replaced by rectangular trenches 373 and 372, respectively, filled with conductor 350A. The embodiment of Figure 3C provides a lower resistance and therefore a higher current carrying capacity than the embodiments of Figures 3A and 3B.

[0036] Figure 3D shows two cross-sectional views of two kinds of terminals 1 (types A and B) and a plan view of terminal 2 according to a fourth type (type D) of thin-film capacitor. In the embodiment of Figure 3D, the rectangular trench 373 of Figure 3C is replaced by a pair of non-rectangular trenches 373B filled with semicircular conductors 350 and vias 350, respectively, and the vias 300 / 340 of Figures 3A and 3B are replaced by a single via 300 / 340 in trench 373C that serves as the capacitor anode. In Figure 3D, the non-rectangular trench 373B is semicircular, but other shapes may be used.

[0037] The following table summarizes combinations of thin film capacitor structures that can be used with the configurations of FIGS. 3A-3D. [Table 1]

[0038] Thus, terminal 1 can be one of two types: Type A, where PTH 300 is connected to the side of core 310, or Type B, where blind via 340 is dropped to contact core 310. Terminal 2 can be one of four types: Type A (FIG. 3A), where multiple blind vias 350 and PTH 350 are connected to form a terminal; Type B (FIG. 3B), where a rectangular slot 370 is provided in core 310 to group multiple PTHs together; Type C (FIG. 3C), where the rectangular slot forms a single large trench 372 / 373 filled with conductors 350A and 300A / 340A; and Type D (FIG. 3D), where the trench is non-rectangular, improving performance (e.g., lowering series inductance) while allowing flexibility in capacitor shape.

[0039] With respect to the third general aspect, Figures 4-9 show cross-sectional views of different embodiments of thin film capacitors that have been encapsulated after via / PTH trenches have been drilled and terminal metal plating has been applied to complete the capacitor, Figures 8 and 9 show cross-sectional views of different embodiments of thin film stacks that have been hermetically sealed before via / PTH trenches have been drilled and metal plating has been applied to complete the capacitor, and Figure 10 shows a seal ring around a capacitor(s) according to aspects of the invention. Because capacitor embodiments described herein may be moisture sensitive, the encapsulant acts as a barrier to prevent moisture / gases / chemicals etc. from penetrating the functional layers of the capacitor.

[0040] Referring to FIG. 4A, a thin film capacitor is shown in which an encapsulant 400 is applied prior to singulating a thin film sheet 410 into multiple capacitors. After vertical connections (e.g., via holes / PTHs) are drilled, terminal contacts are made, etc., the sheet 410 is coated with an airtight or nearly airtight material 400 and then cut (singulated) into sections (e.g., single capacitors or a network / string of capacitors) that can be embedded into a substrate core of a package. While the top and bottom are encapsulated, the sidewalls are exposed and require additional encapsulant 405 to be added during or after embedding the capacitor into the substrate core, as described below with reference to FIG. 5A and FIG. 5B.

[0041] Referring to FIG. 4B, steps of a method 420 for making a number of hermetically sealed thin film capacitors are shown. At 430, both sides (i.e., flat top and bottom surfaces) of a thin film sheet 410 are coated with a hermetic sealant, the thin film sheet including the structure shown in FIG. 3, FIG. 3A, FIG. 3B, FIG. 3C and FIG. 3D, i.e., an insulator 305, a conductive core 310 within the insulator, and a current collector 320 separated from the conductive core by a dielectric 330. The top and bottom surfaces can be coated using any of a number of known techniques, such as dipping, spinning, etc. At step 440, at least one first terminal forming either a cathode or an anode connected to the conductive core 310 through the insulator 305, and at least one second terminal forming the other of the cathode or an anode connected to the current collector 320 are made. In some embodiments, the anode and cathode terminals can be made by sputtering metal through a mask on top of the hermetic sealant 400. At 450, the thin film sheet 410 is singulated into a plurality of individual thin film capacitors that are hermetically sealed on both planar sides (i.e., top and bottom) but unsealed on adjacent sides (i.e., exposed left and right sides where singulation occurs). The unsealed adjacent sides are then coated with additional hermetic sealing material 405 at 460.

[0042] In the embodiment of FIG. 5, an additional hermetic sealant 405 is applied during embedding of the capacitors into the substrate core 120, for example by gap filling the sides of the thin film sheet and then singulating the sheet.

[0043] Alternatively, as shown in the embodiment of FIG. 6, a thin film sheet 410 can be singulated and sealed on all sides with a hermetic sealant 400, and then the individual encapsulated capacitors (or networks of capacitors) can be embedded within a substrate core.

[0044] In the embodiment of Figure 7A, the singulated and sealed thin film sheet of Figure 6 is gap sealed after embedding, for example using method 700 of Figure 7B, which creates at step 730 at least one thin film capacitor having an insulator 305, a conductive core 310 within the insulator, and a current collector 320 separated from the conductive core by a dielectric 330, as well as vias / PTHs and anode / cathode terminal contacts. At 740, the at least one thin film capacitor is embedded within the substrate core 120. Then, at 750, all sides of the embedded thin film capacitor are coated using a hermetic sealant 405 gap fill.

[0045] Referring to FIG. 8A, an embodiment is shown in which a thin film stack 800 including a conductive core, current collectors and dielectrics is encapsulated in an insulator 820 and coated with a hermetic sealant 810 before drilling trenches / vias / PTHs to create terminals and DC pass-throughs, sealing most of the capacitor area but not the side of the thin film stack 800. FIG. 8B shows steps for creating the structure of FIG. 8A. In step 830, a thin film stack 800 is created including an insulator, a conductive core within the insulator, and a current collector separated from the conductive core by a dielectric. In 840, the top and bottom surfaces of the thin film stack are coated with a hermetic sealant. Then, in 850, a first terminal is created (e.g., using via / PTH drilling followed by metallization) forming either a cathode or an anode connected to the conductive core through the hermetic sealant and insulator, and a second terminal is created forming either a cathode or an anode connected to the current collector through the insulator and hermetic sealant.

[0046] As an alternative to the embodiment of FIG. 8A, the hermetic sealant can be applied after trench formation and drilling, but before embedding the thin film stack in an insulator and metallizing to form the anode and cathode terminals, resulting in the structure of FIG. 9A in which all sides of the thin film stack 900 are coated with sealant. FIG. 9B shows steps for making the structure of FIG. 9A. In step 930, a thin film stack 900 is made, including an insulator, a conductive core within the insulator, and a current collector separated from the conductive core by a dielectric. In 940, via / PTH drilling and trench formation is performed. In 950, all sides of the thin film stack are coated with hermetic sealant. Then, in 960, the thin film stack is surrounded by an insulator, and anode / cathode contact terminals and DC pass-throughs are made through the via / PTH holes drilled in step 940.

[0047] As a further alternative to the embodiments of Figures 8A and 9A, as shown in Figure 10, a seal ring 1000 / 1050 that acts as a barrier to moisture, gases, chemicals, etc. entering the dielectric and current collector can surround the capacitor, and the height of the barrier can extend to the top and bottom / terminal metal as shown at 1000, or can be the same as the functional layer thickness of the thin film stack as shown at 1050. Also, a recess can be provided around the seal ring 1000 / 1050 as shown at 1060.

[0048] 11 shows a cross-sectional view of one embodiment of a semiconductor package 1100 having area dependent cathodes and anodes for better ESR / ESL and current carrying capability. In FIG. 11, a capacitor Cap 1、2 , Cap 3 and Cap n are completely custom drawn within the package core to meet individual capacitance and current handling capabilities. Furthermore, the surface mountable device outline of each device (e.g., surface mountable device 3) or a combination of adjacent devices (e.g., surface mountable devices 1 and 2, and surface mountable device n) represents the "shadow" beneath which the capacitor is fabricated. Thus, in FIG. 11, Cap 1、2 is placed in the shadow of the surface mountable devices 1 and 2, and the Cap 2 The device is placed in the shadow of the surface mountable device 3 and two caps are attached. nA capacitor is placed in the shadow of surface mountable device n. The connection between the capacitor and the surface mountable device is made through the package RDL as described above. The capacitors may also vary in size and thickness. As can be seen, a single capacitor can service a single surface mountable device under its shadow, or multiple surface mountable devices under their combined shadows, and multiple capacitors can service a single surface mountable device under its shadow. In summary, each capacitor can follow the physical layout or profile of each domain / functional block of a single surface mountable device.

[0049] The present invention has been described with respect to various alternatives and embodiments.

[0050] The many features and advantages of the present invention are apparent from the detailed specification, and it is, therefore, intended by the appended claims to cover all such features and advantages of the present invention that fall within the true spirit and scope of the invention. Moreover, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and operation illustrated and described, and therefore, all suitable modifications and equivalents may be deemed to be within the scope of the present invention.

Claims

1. 1. An improvement in a package having at least one surface mountable device, a substrate core to which the semiconductor die is attached via a first level of interconnects on one side, and a second level of interconnects on an opposite side of the substrate core for connection to an external circuit, comprising: at least one capacitor forming at least a portion of said substrate core; at least one redistribution layer adjacent the capacitor and at least one of the first level interconnect and the second level interconnect; Including, the at least one redistribution layer having wiring for either interconnecting a plurality of surface mountable devices, fanning out external connections from the plurality of surface mountable devices, or powering the plurality of surface mountable devices from the external circuitry, the at least one redistribution layer comprising: at least one vertical connection on at least one side of the capacitor for connecting the capacitor to the external circuitry; and at least one surface mountable device for filtering AC noise. at least one further vertical connection through said at least one capacitor; Including, Improvement.

2. The improvement of claim 1 wherein said at least one capacitor forms an entirety of said substrate core.

3. The improvement of claim 1 wherein the at least one capacitor is embedded within the substrate core.

4. 4. The improvement of claim 3, wherein said package includes fine pitch wiring between different surface mountable devices on said package and coarser density wiring for connecting said surface mountable devices to said external circuitry.

5. The improvement of claim 1 wherein the at least one additional vertical connection is a plated through hole.

6. The improvement of claim 1 wherein said at least one capacitor comprises a single component embedded within said substrate core.

7. The improvement of claim 1 wherein said at least one capacitor comprises a plurality of components embedded within said substrate core.

8. The improvement of claim 7 wherein said multiple components are packaged as a single component embedded within said substrate core.

9. The improvement of claim 7 wherein terminal metal within said capacitor is configured as an alignment datum onto which at least one vertical connection can be dropped from at least one of said one side and said opposite side.

10. The at least one capacitor is An insulator; a conductive core within the insulator; at least one first terminal forming either a cathode or an anode connected to the conductive core through the insulator; a current collector separated from the conductive core by a dielectric; at least one second terminal forming the other of the cathode or anode connected to the current collector; 10. The improvement of claim 1 which is a thin film capacitor comprising:

11. The thin-film capacitor of claim 10 , wherein the first terminal is connected to either the top or bottom surface of the conductive core using multiple blind vias.

12. The thin-film capacitor of claim 10 , wherein the first terminal is connected to a side of the conductive core using at least one plated through hole.

13. The thin-film capacitor of claim 10 , wherein the second terminal has at least one plated through hole for passing DC current through the conductive core.

14. 11. The thin-film capacitor of claim 10, wherein the second terminal is connected to the current collector using a plurality of ganged vias and a plurality of plated-through holes for passing DC current through the conductive core.

15. The thin-film capacitor of claim 14 , wherein the plurality of paired vias and the plurality of plated-through holes are each paired within a respective slot in the insulator.

16. 14. The thin-film capacitor of claim 13, wherein the second terminal is connected to the current collector through a first trench filled with a conductor, and the at least one plated through hole for passing DC current includes a second trench filled with a conductor.

17. The thin-film capacitor of claim 15 , wherein the slot is rectangular.

18. The thin-film capacitor of claim 16 , wherein the first trench and the second trench are rectangular.

19. The thin-film capacitor of claim 15 , wherein the slot is non-rectangular.

20. The thin-film capacitor of claim 16 , wherein the first trench and the second trench are non-rectangular.

21. 1. A method for manufacturing a plurality of encapsulated thin film capacitors, comprising the steps of: Coating both sides of the thin film sheet with an encapsulant to prevent moisture / gas / chemicals from penetrating into the functional layer of the capacitor, the thin film sheet comprising: An insulator; a conductive core within the insulator; a current collector separated from the conductive core by a dielectric; and coating the creating at least one first terminal forming either a cathode or an anode connected to the conductive core through the insulator, and at least one second terminal forming the other of the cathode or the anode connected to the current collector; singulating the thin film sheet into a plurality of individual thin film capacitors, each capacitor having both sides encapsulated but an adjacent side unencapsulated; coating said unsealed adjacent side with additional sealing material; A method comprising:

22. 22. The method of claim 21, further comprising embedding the thin film sheet into a package substrate core while coating the adjacent unencapsulated side with gap filling with the additional encapsulant, and then singulating the thin film sheet and substrate core.

23. 22. The method of claim 21, further comprising embedding the plurality of individual thin film capacitors in a package substrate core and then coating the adjacent unencapsulated side with a gap fill of the additional encapsulant.

24. 1. A method of making a package having at least one semiconductor die, a substrate core to which the semiconductor die is attached via a first level of interconnects on one side, and a second level of interconnects on an opposite side of the substrate core for connection to an external circuit, comprising: creating a thin film capacitor having an insulator, a conductive core within the insulator, at least one first terminal forming either a cathode or an anode connected to the conductive core through the insulator, a current collector separated from the conductive core by a dielectric, and at least one second terminal forming the other of the cathode or the anode connected to the current collector; singulating the thin film sheet into a plurality of individual thin film capacitors; coating the singulated thin film capacitors on all sides with an encapsulant; embedding said thin film capacitor within said substrate core; A method comprising:

25. 1. A method of making a package having at least one semiconductor die, a substrate core to which the semiconductor die is attached via a first level of interconnects on one side, and a second level of interconnects on an opposite side of the substrate core for connection to an external circuit, comprising: Producing a thin film stack including a conductive core and a current collector separated from the conductive core by a dielectric; coating the top and bottom of the thin film stack with an encapsulant; forming an insulator around the thin film stack; drilling one or more vertical connections, including at least two vertical connections, in the thin film stack to create at least one first terminal forming either a cathode or an anode connected to the conductive core through the insulator, and at least one second terminal forming the other of the cathode or the anode connected to the current collector through the insulator; A method comprising:

26. 1. A method of making a package having at least one semiconductor die, a substrate core to which the semiconductor die is attached via a first level of interconnects on one side, and a second level of interconnects on an opposite side of the substrate core for connection to an external circuit, comprising: Producing a thin film stack including a conductive core and a current collector separated from the conductive core by a dielectric; drilling one or more vertical connections through the thin film stack; coating all sides of the thin film stack with an encapsulant; surrounding the encapsulated thin film stack with an insulator; making at least one first terminal forming either a cathode or an anode connected to the conductive core using one of the vertical connections through the insulator and encapsulant, and making at least one second terminal forming the other of the cathode or the anode connected to the current collector using a further one of the vertical connections through the insulator and encapsulant; A method comprising:

27. The improvement of claim 1 , wherein the redistribution layer is either above, below, or around the at least one capacitor.

28. The improvement of claim 1 , wherein said at least one capacitor comprises a plurality of capacitors of different shapes, sizes and thicknesses within a contour of a respective surface mountable device thereon.

29. The improvement of claim 1 , wherein the at least one capacitor is either a multi-layer ceramic capacitor, a thin film capacitor, or a polymer capacitor to accommodate different voltages, frequencies, and densities.

30. 30. The improvement of claim 28, wherein the redistribution layer connects a network of capacitors to the first level interconnects and second level interconnects on opposite sides of the substrate core.

31. 1. A method of making a package having at least one semiconductor die, a substrate core to which the semiconductor die is attached via a first level of interconnects on one side, and a second level of interconnects on an opposite side of the substrate core for connection to an external circuit, comprising: Producing a thin film stack including an insulator, a conductive core within the insulator, and a current collector separated from the conductive core by a dielectric; drilling one or more vertical connections through the thin film stack; making at least one first terminal forming either a cathode or an anode connected to the conductive core using one of the vertical connections through the insulator and encapsulant, and making at least one second terminal forming the other of the cathode or anode connected to the current collector using a further one of the vertical connections through the insulator and encapsulant; creating a seal ring surrounding the thin film stack as a barrier against one or more of moisture, gases, and chemicals entering the dielectric and current collector; A method comprising:

32. 32. The method of claim 31 , wherein the barrier height extends to the first and second terminals.

33. 32. The method of claim 31 , wherein the barrier height is the same as the thickness of the thin film stack.

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