Power Switch with Normally-On Transistor

Abstract

The power switch includes a cascode having a normally-on transistor connected in series with a normally-off transistor at a cascode node, a first diode connected between a gate of the normally-on transistor and a first ground common to the cascode and the diode, and a controller, the controller including a controller power supply having a power supply output connected to the cascode node, where an output of the controller power supply at the cascode node provides a voltage relative to a second ground that is floating with respect to the first ground, and a first controller output connected to the gate of the normally-on transistor, where the controller generates a first voltage at the gate of the normally-on transistor relative to the second ground.

Description

[Technical field]

[0001] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention relates to a power switch that includes a normally-on transistor, typically a depletion mode transistor that is controlled to be normally-off. [Background technology]

[0002] Almost every type of modern optical and electronic device, from computers to powertrains, includes power switching circuits to generate timing pulses and data packets and / or provide power. To power an electric powertrain, such as a powertrain used to power an electric vehicle, a power switch is needed that can be rapidly turned on and off to couple and disconnect a high voltage power source to a load. For such applications, III-V high electron mobility transistors (HEMTs), such as GaN (gallium nitride) transistors, are particularly advantageous. III-V HEMTs are wide bandgap transistors that are characterized by high breakdown voltages, high current densities, and low on-resistance. However, III-V HEMTs are generally normally-on depletion mode transistors. As a result, in power switching circuits that use these transistors as switching elements, a controller must constantly control the on / off state of the transistor, keeping it off unless it is coupled to a power source and needs to be turned on to switch power from the power source to the load. Without such control, for example if the switching circuitry is connected to the power supply before being connected to the controller or if the controller fails during operation, large current transients may occur that can damage the power switch, the load, and / or the power supply. Summary of the Invention

[0003] One aspect of an embodiment of the present disclosure relates to providing a fast switching power switch including a normally-on transistor, and optionally a depletion mode transistor, configured to electrically connect and disconnect a load and a load power supply, and to prevent the occurrence of high current transients that may be damaging to the power switch, the load, and / or the load power supply.

[0004] In one embodiment, the power switch includes a cascode, where a normally-on transistor is connected in series with a normally-off transistor, optionally an enhancement mode transistor, at a node of the cascode. A diode, optionally also called a safety diode, is connected between the gate of the normally-on transistor and a first ground common to the cascode and the diode. A controller, powered by a controller power supply, controls the gates of the depletion mode transistor and the enhancement mode transistor. An output of a controller power supply, providing a controller voltage relative to a second ground, is connected to the cascode node. The second ground, sometimes called a floating ground or a ground floating with respect to the first ground, is not directly connected to the first ground and has a voltage offset with respect to the first ground depending on the voltage of the cascode node minus the controller voltage. The controller power supply voltage has an absolute value greater than the absolute value of the threshold voltage of the normally-on transistor.

[0005] The controller is configured to turn the power switch on and off by dynamically controlling the on / off states of the transistors, and to keep the normally-on transistor off as long as the enhancement-mode transistor is off to prevent large transient currents. The controller controls the gate to make the cascode conductive and turn the power switch on by first turning on the enhancement-mode transistor and then turning on the normally-on transistor. When the power switch is on, the cascode provides a conductive path for current to flow from a load power source connected to the power switch, supplying power to a load connected to the power switch. The controller controls the gate to make the cascode non-conductive and turn the power switch off by turning off the normally-on transistor when the enhancement-mode transistor is on, thereby preventing current from the load power source from flowing through the cascode and supplying power to the load.

[0006] In the event that the power switch is connected to a load power supply and the controller does not operate to keep the normally-on transistor off when the enhancement mode transistor is off (also referred to as an abnormal situation), the safety diode operates to turn off the normally-on transistor and protect the power switch, the load, and / or the load power supply from damage due to large transient currents.

[0007] Also, in one embodiment of the present disclosure, the depletion and enhancement transistors may be n-channel or p-channel transistors, but for convenience of explanation and reference to voltage polarity, the following description assumes that the depletion and enhancement mode transistors are n-channel transistors as an example. Assume that the source of the enhancement mode transistor is connected to a first ground and the anode of the safety diode is connected to the gate of the normally-on transistor. Assume that the first ground voltage is a zero reference voltage and that the load power supply provides a positive voltage with respect to the first ground.

[0008] In the abnormal situation where the power switch is connected to a load power supply and the controller does not operate to keep the normally-on transistor off when the enhancement-mode transistor is off, the voltage at the drain and source of the normally-on transistor will be substantially equal to the positive voltage provided by the load power supply with respect to the first ground. The safety diode limits the voltage at the gate of the normally-on transistor with respect to the first ground to a positive forward voltage of the safety diode, which is less than the positive voltage of the power supply by at least the absolute value of the threshold voltage of the normally-on transistor. The forward voltage of the safety diode thereby generates a gate-to-source voltage that is less than the threshold voltage of the normally-on transistor, turning off the normally-on transistor and preventing transient current flow from damaging the power switch, the load, and / or the load power supply.

[0009] The controller then turns on the enhancement mode transistor, the cascode node, the source of the normally-on transistor, and the drain of the enhancement mode transistor, as well as the output of the controller power supply, are electrically connected to the first ground. The voltage of the second ground is therefore assumed to be a voltage (optionally referred to as the controller power supply voltage) less than the first ground. As a result, the controller sets the voltage of the gate of the normally-on transistor to the controller operating reference voltage, keeps the normally-on transistor off, and keeps the power switch off. The controller operates to turn on the normally-on transistor and turn on the power switch by applying a "turn on" positive voltage with respect to the controller operating reference voltage to the normally-on transistor gate. The turn on voltage has a magnitude that raises the voltage of the gate of the normally-on transistor to a voltage greater than the voltage of the first ground minus the absolute value of the threshold voltage of the normally-on transistor, but less than the voltage of the first ground plus the forward voltage of the safety diode. Thus, the turn-on voltage is not shunted to ground by a safety diode, but generates a gate-source voltage for the normally-on transistor that turns on the normally-on transistor and turns on the power switch.

[0010] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. [Brief description of the drawings]

[0011] Non-limiting examples of embodiments of the present invention will now be described with reference to the accompanying drawings herein, listed after this paragraph. Identical structures, elements, or parts that appear in more than one drawing are generally labeled with the same reference numerals in all drawings in which they appear. Dimensions of components and features shown in the drawings have been selected for convenience and clarity of presentation and are not necessarily shown to scale.

[0012] [Figure 1A] FIG. 2 shows a schematic diagram of a power switch including a controller, a cascode including depletion mode and enhancement mode transistors controlled by the controller, and a safety diode according to an embodiment of the present disclosure. [Figure 1B] 1 illustrates a timeline that generally illustrates the voltage generated by a controller to control a power switch as a function of time, according to an embodiment of the present disclosure. [Diagram 2] 1B illustrates a schematic diagram of a power switch similar to that shown in FIG. 1A but with an additional safety diode to protect the controller power supply from parasitic current flow, according to an embodiment of the present disclosure. [Figure 3A] 3 illustrates, in accordance with one embodiment of the present disclosure, a power switch similar to that shown in FIG. 2 , but including a comparator that disables operation of the controller when the voltage from the controller power supply is insufficient to enable the intended operation of the power switch. [Figure 3B] 3B illustrates a schematic diagram of a power switch similar to that shown in FIG. 3A, but with the safety diode replaced by a normally closed switch, according to one embodiment of the present disclosure. [Figure 4A] 1A-1D illustrate schematic diagrams of different configurations of a control circuit operable to control a normally-off enhancement mode transistor of a power switch having a cascode according to an embodiment of the present disclosure; [Figure 4B] 1A-1D illustrate schematic diagrams of different configurations of a control circuit operable to control a normally-off enhancement mode transistor of a power switch having a cascode according to an embodiment of the present disclosure; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] In this specification, unless otherwise stated, adjectives such as "substantially" and "about" modifying conditions or relationship characteristics of features of embodiments of the present disclosure are understood to mean that the condition or characteristic is defined within a tolerance allowed for operation for the intended use of the embodiment. Whenever a general term in this disclosure is described by reference to an exemplary example or a list of exemplary examples, the examples referred to are non-limiting examples of the general term, and the general term is not intended to be limited to the specific examples referred to. The phrase "in one embodiment", whether in conjunction with an allowance such as "may", "optionally", or "as an example", is used to introduce an example for consideration, but not necessarily a required configuration of possible embodiments of the present disclosure. Unless otherwise indicated, the word "or" in the specification and claims is considered an inclusive "or" rather than an exclusive or, indicating any combination of at least one, or more than one, of the items it connects to.

[0014] 1 illustrates a schematic of a power switch 20 according to one embodiment of the present disclosure. The power switch 20 includes a cascode 30 having a normally-on transistor, optionally a depletion mode transistor 31, connected in series with a normally-off transistor 32, a controller 60 controlling the transistors, and a safety diode 50 operative to turn off the normally-on transistor in the absence of proper control by the controller.

[0015] The cascode 30 is connected between terminals 41, 42 to which a load and a load power supply are connected, and the power switch controls the transfer of power from the load power supply to the load. Optionally, the terminal 42 is connected to ground G1, but for ease of explanation, it is assumed that the voltage of ground G1 is 0. The drain D31 of the normally-on transistor 31 is connected to the terminal 41, and the source S32 of the enhancement mode transistor 32 is connected to the terminal 42 and further to ground G1. The drain D32 of the enhancement mode transistor 32 is connected to the source S31 of the normally-on transistor 31 at a cascode node N33. Optionally, as shown in FIG. 1, the transistors 31, 32 are n-channel transistors, each having a threshold voltage V31. th , V32 th , and the normally-off transistor 32 is an enhancement mode transistor. A safety diode 50 is connected between the gate G31 of the normally-on transistor 31 and ground G1, with the anode of the safety diode connected to the gate. As an example, in FIG. 1, a load, represented diagrammatically by a resistor 40, and a positive voltage V LPS A load power supply LPS, which supplies power to a load by supplying a current to the load, is connected in series to power switch terminals 41 and 42.

[0016] The voltage signal generated by the controller 60 is referenced to a ground G2 which is floating with respect to a ground G1. The controller includes a controller power supply CPS which provides a positive voltage V CPS generates a positive voltage V CPS is the threshold voltage V31 th and optionally a threshold voltage V32 th The output 61 is electrically connected to the cascode node N33 and to a DC isolator or isolated gate driver 62 (optionally, but commonly referred to as a DC isolator). The DC isolator 62 connects a controller power supply CPS to the gate G32 of the enhancement transistor 32. When the controller power supply CPS is connected to a voltage V CPSto the DC isolator 62, the DC isolator generates or is controllable to generate a DC voltage at gate G32 relative to ground G1. The DC voltage provided by the DC isolator at gate G32 is the gate-to-source voltage V32 of the enhancement mode transistor 32. GS This generates a gate-source voltage V32 GS is the threshold voltage V32 of the enhancement mode transistor th , turning on the enhancement mode transistor N33 and connecting the cascode node N33 to ground G1.

[0017] In one embodiment of the present disclosure, the controller 60 includes an isolated power amplifier that receives power from a controller power supply CPS and operates as a gate driver 70 that controls the on / off state of the normally-on transistor 31. The gate driver has an output 71 connected to the gate G31 of the normally-on transistor 31 and an input 72 at which the gate driver receives a switch control signal from a gate driver controller (not shown). CPS When powered by 71 Controls the voltage V 71 represents the voltage of the gate G31 and the gate-source voltage V31 of the normally-on transistor 31 that controls the on / off state of the normally-on transistor 31. GS As described below, as long as the controller power supply CPS powers the DC isolator 62 to keep the enhancement mode transistor 32 on, the V 71 , and voltage V31 GS controls whether normally-on transistor 31 is turned off or on, which in turn controls whether power switch 20 is turned off or on, respectively.

[0018] Since the output 61 of the controller power supply CPS is connected to the cascode node N33 and the ground G2 is floating with respect to the ground G1, the voltage V71 is the gate-source voltage V31 of the normally-on transistor 31 GS =(V 71 -V CPS In the absence of a switch control signal from the gate driver, the controller voltage V 71 becomes 0 for G2, and the gate-source voltage V31 GS -V CPS As a result, V CPS is the absolute value of the threshold voltage of the normally-on transistor 31 |V31 th V31 because it is greater than | GS is V31 th and operates to turn off and keep a normally-on transistor off.

[0019] On the other hand, in one embodiment of the present disclosure, when triggered by an appropriate switch control signal at input 72, gate driver 70 supplies a voltage V 71 Increase V31 th Gate-source voltage V31 is greater than GS =(V 71 -V CPS ) is generated. Therefore, the gate-source voltage V31 GS turns on normally-on transistor 31, making cascode 30 conductive and turning on power switch 20.

[0020] 1A shows a schematic of a gate driver 70 receiving a switch control signal that is a series of voltage pulses 75 that causes the gate driver 70 to generate a corresponding series of output (also called "turn on") pulses 76. The voltage pulses are of positive magnitude V 76 and the gate-source voltage pulse V31 GS =(V 76 -V CPS In one embodiment, the intensity V 76 is (V 76 -V CPS )≧V31 th and each pulse 76 is V 76 ≧(V31th +V CPS )。 With enhancement mode transistor 32 on, switch control pulses 75 operate to turn power switch 20 on and off, delivering power from load power supply LPS to load 40 at a repetition frequency and duty cycle determined by the frequency and pulse width of the switch control signal pulses.

[0021] In the case of the power switch 20, the voltage pulse V 76 is referenced to ground G2 and V CPS With respect to ground G1, ground G2 has a maximum strength equal to (V N33 -V CPS Establish an operating reference voltage for the controller 60 equal to V N33 is the voltage at the cascode node N33. Because the enhancement transistor 32 is turned on, the cascode node N33 is electrically connected to the ground G1 through the turned-on enhancement transistor 32. Thus, the voltage V N33 is the voltage drop V32 across enhancement transistor 32 in G1 ds The operating reference voltage of ground G2 is approximately equal to the voltage (G1+V32 ds )-V CPS In one embodiment, the safety diode 50 is approximately equal to the voltage drop V32 expected when the power switch 20 is turned on. ds Forward voltage V is greater than f Thus, with respect to the ground G1 to which the safety diode 50 is directly connected, the voltage pulse 76 has a forward voltage V f As a result, the voltage pulse is not shunted to ground G1 by the safety diode and turns on transistor 31, which in turn turns on power switch 20, resulting in a voltage V31 GS The occurrence of the above is prevented.

[0022] 1B shows a graph 100 that illustrates a schematic time evolution and relative timing of voltages associated with the operation of the power switch 20 along timelines 101, 102, 103, and 104, according to an embodiment of the present disclosure. CPS is shown along timeline 101. Timeline 102 shows the time when the controller power supply 60 is at a voltage V CPS to the DC isolator, the gate voltage V32 that the DC isolator 62 (FIG. 1A) applies to the gate G32 to turn on and keep the enhancement mode transistor 32 on. GS The timeline 102 shows a time when the controller power supply is at a voltage V CPS 1A , which controls the gate driver 70 to generate a gate driver output pulse 76 ( FIG. 1A ) that turns on the normally-on transistor 31 and turns on the power switch 20. A timeline 104 shows the voltage of the output pulse 76 of the normally-on transistor 31 relative to ground G2 and ground G1, and the threshold voltage V31 th As described above, the controller power supply CPS is turned on and supplies the voltage V CPS When the power supply GND is turned on, the voltage of the ground G2 is higher than the voltage of the ground G1 to which the source S31 is electrically connected through the turned-on enhancement mode transistor 32. CPS The voltage of the gate driver pulse 76 exceeds G2 (G1-|V31 th When the gate driver pulse 76 rises to a voltage (assuming V31 is negative) greater than (G1-|V31 |), the normally-on transistor 31 turns on, turning on the power switch 20. th The voltage that rises above |) and turns on the power switch 20 is indicated by the area of ​​the pulse that is not hatched.

[0023] On the other hand, as long as the controller 60 is connected to the cascode 30 and properly controls the transistors 31, 32 to keep the normally-on transistor 31 off and the enhancement mode transistor 32 on when attempting to turn off the power switch 20, the controller 60 will operate as described above and prevent the generation of potentially large harmful transient currents. However, if the load power source LPS is connected to the power switch 20 and the normally-on transistor 31 is turned on and the enhancement mode transistor is turned off, for example as a result of the controller 60 failing or not being properly connected to the cascode 30, a large harmful transient current may be generated. If such an abnormal situation occurs, the voltages at the drain D31, gate G31, and source S31 of the normally-on transistor 31 may exceed the voltage V of the load power source. LPS , which operates to turn on the normally-on transistor and allow harmful transient currents to occur. In one embodiment of the present disclosure, the safety diode 50 operates to prevent the normally-on transistor from turning on. The voltage on the gate G31 rises to a voltage above the forward voltage threshold V f When the negative gate-source voltage V31 exceeds V 1 , the diode turns on and limits the voltage of the gate G31 with respect to ground G1 to the diode's forward voltage threshold, turning off the normally-on transistor 31. GS and limit the occurrence and / or duration of large transients that may damage the power switch 20 and the circuitry connected to the power switch.

[0024] 2 illustrates a schematic of a power switch 220 according to one embodiment of the present disclosure. Power switch 220 is similar to power switch 20, but includes a controller 260 with an additional safety diode 250 that operates to block a parasitic current path from cascode node 33 to the controller.

[0025] 3A illustrates a schematic of a power switch 320 according to an embodiment of the present disclosure. The power switch 320 is similar to the power switch 220, but includes a controller 360 having a comparator 362, optionally a Schmitt trigger, with the comparator 362 having an input 364 connected to the output 61 of the controller power supply CPS, and an output 366 connected to the DC isolator 62 and the gate driver 70. In one embodiment, the controller power supply CPS calculates the absolute value |V31 of the threshold voltage of the normally-on transistor 31. th Voltage V greater than | CPS If the power supply CPS does not provide sufficient voltage to enable proper operation of the controller, the comparator 362 disables operation of the DC isolator 62 and the gate driver 70. If the power supply CPS provides sufficient voltage, the comparator 362 generates an enable signal at output 366 that enables operation of the DC isolator 62 and the gate driver 70. By preventing operation of the DC isolator 62 and the gate driver 70, the safety diode 50 turns off the normally-on transistor 31, as described above, turning off the power switch 360.

[0026] Although in the above description the power switch is described as including a safety diode 50 that operates to turn off the normally-on transistor and protect the power switch from damage due to large transient currents, implementation of the embodiments of the present disclosure is not limited to a safety diode. For example, a normally-on switch that turns off when the normally-off transistor 32 turns on can be used to protect the power switch from damaging transients. FIG. 4B illustrates a schematic of a power switch 321 according to an embodiment, similar to the power switch 320 shown in FIG. 3A, but with a normally-on switch 150 instead of the diode 50 (FIG. 3A). The normally-on switch 150 is optionally coupled to a voltage, e.g., V32, generated by the gate driver 62 or by an enable signal provided by the comparator 362 at output 366. GS It will be turned off by

[0027] FIG. 4A illustrates an embodiment of the present disclosure in which a controller power supply CPS is connected to an enhancement-mode transistor 32 to generate a DC gate-source voltage V32 that turns on the enhancement-mode transistor. GS 1 shows schematic details of a circuit configuration 62-1 of a DC isolator 62 that generates

[0028] The circuit configuration 62-1 optionally includes an inverting operational amplifier 500 coupled to a resistor R1 and a capacitor C1 connected in series to ground G1. The rails 501, 502 of the amplifier 500 are connected to the output 61 of the controller power supply CPS and to ground G2, respectively. A resistor R1 is connected between the output 505 and the input 506 of the inverting amplifier 500. As a result, the DC voltage V supplied by the controller power supply CPS is CPS In response to this, the inverting amplifier 500 generates an oscillating voltage and current that is rectified by resistor R2, capacitors C2, C3, and diodes D1, D2 to generate a DC gate-to-source voltage V32 that turns on the enhancement mode transistor 32. GS Capacitors C2, C3 DC isolate the controller power supply CPS from enhancement transistor 32. Resistor R3 is a bleeder resistor.

[0029] FIG. 4A illustrates an embodiment of the present disclosure in which a controller power supply CPS is connected to an enhancement-mode transistor 32 to generate a DC gate-source voltage V32 that turns on the enhancement-mode transistor. GS 13 shows schematic details of another circuit configuration 62-2 of the DC isolator 62 for generating

[0030] In one embodiment of the present disclosure, circuit configuration 62-2 is similar to circuit configuration 62-1, but instead of generating an oscillating current by coupling the output 505 of an inverting operational amplifier 500 to the input 506 of the amplifier, in configuration 62-2 the input is configured to receive a series of input pulses 601 from an external driver (not shown) at input 506. In response to the input pulses 601, amplifier 500 generates a DC gate-to-source voltage V32 that turns on enhancement mode transistor 32. GS 6, which generates a series of output pulses 602 that are rectified to provide

[0031] In this specification and claims, the verbs "comprise," "include," and "have," and each of their conjugations, are used to indicate that the object of the verb is not necessarily an exhaustive list of components, elements, or parts of the subject of the verb.

[0032] The description of the embodiments of the invention in this application is provided by way of example and is not intended to limit the scope of the invention. The described embodiments include different features, not all of which are necessary for all embodiments of the invention. Some embodiments utilize only some of the features or possible combinations of the features. Various embodiments of the invention, including variations of the described embodiments of the invention and different combinations of the features mentioned in the described embodiments, will occur to those skilled in the art. The scope of the invention is limited only by the claims.

Claims

1. a cascode having a normally-on transistor connected in series with a normally-off transistor at a cascode node; a first diode connected between the gate of the normally-on transistor and a first ground, the first ground being common to the cascode and the diode; A controller, a controller power supply having a power supply output connected to the cascode node, the controller power supply output at the cascode node providing a voltage relative to a second ground that is floating relative to the first ground; a first controller output connected to the gate of the normally-on transistor, the controller generating a first voltage at the gate of the normally-on transistor relative to the second ground; A controller including: Including, power switch.

2. 2. The power switch of claim 1, further comprising a second diode connecting the output of the controller power supply to the cascode node.

3. 3. The power switch of claim 1, wherein the controller includes a second controller output connected to the gate of the normally-off transistor, and wherein the controller generates a voltage at the gate of the normally-off transistor relative to the first ground to turn the normally-off transistor on and off.

4. 4. The power switch of claim 3, further comprising a DC isolated driver, the primary side of which is powered by the controller power supply that generates a voltage at the second controller output.

5. The power switch of claim 4 , wherein the DC isolation is capacitive.

6. The power switch according to any one of claims 1 to 5, wherein an anode of the first diode is connected to the gate of the normally-on transistor.

7. a cascode having a normally-on transistor connected in series with a normally-off transistor at a cascode node; a normally-on switch connected between a gate of the normally-on transistor and a first ground, the first ground being common to the cascode and the diode; A controller, a controller power supply having a power supply output connected to the cascode node, the controller power supply output at the cascode node providing a voltage relative to a second ground that is floating relative to the first ground; a first controller output connected to the gate of the normally-on transistor, the controller generating a first voltage at the gate of the normally-on transistor relative to the second ground; A controller including: Including, power switch.

8. 8. The power switch of claim 7, further comprising a second diode connecting the output of the controller power supply to the cascode node.

9. 9. The power switch of claim 7 or 8, wherein the controller includes a second controller output connected to the gate of the normally-off transistor, the controller generating a voltage at the gate of the normally-off transistor relative to the first ground to turn the normally-off transistor on and off.

10. The power switch of claim 9 , wherein the controller generates a signal to turn off the normally-on switch substantially simultaneously or immediately after turning on the normally-off transistor when the controller turns on the normally-off transistor.

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