User-configurable hardware settings for overclocking

Abstract

User configurable hardware settings for overclocking are described. In accordance with the described techniques, a user input is received to adjust a hardware setting for operating a processing unit in an overclocked mode. The user input adjusts, for example, at least one of a voltage droop threshold or a frequency adjustment of a clock rate. A voltage droop is detected while operating the processing unit in the overclocked mode. In response to detecting the voltage droop, a clock rate of the processing unit is adjusted based at least in part on the adjusted hardware setting.

Description

[Technical field]

[0001] (Related Applications) This application claims priority to U.S. patent application Ser. No. 17 / 704,684, entitled "User Configurable Hardware Settings for Overclocking," filed March 25, 2022, the disclosure of which is incorporated herein by reference in its entirety. [Background technology]

[0002] A processing unit in an integrated circuit consumes a variable amount of power depending on the process being executed on the processing unit. The processing unit consumes very little power while it is idle, but power consumption increases rapidly when the processing unit needs to perform an action. Some operations require more power than others, and when higher performance is required from the processing unit, the clock rate of the processing unit is increased so that the processing unit operates at a higher frequency than the specified frequency, also known as "overclocking." An overclocked state typically has a higher operating voltage. One factor that adversely affects the power integrity of a circuit is the occurrence of supply voltage droop. Supply voltage droop is a temporary drop or reduction in the supply voltage provided by a power supply to one or more elements in a circuit, such as transistors. Supply voltage droop can be the result of a drop in the supply voltage provided to the power supply, an operational change to the power supply, a surge in the power supply current provided by the power supply, or any combination thereof.

[0003] The detailed description will now be described with reference to the accompanying drawings. [Brief description of the drawings]

[0004] [Figure 1] FIG. 1 illustrates a non-limiting example of a processor system operable to implement user-configurable hardware settings for overclocking. [Diagram 2] FIG. 2 illustrates a non-limiting example of a clock generator in one or more embodiments. [Diagram 3] FIG. 2 illustrates another non-limiting example of a clock generator in one or more embodiments. [Figure 4] FIG. 1 illustrates a non-limiting example of a multi-processor core system in one or more embodiments. [Diagram 5] FIG. 1 illustrates a non-limiting example of a user interface in one or more embodiments. [Figure 6] FIG. 2 illustrates a procedure in an exemplary embodiment for adjusting a clock rate of a processing unit based on adjusted hardware settings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0005] (overview) Voltage droop can result in a reduction in the maximum clock frequency or an increase in the voltage required to operate the processing unit in overclocked mode. Some conventional processing units are configured to operate at a higher voltage in overclocked mode to account for voltage droop, but doing so consumes a larger amount of power than is required for operation. As an example, if the voltage required to operate a processing unit in overclocked mode is 1 volt and a voltage droop of 50 millivolts is expected during operation, the conventional processing unit may choose to operate at 1.005 volts to continue operating in overclocked mode if a voltage droop of 50 millivolts occurs. However, doing so would waste system power since the extra 50 millivolts are needed just to cover a voltage droop that may only last for a few milliseconds.

[0006] To solve the problems of conventional systems, the described technique dynamically performs one or more actions in response to detection of a voltage droop to compensate for the voltage droop. As an example, the processing unit's clock is stretched by momentarily reducing the clock rate to compensate for the voltage droop and allow the processing unit to continue to operate in the overclocked mode. Furthermore, unlike conventional systems, the hardware settings associated with operating the processing unit in the overclocked mode are user configurable. For example, the hardware settings are exposed via a user interface that allows a user to adjust various hardware settings, such as by adjusting voltage droop thresholds and responses to detected voltage droop. Enabling user configuration of the hardware settings associated with the overclocked mode allows the processing unit to be optimized for the system's unique operating conditions or workload. Thus, the processing unit can achieve a higher overclocked stable frequency, and therefore better performance, than conventional processing units.

[0007] In some aspects, the techniques described herein relate to a method that includes receiving user input for adjusting hardware settings to operate a processing unit in an overclocked mode, detecting voltage droop while operating the processing unit in the overclocked mode, and adjusting a clock rate of the processing unit based at least in part on the adjusted hardware settings in response to detecting the voltage droop.

[0008] In some aspects, the techniques described herein relate to methods in which the hardware settings include a voltage droop threshold and a droop response that specifies one or more actions to compensate for the voltage droop.

[0009] In some aspects, the techniques described herein relate to how the droop response specifies the amount by which the clock rate of a processing unit is reduced to compensate for voltage droop.

[0010] In some aspects, the techniques described herein relate to a method further including exposing at least the voltage droop threshold and the droop response in a user interface.

[0011] In some aspects, the techniques described herein relate to methods in which user input adjusts at least one of a voltage droop threshold or a droop response.

[0012] In some aspects, the techniques described herein relate to a method in which detecting voltage droop includes detecting an output voltage and determining that a voltage droop threshold is met by the output voltage.

[0013] In some aspects, the techniques described herein relate to a method in which adjusting a clock rate of a processing unit based at least in part on the adjusted hardware setting further includes adjusting the clock rate based on a droop response associated with a voltage droop threshold.

[0014] In some aspects, the technology described herein relates to how voltage droop thresholds and droop responses are related to temperature ranges.

[0015] In some aspects, the techniques described herein relate to methods where the hardware configuration further includes an additional voltage droop threshold and an additional droop response associated with the additional voltage droop threshold, where the additional voltage droop threshold and the additional droop response are associated with an additional temperature range.

[0016] In some aspects, the techniques described herein relate to methods in which hardware settings are maintained in a table accessible by a controller, and the controller updates the hardware settings in response to user input.

[0017] In some aspects, the techniques described herein relate to a system that includes a storage device for maintaining hardware settings for operating a processing unit in an overclocked mode; a controller for detecting voltage droop while the processing unit is operating in the overclocked mode and determining a frequency adjustment of a clock rate of the processing unit based at least in part on the hardware settings; and a clock generator for generating an output clock rate based on the determined frequency adjustment such that the processing unit remains overclocked.

[0018] In some aspects, the technology described herein relates to a system in which the controller is further configured to expose at least a portion of the hardware settings via a user interface to enable the hardware settings to be adjusted by user input.

[0019] In some aspects, the technology described herein relates to a system in which the controller is further configured to update hardware settings maintained in the storage device in response to user input.

[0020] In some aspects, the technology described herein relates to a system that enables a processing unit to maintain an overclock through frequency adjustment.

[0021] In some aspects, the technology described herein relates to a system further including a voltage sensor for detecting an output voltage of the processing unit.

[0022] In some aspects, the techniques described herein relate to a system in which hardware settings include a voltage droop threshold and a droop response that specifies the amount to reduce the clock rate of a processing unit to compensate for voltage droop.

[0023] In some aspects, the technology described herein relates to a system in which a controller detects voltage droop by determining that a voltage droop threshold is met by an output voltage detected by a voltage sensor.

[0024] In some aspects, the technology described herein relates to a system in which a controller determines a frequency adjustment based on a droop response that specifies the amount to reduce the clock rate of a processing unit to compensate for voltage droop.

[0025] In some aspects, the technology described herein relates to a system in which a voltage droop threshold and droop response are associated with a temperature range.

[0026] In some aspects, the techniques described herein relate to a method that includes displaying a user interface including user interface elements for adjusting a droop threshold and a droop response associated with operating a processing unit in an overclocked mode; receiving user input via the user interface to adjust the droop threshold and the droop response; detecting a voltage droop when an output voltage of the processing unit meets the adjusted droop threshold; and, in response to detecting the voltage droop, adjusting a clock rate of the processing unit based on the adjusted droop response.

[0027] 1 illustrates a non-limiting example of a processor system 100 operable to implement user-configurable hardware settings for overclocking. The processor system 100 includes one or more cores coupled with system firmware, such as a controller 104, via a data communication bus to transmit information between the cores 102 and the controller 104 (only one core 102 is shown for simplicity). The processor system 100 also includes a clock generator 106, a voltage sensor 108, a voltage generator 110, and a reference clock generator 112. The clock generator 106 may be implemented in a variety of different ways, such as a phase-locked loop (PLL) or a frequency-locked loop (FLL). In one or more embodiments, the one or more cores 102 include one or more temperature sensors 114. The controller 104 may be implemented in any suitable manner, such as one or more state machines, a programmable processor, and / or a combination of a processor executing software instructions and one or more state machines.

[0028] The clock generator 106 is shown as receiving multiple inputs from a reference clock generator 112, a controller 104, and a voltage generator 110. In the processor system 100, these inputs include a reference clock signal 116, an analog voltage supply value 118 (e.g., a VDDA value), an input voltage value 120, an analog voltage supply 124 (e.g., VDDA), and an input voltage 126. In this example, the analog voltage supply value 118 and the input voltage value 120 are collectively referred to as an overclocking parameter 122. A voltage sensor 108 coupled to the clock generator 106 can sense and obtain a measurement of an output voltage 128 provided from the voltage generator 110 to the core 102. In one or more embodiments, the voltage sensor 108 is implemented within the clock generator 106. Alternatively, the voltage sensor 108 is located external to the clock generator 106, but is operatively coupled to the clock generator 106.

[0029] In one or more embodiments, the controller 104 determines the overclocking parameters 122 based on a measured frequency 130 in the core 102. Alternatively or additionally, the controller 104 determines the overclocking parameters based on frequency adjustments made to the clock rate of the core 102, as described further herein. Based on the aforementioned inputs, the clock generator 106 generates an adjusted output clock 132 from the reference clock signal 116 obtained from the reference clock generator 112. The output clock 132 controls the operating frequency of the core 102. The generation of the output clock 132 based on the adjustment of the reference clock signal 116 by the clock generator 106 is described in more detail in conjunction with FIG. 2.

[0030] According to the described techniques, the controller 104 accesses the hardware configuration 134. In one or more embodiments, the hardware configuration 134 is maintained (e.g., as a table) in a storage device accessible by the controller 104. Generally, the hardware configuration 134 specifies settings for operation of the processor system 100 under various operating conditions. This includes specifying settings for different operating conditions in which an overclocking mode of the processor system 100 is used. Examples of such different operating conditions include, but are not limited to, different temperature ranges in which the processor system 100 is operating, execution of processes for different types of applications (e.g., computer games as opposed to productivity tools), different stages associated with booting up the system (e.g., during boot, after boot, etc.), and / or other "profiles" of use of the system 100.

[0031] In contrast to conventional approaches, the controller 104 exposes the hardware settings 134 such that the settings can be adjusted by user input. In other words, the controller 104 exposes at least a portion of the hardware settings 134 such that one or more of the hardware settings can be adjusted. Such adjustments include adjusting the operating conditions of a particular profile, such that the controller 104 causes the use of the hardware settings 134 associated with the profile based on detection of the adjusted operating conditions, rather than based on detection of a previous operating condition (e.g., before adjustment). Such adjustments also include adding a profile by defining the operating conditions under which the controller 104 causes the processor system 100 to operate using the hardware settings 134 associated with the profile and by specifying one or more of the associated hardware settings. Additionally or alternatively, such adjustments include adjusting the hardware settings 134 associated with an existing profile, such that the controller 104 causes the processor system 100 to use the adjusted hardware settings 134 based on detection of the operating conditions of the existing profile.

[0032] In one or more embodiments, the controller 104 exposes one or more portions of the hardware settings 134 to an application, which causes the output (e.g., display) of a user interface for adjusting the hardware settings 134 to operate one or more processing units of the processor system 100 in an overclocked mode. By way of example, the user interface presents user interface elements (e.g., menus, drop-down boxes, radio buttons, dialog boxes, graphical knobs, slider bars, text boxes, etc.) to which a user provides user input to define or adjust operating conditions and / or define respective hardware settings 134 (e.g., hardware configurations) to activate in response to detecting operation under such conditions. A user interface for adjusting the hardware settings 134 of the processor system 100 to operate in an overclocked mode is described in more detail in connection with FIG. 5.

[0033] In the illustrated example, the controller 104 is shown receiving the setting specification 136. In one or more embodiments, the setting specification 136 corresponds to a user input, as described immediately above, for adjusting one or more hardware settings 134 and / or operating conditions for operating the processing unit in an overclocked mode. Alternatively or in addition, the setting specification 136 is received from another source, such as an application, such that when the application is executed, the controller 104 operates the processor system 100 according to the settings specified by the setting specification 136. Other exemplary setting sources include firmware updates (e.g., for the processor system 100) and importing settings from one or more files. It should be understood that in variations, the setting specification 136 is received from other sources without departing from the spirit or scope of the described technology.

[0034] 1, the hardware settings 134 are shown as including a voltage droop threshold 138, a droop response 140, and a temperature range 142. These settings are merely exemplary hardware settings 134 accessible by the controller 104. It should be understood that the controller 104 may access other hardware settings 134 without departing from the spirit or scope of the described technology. Thus, in various embodiments, the controller 104 allows user input to adjust different settings in which the processor system 100 is capable of operating.

[0035] As described herein, the voltage droop threshold 138 specifies the amount of voltage droop in the output voltage 128 that, when met, will cause the controller 104 to initiate a response of the processor system 100 to the voltage droop by performing one or more actions, such as, for example, by momentarily decreasing the clock rate to account for the voltage droop. The voltage droop threshold 138 can be defined in different ways in various embodiments. In one or more embodiments, for example, the voltage droop threshold 138 is defined as a percentage of the analog voltage supply value 118, and if the output voltage 128 as a percentage of the analog voltage supply value 118 meets (e.g., is below) the voltage droop threshold 138, the controller 104 initiates a corresponding response defined by the hardware settings 134. Alternatively or in addition, the voltage droop threshold 138 is defined as a fixed offset from the analog voltage supply value 118, and if the amount by which the output voltage 128 is offset from the analog voltage supply value 118 meets (e.g., is above) the voltage droop threshold 138, the controller initiates a corresponding response. Alternatively or additionally, the voltage droop threshold 138 is a fixed voltage level, and when the output voltage 128 corresponds to a voltage level that meets (e.g., is less than or equal to) the threshold, the controller initiates a corresponding response. In variants, the voltage droop threshold 138 can be defined in other ways.

[0036] The droop response 140 defines the response of the controller 104 to the respective voltage droop threshold 138 being detected as being met by the output voltage 128. For example, based on the voltage droop threshold 138 being detected as being met, the controller 104 performs one or more actions to compensate for the voltage droop. For example, in response to detecting the voltage droop, the controller sends a change signal to the voltage generator 110 to set the analog voltage supply 124 and / or the input voltage 126 and sends overclocking parameters 122 indicative of those changes to the clock generator 106. In one or more embodiments, the droop response 140 includes a frequency adjustment that specifies the amount by which the clock rate is reduced to mitigate the voltage droop defined by the respective voltage droop threshold 138, for example, by stretching the reference clock signal 116. In one or more embodiments, the droop response 140 includes instructions to implement a clock stretch (e.g., stretch the reference clock signal 116) to reduce the effects of the voltage droop. As an example, a user interface exposed to a user may allow the user to configure the voltage droop threshold 138 to be 2.5% of the output voltage and the droop response 140 to be a frequency adjustment of 25 megahertz. If the output voltage subsequently decreases by 2.5% (thus meeting the user-configured voltage droop threshold), the clock rate of the processing unit is temporarily stretched by decreasing the clock rate by 25 megahertz to account for the voltage droop. An example of stretching the reference clock signal 116 based on frequency is described in more detail in connection with FIG. 2.

[0037] Temperature range 142 is an example of a type of operating condition with which hardware settings 134 (e.g., at least one voltage droop threshold 138 and at least one droop response 140) are associated in one or more embodiments. In this example, temperature sensor 114 detects an environmental temperature in which core 102 is processing instructions. If the temperature detected by temperature sensor 114 is within temperature range 142, controller 104 utilizes voltage droop threshold 138 and droop response 140 corresponding to temperature range 142. In this manner, if processor system 100 operates at a temperature within temperature range 142 and a voltage droop that meets the respective voltage droop threshold 138 is detected, controller 104 signals processor system 100 to initiate the respective droop response 140 to mitigate the voltage droop.

[0038] In one or more embodiments, the hardware configuration 134 includes a number of different temperature ranges 142, each of which has a corresponding voltage droop threshold 138 and droop response 140. As discussed above, each temperature range corresponds to a profile of system operation, and by specifying the number of temperature ranges included in the hardware configuration 134, multiple profiles are generated. As discussed above, the hardware configuration 134 is configured to include profiles based on types of operating conditions other than temperature, such as for performing processes corresponding to different types of applications (e.g., computer games as opposed to productivity tools), for different stages associated with booting up the system (e.g., during boot, post boot, etc.), etc. Indeed, profiles for other detectable operating conditions of the system 100 are used in various embodiments.

[0039] In at least one example, a profile is associated with multiple voltage droop thresholds 138 and multiple droop responses 140. By having multiple voltage droop thresholds and corresponding responses, the processor system 100 is controlled to respond in a specified (e.g., different) manner when the voltage droop increasingly deviates from the desired voltage while operating under the specific conditions of the profile. For example, if a profile has multiple voltage droop thresholds 138 and multiple droop responses 140, the controller 104 initiates a first droop response 140 in response to detecting a voltage droop that meets a first voltage droop threshold 138. If the voltage droop increases beyond the first threshold and subsequently meets a second voltage droop threshold 138, the controller 104 initiates a corresponding second droop response 140 to mitigate the impact of the voltage droop on performance. It should be appreciated that in one or more embodiments, more than two steps, e.g., more than two pairs of voltage droop thresholds 138 and corresponding droop responses 140, are maintained in the hardware configuration 134 for a particular profile. In the context of stretching the reference clock signal 116 to overclock the processor system 100, consider the following discussion.

[0040] 2 illustrates a non-limiting example 200 of a clock generator in accordance with one or more embodiments. In this example 200, the clock generator 106 includes three components: an oscillation adjustment module 202, a calibration module 204, and a clock oscillator 206. The oscillation adjustment module 202 is coupled to the controller 104 to receive the overclocking parameters 122 therefrom, and is coupled to the voltage sensor 108 to receive a sensed output voltage 210 based on the output voltage 128 provided by the voltage generator 110. The calibration module 204 is coupled to the controller 104 to receive the overclocking parameters 122. The calibration module 204 also generates a calibrated calibration value 208. The calibrated calibration value 208 is a calibrated voltage value for programming the clock oscillator 206, which includes an adaptive oscillator circuit.

[0041] A voltage sensor 108, which may be part of the clock generator 106 or an external device coupled thereto, receives the overclocking parameters 122, or more specifically at least an analog voltage supply value 118 (e.g., a VDDA value) (corresponding to an analog voltage supply 124 from the voltage generator 110 or more specifically from an analog voltage source), as well as an output voltage 128 provided to the core 102. The voltage sensor 108 uses the analog voltage supply value 118 to compare the output voltage 128 to the analog voltage supply 124 (e.g., VDDA) to detect any voltage droop in the output voltage 128.

[0042] In some conventional systems, the voltage sensor receives only the output voltage and compares it to a predetermined reference VDDA value, which is less accurate than directly comparing the output voltage to the supplied VDDA. In one or more embodiments, the voltage sensor 108 facilitates a dynamic means of sensing voltage droop in the output voltage 128 by implementing a flexible output voltage vs. VDDA comparison that is not based on a predetermined reference VDDA value. The advantage of this comparison is a reduced error band corresponding to the voltage droop estimate provided by the voltage sensor 108.

[0043] The voltage sensor 108 generates a sensed output voltage 210 that includes detection of any voltage droop in the output voltage 128. The oscillation adjustment module 202 receives the sensed output voltage 210 and the overclocking parameters 122 and generates a frequency adjustment 212 based on the input. The frequency adjustment 212 includes instructions to adjust the clock rate of the processing system (e.g., by stretching the reference clock signal 116) to reduce the effects of the voltage droop. In one or more embodiments, the frequency adjustment 212 is based on the droop response 140, which may be adjusted based on user input as described throughout this specification. For example, the oscillation adjustment module 202 may determine the magnitude of the frequency adjustment 212 based on a user-defined frequency adjustment relative to a respective voltage droop threshold 138. The clock oscillator 206 receives, for example, the reference clock signal 116 and the frequency adjustment 212, as well as the output voltage 128, the corrected calibration value 208, the analog voltage supply 124 (e.g., VDDA), and the input voltage 126 from the voltage generator 110. Based on these inputs, the clock generator 206 generates the output clock 132 for the core 102 .

[0044] In the techniques described herein, the clock generator 106 detects an indication of overclocking via the overclocking parameter 122, and the voltage sensor 108 detects an indication of voltage droop. The clock oscillator 206 generates the output clock 132 such that the reference clock signal 116 is stretched to reduce the effects of voltage droop while maintaining the core 102 operating in an overclocked state, i.e., without reducing the operating frequency or clock rate of the core 102. Thus, clock stretching only causes a delay in the clock signal without slowing down the clock rate. In such an embodiment, the core 102 can maintain operation at a higher performance facilitated by overclocking while the effects of voltage droop from the voltage generator 110 are reduced.

[0045] 3 illustrates another non-limiting example 300 of a clock generator in one or more embodiments. In this example 300, instead of the clock oscillator 206 receiving the output voltage 128 as shown in FIG. 2, the clock generator 106 includes a set of clock buffers 302, e.g., inverters, amplifiers, CML buffers, etc., that receive the output voltage 128. Because the clock oscillator 206 does not receive the output voltage 128, the generated output clock is an unbuffered output clock 304, which is received by the clock buffer 302 to generate a buffered output clock 306 used by the core 102 or multiple cores. The clock buffer 302 may be any suitable type of buffer that facilitates distributing multiple copies of a clock to multiple cores with the same frequency requirements, for example, to save space and cost by eliminating additional timing components, external voltage dividers, or signal level transition circuits.

[0046] 4 illustrates a non-limiting example of a multi-processor core system 400 in accordance with one or more embodiments. The system 400 includes a total of N+1 cores 102, core 0 through core N, which may be implemented in a common integrated circuit. The voltage generator 110 in this example includes an analog voltage source 402, e.g., a VDDA 1.8V supply, which is coupled to a voltage regulator 404. In one or more embodiments, the voltage regulator 404 receives an analog voltage supply 124 (e.g., VDDA) from the voltage source 402, adjusts the voltage of the supply, and distributes an output voltage 128 to each of the cores 102 and also to the clock generator 106 as inputs to those components. Thus, the voltage regulator 404 uses the provided analog voltage supply 124 (e.g., VDDA) to provide an output voltage 128 to each of the cores 102 and also to the clock generator 106, or more specifically, to a voltage sensor 108 coupled to the clock generator 106. In one or more embodiments, the voltage generator 110 is implemented within an integrated circuit that includes the core 102. Alternatively, in one or more implementations, the voltage generator 110 is implemented separately from the integrated circuit. The voltage generator 110 provides a variable output voltage 128 according to a voltage level selected by the controller 104.

[0047] The system 400 also includes a controller 104 coupled to each of the cores 102, the controller 104 receiving the measured frequency 130 of each core 102 and possibly a frequency adjustment 212 from the core 102, which may alternatively be provided directly by the clock generator 106 as shown or may be determined based on a user-configurable loop response 140. The controller 104 also includes an overclocking decision module 406 that determines whether to implement an overclocking to improve performance of the core 102 based on the measured frequency 130 (e.g., a current measured frequency) and the frequency adjustment 212. For example, the overclocking decision may be in the form of changing a performance state (P-state) of the core 102, as described further herein.

[0048] In response to a determination by the overclocking decision module 406 that overclocking should be enabled, the controller 104 sends an analog voltage supply change signal 408 to the voltage source 402 and an input voltage change signal 410 to the voltage generator 110. The signals 408 and 410 contain the newly set input voltage and VDDA values ​​by the controller 104, which are relayed to the clock generator 106 in the form of overclocking parameters 122.

[0049] In some examples, the overclocking determination module 406 enables overclocking at initial system boot, i.e., when the system 400 is powered on and begins operation. In some examples, the overclocking determination module 406 provides an adjustment request, including signals 408 and 410, indicative of overclocking, based on factors such as the type of software or hardware application running using the core 102. Such applications may include system-intensive applications, such as games that incorporate different subsystems on the computer, such as hard drives, graphics, memory, and CPU, or CPU-intensive applications, such as multi-threaded applications, including, but not limited to, photo editing and video transcoding applications. In some examples, the adjustment request may be provided directly via user input, e.g., via a user interface, when a user desires to increase system performance. In some examples, the adjustment request may be based on feedback from a processing unit, e.g., feedback based on a generated output clock rate, such as a core detecting a potential need for an increase in operating frequency to accommodate increased performance requirements. Any other suitable circumstances may be considered regarding when and how such an adjustment request may be generated by the overclocking determination module 406.

[0050] System 400 may be any type of processor system, such as a Central Processing Unit (CPU) or a Graphics Processing Unit (GPU). For example, system 400 may be implemented as an x86 processor having an x86 64-bit instruction set architecture and used in desktop, laptop, server and superscalar computers, an Advanced Reduced Instruction Set Computer (ARM) processor used in mobile phones or digital media players, or a Digital Signal Processor (DSP) useful in processing and implementing algorithms related to digital signals such as voice data and communication signals, and a microcontroller useful in consumer applications such as printers and copiers.

[0051] Cores 102 form the computational center of system 400 and are responsible for performing a number of computational tasks. For example, processor cores 102 may include, but are not limited to, execution units that perform addition, subtraction, shifting, and rotation of binary numbers, and address generation and load and store units that perform address calculations for memory addresses and loading and storing data from memory. The operations performed by processor cores 102 enable the execution of computer applications.

[0052] The processor core 102 operates according to a specific performance state (P-state) as controlled by the controller 104. The P-states are described as follows: The Advanced Configuration and Power Interface (ACPI) standard is an operating system-based specification that regulates the power management of a computer system. For example, the ACPI standard can control and instruct the processor core for better management of battery life. In so doing, ACPI assigns processor power states, called C-states, and forces the processor to operate within the limits of these states. There are various levels of C-states to which the processor may be assigned, with corresponding implications on the processor's performance (e.g., C0, a fully operational state with full power consumption and full energy dissipation; C1, a sleep state where instruction execution is stopped and the processor may return to execute instructions instantly; or C2, another sleep state where the processor may take longer to return to the C0 state), and the processor will perform in a manner specified by each state.

[0053] While the processor is in the fully operational C0 state, the processor is associated with other states called performance states or P-states. There are various levels of P-states, each associated with an operating voltage and frequency. The highest performance state is P0, which may correspond to maximum operating power, voltage and frequency. However, the processor may also be placed in lower performance states, e.g., P1 or P2, which correspond to lower operating power, voltage and / or frequency. Generally, when the processor transitions to a lower P-state, the processor operates at a lower capacity than before.

[0054] 5 illustrates a non-limiting example user interface 500 in accordance with one or more embodiments. The example 500 includes a display device 502 that outputs a settings adjustment user interface 504 that receives user input for adjusting settings of the hardware configuration 134.

[0055] In one or more embodiments, the settings adjustment user interface 504 includes user interface elements that allow a user to at least one of adjust settings (e.g., of an existing profile), add new settings or new profiles, or delete settings or existing profiles. In variations, the settings adjustment user interface 504 includes user interface elements that allow a user to provide user inputs to perform different actions with respect to the settings of the hardware settings 134 without departing from the spirit or scope of the described technology.

[0056] In this example 500, the user interface 504 includes an adjust existing element 506, an add new element 508, and a delete element 510. The adjust existing element 506 is selectable by a user to adjust an existing setting, such as the setting of a profile maintained by the hardware configuration 134. The add new element 508 is selectable by a user to add a new setting and / or a new profile to the hardware configuration 134. The delete element 510 is selectable by a user to remove a setting and / or a profile from the hardware configuration 134.

[0057] In one or more embodiments, as in the depicted example, settings adjustment user interface 504 includes a profile selection element 512 that allows a user to provide user input to select an existing profile maintained with hardware configuration 134, e.g., causing user interface 504 to output settings associated with the selected profile and / or adjust settings associated with the selected profile. As discussed above, the settings maintained by hardware configuration 134 and associated with the profile are used to operate in overclocking mode in one or more embodiments.

[0058] Here, the user interface 504 also includes a profile-specific portion 514, which can be configured in various ways in different embodiments to enable adjustment of the setting profile maintained using the hardware settings 134. In this example 500, for example, the profile-specific portion 514 displays a profile identifier 516, operating conditions 518 under which the profile is specified to be used, and hardware settings 520 associated with the profile that control overclocking of the processor system 100 while operating under the respective operating conditions.

[0059] In example 500, profile identifier 514 is shown with an edit element selectable by a user to edit the profile's identifier (e.g., name) or to add an identifier to a new profile, and the identifier can be stored in or associated with hardware configuration 134 in one or more embodiments.

[0060] The operating conditions 518 in this example include a temperature range, e.g., −190 to −160, associated with the identified profile. As discussed above, a temperature range is one type of operating condition for which overclocking settings can be specified in accordance with the described techniques. The settings adjustment user interface 504 includes a condition type element 522 that is selectable to specify the type of operating condition to be detected for using the profile. As discussed above, different types of conditions include the type of application utilizing the processor system 100, the stage relative to booting the system 100, and the like. Indeed, other types of conditions can be specified via the settings adjustment user interface 504 for association with a set of hardware settings (e.g., overclocking settings) without departing from the spirit or scope of the described techniques. Although a single operating condition is shown in the illustrated example, it should be understood that in one or more embodiments, the user interface 504 and hardware settings 134 support the addition of at least one additional operating condition (e.g., a temperature range and a type of application utilizing the processing system) for a given profile.

[0061] The hardware configuration 520 includes one or more voltage droop thresholds 138 and one or more corresponding droop responses 140 associated with the identified profile. In this example 500, the identified profile is shown to have two voltage droop thresholds 138 and two corresponding droop responses 140 shown as frequency adjustments. In particular, the identified profile includes a first voltage droop threshold 138 configured by the user at 97.5% of the voltage and a first droop response 140 configured by the user at -25 megahertz. The identified profile also includes a second voltage droop threshold 138 configured by the user at 95% of the voltage and a second droop response 140 configured by the user at -50 megahertz. Indeed, one voltage droop threshold 138 and respective droop response 140, or more than two voltage droop thresholds 138 and respective droop responses 140, may be used for a profile, as described above. However, in this configuration, the processor system 100 reduces the clock rate by 25 megahertz if the voltage droop exceeds a 97.5% threshold (e.g., a 2.5% voltage drop) and reduces the clock rate by 50 megahertz if the voltage droop exceeds a 95% threshold (e.g., a 5% voltage drop).

[0062] Also, as discussed above, the voltage droop thresholds 138 can be specified in a variety of manners. In this example, the voltage droop thresholds 138 are shown as percentages. However, the user interface 504 includes selectable elements to change the type of threshold. For example, an element is selectable to change the type of voltage droop threshold to a voltage level offset. Additionally, the specified voltage droop thresholds 138 are displayed along with elements that allow those thresholds to be individually adjusted by the user. The user interface 504 also includes selectable elements to allow the droop responses 140 to be individually adjusted by the user.

[0063] In this example 500, the profile-specific portion 514 of the settings adjustment user interface 504 also includes an additional settings element 524, a save element 526, and an activation element 528. In embodiments where there are more adjustable settings than the voltage droop threshold 138 and the droop response 140, the settings adjustment user interface 504 includes user interface elements that allow more settings to be adjusted, for example, via the additional settings element 524. The save element 526 is selectable to save adjustments made to the profile's operating conditions and / or settings via the user interface 504. In response to a selection of the save element 526, for example, the hardware settings 134 are updated to maintain the adjusted overclocking settings, for example, replacing the previous settings with the adjusted settings.

[0064] The activation element 528 is selectable by a user to cause the controller 104 to use the settings of the identified profile and to monitor for specified operating conditions, such as, for example, that the associated settings are used if the operating conditions are detected. In one or more embodiments, in the absence of a selection of the activation element 528, the settings are maintained in the hardware settings 134, but are not used if the operating conditions specified for the profile are detected. After selecting the activation element 528, if the operating conditions specified for the profile are detected, the settings are used. In a scenario where no operating conditions are specified for the profile, a user's selection of the activation element 528 causes the specified hardware settings to be used immediately by the system 100, and simply causes the controller 104 to implement the corresponding droop response 140 on the system in response to detecting the specified voltage droop 138.

[0065] It should be understood that the setting adjustment user interface 504 is only one example of a user interface that can be used to adjust the settings of the hardware settings 134. Different user interfaces that display different user interface elements and adjust different settings can be used to adjust the settings of the hardware settings 134 without departing from the spirit or scope of the described technology. Although the user interface is shown as being displayed via the display device 502, it should be understood that the user interface can alternatively or additionally be output to interact with the user in different manners in accordance with the described technology, such as a voice-based interface presented via a voice assistant device, etc.

[0066] FIG. 6 illustrates a procedure 600 in an exemplary embodiment for adjusting a clock rate of a processing unit based on adjusted hardware settings.

[0067] User input is received for adjusting hardware settings to operate a processing unit in an overclocked mode (block 602). As an example, the settings adjustment user interface 504 receives user input for adjusting hardware settings 134 of a processing unit, such as a CPU or GPU. The adjustment user interface 504 displays hardware settings 134, such as, for example, one or more voltage droop thresholds 138 and corresponding droop responses 140, along with elements that allow those thresholds and corresponding responses to be individually adjusted by the user. Thus, the user input modifies one or more voltage droop thresholds 138 and / or corresponding droop responses 140.

[0068] Voltage droop is detected while operating the processing unit in overclock mode (block 604). As an example, the controller 104 detects voltage droop when the output voltage 128 meets a voltage droop threshold 138. The voltage droop threshold 138 can be defined in different ways in various embodiments. In one or more embodiments, for example, the voltage droop threshold 138 is defined as a percentage of the analog voltage supply value 118, and if the output voltage 128 as a percentage of the analog voltage supply value 118 meets (e.g., is below) the voltage droop threshold 138, the controller 104 initiates a corresponding response defined by the hardware settings 134. Alternatively or in addition, the voltage droop threshold 138 is defined as a fixed offset from the analog voltage supply value 118, and if the amount by which the output voltage 128 is offset from the analog voltage supply value 118 meets (e.g., is above) the voltage droop threshold 138, the controller 104 initiates a corresponding response. Alternatively or additionally, the voltage droop threshold 138 is a fixed voltage level, and when the output voltage 128 corresponds to a voltage level that meets (eg, is below) the threshold, the controller 104 initiates a corresponding response.

[0069] In response to detecting the voltage droop, the clock rate of the processing unit is adjusted based at least in part on the adjusted hardware settings (block 606). As an example, in response to detecting the voltage droop, the controller 104 sends an instruction to the clock generator 106 to perform a clock stretch (e.g., stretch the reference clock signal 116) to reduce the effect of the voltage droop, thereby causing the droop response 140. The adjustment is based on the adjusted hardware settings, including at least one of the adjusted voltage droop threshold 138 or the adjusted droop response 140. In other words, the user provides an input for adjusting one or both of the voltage droop threshold 138 and the droop response 140, which is utilized by the controller 104 to determine the frequency response to the voltage droop.

[0070] It should be understood that many variations are possible based on the disclosure herein, and although features and elements have been described above in particular combinations, each feature or element can be used alone without the other features and elements, or in various combinations with or without the other features and elements.

[0071] The various functional units illustrated in the figures and / or described herein (including, as appropriate, one or more of the cores 102, the controller 104, the clock generator 106, and the voltage generator 110) may be implemented in any of a variety of different ways, such as hardware circuits, software or firmware running on a programmable processor, or any combination of two or more of hardware, software, and firmware. The provided methods may be implemented in any of a variety of devices, such as a general purpose computer, a processor, or a processor core. Suitable processors include, by way of example, a general purpose processor, a special purpose processor, a conventional processor, a digital signal processor (DSP), a graphics processing unit (gGPU), a parallel accelerated processor, multiple microprocessors, one or more microprocessors associated with a DSP core, a controller, a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) circuit, any other type of integrated circuit (C), and / or a state machine.

[0072] In one or more embodiments, the methods and procedures provided herein may be implemented in a computer program, software, or firmware embodied in a non-transitory computer-readable storage medium for execution by a general purpose computer or processor. Examples of non-transitory computer-readable storage media include Read Only Memory (ROM), Random Access Memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD-ROM disks and Digital Versatile Disks (DVDs).

Claims

1. 1. A method comprising: receiving user input for adjusting a hardware setting to operate the processing unit in an overclocked mode; detecting a voltage droop while operating the processing unit in the overclocked mode; and adjusting a clock rate of the processing unit based at least in part on an adjusted hardware setting in response to detecting the voltage droop. method.

2. The hardware settings include a voltage droop threshold and a droop response that specifies one or more actions to compensate for the voltage droop.

2. The method of claim 1.

3. The droop response specifies an amount of reduction in the clock rate of the processing unit to compensate for the voltage droop. The method of claim 2.

4. and exposing at least the voltage droop threshold and the droop response in a user interface. The method of claim 2.

5. the user input adjusts at least one of the voltage droop threshold or the droop response. The method of claim 2.

6. Detecting the voltage droop Detecting an output voltage; determining that the voltage droop threshold is met by the output voltage. The method of claim 2.

7. adjusting a clock rate of the processing unit based at least in part on the adjusted hardware setting includes adjusting the clock rate based on the droop response associated with the voltage droop threshold. The method of claim 6.

8. the voltage droop threshold and the droop response are associated with a temperature range; The method of claim 2.

9. the hardware configuration includes an additional voltage droop threshold and an additional droop response associated with the additional voltage droop threshold; the additional voltage droop threshold and the additional droop response are associated with an additional temperature range.

9. The method of claim 8.

10. the hardware configuration is maintained in a table accessible by a controller, the controller updating the hardware configuration in response to the user input; 2. The method of claim 1.

11. 1. A system comprising: a storage device for maintaining hardware settings for operating the processing unit in an overclocked mode; A controller; a clock generator; The controller: detecting a voltage droop while the processing unit is operating in the overclocked mode; determining a frequency adjustment to a clock rate of the processing unit based at least in part on the hardware configuration; The device is configured to: The clock generator includes: and wherein the processing unit is configured to generate an output clock rate based on the determined frequency adjustment to maintain the overclocking. system.

12. the controller is configured to expose at least a portion of the hardware settings via a user interface to enable the hardware settings to be adjusted by user input; The system of claim 11.

13. the controller is configured to update the hardware configuration maintained on the storage device in response to user input. The system of claim 12.

14. The frequency adjustment enables the processing unit to maintain the overclocking. The system of claim 11.

15. Further comprising a voltage sensor for detecting an output voltage of the processing unit. The system of claim 11.

16. the hardware settings include a voltage droop threshold and a droop response that specifies an amount of reduction in the clock rate of the processing unit to compensate for the voltage droop; 16. The system of claim 15.

17. the controller detects the voltage droop by determining that the voltage droop threshold is met by the output voltage detected by the voltage sensor.

17. The system of claim 16.

18. the controller determines the frequency adjustment based on the droop response specifying an amount of reduction in the clock rate of the processing unit to compensate for the voltage droop.

20. The system of claim 17.

19. the voltage droop threshold and the droop response are associated with a temperature range; 17. The system of claim 16.

20. 1. A method comprising: displaying a user interface including user interface elements for adjusting a droop threshold and a droop response associated with operating the processing unit in an overclocked mode; receiving user input via the user interface to adjust the droop threshold and the droop response; detecting a voltage droop when an output voltage of the processing unit satisfies the adjusted droop threshold; and in response to detecting the voltage droop, performing one or more actions to compensate for the voltage droop based on an adjusted droop response. method.

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