Start-up circuit for flyback converter

Abstract

The converter includes a power stage for providing a current through a primary winding of the transformer in response to a PWM signal and for inducing a current in a secondary winding of the transformer to generate an output voltage. The power stage has a switching terminal. The converter also includes a controller (260), a clamp circuit (320), and an impedance device (330). The controller (260) includes a first transistor (Q1) coupled to a second transistor (Q3) for initiating an operating voltage during a start-up mode and for providing a control voltage based on an amplitude of a switching voltage at the switching terminal during a switching mode. The clamp circuit (320) is coupled between a control input of the first transistor (Q) and a reference terminal and clamps the voltage at the first control input in response to the switching voltage exceeding a clamp voltage. The impedance device (330) is coupled between the switching terminal and the clamp circuit (320).

Description

[Technical field]

[0001] Power converters may be implemented in a variety of ways. One type of power converter is the flyback converter. Like many switching converters, a flyback converter includes a controller that implements pulse width modulation (PWM) of a transistor coupled to a primary winding of a transformer. The output voltage from the flyback converter is derived from a secondary winding of the transformer. An auxiliary voltage derived from the secondary side of the transformer (through an auxiliary winding) also provides an operating voltage to the controller. Most, if not all, flyback converters include a start-up circuit to provide an operating voltage to the controller from the input voltage of the flyback converter until the controller can subsequently initiate a PWM switching cycle of the transistor. At that point, the start-up circuit is deactivated and the controller continues to operate based on the auxiliary voltage derived from the secondary side of the transformer. Some flyback converters also implement switch node sensing via a switch node sensing circuit to reduce switching losses associated with the transistor controlled by the controller. The start-up circuit and the switch node sensing circuit are separate circuits. Another trend with flyback converters is that the input voltage to the converter is being pushed to higher and higher levels. In some instances, the input voltage can be in the range of 1000 V or more. Such high input voltages can present design challenges for a flyback converter. Summary of the Invention

[0002] In one example, a power converter includes a power stage for providing a current through a primary winding of a transformer in response to a PWM signal and for inducing a current in a secondary winding of the transformer to generate an output voltage. The power stage has a switching terminal. The power converter also includes a controller, a clamping circuit, and an impedance device. The controller includes a first transistor coupled to a second transistor for initiating an operating voltage during a start-up mode and for providing a control voltage based on an amplitude of a switching voltage at the switching terminal during a switching mode. The clamping circuit is coupled between a control input and a reference terminal of the first transistor and clamps a voltage at the first control input in response to the switching voltage exceeding a clamping voltage. The impedance device is coupled between the switching terminal and the clamping circuit. [Brief description of the drawings]

[0003] [Figure 1] 1 is a schematic diagram of an example power converter having separate start-up and switching terminal sensing circuits;

[0004] [Diagram 2] FIG. 1 is a schematic diagram of an example power converter having circuitry that implements both start-up and switching terminal sensing functions using multiple transistors to accommodate higher level input voltages.

[0005] [Diagram 3] 3 is a schematic diagram of a switching controller that can be used in the power converter of FIG. 2 in one example.

[0006] [Figure 4] FIG. 3 is a schematic diagram of a switching controller that can be used in the power converter of FIG. 2 in another example.

[0007] [Diagram 5] 5 is a graph illustrating various voltages within the switching controller of FIG. 4 in one example.

[0008] [Figure 6] FIG. 1 is a schematic diagram of a switching controller that implements a start-up function but no switching terminal detection function in one example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] In the drawings, the same reference numbers or other reference identifiers are used to denote the same or similar (structural and / or functional) features.

[0010] The present disclosure generally relates to a power converter with switching control. The power converter generates an output voltage in response to an input voltage. As an example, the power converter may be configured as a flyback power converter. The power converter includes a gate driver stage that generates one or more switching signals in response to a respective one or more pulse width modulation (PWM) signals. In an example, the gate driver generates a first switching signal in response to a first PWM signal and generates a second switching signal in response to a second PWM signal. The power converter may also include a power stage. The power stage includes a transformer and a first switch (e.g., a transistor) controlled by switching signals (e.g., first and second switching signals). As an example, the first switch may be activated via the first switching signal to provide a primary current through a primary winding of the transformer, for example, from an input voltage to a reference terminal (e.g., ground). The primary current in the primary winding may induce a secondary current in a secondary winding of the transformer. A rectifier may be coupled to the secondary winding to rectify a voltage at the secondary winding, thereby generating an output voltage. A second switch in the power stage may be activated via a second switching signal to circulate a magnetizing current associated with the transformer in a circuit path that includes the LC resonator.

[0011] The power converter may also include a controller that generates a PWM signal based on a feedback signal from the power stage. In one example, the controller includes a comparator configured to generate the PWM signal in response to a comparison of an amplitude of the control voltage to a predefined switching threshold voltage. The power converter may also include a plurality of control transistors that are serially coupled to switching terminals in the power stage. The plurality of control transistors are operable to initiate an operating voltage for the switching controller during a start-up mode, which is a state of the power converter when the input voltage is increasing from 0V toward a steady-state level (e.g., 800V, 1000V, etc.) and before the switching controller begins implementing PWM switching cycles in the power stage. In some examples, the plurality of control transistors are also used to implement switching terminal voltage sensing. The controller provides a control voltage based on an amplitude of a switching voltage associated with the switching terminal. In one example, the predefined switching threshold voltage has a low amplitude (e.g., less than 1 volt), and the comparison provides a PWM signal to implement near zero-volt switching (ZVS) of the first switch to reduce switching losses associated with the first switch. Thus, in some examples, the multiple control transistors can be used to (a) provide a start-up operating voltage for the switching controller and, in the case of a flyback converter that requires switching terminal sensing, (b) provide a switching terminal sensing function (e.g., zero voltage switching of the first switch).

[0012] 1 is a schematic diagram of an example power converter 100. In this example, power converter 100 is a flyback converter. An input voltage V IN is provided at the input terminal 101 of the power converter, and the power converter provides an output voltage V OUTThe power converter 100 includes a power stage 154, a switching controller 110, a switching terminal detection circuit 120, and a start-up circuit 130. The power stage includes a transformer 56, a transistor Q1, diodes D1, Z1 (Z1 is a Zener diode), D OUT , and D AUX , capacitor C F , and C VDD The transformer 56 includes a primary winding W P , secondary winding W S , and the auxiliary winding W A In this example, the transistor Q1 is an n-channel field effect transistor (NFET) and includes a primary winding W P and a reference terminal 103 (e.g., ground). The switching controller 110 has an output 111 coupled to the gate of the transistor Q1. The switching controller 110 generates a control signal PWM for the transistor Q1 at the output 111 and controls the on-off state of the transistor Q1 according to a target duty cycle of the PWM control signal.

[0013] The drain of transistor Q1 is connected to switching terminal 58 via the primary winding W P The voltage on switching terminal 58 is coupled to a switching voltage V SW The switching terminal 58 is also coupled to a switching terminal detection circuit 120. The switching terminal detection circuit 120 detects the switching voltage V SW , generating a control signal 121 for the switching controller 110 to control the voltage V SW is equal to or close to 0V. Therefore, the switching controller 110 SW falls below a threshold (e.g., close to or equal to the voltage at the reference terminal 103) and the controller may activate (turn ON) transistor Q1 when the drain-to-source voltage (Vds) of transistor Q1 is close to or equal to 0V, thereby reducing switching losses associated with transistor Q1.

[0014] Diode D OUT The anode of the secondary winding W S is coupled to the capacitor C F But, diode D OUT and the secondary reference terminal 133. OUT But the secondary winding W S The voltage from the power converter is rectified and output voltage V OUT Diode D AUX The anode of the auxiliary winding W A is coupled to the capacitor C VDD is the diode D AUX and the secondary reference terminal 133. AUX is the auxiliary winding W A The voltage from is rectified to produce voltage V DD Generates a voltage V DD is provided as an operating voltage to the switching controller 110 during a normal operation mode, which refers to a mode in which the switching controller 110 is powered on and controls the on-off state of the transistor Q1 according to the PWM switching cycles of the PWM signal.

[0015] Voltage V OUT and V DD The switching controller 110 is powered on so that it can generate a PWM control signal for the gate of the transistor Q1, thereby controlling the switching voltage V SW to transfer the energy through the transformer 56. The start-up circuit 130 is coupled between the input terminal 101 and the switching controller 110. During start-up of the power converter 100, the start-up circuit provides a voltage VDD_SU to power up the controller 110. Once the switching controller 110 is powered on with the help of the start-up circuit 130, the switching controller 110 starts to provide a PWM control signal to the gate of the transistor Q1, causing the energy to be transferred through the transformer 56. The energy transferred through the transformer 56 is converted to an operating voltage V DDand the output voltage V for the switching controller 110 OUT The wake-up circuit 130 may then be deactivated.

[0016] Start-up circuit 130 is a separate circuit from switching terminal sense circuit 120. Unfortunately, these two separate circuits occupy a large amount of area on the semiconductor die on which power converter 100 is manufactured.

[0017] 2 illustrates an example of a power converter circuit 250 that solves one or more of the problems described above. The power converter circuit 250 receives a DC input voltage V IN (e.g., a rectified AC input voltage) to the DC output voltage V at output terminal 255. OUT Some or all of the components of the power converter circuit 250 may be implemented in any of a variety of ways, such as on an integrated circuit (IC). In the example of FIG. 2, the power converter circuit 250 includes a gate driver 252, a power stage 254, and a switching controller 260. The power stage 254 includes a primary winding W P and the secondary winding W S and the auxiliary winding W A The power stage 254 includes a transformer 256 having an input inductor L K and the resonant capacitor C F 2 as transistors Q1 and Q2. In this example, transistors Q1 and Q2 are NFETs. The source of transistor Q2 is connected to the drain of transistor Q1 and to the primary winding W at switching terminal 258. P The voltage on the switching terminal 258 is a switching voltage V SW Diode D OUT The anode of the capacitor C is coupled to the secondary winding. F is the diode D OUT and a reference terminal 133. F The voltage acrossOUT Diode D AUX The anode of the auxiliary winding W A is coupled to a capacitor C VDD is the diode D AUX and a reference terminal 133. VDD The voltage across the VDD and is provided as the operating voltage to the switching controller 260 during the normal operating mode.

[0018] The switching controller 260 includes a comparator 262 and a plurality of control transistors 264. The switching controller 260 includes an output terminal 255, a capacitor C VDD , and to switching terminal 258. The switching controller generates signals PWM1 and PWM2 for the input of the gate driver 252. The output of the gate driver 252 is coupled to the gates of transistors Q1 and Q2 and provides switching signals SS1 and SS2 to the gates of transistors Q1 and Q2, respectively, as shown. Thus, transistor Q1 is controlled via switching signal SS1 and transistor Q2 is controlled via switching signal SS2.

[0019] The power converter circuit 250 implements repeating PWM switching cycles. Each switching cycle includes at least a first switching phase and a second switching phase. During the first switching phase, the switching controller 260 activates (turns ON) the transistor Q1 into the saturation region via the first switching signal SS1 to drive the primary current Ip through the input terminal 201 (V IN ) to the input inductor L K , primary winding W P , and to the reference terminal 103 via the transistor Q1. P In response to the primary current Ip in S But the secondary winding W S Induced in the diode D OUT It flows through the load (not shown) and the capacitor C FThe output voltage V OUT Generate.

[0020] When the transistor Q1 is deactivated via the first switching signal SS1, after a short predefined dead time, during the second switching phase, the switching controller 260 activates the transistor Q2 via the gate driver switching signal SS2, thereby energizing the secondary winding W. S , output voltage V OUT , and diode D OUT Together, this causes the magnetizing current, which is a component of the current Ip in the primary winding, to decay to zero amperes and then reverse direction due to the voltage on resonant capacitor C1. The negative magnetizing current discharges the junction capacitance of transistor Q1 and charges the junction capacitance of transistor Q2 following the deactivation of transistor Q2. When the charge on transistor Q1 is removed, the Vds of transistor Q1 drops to approximately zero volts before switching controller 260 activates transistor Q1 again. As mentioned above, activating transistor Q1 when the drain-source voltage is approximately zero volts is referred to as zero voltage switching (ZVS). As a result of switching controller 260 implementing ZVS, which is useful for, for example, activated clamp flyback and ZVS flyback converters, the switching losses associated with transistor Q1 in power converter circuit 250 are relatively low. During the activation time of transistor Q2, leakage inductance L K and capacitor C1 form the aforementioned LC resonant tank and have leakage inductance L K Energy may be circulated to the output, thus effectively reducing clamp losses as well.

[0021] Voltage V OUT The magnitude of is determined in part by the primary winding W P and the secondary winding W S Similarly, the auxiliary winding W A The voltage across V AUX The amplitude of is partially due to the primary winding W P and the auxiliary winding W AThe operating voltage of the controller V DD is the auxiliary winding W A Auxiliary voltage V related to AUX Corresponding to (V DD V AUX From Diode D AUX (minus the forward bias voltage drop associated with

[0022] In some examples, the plurality of control transistors 264 associated with the switching controller 260 includes two transistors. In other examples, the plurality of control transistors 264 includes three (or more) transistors. The plurality of control transistors 264 is connected to a switching voltage V SW The comparator 262 may be a depletion mode transistor that generates the switching control voltage V in response to the switching control voltage V SW 2. As an example, power converter circuit 250 may implement zero voltage switching of transistor Q1, thereby asserting signal PWM2 based on a comparison of switching voltage V at switching node 258. SW The control transistors 264 may also provide a start-up voltage for the switching controller 260 when the power converter circuit 250 is started up.

[0023] FIG 3 is a schematic diagram of an example switching controller 350 that can be used to implement the switching controller 260 of FIG 2. In the example of FIG 3, the switching controller 350 includes a voltage regulator 356 (e.g., a low dropout (LDO) voltage regulator), a mode controller 358, a comparator 262, a voltage source circuit 362 (which may be programmable), (which may be non-programmable), a timing generator 364, a plurality of control transistors 264, a clamp circuit 320, an impedance device 330, a capacitor C HVG , resistors R1, R2, R3, and R Z, and switches SW1, SW2, SW3, and SW4. Each switch SW1-SW4 may be implemented as a separate transistor. In this example, the plurality of control transistors 264 includes two transistors Q3 and Q4 coupled in series. Each of the transistors Q3 and Q4 may be a depletion mode transistor (e.g., an n-channel depletion mode transistor). A depletion mode transistor is normally on and is turned off by application of a gate voltage at least at a threshold voltage lower than its source voltage. Thus, a depletion mode transistor is on when Vgs is equal to 0V. The drain of the transistor Q4 is coupled to the switching terminal 258. An impedance device is coupled between the switching terminal 258 and the gate of the control transistor Q4. The clamp circuit 320 is coupled between the gate of the transistor Q4 and the reference terminal 103. A resistor Rz is coupled between the source of the transistor Q4 (and the drain of the transistor Q3) and the gate of the control transistor Q4.

[0024] Capacitor C HVG is coupled between the gate of transistor Q3 and reference terminal 103. Resistor R1 is coupled between the source of transistor Q3 and capacitor C HVG One terminal of the switch SW4 is coupled between a resistor R1 and a capacitor C HVG The other terminal of the switch SW4 is coupled to an output terminal 356a of the voltage regulator 356. AUX 2) is coupled to an input terminal 356b of a voltage regulator 356 and to a power input terminal 358a of a mode controller 358. Thus, the power input terminal 358a of the mode controller 358 and the input terminal 356b of the voltage regulator 356 are coupled to the auxiliary winding W of the transformer 256 during the normal operating mode of the power converter 250. A to operating voltage V DD The switch SW3 receives the capacitor C HVG (coupled to the gate of transistor Q3) and a power input terminal 358 of a mode controller 358.

[0025] A resistor R3 is coupled between the source of transistor Q3 and one terminal of a switch SW2, the other terminal of which is coupled to the negative (-) input of a comparator 262. The voltage on the source of transistor Q3 is voltage V SWC and the voltage on the negative input of comparator 262 is voltage V SWC A resistor R4 is coupled between the negative input of the comparator 262 and the reference terminal 103, and a resistor R2 is coupled between the source of the transistor Q3 and one terminal of a switch SW1, the other terminal of which is coupled to a power input terminal 358a of the mode controller 358.

[0026] A voltage source circuit 362 is coupled to the positive (+) input of the comparator 262. The voltage source circuit 362 may be programmable (as shown) or non-programmable and provides a voltage V TH_ZVS The output of comparator 262 is coupled to an input 364a of a timing generator 364. An output 364b of timing generator 364 provides signal PWM2 and is coupled to an input 358b of mode controller 358.

[0027] The mode controller 358 may be implemented as a finite state machine including logic gates, flip-flops, registers, etc. The mode controller 358 generates output signals on outputs 358c, 358d, 358e, and 358f, which are coupled to the control inputs of switches SW1, SW2, SW3, and SW4, respectively. The mode controller 358 generates signals SC1, SC2, SC3, and SC4 to the control inputs of switches SW1, SW2, SW3, and SW4, respectively. Through each of the signals SC1-SC4, the mode controller 358 may open (disable) or close (enable) the respective switch.

[0028] Clamp circuit 320 is coupled between the gate of transistor Q4 at clamp terminal 321 and reference terminal 103. In the example of FIG. 3, clamp circuit 320 includes multiple Zener diodes 320a coupled in series between clamp terminal 321 and reference terminal 103. The number of Zener diodes and their breakdown voltages define the clamp voltage of clamp circuit 320. The target clamp voltage of clamp circuit 320 is application specific and may be, for example, a voltage V SW When the clamp circuit 320 is activated, the voltage on the clamp terminal 321 is a fixed voltage (clamp voltage) that is the sum of the breakdown voltages of the Zener diodes 320a of the clamp circuit 320. In one example, the clamp voltage on the clamp terminal 321 is the voltage V during normal operation mode. SW For example, during normal operation, the voltage V SW If the maximum value of V is 1000V, SW When the voltage V reaches approximately 500V, the clamp circuit 320 is activated. SW is lower than the clamp voltage of clamp circuit 320, clamp circuit 320 is not activated and the Vgs of transistor Q4 is approximately 0V due to the resistor coupled between the gate and source of transistor Q4.

[0029] In the example of FIG. 4, the impedance device 330 is a capacitor C FF The impedance device 330 may be implemented, for example, as multiple capacitors coupled in series and / or parallel. In another example, the impedance device 330 includes a capacitor coupled in series with a resistor.

[0030] During the start-up mode of the power converter, the switching controller 350 provides the operating voltage to the mode controller 358. During the normal mode operation of the power converter, the auxiliary winding W A The switching controller 350 is supplied with an operating voltage V DD, and switching controller 350 senses the voltage on switching terminal 258 and implements ZVS for transistor Q1 (FIG. 2). That is, switching controller 350 provides both a start-up function and a switching terminal sensing function.

[0031] During the start-up mode of the power converter circuit 250, the auxiliary winding W A Operating voltage from V DD The amplitude of V is less than an undervoltage lockout (UVLO) amplitude, which may have a predefined amplitude stored in the amplitude mode controller 358. The mode controller 358 controls the operating voltage V DD to the UVLO amplitude to ensure that the power converter circuit 250 is in start-up mode (e.g., V DD is below the UVLO voltage) or in normal operating mode (for example, V DD It can be determined whether the operating voltage V is equal to or greater than the UVLO voltage. DD is less than the UVLO amplitude (e.g., the first UVLO amplitude), mode controller 358 determines that power converter circuit 250 is in the start-up mode, so that, as described further below, circuit elements within switching controller 350 respond by establishing a sufficient operating voltage for mode controller 358 such that mode controller 358 can provide pulse width modulated switching of transistors Q1 and Q2. In response to determining that power converter circuit 250 is in the start-up mode, mode controller 358 deactivates (opens) SW2 and SW4 via respective switch control signals SC2 and SC4, and activates (e.g., closes) switches SW1 and SW3 via respective switch control signals SC1 and SC3.

[0032] In start-up mode, the power stage 254 operates as the input voltage V increases towards a steady-state level (e.g., 1000V). IN In the absence of PWM switching of transistors Q1 and Q2 (because mode controller 358 is not yet powered on), the voltage V SW is the input voltage VIN From the primary winding W P , and the voltage drop across Vgs. As previously mentioned, transistors Q3 and Q4 may be depletion mode transistors and are activated (ON) in response to approximately zero amplitude Vgs. Thus, during start-up mode, transistors Q3 and Q4 are in an activated state. When transistors Q3 and Q4 are activated, they collectively function as a current source during start-up mode, drawing current through resistor R1 and current through closed switches SW1 and SW3 into capacitor C HVG and C VDD Start charging the battery.

[0033] As a result, the operating voltage V DD and voltage V HVG begins to increase during the start-up mode. Finally, the operating voltage V DD reaches an amplitude approximately equal to the UVLO amplitude (e.g., the first UVLO amplitude). Until that point, the current through the activated transistors Q3 and Q4 is HVG and CV DD and provides a bias voltage to power on mode controller 358. In this manner, switching converter 350 provides a voltage start-up function for power converter 250.

[0034] Operating voltage V DD In response to the UVLO amplitude reaching an amplitude approximately equal to the UVLO amplitude, the mode controller 358 switches to the normal operation mode. Upon entering the normal operation mode, the mode controller 358 deactivates (opens) the switches SW1 and SW3 via the switch control signals SC1 and SC3, and maintains the switches SW1 and SW3 in a deactivated state. The mode controller 358 also activates (closes) the switch SW4, causing the regulated output voltage VHVG from the voltage regulator 356 to be provided to the gate of the transistor Q3. The gate voltage (V HVGIf V ) is a fixed voltage controlled by the voltage regulator 356, then when the source voltage at Q3 is at the threshold voltage of Q3 above the output voltage of the voltage regulator, then transistor Q3 is deactivated; otherwise, transistor Q3 is activated. SW When the voltage becomes large enough to activate clamp circuit 320, the voltage on the gate of transistor Q4 is clamped and as its source voltage rises further, transistor Q4 is deactivated.

[0035] During the normal operating mode, the mode controller 358 controls the operating voltage V DD Monitor the operating voltage V DD When the controller 260 detects that the UVLO amplitude falls below the UVLO amplitude (e.g., when the controller 260 detects a fault condition in the power converter or due to an abnormal output voltage drop), the auxiliary winding (W A If the VDD voltage from the rectified voltage of V VIN falls below the UVLO, the mode controller 358 returns the power converter circuit 250 to the start-up mode (e.g., by opening switches SW2 and SW4 and closing switches SW1 and SW3). DD falls below a second UVLO amplitude that is less than the first UVLO amplitude corresponding to a threshold for the normal operating mode, the power converter circuit 250 is returned to the start-up mode.

[0036] In the normal operating mode, as previously described, the switching controller 350 receives the voltage V TH_ZVS Voltage V compared to SWC Following the deactivation of transistor Q1, the switching voltage V SW may have a relatively high amplitude. For example, when transistor Q1 is deactivated, the voltage V SW The amplitude of is Vm (for example, 1000V) and the primary winding W P In response to the deactivation of transistor Q2, switching terminal 258 begins to resonantly transition downward such that switching voltage VSW , and therefore, V SWC Some power converters may implement ZVS of transistor Q1, where the switching voltage V SW At approximately zero volt amplitude, transistor Q1 is activated (turned ON).

[0037] During normal operation mode, the voltage V SW , which converts a voltage from a lower voltage (e.g., the voltage at the reference terminal 103) to a higher voltage (e.g., the input voltage V IN Primary winding W P As will be explained later, transistors Q3 and Q4 transition to a voltage equal to or greater than V SW is disabled (OFF) at a higher voltage level, and V SW When transistors Q3 and Q4 are OFF, they are enabled (ON) at a lower voltage level of V SW and the voltage at the reference terminal 103. Thus, each of the transistors Q3 and Q4 advantageously functions as a voltage divider between V IN Total voltage amplitude (or input voltage Vix to primary winding W P The transistors Q3 and Q4 do not need to be rated (e.g., maximum allowable Vds) for a given Vds voltage (Vds = 1000V plus Vds), so the transistors Q3 and Q4 can be smaller than if they were rated for a Vds of 1000V. IN In an application where the Vds rating is 1000V, transistors Q3 and Q4 each have a Vds rating of only 600V, and a V ds The advantage of this is that it is not rated for

[0038] The following description describes the operation of the switching controller 350 as the voltage Vsw transitions from a lower voltage (when the transistor Q1 is active) to a higher voltage (when the transistor Q1 is inactive) and then back to the lower voltage. SW is the voltage V SW, which is below the clamp voltage of clamp circuit 320 (e.g., 500V), clamp circuit 320 is not activated. Thus, no current flows through clamp circuit 320, so the gate and source of transistor Q4 are at the same voltage (Vgs of transistor Q4 is 0V). When the Vgs of transistor Q4 is 0V, transistor Q4 is in an activated state (ON). When transistor Q4 is activated, the voltage on the drain of transistor Q3 is at a lower voltage, which is lower than the threshold voltage of transistor Q3, which is lower than voltage VHVG, so transistor Q3 is also activated.

[0039] The mode controller 358 activates the switch SW2 so that the comparator 262 detects the voltage V SWC (This is the voltage V SW (approximately equal to) is the threshold voltage V TH_ZVS To be able to compare with the voltage V SWC is the voltage V TH When the signal CMP falls to logic high, the comparator forces the output signal CMP to a logic high state. A logic high of the signal CMP occurring within the defined dead time (from the falling edge of PWM2 to the rising edge of PWM1) indicates that the current switching cycle can achieve zero voltage switching, even with a relatively high negative magnetizing current. In response, the timing generator slightly decreases the on-time of PWM2 in the next switching cycle to gradually decrease the negative magnetizing current. On the other hand, if the signal CMP does not become logic high within the defined dead time, it indicates that the current switching cycle cannot achieve zero voltage switching. In response, the timing generator slightly increases the on-time of PWM2 in the next switching cycle to increase the negative magnetizing current to discharge the switching node voltage slightly more. The timing generator 364 may be or include a one-shot circuit with an adjustable on-time based on the logic level state of the signal CMP. When the PWM1 signal becomes logic low, the transistor Q1 turns off and the positive magnetizing current charges the switch node 258, increasing the switching voltage V SWrises. Signal PWM2 goes to logic high after the dead time from the falling edge of PWM1. Gate driver 252 (FIG. 2) activates transistor Q2 in response to PWM2 to drive voltage V SW reaches a maximum level. The mode controller 358 effectively disables the comparator 262 (which is not needed at this point in the switching cycle) by deactivating the switch SW2 in response to the positive assertion of the signal PWM2.

[0040] Finally, the voltage V SW rises to the clamp voltage of the voltage clamp circuit 320, and the clamp circuit is activated. SW During the ramp-up period, the fast dv / dt creates a charging current through the impedance device 330 (e.g., a capacitor), resulting in a ff This causes the voltage on clamp pin 321 to V SW , and the clamp circuit is quickly activated. Activation of the clamp circuit 320 fixes (clamps) the voltage on the gate of transistor Q4. Resistor Rz provides a current path from the source of transistor Q4 to the Zener diode stack of the clamp circuit 320. Resistor Rz is sized to control the amount of current flowing from the resistor to the Zener stack. The amount of current from resistor Rz is approximately equal to the leakage current in Zener diode 320a. By balancing the leakage current from the Zener diodes, resistor Rz prevents the voltage V SWexceeds the clamping voltage of the clamp circuit, helps to keep the clamp circuit 320 activated. Because power is dissipated in resistor Rz, impedance device 330 allows resistor Rz to have a relatively high resistance and overcome the Zener diode leakage current with little effect on converter efficiency. On the other hand, in an example that does not include impedance device 330, resistor Rz would need to have a relatively low resistance to activate clamp circuit 320 quickly enough during a rising edge of the switch node, which would consume more power and reduce the efficiency of the converter.

[0041] With the gate voltage of the transistor Q4 fixed due to the activation of the clamp circuit 320, the voltage V SW As V continues to rise, the source voltage becomes more than a threshold voltage above the gate voltage of transistor Q4. At this point, transistor Q4 is deactivated. Meanwhile, transistor Q3 continues to rise above its source voltage (V SWS ) becomes greater than a threshold voltage above the gate voltage of transistor Q3, which is fixed by voltage regulator 356. At this point, voltage V SW As V continues to rise (e.g., to 1000V), both transistors Q3 and Q4 protect the remaining circuitry of switching controller 350. The series combination of the drain-source capacitances of transistors Q3 and Q4 acts as a voltage divider, so that the Vds of each transistor is reduced by the voltage V SW It's almost half of that.

[0042] When the one-shot pulse from timing generator 364 ends, signal PWM2 goes to a logic low, followed (after a dead time) by signal PWM1 going to a logic high. During the dead time, the negative magnetizing current discharges the switch node voltage, so that voltage V SWfalls below the clamp voltage of the voltage clamp circuit 320, deactivating the voltage clamp circuit. In response, transistor Q4 activates. With the gate of transistor Q4 coupled to its source via resistor R1 and no current flowing through transistor Q3, transistor Q3 is also activated. The timing generator implements the pulse width of signal PWM2. A falling edge of signal PWM2 causes mode controller 358 to close switch SW2. When transistors Q3 and Q4 are activated and switch SW2 is closed, comparator 262 detects voltage V SWC and V TH again to enable switching controller 350 to detect whether ZVS occurred within the dead time between the falling edge of signal PWM2 and the rising edge of signal PWM1. The above process is repeated.

[0043] 3, the drain of Q4 is coupled to switching terminal 258, so that circuit elements including transistors Q3 and Q4, clamp circuit 320, impedance device 330, and resistor Rz may function to power on mode controller 358 during start-up mode and provide zero-voltage switching of transistor Q1. In some power converter applications (e.g., flyback converters implementing continuous conduction mode (CCM) and / or discontinuous conduction mode (DCM)), start-up functionality is required but zero-voltage switching of transistor Q1 is not required. In such applications, the drain of transistor Q4 may be coupled to input voltage terminal 101 instead of switching terminal 258.

[0044] In the example of FIG. 3, the plurality of control transistors 264 includes two series-coupled depletion mode transistors Q3 and Q4, which are coupled to a higher level voltage V IN (e.g. 1000V). Some applications require even higher voltage levels V IN(1200V, 1500V, etc.). Thus, in some examples, the plurality of control transistors 264 may include three (or more) depletion mode transistors.

[0045] 4 is a schematic diagram of an example switching controller 550 in which the plurality of control transistors 264 includes three transistors, the above-mentioned transistors Q3 and Q4 and transistor Q5. Most of the switching controller 550 is almost the same as the switching controller 350 of FIG. 3, so the above description of the switching controller 350 may be referred to. The transistors Q3, Q4, and Q5 are depletion mode transistors (e.g., NFETs). The transistor Q5 is coupled between the transistors Q3 and Q4.

[0046] An impedance device 330 (e.g., a capacitor C FF ) is coupled between the drain and gate of transistor Q4, as described above. Similarly, resistor Rz is coupled between the source and gate of transistor Q4. Switching controller 550 includes clamp circuit 520, which includes clamp terminals 521 and 522. Clamp terminal 521 is coupled to the gate of transistor Q4, and clamp terminal 522 is coupled to the gate of transistor Q5. Clamp circuit 520 includes parallel-coupled Zener diodes Z 51 , Z 52 , Z 53 , Z 54 , Z 55 , and Z 56 4 includes six Zener diodes, although in other examples clamp circuit 520 may include less than six Zener diodes or more than six Zener diodes. The cathode of Zener diode Z+ is clamp terminal 521, which is coupled to the gate of transistor Q4. The cathode of Zener diode Z54 is clamp terminal 522, which is coupled to the gate of transistor Q5.

[0047] The clamping voltage of the clamp circuit 520 is the sum of the breakdown voltages of the series combination of Zener diodes. In one example, the number of Zener diodes and their breakdown voltages are such that the clamping voltage of the clamp circuit 520 is equal to the voltage V SW The voltage V SW When V exceeds the clamp voltage of clamp circuit 520, clamp circuit 520 is activated and the voltage on the gate of transistor Q4 rises to voltage V SW In the example of FIG. 4, when the clamp circuit 520 is activated, the Zener diode Z 54 The voltage on the cathode of transistor Q3 is approximately one-half the clamp voltage of clamp circuit 520, and therefore the voltage on the gate of transistor Q5 is approximately one-third of the clamp voltage. When the clamp circuit is activated, the gate voltages of transistors Q4 and Q5 are clamped by clamp circuit 520 and transistors Q4 and Q5 are deactivated (OFF). As described above, voltage regulator 356 clamps the voltage on the gate of transistor Q3. Voltage V SW When V is large enough to activate the clamp circuit 520, the transistor Q3 is also deactivated. When all three transistors Q3, Q4, and Q5 are deactivated, the series combination of the transistors Q3-Q5 acts as a voltage divider, dividing the voltage V SW Approximately one third of the voltage V is divided between each of the transistors. SW When the voltage V is 1200 V, the Vds of each of the transistors Q3 to Q5 is approximately 400 V. SW It does not have to be a size that covers the entire area.

[0048] Figure 5 shows the voltage V SW The voltage V vs. time when it increases from approximately 0V to 1400V and then returns to 0V SW 1 is a graph showing an example of a voltage V on the drain of transistor Q5 (VD_Q5) and a voltage V on the drain of transistor Q3 (VD_Q3). SWWhen V is 1400 V, the voltage on the drain of the transistor Q5 is approximately 933 V, and the voltage on the drain of the transistor Q3 is approximately 466 V. SW Therefore, the voltage V SW is substantially smaller than

[0049] As mentioned above, some flyback converters (e.g., flyback converters implementing continuous conduction mode (CCM) or discontinuous conduction mode (DCM)) do not need to implement ZVS of transistor Q1 and therefore only require a start-up function to bias the switching converter. FIG. 6 is a schematic diagram of an example power converter including a switching controller 650 coupled to power stage 154. Switching controller 650 includes a control logic circuit 655, transistors Q3 and Q4 (e.g., depletion mode NFETs as discussed above), transistor Q5 and transistor Q6 (e.g., depletion mode NFETs as discussed above), and a power supply 670 for supplying power to the power stage 154. DISABLE (e.g., an NFET), a clamp circuit 320, an impedance device 330, and a resistor R Z , R LIM , and R ZS2 , Zener diode Z S2 , and a capacitor C VDD (described above as part of the power stage), and C REF Includes.

[0050] The control logic circuit 655 includes terminals such as a VDD terminal 655a, a voltage reference (REF) terminal 655b, and an output terminal 655c. LIM is coupled between the source of transistor Q3 and VDD terminal 655a. VDD is coupled between VDD terminal 655a and reference terminal 103. REF terminal 655b is coupled to transistor Q DISABLE The gate of the capacitor C REFis coupled between REF terminal 655b and reference terminal 103. Output terminal 655c is coupled to the gate of a switching transistor in power stage 154 (e.g., transistor Q1 in FIGS. 1 and 2). Control logic 655 may include switches, logic gates, flip-flops, comparators, etc., and is operable to generate a pulse width modulated signal PWM at output terminal 655c as a control signal for the gate of transistor Q1.

[0051] The transistors Q3 and Q4 are connected to the input voltage terminal 101 and the resistor R LIM As described above, clamp circuit 320 is coupled between the gate of transistor Q4 and reference terminal 103, impedance device 330 is coupled between the drain and gate of transistor Q4, and resistor Rz is coupled between the source and gate of transistor Q4. Clamp circuit 320, impedance device 330, and resistor Rz operate in substantially the same manner as described above to clamp the voltage on the gate of transistor Q4 to a voltage V above the clamp voltage implemented by clamp circuit 320. IN The control logic circuit 655 clamps the voltage V DD The reference voltage at REF terminal 655b may include a voltage regulator to provide a reference voltage at REF terminal 655b based on DISABLE is the gate voltage for transistor Q DISABLE The control logic 655 is deactivated when the reference voltage at the REF terminal 655b is logic low and the voltage on the VDD terminal of the control logic is below the UVLO level, and is activated when the reference voltage at the REF terminal is logic high (VDD is above UVLO). The control logic 655 is configured to deactivate transistor Q during start-up mode. DISABLE During normal operation mode, transistor Q DISABLE Deactivate.

[0052] 6, the drain of transistor Q4 is coupled to input voltage terminal 101 instead of switching terminal 258 (similar to switching controllers 350 and 550 of FIGS. 3 and 5, respectively). During start-up mode, VDD is below UVLO and the voltage on REF terminal 655b is 0V, which causes transistor Q4 to DISABLE is deactivated. Diode Z S2 The voltage drop across Q3 activates transistor Q3, and the voltage on the drain of transistor Q3 is approximately equal to VDD (which is less than the UVLO voltage level). In this state (Q3 is activated and Q DISABLE is deactivated and the voltage VDD is lower than UVLO), the gate voltage (which is IN Since the potential Vcc (which increases as Vcc increases) is higher than the source voltage, transistor Q4 is also activated.

[0053] Eventually, V exceeds the UVLO voltage level, at which point the control logic 655 enables the internal reference voltage circuitry and turns on transistor Q DISABLE Set the voltage REF to a level (e.g., 5V) high enough to activate the transistor Q DISABLE When V is activated, the gate voltage of transistor Q3 is pulled below its source voltage, thereby deactivating transistor Q3. When V is deactivated, IN As V increases, the voltage on the source of transistor Q3 and the voltage on the drain of transistor Q4 increase. When the source voltage of transistor Q4 exceeds the gate voltage of transistor Q4, transistor Q4 is deactivated. Also, when V reaches the clamp voltage of clamp circuit 320, clamp circuit 320 is activated and clamps the gate voltage for transistor Q4. When both transistors Q3 and Q4 are in the deactivated state, the drain-source capacitances of transistors Q3 and Q4 act as a voltage divider, dividing the input voltage V IN is split approximately equally between transistor Q3 and transistor Q4. Thus, neither transistor Q3 nor transistor Q4 can INThe size does not have to correspond to the overall size of the

[0054] In this description, the term "couple" may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, (a) in a first example, device A is coupled to device B if device A generates a signal to control device B to perform a certain action, or (b) in a second example, device A is coupled to device B via an intervening component C such that device B is controlled by device A via a control signal generated by device A, if the intervening component C does not change the functional relationship between device A and device B.

[0055] Also, in this description, the phrase "based on" means "based at least in part on." Thus, if X is based on Y, then X can be a function of Y as well as any number of other factors.

[0056] A device that is "configured" to perform a certain task or function may be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform that function, or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be through firmware and / or software programming of the device, or through the configuration and / or layout of hardware components, device interconnections, or a combination thereof.

[0057] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are used generally to mean an interconnection or termination between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0058] A circuit or device described as including certain components may instead be adapted to be coupled to those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and be adapted to be coupled to at least some of the passive elements and / or sources, thereby forming the described structure, either at the time of manufacture or at a time thereafter, e.g., by an end user and / or a third party.

[0059] Although the use of certain transistors is described herein, other transistors (or equivalent devices) may be used instead with little or no modification to the remaining circuit elements. For example, field effect transistors (FETs) (such as n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs - e.g., NPN or PNP transistors), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in conjunction with one or more of the devices described herein. The transistors may be depletion mode devices, drain extension devices, enhancement mode devices, natural transistors, or other types of device structure transistors. Also, the devices may be implemented in or on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs).

[0060] Reference may be made in the claims to a transistor's control input and its current terminals. In the context of a FET, the control input is the gate and the current terminals are the drain and source. In the context of a BJT, the control input is the base and the current terminals are the collector and emitter.

[0061] As used herein, a reference to a transistor being "activated" or "ON" means that the transistor's conduction channel is present and drain current can flow through the transistor. A reference to a transistor being "deactivated" or "OFF" means that the conduction channel is not present and therefore drain current does not flow through the transistor. However, a "deactivated" transistor may have current flowing through the transistor's body diode.

[0062] The circuits described herein are reconfigurable to include additional or different components to provide functionality at least partially similar to that available prior to the replacement of the components. Unless otherwise noted, a component shown as a resistor generally represents any one or more elements coupled in series or parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor described herein as a single component may instead be multiple resistors or capacitors, each of which may be multiple resistors coupled in parallel between the same nodes. For example, a resistor or capacitor illustrated and described herein as a single component may instead be multiple resistors or capacitors, each of which may be coupled in parallel between the same nodes, as a single resistor or capacitor. For example, a resistor or capacitor illustrated and described herein as a single component may instead be multiple resistors or capacitors, each of which may be coupled in series between the same two nodes, as a single resistor or capacitor.

[0063] While some elements of the illustrated examples are included in an integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. Also, some or all of the features shown as being external to the integrated circuit may be included in the integrated circuit and / or some features shown as being internal to the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are (1) incorporated in / on a semiconductor substrate, (2) incorporated in a single semiconductor package, (3) incorporated in the same module, and / or (4) incorporated on the same printed circuit board.

[0064] Use of the term "ground" in the preceding description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable to the teachings of the present description. In this description, unless otherwise specified, "about," "approximately," or "substantially" preceding a number means + / - 10 percent of the stated parameter, or a reasonable range of values ​​around zero if the parameter is zero.

[0065] Modifications in the described embodiments are possible, and other embodiments are possible, within the scope of the claims.

Claims

1. 1. A power converter comprising: A power stage; A switching controller; Including, the power stage having an output, the output configured to provide a primary current through a primary winding of a transformer in response to a pulse width modulated (PWM) signal, and to induce a secondary current in a secondary winding of the transformer to generate an output voltage, the power stage having a switching terminal between a power switch and the primary winding; The switching controller: A first control transistor; A clamp circuit; An impedance device; Including, the first control transistor is coupled in series with the second control transistor for initiating an operating voltage during a start-up mode of the power converter and for providing a control voltage based on an amplitude of a switching voltage at the switching terminal during a switching mode, the first control transistor having a first control input; the clamp circuit is coupled between the first control input and a reference terminal, the clamp circuit being configured to clamp a voltage at the first control input in response to the switching voltage exceeding a clamp voltage of the clamp circuit; the impedance device is coupled between the switching terminal and the clamp circuit; Power converter.

2. 2. The power converter of claim 1, wherein the clamp circuit comprises a plurality of Zener diodes coupled in series between the first control input and the reference terminal.

3. 2. The power converter of claim 1 wherein the impedance device comprises a capacitor.

4. 2. The power converter of claim 1 , wherein the first control transistor is coupled to the second control transistor at a transistor terminal, the power converter further comprising a resistor coupled between the transistor terminal and the clamp circuit.

5. 2. The power converter of claim 1, wherein the first control transistor and the second control transistor are depletion mode transistors.

6. 2. The power converter of claim 1, further comprising a third control transistor coupled between the first transistor and a second control transistor, the third control transistor having a second control input, the clamp circuit coupled to the second control input, the clamp circuit configured to clamp a voltage at the second control input in response to the switching voltage exceeding a clamp voltage of the clamp circuit.

7. 7. The power converter of claim 6, wherein the first, second and third control transistors are depletion mode transistors.

8. 1. A power converter comprising: a power stage having a switching terminal; a switching controller coupled to the switching terminal; Including, The switching controller: a comparator having a first input and a second input; a first depletion mode transistor having a first current terminal and a second current terminal, the second current terminal coupled to the first input; a second depletion mode transistor coupled between the switching terminal and the first current terminal, the second depletion mode transistor having a control input; a clamp circuit having a clamp terminal coupled to the control input; an impedance device coupled between the switching terminal and the clamp terminal; Including, Power converter.

9. 9. The power converter of claim 8, wherein the clamp circuit comprises a plurality of Zener diodes coupled in series between the first current terminal and a reference terminal.

10. The power converter of claim 8 wherein the impedance device comprises a capacitor.

11. 9. The power converter of claim 8, wherein the first depletion mode transistor is coupled to the second depletion mode transistor at a transistor terminal, the power converter further comprising a resistor coupled between the first current terminal and the clamp terminal.

12. 9. The power converter of claim 8, further comprising a reference voltage circuit coupled to the second input.

13. 1. A circuit comprising: a first depletion mode transistor having a first control terminal, a first current terminal, and a second current terminal; a second depletion mode transistor having a second control terminal, a third current terminal, and a fourth current terminal, the fourth current terminal coupled to the first current terminal; a clamp circuit having a clamp terminal coupled to the second control terminal; an impedance device coupled between the third current terminal and the clamp terminal; The circuit includes:

14. 14. The circuit of claim 13, further comprising a third depletion mode transistor having a third control terminal, the third depletion mode transistor coupled between the first depletion mode transistor and the second depletion mode transistor.

15. 15. The circuit of claim 14, wherein the clamp terminal is a first clamp terminal and the clamp circuit has a second clamp terminal coupled to the third control terminal.

16. 16. The circuit of claim 15, wherein the clamp circuit includes a plurality of Zener diodes coupled in series between the second control terminal and a reference terminal, the first clamp terminal being coupled to a cathode of one Zener diode of the plurality of Zener diodes and the second clamp terminal being coupled to a cathode of another Zener diode of the plurality of Zener diodes.

17. 14. The circuit of claim 13, wherein the clamp circuit comprises a plurality of Zener diodes coupled in series between the second control terminal and a reference terminal.

18. The circuit of claim 13 , wherein the impedance device comprises a capacitor.

19. 14. The circuit of claim 13, further comprising a resistor coupled between the fourth current terminal and the clamp terminal.

20. 14. The circuit of claim 13, a first resistor coupled to the first control terminal; a third transistor having a third control terminal coupled between the first resistor and a reference terminal; a Zener diode having an anode and a cathode, the anode coupled to the first control terminal; a second resistor coupled between the second current terminal and the cathode; The circuit includes:

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