Small pitch filling support layer

Abstract

A DRAM device is provided having a support layer that retains the bWL features before being filled with electrode metal. The support layer continues to support the structure from the top surface but does not impede gap filling. A temporary gap filling material is first deposited in the bWL gaps and then recessed to expose the top edges. A support layer material is then deposited on the structure by plasma enhanced chemical vapor deposition (PECVD). The device is then orthogonalized and patterned with a pitch larger than the bWL pitch. The temporary gap filling material is then removed to form support beams that include the support material. Metal can then be deposited to fill the bWL gaps below the support beams.

Description

[Technical field]

[0001]

[0001] Embodiments of the present disclosure relate to the field of electronic devices and electronic device manufacturing. More particularly, embodiments of the present disclosure provide an electronic device and a method of forming the same that includes a support layer that retains buried wordline features prior to filling. [Background technology]

[0002]

[0002] Electronic devices such as personal computers, workstations, computer servers, mainframes, and other computer-related equipment such as printers, scanners, hard disk drives, etc. use memory devices that consume low power while providing substantial data storage capacity. There are two main types of random access memory cells suitable for use in electronic devices: dynamic and static. Dynamic random access memory (DRAM) can be programmed to store a voltage that represents one of two binary values, but must be periodically reprogrammed or "refreshed" to maintain this voltage for more than a short time. Static random access memory (SRAM) is so named because it does not require periodic refreshing.

[0003]

[0003] DRAM memory circuits are manufactured by replicating billions of identical circuit elements, known as DRAM cells, on a single semiconductor wafer. Each DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components: a field effect transistor (FET) and a capacitor.

[0004]

[0004] Fabrication of a DRAM cell involves fabricating a transistor, a capacitor, and three contacts (one each for the bit line, word line, and reference voltage). DRAM fabrication is a competitive business. There is a constant drive to reduce the size of individual cells and increase the density of memory cells to allow more memory to be packed onto a single memory chip, especially for densities of 8 gigabits and beyond. Limitations to reducing cell size include running both active and passive word lines through the cell, the size of the cell capacitor, compatibility of array and non-array devices, etc.

[0005]

[0005] One difficulty with DRAM is that the buried wordlines must be low-resistance metals that can withstand high temperatures. Buried wordline pitches will soon be below 30 nm and will continue to shrink with each generation. The mechanical stability of buried wordlines is already an issue and is getting worse.

[0006]

[0006] Current methods use lower stress films or "V" shaped gaps, but these methods have higher resistance. There is still bending, and any imbalance in the gap being filled exacerbates the bending of the line. This bending not only causes an imbalance in the width of the gap that is filled with metal, but also causes a local misalignment of the line in the gap. In the case of buried wordlines, this is a misalignment of the silicon that forms the contact area of ​​the cell and bitline.

[0007]

[0007] Therefore, there is a need in the art for improved DRAMs and methods of manufacturing same. Summary of the Invention

[0008]

[0008] One or more embodiments of the present disclosure are directed to a memory device, in one or more embodiments, the memory includes a substrate having a substrate surface, the substrate surface having a plurality of trenches extending a depth into the substrate, each trench including a bottom and a sidewall, and a beam extending on the substrate surface between the plurality of trenches, the beam including a support layer.

[0009]

[0009] Additional embodiments of the present disclosure are directed to a method of forming a memory device. In one or more embodiments, the method includes providing a substrate having a plurality of trenches thereon, depositing a temporary fill layer on a top surface of the substrate to seal the plurality of trenches, recessing the temporary fill layer to form recesses in each of the plurality of trenches, depositing a support layer material in the recesses, removing the temporary fill material to expose sidewalls and a bottom surface of each of the plurality of trenches, depositing a gap fill material in the plurality of trenches, and removing the support layer material.

[0010]

[0010] In order that the above-mentioned features of the present disclosure may be understood in detail, the present disclosure summarized above will now be more particularly described with reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings only illustrate exemplary embodiments of the present disclosure and therefore should not be considered as limiting its scope, as the present disclosure may admit of other equally effective embodiments. The embodiments described herein are presented by way of example and not by way of limitation to the figures of the accompanying drawings in which like references indicate similar elements. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a process flow diagram illustrating a method of forming a device according to one or more embodiments. [Diagram 2] 1 illustrates a cross-sectional view of a DRAM device according to one or more embodiments. [Diagram 3] 1 illustrates a cross-sectional view of a DRAM device according to one or more embodiments. [Figure 4] 1 illustrates a cross-sectional view of a DRAM device according to one or more embodiments. [Diagram 5] 1 illustrates a cross-sectional view of a DRAM device according to one or more embodiments. [Figure 6] 1 illustrates a cross-sectional view of a DRAM device according to one or more embodiments. [Figure 7]1 illustrates a cross-sectional view of a DRAM device according to one or more embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012]

[0018] To facilitate understanding, the same reference numbers have been used, whenever possible, to designate identical elements common to the drawings. The drawings are not drawn to scale and may be simplified for clarity. It is envisioned that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0013]

[0019] Before describing several example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description as the present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0014]

[0020] The term "substrate" as used herein and in the appended claims refers to a surface, or a portion of a surface, upon which a process acts. Additionally, unless the context clearly indicates otherwise, those skilled in the art will understand that a reference to a substrate may refer to only a portion of a substrate. Additionally, a reference to deposition on a substrate may refer to both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0015]

[0021] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which a film treatment is performed in a manufacturing process. For example, substrate surfaces on which treatment may be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes that polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to film treatment directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film treatment steps may also be performed on underlying layers formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlying layers as the context indicates. Thus, for example, when a film / layer or partial film / layer is deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0016]

[0022] The term "on" indicates that there is direct contact between the elements. The term "directly on" indicates that there is direct contact between the elements, with no intervening elements.

[0017]

[0023] As used herein and in the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to refer to any gas species capable of reacting with the substrate surface.

[0018]

[0024] As used herein, "atomic layer deposition" or "cyclic deposition" refers to the sequential exposure of two or more reactive compounds to deposit layers of material on a substrate surface. The substrate or a portion of the substrate is separately exposed to two or more reactive compounds that are introduced into a reaction zone of a processing chamber. In a time-domain ALD process, the exposure to each reactive compound is separated by a time delay so that each compound can deposit and / or react on the substrate surface and then be purged from the processing chamber. These reactive compounds are said to be sequentially exposed to the substrate. In a spatial ALD process, different portions of the substrate surface, or materials on the substrate surface, are exposed to two or more reactive compounds simultaneously, so that any point on the substrate is not substantially exposed to more than one reactive compound at the same time. As used herein and in the appended claims, the term "substantially" as used in this respect means that it is possible that a small portion of the substrate may be exposed to more than one reactive gas at the same time due to diffusion, as will be understood by those skilled in the art, and simultaneous exposure is not intended.

[0019]

[0025] In one aspect of a time-domain ALD process, a first reactive gas (i.e., a first precursor or compound A) is pulsed into the reaction zone following a first time delay. Then, a second precursor or compound B is pulsed into the reaction zone, followed by a second delay. During each time delay, a purge gas, such as argon, is introduced into the process chamber to purge the reaction zone or remove any residual reactive compounds or reaction by-products from the reaction zone. Alternatively, the purge gas can flow continuously throughout the deposition process, with the purge gas only flowing during the time delay between pulses of reactive compounds. The reactive compounds are pulsed alternately until a desired film or film thickness is formed on the substrate surface. In either scenario, the ALD process of pulsing compound A, purge gas, compound B, purge gas is one cycle. The cycle can start with either compound A or compound B and continue in the respective order of the cycle until a film of a predetermined thickness is obtained.

[0020]

[0026] In an embodiment of a spatial ALD process, a first reactive gas and a second reactive gas (e.g., nitrogen gas) are simultaneously supplied to a reaction zone but separated by an inert gas curtain and / or a vacuum curtain. By moving the substrate relative to the gas supply system, any point on the substrate is exposed to the first reactive gas and the second reactive gas.

[0021]

[0027] As used herein, "chemical vapor deposition" refers to a process in which a substrate surface is exposed to precursors and / or co-reagents simultaneously or substantially simultaneously. As used herein, "substantially simultaneously" refers to either co-flow or where there is a substantial overlap in the exposure of the precursors.

[0022]

[0028] Plasma enhanced chemical vapor deposition (PECVD) is widely used for the deposition of thin films due to its cost-effectiveness and versatility of film properties. In a PECVD process, a hydrocarbon source, such as a gaseous or liquid phase hydrocarbon vapor entrained in a carrier gas, is introduced into a PECVD chamber. A plasma-generated gas, typically helium, is also introduced into the chamber. A plasma is then generated in the chamber, generating excited CH radicals. The excited CH radicals chemically bond to the surface of a substrate positioned in the chamber to form a desired film thereon. The embodiments described herein with respect to PECVD processes can be implemented using any suitable thin film deposition system. Any apparatus descriptions provided herein are exemplary and should not be construed or interpreted as limiting the scope of the embodiments described herein.

[0023]

[0029] As used herein, the term "dynamic random access memory" or "DRAM" refers to a memory cell that stores datum bits by storing a packet of charge (i.e., a binary 1) or no charge (i.e., a binary 0) on a capacitor. The charge is gated onto the capacitor through an access transistor and sensed by turning on the same transistor and looking at the voltage fluctuation caused by dumping the charge packet onto an interconnect line at the transistor output. Thus, a single DRAM cell is made of one transistor and one capacitor.

[0024]

[0030] Traditionally, DRAM cells have high work function metal structures recessed into a buried word line structure. In a DRAM device, the bit lines are formed in a metal level located above the substrate, and the word lines are formed at the polysilicon gate level at the substrate surface. In buried word line (bWL), the word lines are buried below the surface of the semiconductor substrate, using metal as the gate electrode.

[0025]

[0031] One difficulty with DRAM is that the buried wordline (bWL) needs to be a low resistivity metal that can withstand high temperatures. Soon the pitch of bWL will be 30 nanometers or less, and will shrink further with each generation. The mechanical stability of bWL is already an issue and is getting worse. Current methods use lower stress films or "V" shaped gaps, but these methods are more resistive. There is still bending, and if there is an imbalance in the gap being filled, the bending of the line is exacerbated. This bending not only causes an imbalance in the width of the gap that is filled with metal, but also causes a local misalignment of the gap line. In the case of bWL, this is a misalignment of the silicon that forms the cell and BL contact regions. One or more embodiments advantageously provide a method for fabricating bWL features with pitch of 30 nm or less with a vertical aspect ratio of more than 10:1 that can be filled with stressful films without bending the line or collapsing the feature, especially in the case of imbalances in the lines or spaces between the features.

[0026]

[0032] In one or more embodiments, a support layer is advantageously introduced to preserve the bWL characteristics before filling. The support layer continues to support the structure from the top surface but does not impede gap filling. In one or more embodiments, the support layer limits the elastic deformation of the structure during filling.

[0027]

[0033] In one or more embodiments, a low stress temporary gap-filling material is first deposited in the bWL gap and then recessed to expose the top edge. A support layer material is then deposited on the structure by plasma enhanced chemical vapor deposition (PECVD). The devices are then orthogonalized and patterned with a pitch larger than the bWL pitch. The temporary gap-filling material is then removed to form support beams that include the support material. Metal can then be deposited to fill the bWL gaps below the support beams.

[0028]

[0034] Embodiments of the present disclosure are described with reference to figures illustrating devices (e.g., DRAMs) and processes for forming DRAMs according to one or more embodiments of the present disclosure. The illustrated processes are merely illustrative of possible applications of the disclosed processes, and one skilled in the art will recognize that the disclosed processes are not limited to the illustrated applications.

[0029]

[0035] Exemplary embodiments are described herein with reference to cross-sectional views that are schematic illustrations of exemplary embodiments (and intermediate structures). As such, variations from the shapes of the exemplary figures are expected, for example, as a result of manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the specific region shapes illustrated herein, which may include, for example, deviations in shape due to manufacturing. For example, an implanted region illustrated as a rectangle may typically have rounded or curved features and / or have a gradient of implant concentration at its edges, rather than a binary change from implanted to non-implanted regions. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface from which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not indicative of the actual region shapes of a device, nor are they intended to limit the scope of exemplary embodiments.

[0030]

[0036] FIG. 1 is a process flow diagram illustrating a method 10 for manufacturing an electronic device according to one or more embodiments of the present disclosure. Referring to FIG. 1, the method 10 begins in step 12 by providing a DRAM substrate. As used herein, the term "provided" means that the substrate is made available for processing (e.g., positioned in a processing chamber). In step 14, a temporary gap fill material is deposited in the trenches. In step 16, the temporary gap fill material is optionally recessed. In step 18, a support layer material is deposited over the structure. In step 20, the support layer material is patterned. In step 22, the temporary gap fill material is removed. In step 24, metal is deposited to fill the trenches. In step 26, the support layer material is removed. In step 28, the gap fill material is recessed.

[0031]

[0037] In some embodiments, the memory device 100 is a DRAM structure, and the trenches 108 are gaps of buried word lines (bWL). The buried word line structure shown is similar to a FinFET device. Thus, in one or more embodiments, the support layer 114 allows for narrow fin widths with significantly reduced fin bending. This concept can also be applied to variable gap, variable width low-k materials filled with interconnect metal. Thus, although the figures show DRAM with buried word lines (bWL), the invention is not limited to only such structures. Instead, in one or more embodiments, the support layer is formed on a semiconductor structure having high aspect ratio / small critical dimension (CD) trenches. In such structures with high aspect ratio / small critical dimension (CD) trenches, the process of filling the trenches with gap-fill material can cause small pitch line bending. Thus, the support layer of one or more embodiments holds the small pitch trenches before they are filled with gap-fill material (e.g., metal). The support layer of one or more embodiments continues to support the structure from the top, but does not interfere with gap filling.

[0032]

[0038] FIG. 2 illustrates a cross-sectional view of a memory device 100. Those skilled in the art will recognize that the stack shown is an exemplary portion of a DRAM device taken across a buried wordline (bWL). With reference to FIGS. 1 and 2, the DRAM device 100 includes a buried wordline stack 101 including an active area 102 and a gate oxide layer 104. A nitride layer 106 overlies a pad oxide 105 on the buried wordline stack 101. The active area 102 may include any suitable material known to those skilled in the art. In one or more embodiments, the active area 102 includes silicon (Si).

[0033]

[0039] As shown in FIG. 2, a number of trenches 108 are located between adjacent gate stacks 101. Each of the trenches 108 has a bottom and sidewalls. The trenches 108 may have any suitable shape, including but not limited to square, tapered, etc. The trenches 108 may have any suitable aspect ratio (ratio of feature depth to feature width). In some embodiments, the aspect ratio is about 5:1, 10:1, 15:1, 20:1, 25:1, 30:1, 35:1, or 40:1 or greater.

[0034]

[0040] The trenches 108 may be formed to have a width within a range of about 3 to about 30 nm, including but not limited to a range of about 3 nm to about 20 nm, about 3 nm to about 15 nm, about 3 nm to about 10 nm, about 3 nm to about 8 nm, or about 3 nm to about 5 nm. As will be appreciated by those skilled in the art, the width of the trenches 108 is defined as the distance W1 from one sidewall to another sidewall. As will be appreciated by those skilled in the art, the depth of the trenches 108 is defined as the distance D1 from the active area surface 103 to the bottom 107 of the trenches 108.

[0035]

[0041] 2, a gate oxide layer 104 is conformally formed on the active area 102, on the active area surface 103, and along the sidewalls and bottoms 107 of the plurality of trenches 108. In one or more embodiments, the gate oxide layer 104 may include any suitable material known to those skilled in the art. In one or more embodiments, the gate oxide layer 104 includes one or more of an oxide, a low-k dielectric material, or a high-k dielectric material. In some embodiments, the gate oxide layer 104 includes an annealed oxide material. In other embodiments, the gate oxide layer 105 includes one or more of a silicon oxynitride (SiON), a silicon oxide, or a high-k dielectric material. Although the term "silicon oxide" may be used to describe the gate oxide layer 104, one skilled in the art will recognize that the present disclosure is not limited to a particular stoichiometry. For example, the terms "silicon oxide" and "silicon dioxide" may both be used to describe a material having silicon atoms and oxygen atoms in any suitable stoichiometric ratio. The same is true for other materials listed in this disclosure, such as silicon nitride, silicon oxynitride, tungsten oxide, zirconium oxide, aluminum oxide, hafnium oxide, and the like.

[0036]

[0042] In one or more embodiments, the term "high-k dielectric" refers to a material that has a high dielectric constant (e.g., compared to silicon dioxide). In one or more embodiments, the high-k dielectric material is selected from one or more of hafnium oxide (HfO2), zirconium oxide (ZrO2), vanadium oxide (VO2), titanium oxide (TiO2), tin oxide (SnO2), aluminum oxide (Al2O3), hafnium silicon oxide (HfSiO), or zirconium silicon oxide (ZrSiO).

[0037]

[0043] In one or more embodiments, the gate oxide layer 104 has a thickness in the range from about 1 nm to about 10 nm, or in the range from about 5 nm to about 7 nm, including about 1 nm, about 2 nm, about 3 nm, about 4 nm, about 5 nm, about 6 nm, about 7 nm, about 8 nm, about 9 nm, or about 10 nm.

[0038]

[0044] 1 and 3, in one or more embodiments, step 14 deposits a temporary fill layer 110 on top of the gate oxide layer 104 to seal the tops of the trenches 108. The temporary fill layer 110 may include any suitable material known to those skilled in the art. In one or more embodiments, the temporary fill layer 110 is a low stress material. In one or more embodiments, the temporary fill layer 110 includes one or more of spin-on carbon, CVD carbon, CVD silicon germanium (SiGe), polysilicon, n-type doped polysilicon, and the like.

[0039]

[0045] The temporary fill layer 110 may be formed by any suitable deposition process known to those of skill in the art. In one or more embodiments, the deposition process includes atomic layer deposition (ALD), molecular layer deposition (MLD), physical vapor deposition (PVD), chemical vapor deposition (CVD), etc.

[0040]

[0046] The process of forming the provisional fill layer 110 can begin by exposing the substrate to a precursor for a period of time. In some embodiments, the precursor is delivered without the use of a plasma.

[0041]

[0047] In one or more embodiments, buried voids 111 may form when the temporary fill layer 110 is deposited. As long as these voids are below the level of overburden removal, the support layer may still be prevented from being deposited in the gaps.

[0042]

[0048] 1, in some embodiments, once the temporary fill layer 110 is deposited with an overburden, in step 16 the overburden of the temporary fill layer 110 must be removed to form the recess 112. The overburden of the temporary fill layer 110 may be removed by any means known to one of ordinary skill in the art. In one or more embodiments, the overburden of the temporary fill layer 110 is removed by recessing to form the recess 112. In one or more embodiments, the temporary fill layer 110 is removed from the top surface of the device 100 to expose at least the top edges of the buried word line stacks 101. In one or more embodiments, the temporary fill layer 110 is recessed a distance D to form the recess 112. R The recess 112 is recessed by a recess distance D R may be any suitable distance. In some embodiments, the recess distance D R is in the range of 0 nm to 60 nm, or in the range of greater than 0 nm to 60 nm, including 2 nm, 4 nm, 6 nm, 8 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 50 nm, or 60 nm.

[0043]

[0049] 1 and 4, in step 18, a support layer 114 is deposited in the recess 112. The support layer 114 is formed as a beam of material. The support layer 114 may be formed by any suitable deposition means known to those of skill in the art. In one or more embodiments, the support layer 114 is formed by plasma enhanced chemical vapor deposition (PECVD). The support layer 114 may include any suitable material known to those of skill in the art. In one or more embodiments, the support layer 114 includes one or more of polysilicon, low temperature oxide, high dielectric constant material, metal, metal nitride, p-type doped polysilicon, and the like.

[0044]

[0050] 1 and 5, the device is patterned and etched to narrow the lines and widen the spaces in step 20. This patterning can be self-aligned double patterning (SADP) where the spacers used for double patterning can be used directly as the support layer, as shown in Figure 5, or the spacers can be used as a mask to etch the underlying support layer.

[0045]

[0051] 6 is a cross-sectional view 100b of the DRAM device. Referring to FIGS. 1 and 6, in step 22, the temporary support layer 110 is removed to expose the plurality of trenches 108. The temporary support layer 110 may be removed by any suitable means known to those skilled in the art. In one or more embodiments, the temporary support layer 110 is selectively isotropically removed beneath the support layer 114 and in the plurality of trenches 108.

[0046]

[0052] 1 and 7, in step 24, a gap fill material 116 is deposited to fill the plurality of trenches 108. The gap fill material 116 may include any suitable material required in the final device fabrication. In one or more embodiments, the gap fill material 116 does not interact with the support material 114. In other words, the support material 114 is inert to the gap fill material 116. In one or more embodiments, the gap fill material 116 includes one or more of a metal nitride, including but not limited to titanium nitride (TiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), etc., a metal, including but not limited to molybdenum (Mo) and tungsten (W), etc. In one or more embodiments, the gap fill material 116 includes one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), molybdenum (Mo), tungsten (W), etc. In one or more embodiments, the gap fill material 116 is deposited to fill the plurality of trenches 108 but leave gaps 118 between adjacent beams of the support layer 114 .

[0047]

[0053] 1, in step 26, the gap fill material 116 is partially or completely removed from around the beams of support layer 114 such that the support layer 114 may be effectively removed. In one or more embodiments, after the beams of support layer 114 are removed, the gap fill material 116 is further recessed to a desired depth in the plurality of trenches 108.

[0048]

[0054] In one or more embodiments, a plasma processing apparatus is used to generate a plasma and process the metal film with an ammonia plasma. In one or more embodiments, the plasma processing apparatus is a stand-alone tool and is not part of a cluster tool. In other embodiments, the plasma processing apparatus is part of a cluster tool.

[0049]

[0055] Some well-known cluster tools that can be adapted for the present disclosure are Olympia®, Continuum®, and Trillium®, all available from Applied Materials, Inc., Santa Clara, Calif. However, the exact arrangement and combination of chambers can be varied to perform the specific steps of the processes described herein. Other process chambers that can be used include, but are not limited to, cyclic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma treatment, etching, pre-cleaning, chemical cleaning, thermal treatment such as RTP, plasma nitridation, degassing, hydroxylation, and other substrate processes. By performing the process in a chamber on a cluster tool, it is possible to avoid surface contamination of the substrate from atmospheric impurities without oxidation before depositing a subsequent film.

[0050]

[0056] According to one or more embodiments, the substrate is continuously under vacuum or "load-lock" conditions and is not exposed to ambient air when being transferred from one chamber to the next. The transfer chamber is therefore under vacuum and is "pumped down" under vacuum pressure. An inert gas may be present in the processing chamber or the transfer chamber. In some embodiments, an inert gas is used as a purge gas to remove some or all of the reactants (e.g., single reactants). According to one or more embodiments, a purge gas is injected at the exit of the deposition chamber to prevent the transfer of the reactants (e.g., single reactants) from the deposition chamber to the transfer chamber and / or further processing chambers. This causes the flow of inert gas to form a curtain at the exit of the chamber.

[0051]

[0057] Substrates may be processed in a single substrate deposition chamber where a single substrate is loaded, processed, and unloaded before another substrate is processed. Substrates may also be processed in a continuous manner, similar to a conveyor system where multiple substrates are individually loaded into a first portion of the chamber, moved through the chamber, and unloaded from a second portion of the chamber. The geometry of the chamber and associated conveyor system may form a linear or curved path. Additionally, the processing chamber may be a carousel where multiple substrates move about a central axis and are exposed to processes such as deposition, etching, annealing, cleaning, etc., throughout the carousel path.

[0052]

[0058] During processing, the substrate may be heated or cooled. Such heating or cooling may be accomplished by any suitable means, including, but not limited to, changing the temperature of the substrate support and flowing a heated or cooled gas over the substrate surface. In some embodiments, the substrate support includes a heater / cooler that is controllable to change the substrate temperature by conduction. In one or more embodiments, a gas (either a reactive gas or an inert gas) employed to locally change the substrate temperature is heated or cooled. In some embodiments, the heater / cooler is positioned within the chamber adjacent to the substrate surface to change the substrate temperature by convection.

[0053]

[0059] The substrate may also be stationary or rotating during processing. A rotating substrate may be rotated (about the substrate axis) continuously or in discrete steps. For example, the substrate may be rotated throughout the entire process, or the substrate may be rotated only a small amount between exposures to different reactive or purge gases. Rotating the substrate (continuously or in steps) during processing may help minimize the effects of, for example, local variations in gas flow profiles, resulting in a more uniform deposition or etching.

[0054]

[0060] One or more embodiments provide a non-transitory computer readable medium comprising instructions, when executed by a controller of a processing chamber, that cause a processing chamber to perform the steps of: providing a substrate having a plurality of trenches thereon; depositing a conformal gate oxide layer on the substrate; depositing a temporary fill layer on a top surface of the gate oxide layer to seal the plurality of trenches; recessing the temporary fill layer to form recesses in each of the plurality of trenches; depositing a support layer material in each of the plurality of trenches; depositing the support layer material in the recesses and on a top surface of the gate oxide layer; removing the temporary fill material to expose the gate oxide layer on sidewalls and a bottom surface of each of the plurality of trenches; depositing a gap fill material in the plurality of trenches; and removing the support layer material.

[0055]

[0061] Spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to facilitate the description of an element or feature illustrated in the figures in relation to another element(s) or feature(s). It will be understood that the spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, an element described as "below" or "beneath" the other element or feature would then be oriented "above" the other element or feature. Thus, the exemplary term "below" may encompass both an upper and lower orientation. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0056]

[0062] The use of the terms "a" and "an" and "the" and similar referents in the context of describing the materials and methods described herein (particularly in the context of the claims below) should be construed to cover both the singular and the plural, unless otherwise stated herein or clearly contradicted by context. The recitation of ranges of values ​​herein is merely intended to serve as a shorthand method of individually referring to each individual value falling within the range, unless otherwise stated herein, and each individual value is incorporated herein as if the value were individually recited herein. All methods described herein may be performed in any suitable order, unless otherwise stated herein or clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., "etc.") provided herein is intended merely to better illuminate the materials and methods, and does not impose limitations on the scope unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0057]

[0063] As used throughout this specification, the terms "one embodiment," "particular embodiment," "one or more embodiments," or "embodiments" mean that a particular feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of phrases such as "in one or more embodiments," "in a particular embodiment," "in one embodiment," or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment of the disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0058]

[0064] Although the disclosure of this specification has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the disclosure. Therefore, the disclosure is intended to cover such modifications and variations provided they come within the scope of the appended claims and their equivalents.

Claims

1. 1. A memory device comprising: a substrate having a substrate surface, the substrate surface having a plurality of trenches extending a depth into the substrate, each trench including a bottom and a sidewall; a beam extending on the substrate surface between the plurality of trenches, the beam including a support layer; A memory device comprising:

2. The memory device of claim 1 , further comprising a gate oxide layer on each bottom and sidewall of the plurality of trenches.

3. 3. The memory device of claim 2 further comprising a gap fill material recessed onto said gate oxide layer and into each of said plurality of trenches.

4. 10. The memory device of claim 1, wherein the support layer comprises one or more of polysilicon, low temperature oxide, high dielectric constant material, metal, metal nitride, p-type doped polysilicon, or the like.

5. 3. The memory device of claim 2, wherein the gate oxide layer comprises one or more of an oxide, a low-k dielectric material, a high-k dielectric material, and an annealed oxide material.

6. The memory device of claim 5 , wherein the gate oxide layer has a thickness in the range of 5 nm to 7 nm.

7. 4. The memory device of claim 3, wherein the recessed gap-fill material comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), molybdenum (Mo), tungsten (W), or the like.

8. The memory device of claim 1 , wherein the trenches have an aspect ratio of 10:1 or greater.

9. 1. A method of forming a memory device, comprising: Providing a substrate having a plurality of trenches thereon; depositing a temporary fill layer on an upper surface of the substrate to seal the plurality of trenches; recessing the temporary fill layer to form recesses in each of the plurality of trenches; depositing a support layer material within the recess; removing the temporary fill material to expose a sidewall and a bottom surface of each of the plurality of trenches; depositing a gap fill material into the plurality of trenches; removing said support layer material; The method includes:

10. The method of claim 9 , wherein the temporary filling material comprises a low stress material.

11. The method of claim 10 , wherein the temporary fill material comprises one or more of spin-on carbon, CVD carbon, CVD silicon germanium (SiGe), polysilicon, n-type doped polysilicon, and the like.

12. 10. The method of claim 9, wherein the support layer material comprises one or more of polysilicon, low temperature oxide, high dielectric constant material, metal, metal nitride, p-type doped polysilicon, and the like.

13. 10. The method of claim 9, further comprising depositing a conformal gate oxide layer on the substrate to form buried wordlines prior to depositing the temporary fill layer.

14. 14. The method of claim 13, wherein the conformal gate oxide layer comprises one or more of an oxide, a low-k dielectric material, a high-k dielectric material, and an annealed oxide material.

15. 10. The method of claim 9, wherein the gap-filling material comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), molybdenum (Mo), tungsten (W), or the like.

16. The method of claim 9 , further comprising recessing the gap fill material in the plurality of trenches prior to removing the support layer material.

17. The method of claim 9 , wherein the support layer material forms a beam that extends across the plurality of trenches.

18. 10. The method of claim 9, wherein the recess of each of the plurality of trenches has a depth in the range of greater than 0 nm to 15 nm.

19. The method of claim 9 , wherein depositing the support layer material comprises plasma enhanced chemical vapor deposition (PECVD).

20. The method of claim 9 , wherein depositing the temporary fill material forms buried voids in the plurality of trenches.

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